Single-Supply, High Speed PECL/LVPECL Comparators ADCMP551/ADCMP552/ADCMP553 Data Sheet FUNCTIONAL BLOCK DIAGRAM Single power supply 500 ps propagation delay input to output 125 ps overdrive dispersion Differential PECL/LVPECL compatible outputs Differential latch control Internal latch pull-up resistors Power supply rejection greater than 70 dB 700 ps minimum pulse width Equivalent input rise time bandwidth > 750 MHz Typical output rise/fall of 500 ps Programmable hysteresis HYS* NONINVERTING INPUT INVERTING INPUT Q OUTPUT ADCMP551/ ADCMP552/ ADCMP553 Q OUTPUT LATCH ENABLE INPUT LATCH ENABLE INPUT *ADCMP552 ONLY 04722-001 FEATURES Figure 1. GENERAL DESCRIPTION The ADCMP551/ADCMP552/ADCMP553 are single-supply, high speed comparators fabricated on Analog Devices, Inc., proprietary XFCB process. The devices feature a 500 ps propagation delay with less than 125 ps overdrive dispersion. Overdrive dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP552. APPLICATIONS Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero crossing detectors Line receivers and signal restoration Clock drivers A differential input stage permits consistent propagation delay with a common-mode range from −0.2 V to VCCI − 2.0 V. Outputs are complementary digital signals and are fully compatible with PECL and 3.3 V LVPECL logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VCCO − 2 V. A latch input is included and permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pullups that set the latch in tracking mode when left open. The ADCMP551/ADCMP552/ADCMP553 are specified over the −40°C to +85°C industrial temperature range. The ADCMP551 is available in a 16-lead QSOP package; the ADCMP552 is available in a 20-lead QSOP package; and the ADCMP553 is available in an 8-lead MSOP package. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADCMP551/ADCMP552/ADCMP553 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timing Information ....................................................................... 10 Applications ....................................................................................... 1 Applications Information .............................................................. 11 Functional Block Diagram .............................................................. 1 Clock Timing Recovery ............................................................. 11 General Description ......................................................................... 1 Optimizing High Speed Performance ..................................... 11 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ........................... 11 Specifications..................................................................................... 3 Comparator Hysteresis .............................................................. 12 Absolute Maximum Ratings............................................................ 5 Minimum Input Slew Rate Requirement ................................ 12 Thermal Considerations .............................................................. 5 Typical Application Circuits ......................................................... 13 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 14 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 15 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 3/15—Rev. A to Rev. B Changed ADCMP55x to ADCMP551/ADCMP552/ADCMP553 ..................... Throughout Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 6/13—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 10/04—Revision 0: Initial Version Rev. B | Page 2 of 15 Data Sheet ADCMP551/ADCMP552/ADCMP553 SPECIFICATIONS VCCI = 3.3 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted. Table 1. Electrical Characteristics Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Voltage Range Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Voltage Range Latch Enable Differential Voltage Range Latch Enable Input High Current Latch Enable Input Low Current LE Voltage, Open LE Voltage, Open Latch Setup Time Latch Hold Time Latch to Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS Output Voltage—High Level Output Voltage—Low Level AC OUTPUT CHARACTERISTICS Rise Time Fall Time AC OUTPUT CHARACTERISTICS (ADCMP553) Rise Time Fall Time AC PERFORMANCE Propagation Delay Symbol Conditions Min VOS −IN = 0 V, +IN = 0 V −0.2 −3 −10.0 ΔVOS/dT IIN −IN = −0.2 V, +IN = +1.3 V −28.0 Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Within Device Propagation Delay Skew—Channel-to-Channel Overdrive Dispersion Overdrive Dispersion Slew Rate Dispersion ΔtPD/dT −3.0 CIN AV CMRR VCM = −0.2 V to +1.3 V RHYS = ∞ Typ ±2.0 ±1.0 2.0 −6.0 −5.0 ±1.0 1.0 1800 1000 60 76 ±0.5 VCCI − 1.8 0.4 −150 −150 VCCI − 0.15 VCCI/2 − 0.075 Max Unit VCCI − 2.0 +3 +10.0 V V mV mV μV/°C μA nA/°C μA pF kΩ kΩ dB dB mV +5.0 +3.0 VCCI − 0.8 1.0 +150 +150 VCCI VCCI/2 + 0.075 V V μA μA V V ps ps ps ps VCCO − 0.78 VCCO − 1.54 V V tS tH tPLOH, tPLOL tPL @ VCCI − 0.8 V @ VCCI − 1.8 V Latch inputs not connected Latch inputs not connected VOD = 250 mV VOD = 250 mV VOD = 250 mV VOD = 250 mV VOH VOL PECL 50 Ω to VDD − 2.0 V PECL 50 Ω to VDD − 2.0 V tR tF 10% to 90% 10% to 90% 510 490 ps ps tR tF 10% to 90% 10% to 90% 440 410 ps ps tPD VOD = 1 V VOD = 20 mV VOD = 1 V VOD = 1 V 500 625 0.25 35 ps ps ps/°C ps VOD = 1 V 35 ps 20 mV ≤ VOD ≤ 100 mV 50 mV ≤ VOD ≤ 1.0 V 0.4 V/ns ≤ SR ≤ 1.33 V/ns 75 75 75 ps ps ps Rev. B | Page 3 of 15 100 100 450 700 VCCO − 1.15 VCCO − 2.00 ADCMP551/ADCMP552/ADCMP553 Parameter AC PERFORMANCE (continued) Pulse Width Dispersion Duty Cycle Dispersion Common-Mode Voltage Dispersion Equivalent Input Rise Time Bandwidth1 Maximum Toggle Rate Minimum Pulse Width RMS Random Jitter Unit-to-Unit Propagation Delay Skew POWER SUPPLY (ADCMP551/ADCMP552) Input Supply Current Output Supply Current Output Supply Current Input Supply Voltage Output Supply Voltage Positive Supply Differential Power Dissipation Power Dissipation DC Power Supply Rejection Ratio—VCCI DC Power Supply Rejection Ratio—VCCO POWER SUPPLY (ADCMP553) Positive Supply Current Positive Supply Current Positive Supply Voltage Power Dissipation Power Dissipation DC Power Supply Rejection Ratio—VCC HYSTERESIS (ADCMP552 Only) Programmable Hysteresis 1 Symbol BWEQ PWMIN IVCCI IVCCO VCCI VCCO VCCO − VCCI PD Data Sheet Conditions Min 700 ps ≤ PW ≤ 10 ns 33 MHz, 1 V/ns, VCM = 0.5 V 1 V swing, 0.3 V ≤ VCM ≤ 0.8 V 0 V to 1 V swing, 2 V/ns >50% output swing ΔtPD < 25 ps VOD = 250 mV, 1.3 V/ns, 500 MHz, 50% duty cycle @ 3.3 V @ 3.3 V without load @ 3.3 V with load Dual Dual Dual, without load Dual, with load 8 3 40 3.135 3.135 −0.2 40 90 PSRRVCCI PSRRVCCO IVCC VCC PD @ 3.3 V without load @ 3.3 V with load Dual Dual, without load Dual, with load 3.135 PSRRVCC 0 Typ Max 25 10 10 750 800 700 1.1 ps ps ps MHz MHz ps ps 50 ps 12 5 55 3.3 3.3 55 110 75 85 9 35 3.3 30 60 70 17 9 70 5.25 5.25 +2.3 75 130 mA mA mA V V V mW mW dB dB 13 42 5.25 42 75 mA mA V mW mW dB 40 mV Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BWEQ = .22/ (trCOMP2 − trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input. Rev. B | Page 4 of 15 Unit Data Sheet ADCMP551/ADCMP552/ADCMP553 ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS Table 2. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Ground Voltage Differential Input Voltages Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls Output Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range The ADCMP551 16-lead QSOP package has a θJA (junction-toambient thermal resistance) of 104°C/W in still air. Rating −0.5 V to +6.0 V −0.5 V to +6.0 V −0.5 V to +0.5 V −0.5 V to +3.5 V −4.0 V to +4.0 V −0.5 V to +5.5 V The ADCMP552 20-lead QSOP package has a θJA (junction-toambient thermal resistance) of 80°C/W in still air. The ADCMP553 8-lead MSOP package has a θJA (junction-toambient thermal resistance) of 130°C/W in still air. ESD CAUTION 30 mA −40°C to +85°C 125°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 5 of 15 ADCMP551/ADCMP552/ADCMP553 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VCCO 1 20 VCCO QA 2 19 QB QA 1 16 QB QA 3 QA 2 15 QB VCCO 4 ADCMP552 VCCO 3 14 VCCO LEA 5 TOP VIEW (Not to Scale) 13 LEB LEA 6 15 LEB 12 LEB VCCI 7 14 AGND 11 VCCI 6 10 –INA 7 +INA 8 9 AGND –INB +INB –INA 8 +INA 9 HYSA 10 Figure 2. ADCMP551 16-Lead QSOP Pin Configuration 16 LEB 13 –INB 12 +INB 11 HYSB 8 AGND LEA 1 Figure 3. ADCMP552 20-Lead QSOP Pin Configuration LEA 2 ADCMP553 7 VCC +INA 3 TOP VIEW (Not to Scale) 6 QA –INA 4 5 QA 04722-004 TOP VIEW (Not to Scale) 17 VCCO 04722-003 LEA 5 ADCMP551 04722-002 LEA 4 18 QB Figure 4. ADCMP553 8-Lead MSOP Pin Configuration Table 3. Pin Function Descriptions ADCMP551 3, 14 1 Pin No. ADCMP552 1, 4, 17, 20 2 2 ADCMP553 6 Mnemonic VCCO QA 3 5 QA 4 5 2 LEA 5 6 1 LEA 6 7 7 8 4 VCCI −INA 8 9 3 +INA 9 10 11 12 HYSA HYSB +INB 10 13 −INB 11 12 14 15 8 AGND LEB Description Logic Supply Terminal. One of Two Complementary Outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information. One of Two Complementary Outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information. One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to the comparator being placed into latch mode. LEA must be driven in conjunction with LEA. One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator being placed into latch mode. LEA must be driven in conjunction with LEA. Input Supply Terminal. Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. Programmable Hysteresis. Programmable Hysteresis. Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. Analog Ground. One of Two Complementary Inputs for Channel B Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator being placed into latch mode. LEB must be driven in conjunction with LEB. Rev. B | Page 6 of 15 Data Sheet ADCMP551/ADCMP552/ADCMP553 ADCMP551 13 Pin No. ADCMP552 16 15 18 QB 16 19 QB ADCMP553 7 Mnemonic LEB VCC Description One of Two Complementary Inputs for Channel B Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to the comparator being placed into latch mode. LEB must be driven in conjunction with LEB. One of Two Complementary Outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information. One of Two Complementary Outputs for Channel B. QB is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information. Positive Supply Terminal. Rev. B | Page 7 of 15 ADCMP551/ADCMP552/ADCMP553 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VCCI = 3.3 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted. –6.5 –5 –6.6 –7 –8 –10 –0.2 0.1 0.4 0.7 1.0 1.3 NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V) 04722-005 –9 –6.7 –6.8 –6.9 –7.0 –7.1 –7.2 –7.3 04722-008 +IN INPUT BIAS CURRENT (A) (+IN = 0.5V, –IN = 0V) INPUT BIAS CURRENT (A) –6 –7.4 –7.5 –40 –20 0 20 40 TEMPERATURE (C) 60 80 Figure 8. Input Bias Current vs. Temperature Figure 5. Input Bias Current vs. Input Voltage 2.00 2.4 1.95 2.3 1.90 2.2 1.85 1.80 1.75 1.70 1.65 04722-006 1.60 1.55 1.50 –40 –20 0 20 40 TEMPERATURE (C) 60 2.1 2.0 1.9 1.8 1.7 FALL 1.6 04722-012 OUTPUT RISE AND FALL (V) OFFSET VOLTAGE (mV) RISE 1.5 1.4 0 80 0.25 0.50 0.75 1.00 TIME (ns) 1.25 1.50 1.75 Figure 9. Rise and Fall of Outputs vs. Time Figure 6. Input Offset Voltage vs. Temperature 460 525 450 515 RISE TIME (ps) 440 505 495 FALL FALL 0 10 20 30 40 50 TEMPERATURE (C) 60 70 80 410 400 –40 –30 –20 –10 90 04722-010 485 475 –40 –30 –20 –10 430 420 04722-007 TIME (ps) RISE 0 10 20 30 40 50 TEMPERATURE (C) 60 70 80 Figure 10. ADCMP553 Rise/Fall Time vs. Temperature Figure 7. ADCMP551/2 Rise/Fall Time vs. Temperature Rev. B | Page 8 of 15 90 Data Sheet ADCMP551/ADCMP552/ADCMP553 515 505 504 510 500 495 490 480 –40 –30 –20 –10 04722-011 485 0 10 20 30 40 50 TEMPERATURE (C) 60 70 80 501 500 499 498 497 496 495 –0.2 90 Figure 11. Propagation Delay vs. Temperature 1.3 25 100 80 60 40 04722-012 20 0.2 0.4 0.6 OVERDRIVE VOLTAGE (V) 0.8 15 10 5 0 –5 0.7 1.0 Figure 12. Propagation Delay vs. Overdrive Voltage 2.7 3.7 4.7 5.7 6.7 PULSE WIDTH (ns) 7.7 8.7 9.7 Figure 15. Propagation Delay Error vs. Pulse Width 140 120 PROGRAMMED HYSTERESIS (mV) 100 80 60 40 04722-009 20 0 100 1.7 10 RHYS (k) 120 100 80 60 40 20 04722-025 0 20 04722-015 PROPAGATION DELAY ERROR (ps) 120 0 PROGRAMMED HYSTERESIS (mV) 0.1 0.4 0.7 1.0 INPUT COMMON MODE VOLTAGE (V) Figure 14. Propagation Delay vs. Common-Mode Voltage 140 PROPAGATION DELAY ERROR (ps) 502 04722-014 PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 503 505 0 0 1 50 100 150 IHYS (A) 200 Figure 16. Comparator Hysteresis vs. IHYS Figure 13. Comparator Hysteresis vs. RHYS Rev. B | Page 9 of 15 250 300 ADCMP551/ADCMP552/ADCMP553 Data Sheet TIMING INFORMATION LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VREF ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH tPLOL tR 04722-016 50% Q OUTPUT Figure 17. System Timing Diagram Figure 17 shows the compare and latch features of the ADCMP551/ADCMP552/ADCMP553. Table 4 describes the terms in the diagram. Table 4. Timing Descriptions Symbol tPDH Timing Input to Output High Delay tPDL Input to Output Low Delay tPLOH Latch Enable to Output High Delay tPLOL Latch Enable to Output Low Delay tH Minimum Hold Time tPL tS Minimum Latch Enable Pulse Width Minimum Setup Time tR Output Rise Time tF Output Fall Time VOD Voltage Overdrive Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs Minimum time the latch enable signal must be high to acquire an input signal change Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs Amount of time required to transition from a low to a high output as measured at the 20% and 80% points Amount of time required to transition from a high to a low output as measured at the 20% and 80% points Difference between the differential input and reference input voltages Rev. B | Page 10 of 15 Data Sheet ADCMP551/ADCMP552/ADCMP553 APPLICATIONS INFORMATION The comparators in the ADCMP551/ADCMP552/ADCMP553 are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP551/ADCMP552/ ADCMP553 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 μF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close to the power supply pins as possible on the ADCMP551/ADCMP552/ADCMP553 to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input pins may be left open. The internal pull-ups on the latch pins set the latch to transparent mode. If the latch is to be used, valid PECL voltages are required on the inputs for proper operation. The PECL voltages should be referenced to VCCI. Occasionally, one of the two comparator stages within the ADCMP551/ADCMP552 is not used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described previously. The best performance is achieved with the use of proper PECL terminations. The open-emitter outputs of the ADCMP551/ ADCMP552/ADCMP553 are designed to be terminated through 50 Ω resistors to VCCO − 2.0 V or any other equivalent PECL termination. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP551/ADCMP552/ADCMP553. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP551/ADCMP552/ADCMP553. Source resistance in combination with equivalent input capacitance can cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP551/ADCMP552/ADCMP553, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF input capacitance yields a time constant of 15 ns, which is significantly slower than the 500 ps capability of the ADCMP551/ADCMP552/ADCMP553. Source impedances should be significantly less than 100 Ω for best performance. Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the ADCMP551/ ADCMP552/ADCMP553 should be free from oscillation when the comparator input signal passes through the switching threshold. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP551/ADCMP552/ADCMP553 has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 20 mV to 1 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the ADCMP551/ ADCMP552/ADCMP553 is far less sensitive to input variations than most comparator designs. Rev. B | Page 11 of 15 ADCMP551/ADCMP552/ADCMP553 Data Sheet Propagation delay dispersion is an important specification in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 18). For the ADCMP551/ADCMP552/ ADCMP553, overdrive dispersion is typically 125 ps as the overdrive is changed from 20 mV to 1 V. This specification applies for both positive and negative overdrive since the ADCMP551/ADCMP552/ADCMP553 has equal delays for positive- and negative-going inputs. A current source can also be used with the HYS pin. The relationship between the current applied to the HYS pin and the resulting hysteresis is shown in Figure 16. –VH 2 +VH 2 0V INPUT 1 1.5V OVERDRIVE INPUT VOLTAGE 0 VREF ± VOS OUTPUT 120 COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often useful in a noisy environment or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in Figure 19. If the input voltage approaches the threshold from the negative direction, the comparator switches from a 0 to a 1 when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator remains in a 1 state until the −VH/2 threshold is crossed coming from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. Positive feedback from the output to the input is often used to produce hysteresis in a comparator (see Figure 23). The major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero. In the ADCMP552, hysteresis is generated through the programmable hysteresis pin. A resistor from the HYS pin to VCCI creates a current into the part that is used to generate hysteresis. Hysteresis generated in this manner is independent of output swing and is symmetrical around the trip point. The hysteresis versus resistance curve is shown in Figure 20. PROGRAMMED HYSTERESIS (mV) Figure 18. Propagation Delay Dispersion 100 80 60 40 20 0 100 04722-019 Q OUTPUT Figure 19. Comparator Hysteresis Transfer Function 04722-017 DISPERSION 04722-018 20mV OVERDRIVE 10 RHYS (k) 1 Figure 20. Comparator Hysteresis Transfer Function MINIMUM INPUT SLEW RATE REQUIREMENT As for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. Analog Devices recommends a slew rate of 1 V/μs or faster to ensure a clean output transition. If slew rates less than 1 V/μs are used, hysteresis should be added to reduce the oscillation. Rev. B | Page 12 of 15 Data Sheet ADCMP551/ADCMP552/ADCMP553 TYPICAL APPLICATION CIRCUITS VIN VREF + ADCMP551/ ADCMP552/ ADCMP553 – VIN OUTPUTS VREF ADCMP551/ ADCMP552/ ADCMP553 HYS OUTPUTS 0 TO 80k VCCO – 2V ALL RESISTORS 50 ALL RESISTORS 50, UNLESS OTHERWISE NOTED Figure 23. Adding Hysteresis Using the HYS Control Pin VIN + ADCMP551/ ADCMP552/ ADCMP553 – VIN OUTPUTS + ADCMP551/ ADCMP552/ ADCMP553 – 100 LATCH ENABLE INPUTS 50 50 100 Figure 24. How to Interface a PECL Output to an Instrument with a 50 Ω to Ground Input OUTPUTS VCCO –2V ALL RESISTORS 50 UNLESS OTHERWISE NOTED 04722-021 –VREF 50 (VCCO – 2V) 2 VCCO –2V + ADCMP551/ ADCMP552/ ADCMP553 – 50 04722-024 Figure 21. High Speed Sampling Circuits +VREF VCCO – 2.0V 04722-026 VCCI 04722-020 LATCH ENABLE INPUTS Figure 22. High Speed Window Comparator Rev. B | Page 13 of 15 ADCMP551/ADCMP552/ADCMP553 Data Sheet OUTLINE DIMENSIONS 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 1 10 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.025 (0.64) BSC SEATING PLANE 8° 0° 0.012 (0.30) 0.008 (0.20) 0.020 (0.51) 0.010 (0.25) 0.050 (1.27) 0.016 (0.41) 0.041 (1.04) REF 09-12-2014-A COMPLIANT TO JEDEC STANDARDS MO-137-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches and (millimeters) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 1 8 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.050 (1.27) 0.016 (0.41) COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) Rev. B | Page 14 of 15 0.020 (0.51) 0.010 (0.25) 0.041 (1.04) REF 09-12-2014-A 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) Data Sheet ADCMP551/ADCMP552/ADCMP553 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 0.80 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-AA 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model1 ADCMP551BRQ ADCMP551BRQZ ADCMP551BRQZ-REEL7 EVAL-ADCMP551BRQZ ADCMP552BRQ ADCMP552BRQZ EVAL-ADCMP552BRQZ ADCMP553BRMZ EVAL-ADCMP553BRMZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] Evaluation Board 20-Lead Shrink Small Outline Package [QSOP] 20-Lead Shrink Small Outline Package [QSOP] Evaluation Board 8-Lead Mini Small Outline Package [MSOP] Evaluation Board Z = RoHS Compliant Part. ©2004–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04722-0-3/15(B) Rev. B | Page 15 of 15 Package Option RQ-16 RQ-16 RQ-16 Branding RQ-20 RQ-20 RM-8 B53