ETC LC868920A

Ordering number : ENN*6703
CMOS IC
LC868920A
Dot Matrix LCD Segment Driver with On-Chip
1280-Byte Display RAM for the LC868364A Expansion
Preliminary
Overview
The LC868920A is a segment driver with built-in display RAM for the liquid crystal dot matrix-graphic display. It
stores the display data sent from the 8-bit microcontroller in the internal display RAM and generates dot matrix LCD
drive signals to control LCD panels. The LC868920A controls the graphic display simply in such a way that one bit of
the display RAM corresponds to one dot of the LCD.
It is possible to expand the display capacity of LC868364A more than 32 × 100 dots by using this segment driver. The
LCD controller operates on the low frequency clock from the microcontroller except when writing to registers or RAM.
Therefore, it is suitable for personal electronics devices with LCD panelswhich operates in low-power.
Features
(1) Segment driver to expand LCD display capability for LC868364A.
(2) Internal RAM
: 1280 × 8 bits
(3) Segment output port
- Segment output direction
: 80 terminals
: S01 → S80
Ver.1.34
32900
91400 RM (IM) HO No.6703-1/21
LC868920A
(4) LCD automatic display controller
- Display duty
: 1/1 - 1/32 duty
- LCD control functions
1. Number of display bits in horizontal direction control
2. Vertical display scroll function
: by changing the display start address
3. Read/Write display RAM
4. LCD drive frequency control
- Source clock of LCD controller
: Crystal oscillator for low power consumption
- Clock for accessing registers and display RAM (R/W)
: System clock from microcontroller.
(5) Power supply
- Internal logic circuit
- LCD driver
2.5V - 6.5V
3.0V - 6.5V
(6) Shipping form
- Chip delivery form
No.6703-2/21
LC868920A
Pad Assignment
Chip size (X × Y)
Thickness of chip
Pad size
Pad pitch
80
79
78
77
76
: 4.04mm × 3.21mm
: 480µm
: 105µm × 105µm
: 110µm
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
51
52
50
49
81
48
82
47
83
46
84
45
85
44
86
43
87
42
88
41
89
40
90
39
91
38
92
37
93
36
94
35
95
34
96
33
97
32
98
99
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
100
No.6703-3/21
LC868920A
Pad name and Coordinates value
Pin No.
Pad No.
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
S01
S02
S03
S04
S05
S06
S07
S08
S09
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
Coordinates
Xµm
Yµm
-1423
-1365
-1313
-1365
-1203
-1365
-1093
-1365
-983
-1365
-873
-1365
-763
-1365
-653
-1365
-543
-1365
-433
-1365
-323
-1365
-213
-1365
-103
-1365
7
-1365
117
-1365
227
-1365
337
-1365
447
-1365
557
-1365
667
-1365
777
-1365
887
-1365
997
-1365
1107
-1365
1218
-1365
1328
-1365
1438
-1365
1548
-1365
1658
-1365
1768
-1365
1780
-849
1780
-739
1780
-629
1780
-519
1780
-408
1780
-298
1780
-188
1780
-78
1780
32
1780
142
1780
252
1780
362
1780
472
1780
582
1780
692
1780
802
1780
912
1780
1022
1780
1132
1780
1242
Pin No.
Pad No.
Name
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
V2
V3
V5
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
SCK
CS
RD
WR
RS
CL2
M
Coordinates
Xµm
Yµm
1780
1352
1265
1364
1155
1364
1045
1364
935
1364
825
1364
715
1364
605
1364
495
1364
385
1364
275
1364
165
1364
55
1364
-55
1364
-165
1364
-275
1364
-386
1364
--496
1364
-606
1364
-716
1364
-826
1364
-936
1364
-1046
1364
-1156
1364
-1266
1364
-1376
1364
-1486
1364
-1596
1364
-1706
1364
-1816
1364
-1753
909
-1753
788
-1753
668
-1753
548
-1753
428
-1753
308
-1753
188
-1753
68
-1753
-52
-1753
-172
-1753
-292
-1753
-412
-1753
-532
-1753
-652
-1753
-772
-1753
-892
-1753
-1012
-1753
-1132
-1753
-1252
-1753
-1372
Notes:
• When using LC868920A in the form of chip, connect the substrate of chip to VSS or leave it open.
No.6703-4/21
LC868920A
S01
S80
System Block Diagram
V2
V3
V5
LCD DRIVER
Latch for display data
VDD
VSS
START ADDRESS
DOUT
UPPER ADDRESS
DUTY REGISTER
UPPER CURSOR
ADDRESS REGISTER
SCK
CL2
M
RS
RD
WR
CS
RAM
(1280 BYTES)
LOWER CURSOR
ADDRESS REGISTER
TIMING
GENERATOR
HOTIZONTAL WORD
COUNT REGISTER
LOWER ADDRESS
DIN
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DOUT
INSTRUCTION
REGISTER
Terminal Form
A TYPE
B TYPE
VDD
IN
IN
VSS
Terminals: M, RS, RD , W R , CL2
C TYPE
Terminals: SCK
D TYPE
VDD
V5
DATA
IN/OUT
V3
OUTPUT
CONTROL
OUT
V2
VSS
Terminals: DB0 to DB7
Terminals: S1 to S80
No.6703-5/21
LC868920A
Terminal Function Table
Terminal
Pin No.
Input/Output
VSS
VDD
DB0 - DB7
84
93
85 - 92
Input/Output
SCK
94
95
Input
Input
CS
Function Description
Negative power supply (-)
Positive power supply (+)
Built-in Data bus
Terminals for sending/receiving data to/from the MPU
Clock for registers and display RAM access
Chip select terminal : Enable when CS=0
RD
96
Input
Read signal from LC868920A to LC868364A
WR
97
Input
Write signal from LC868364A to LC868920A
RS
98
Input
CL2
M
V2
V3
V5
S1 - S80
99
100
81
82
83
1 - 80
Input
Input
Output
Register selection
RS=1
: Instruction register
RS=0
: Data register
LCD display signal (clock signal)
LCD display signal (synchronization signal)
LCD power supply
LCD segment drive output terminal
No.6703-6/21
LC868920A
1. Absolute Maximum Ratings at Ta=25°C, VSS=0V
Parameter
Supply voltage
LCD Input voltage
Input voltage
Symbol
VDDMAX
VNMAX
VI(1)
VI(2)
Output voltage
VO(1)
VO(2)
Maximum power
consumption
Operating
temperature
Storage
temperature
Pdmax
Conditions
VDD[V]
Pins
VDD
V2,V3,V5
CS,RD,WR,RS,
CL2,M,SCK
DB0 to DB7
(Input mode)
S1 to S80
DB0 to DB7
(Output mode)
min.
-0.3
VSS
-0.3
Ratings
typ.
max.
+7.0
+7.0
VDD+0.3
-0.3
VDD+0.3
-0.3
-0.3
-
V
V5+0.3
VDD+0.3
200
mW
°C
Topr
-30
-
70
Tstg
-55
-
125
min.
Ratings
typ.
max.
*) The following condition has to be satisfied:
unit
V5 ≥ V3 ≥ V2 ≥ VSS
2. Recommended Operating Range at Ta=-30 to +70°C, VSS=0V
Parameter
Symbol
Pins
Operating
supply voltage
range
VDD
VDD
Supply voltage
range in Hold
mode
VHD
LCD supply
voltage range
High level input
voltage
V5
V5
VIH(1)
VIH(2)
DB0 to DB7
(Input mode)
CS,RD,WR ,RS
CL2,M,SCK
VIL(1)
DB0 to DB7
VIL(2)
CS,RD,WR,RS
VIL(3)
CL2,M,SCK
FCL2
FSCK
CL2
SCK
VDD
Conditions
VDD[V]
FSCK ≤ 6MHz
3.3
6.5
FSCK ≤ 4MHz
2.7
6.5
FSCK ≤ 3MHz
2.4
6.5
Keep RAM and
2.0
6.5
unit
V
register data in
standby mode
Low level input
voltage
Input clock
frequency
VSS
Input mode
6.5
4.5 - 6.5 0.75VDD
VDD
2.4 - 4.5 0.75VDD
VDD
4.5 - 6.5 0.75VDD
2.4 - 4.5 0.75VDD
4.5 - 6.5
0
2.4 - 4.5
0
4.5 - 6.5
0
2.4 - 4.5
0
4.5 - 6.5
0
2.4 - 4.5
0
2.4 - 6.5
32
2.4 - 6.5
0.3
2.7 - 6.5
0.3
3.3 - 6.5
0.3
32.768
VDD
VDD
0.25VDD
0.25VDD
0.25VDD
0.25VDD
0.25VDD
0.25VDD
33
kHz
MHz
3
4
6
Note:
The specifications above concerning recommended operating conditions and electrical characteristics
assume the chip is in the QIP100E package. However, the LSI will be delivered in die form, not in a package.
The specifications will be very similar for the die, however, depending on factors such as the board on which
the chip is mounted, the bonding pressure, and the moulded plastic the characteristics will differ.
The ideal operating temperature for the above specifications is Ta= 25°C ± 2°C.
No.6703-7/21
LC868920A
3. Electrical Characteristics at Ta=-30 to +70°C, VSS=0V
Parameter
Symbol
High level output
voltage
VOH(1)
Low level output
voltage
V5-Si drop voltage
(i:1 to 80)
VX-Si drop voltage
(X:2, 3) (i: 1 to 80)
VSS-Si drop voltage
(i:1 to 80)
Hysteresis voltage
VOL(1)
VD(1)
VD(2)
VD(3)
VHIS
Pins
DB0 to DB7
DB0 to DB7
S1 to S80
S1 to S80
S1 to S80
Conditions
• Output mode
• IOH=-0.6mA
• Output mode
• IOH=-0.1mA
• Output mode
• IOL=+0.6mA
• Output mode
• IOL=+0.1mA
• -90µA for each
Si terminal
• V5-VSS=5V
• -15µA for each
Si terminal
• V5-VSS=5V
• -90µA for each
Si terminal
• V5-VSS=5V
• -15 µA for each
Si terminal
• V5-VSS=5V
• +90µA for each
Si terminal
• V5-VSS=5V
• +15µA for each
Si terminal
• V5-VSS=5V
SCK
VDD[V]
4.5 - 6.5
min.
2.4
Ratings
typ.
2.5 - 6.5 VDD-0.5
max.
VDD
0
0.4
2.5 - 6.5
0
0.4
4.5 - 6.5
630
2.5 - 6.5
120
4.5 - 6.5
200
2.5 - 6.5
120
-630
2.5 - 6.5
-120
2.5 - 6.5
V
VDD
4.5 - 6.5
4.5 - 6.5
unit
0.1VDD
mV
V
4. Sample Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V
The sample current dissipation characteristics shows the measurement result of Sanyo evaluation board.
The currents through the output transistors are ignored.
Parameter
Symbol
Current consumption
IDD(1)
during normal operation
IDD(2)
Current consumption
during READ/WRITE
operation to RAM or
registers
IDD(3)
Current consumption
during standby mode
IDD(4)
Pins
Conditions
Ratings
typ.
7
max.
15
2.5 - 4.5
4
10
4.5 - 6.5
15
50
2.5 - 4.5
5
20
• FCL2=32kHz
• FSCK : 3MHz
• Figure 2
• V2=V3=V5=VSS
4.5 - 6.5
170
300
3.0 - 4.5
100
200
• FCL2=0Hz
• FSCK : stop
• Figure 3
• V2=V3=V5=VSS
4.5 - 6.5
0.05
30
2.5 - 4.5
0.02
20
• FCL2=32kHz
• FSCK : stop
• Figure 1
• V2=V3=V5=VSS
• FCLK2=32kHz
• FSCK : stop
• Figure 4
• V5=5V, V3=3V,
V2=2V
VDD[V]
4.5 - 6.5
min.
unit
µA
No.6703-8/21
LC868920A
VDD
VDD
Open
Open
A
A
VDD
Open
S1 S2
SCK
CS
RD
WR
RS
M
S80
LC868920A
CL2
VSS
V2
V3
fSCK=3MHz
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Open
Open
VDD
SCK
CS
RD
WR
RS
M
V5
S80
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
LC868920A
CL2
fCL2=32kHz
VSS
V2
V3
Open
V5
fCL2=32kHz
Figure 1 Current consumption measuring circuit
during normal operation
Figure 2 Current consumption measuring circuit
during READ/WRITE operation to
RAM or registers
VDD
VDD
Open
Open
A
A
VDD
Open
S1 S2
S1 S2
SCK
CS
RD
WR
RS
M
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
LC868920A
CLK2
VSS
VDD
S80
V2
V3
V5
Open
Open
S1 S2
SCK
CS
RD
WR
RS
M
S80
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
LC868920A
CL2
VSS
V2
V3
V5
2V
3V
5V
Open
fCL2=32kHz
fCL2=0Hz
Figure 3 Current consumption measuring circuit
during standby mode
Figure 4 Current consumption measuring circuit
during LCD operation
No.6703-9/21
LC868920A
AC Characteristics at Ta=-30 to +70°C, VSS=0V
(1) MPU Interface
1. Read/write clock
1
4
2
5
3
SCK
RD, WR
6
2. Read cycle
7
6
RD
9
8
10
0.75VDD
0.25VDD
CS, RS
11
12
8
DB0 - DB7
3. Write cycle
7
6
WR
9
10
8
0.75VDD
CS, RS
0.25VDD
13
14
8
DB0 - DB7
No.6703-10/21
LC868920A
No
Item
Conditions
Symbol
MIN
MAX
166
249
333
0.45
0.45
5
5
5
5
3
3340
3340
3340
0.55
0.55
40
100
40
100
6
SCK clock cycle
2
3
4
SCK_H width
SCK_L width
5
RD, WR Hold time
6
RD, WR pulse width pw1
RD, WR
3.3 – 6.5
2.7 – 6.5
2.4 – 6.5
2.4 – 6.5
2.4 – 6.5
4.5 - 6.5
2.4 - 4.5
4.5 - 6.5
2.4 - 4.5
2.4 – 6.5
7
ENABLE cycle time
tcyc1
RD
2.4 – 6.5
12
tcyc2
WR
2.4 – 6.5
12
8
Rising/Falling time
tr1, tf1
RD
9
Address set-up time
tAS1
CS, RS, RD
tAS2
CS, RS, WR
tAH1
CS, RS, RD
4.5 - 6.5
2.4 - 4.5
4.5 - 6.5
2.4 - 4.5
4.5 - 6.5
2.4 - 4.5
2.4 – 6.5
40
40
40
40
0.5
tAH2
CS, RS, WR
2.4 – 6.5
0.5
pw1
tr1,tf1
RD, WR set-up time tRS
Address Hold time
tRH
SCK
VDD
1
10
tsck
Value
SCK
SCK
SCK, RD, WR
SCK, RD, WR
Data delay time
tDDR1
RD, DB0 - DB7, CL=50pF
2.4 – 6.5
12
Data Hold time
tDHR1
RD, DB0 - DB7, CL=50pF
20
20
WR, DB0 - DB7, CL=50pF
4.5 - 6.5
2.4 – 6.5
2.4 – 6.5
WR, DB0 - DB7, CL=50pF
2.4 – 6.5
1
13
Data set-up time
tDSW1
14
Data Hold time
tDHW1
ns
tsck
tsck
ns
ns
tsck
tsck
20
40
11
unit
ns
ns
ns
tsck
2
tsck
ns
1.5
tsck
tsck
CL: Loading Capacity
No.6703-11/21
LC868920A
(2) Display Control Timing at Ta=-30 to +70°C, VSS=0V
1
2
0.75VDD
0.25VDD
CL2
5
3
4
6
0.75VDD
0.25VDD
M
No
Item
Conditions
Symbol
1
2
3
4
Clock cycle
Low level pulse width
High level pulse width
Rising time
tCL2
tWLCL2
tWHCL2
tr
CL2
CL2
CL2
CL2
5
Falling time
tf
CL2
6
M delay time
tDM
M
Value
VDD
MIN
MAX
2.4 - 6.5
2.4 - 6.5
2.4 - 6.5
4.5 - 6.5
2.4 - 4.5
4.5 - 6.5
2.4 - 4.5
4.5 - 6.5
2.4 - 4.5
30
13
13
31
20
50
20
50
60
100
unit
µs
µs
µs
ns
ns
ns
No.6703-12/21
LC868920A
Example circuit for reference
1. 32 × 112 dots
LCD Panel (32 × 112 dots)
S32
S1
P41(CL2)
P42(LCDP2)
P43(M)
C1
P00
P01
P02
P40(2KOUT)
P03
P04
P05
LC868364A
P06
P07
VLCD
P46(RD)
P47(WR)
P44
P45
VDD
V2
V3
V5
VSS
C32
External
Voltage up
converter
S80
CL2
SCK
M
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
RD
WR
CS
RS
VDD
V2
V3
V5
VSS
S1
LC868920A
2. 32 × 192 dots
LCD Panel (32 × 192 dots)
C32
S32
S1
S80
S1
S80
S1
LC868920A
LC868920A
DB
RD
WR
CS
RS
CL2
SCK
M
LCD power
VDD
VSS
VLCD
LC868364A
P0
P46(RD)
P47(WR)
P44
P45
P41(CL2)
P42(LCDP2)
P43(M)
LCD power
VDD
VSS
P40(2KOUT)
DB
RD
WR
CS
RS
CL2
SCK
M
LCD power
VDD
VSS
C1
External
Voltage up
converter
No.6703-13/21
LC868920A
! Evaluation Sample (ES)
Shipping Form:
LC868920A: chip, Evaluation sample: QIP100E (shown below) or chip
If you use the ES in the package to design and fabricate an evaluation board, refer to the following pin assignment.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
Terminal Assignment
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
V2
V3
V5
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
SCK
CS
RD
WR
RS
CL2
M
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
(FLP100)
No.6703-14/21
LC868920A
Functions
1. Interface control
The interface control block consists of the instruction register and the timing generator.
(Note) When accessing to registers or the display RAM of LC868920A, the system clock of LC868364A has to be either
CF oscillation or RC oscillation. It will cause the irregular operation if the crystal oscillation is used in
LC868364A when reading/writing data from/to LC868920A.
The STX instruction of LC868364A should be used to write data to LC868920A. The LDX instruction of
LC868364A should be used to read data from LC868920A.
(1) Instruction register (4-bit data)
- When RS = '1', the lower 4-bits data of the eight bit data bus (DB0-DB7) is sent to this register.
- The following conditions have to be set to write data to the instruction register.
: Enable the chip select.
1. CS = '0'
: Writing mode from LC868364A to LC868920A
2. WR = '0'
3. RS = '1'
: Select the instruction register.
4. Feed clock to SCK.
- The value of the instruction registers serves as the address of 7 kinds of data registers.
The instruction register holds the data until the instruction code is rewritten. A list of instruction codes is shown below.
DB3
0
0
1
1
1
1
1
Instruction code
DB2
DB1
0
1
0
1
0
0
0
1
0
1
1
1
1
1
DB0
0
1
0
0
1
0
1
Description
Select the horizontal word count register
Select the duty register
Select the start address register
Select the lower cursor address register
Select the upper cursor address register
Set the display data writing mode
Set the display data reading mode
Notes:
Don’t write to the Test Register.
The Test Register can be specified by writing ‘00H’ to the Instruction Register.
will cause malfunction since this register is only used for testing.
However, setting any bits in this register
(2) Writing to each data register
- The following indicates how to write data to the registers or the display RAM specified by the instruction register setting.
- The following conditions should be set to write data to each register or the display RAM.
: Enable the chip select
1. CS = '0'
2. WR = '0'
: Writing mode from LC868364A.to LC868920A
3. RS = '0'
: Select writing data
4. Feed clock to SCK
- The data output from LC868364A through the 8 bits data bus (DB0 - DB7) is written to the register specified by the
instruction register. (Data can not be written without a SCK clock signal.)
- By selecting the display data writing mode with the instruction register and setting the condition shown above, the output
data from LC868364A through the data bus (DB0 - DB7) is written to the display RAM address specified by the cursor
address. After the completion of writing, the cursor address is automatically decremeted by 1. Therefore, the data can
be written contiguously to the display RAM.
No.6703-15/21
LC868920A
(3) Reading display RAM
- Refer to "Section 2 Display control registers and display RAM (8)" about how to output the display RAM data to the data
bus (DB0 - DB7).
- The following conditions are necessary to be set to read display RAM data.
: Enable the chip select
1. CS = '0'
: Reading mode from LC868920A to LC868364A
2. RD = '0'
3. RS = '0'
: Select the display RAM
4. Feed clock to SCK.
- Each time data is read from the display RAM, the address of the display RAM (cursor address) is automatically
decremented by 1.
(4) Timing generator
- The interface control block and the display are controlled by the timing signals and control signals generated in this circuit.
The control signals and timing signals are used to transfer the data output from terminals DB0 - DB7 to the internal
registers and to transfer data between terminals DB0 - DB7 and the display RAM. This circuit also produces the data
input/output control signals and read/write timing signals.
2. Display control registers and display RAM
- The display is controlled by writing data to the instruction register and 7 internal data registers.
(1) LCD drive frequency
- DP indicates the number of clocks which is necessary to display 1 word (16 dots). DP is fixed to '2' in
LC868920A.
- LC868920A is a segment driver to expand the LCD display capability for LC868364A. The common signal is
output from LC868364A. Therefore, the number of dots to display a line may vary between the internal driver
in microcontroller and the segment driver for expansion. Even if the number of display dots is different, the
LCD driver frequency has to be the same on each side.
(Example 1)
When selecting 32COM × 32SEG in LC868364A
The number of dots per line in microcontroller
The number of dots per line in LC868920A
: 32 dots
: 80 dots
The time required to display a line is the same for both the microcontroller and LC868920A by setting as
follows.
LC868364A
: HP = 5
32 × 5 (Hp) = 160
LC868920A
: Dp = 2
80 × 2 (Dp) = 160
32
C1
|
C32
LCD Panel
32
80
S32 - S1
S80 - S1
LC868364A
LC868920A
No.6703-16/21
LC868920A
(Example 2) When selecting 16COM in LC868364A
The number of dots per line in LC868920A : 80 dots
80 × 2 (DP) = 160
It is necessary to set as follows to have the same time required to display a line in LC868364A as in
LC868920A.
32 × 5 (Hp) = 160
(Note)
If 16COM is selected in LC868364A and LC868920A is used to expand segments, S1 to S32 segments
can only be used in LC868364A and segments S33 to S48 can not be used. HP = 5 should be set to
LC868364A by program.
16
C1
|
C16
LCD Panel
(Note)
S33 to S48 can not be used.
32
80
S32 - S1
S80 - S1
LC868364A
LC868920A
(2) Horizontal word count register
Register
RD WR
Instruction register
1
0
0
Horizontal word count register 1
RS
1
0
DB7
0
-
DB6
0
-
DB5
0
-
DB4
0
-
DB3
0
DB2 DB1
0
1
Dn-1
DB0
0
- This register sets the number of horizontal words.
- Dn indicates the number of words in horizontal direction.
- The total number of horizontal dots on the LCD panel (n) is given by the following formula.
n = 8 × (Dn ×2)
(n≤80)
- 1 to 5 ( in decimal) can be set as Dn.
- The relation between the total number of horizontal dots (n), the number of horizontal words (Dn) and register settings is
shown below.
Total number of horizontal dots (n)
16
32
48
64
80
Dn
1
2
3
4
5
DB2
0
0
0
0
1
DB1
0
0
1
1
0
DB0
0
1
0
1
0
(3) Duty register
Register
Instruction register
Divider ratio register
RD
WR
1
1
0
0
RS
1
0
DB7
0
0
DB6
0
0
DB5
0
DB4
0
DB3
DB2
0
0
Nx-1
DB1
1
DB0
1
- This register sets the divider ratio (Nx). (Display duty = 1/Nx)
- Nx represents the divider ratio of display and 1/Nx indicates a display duty.
- 2 to 32 (in decimal) can be set as Nx.
No.6703-17/21
LC868920A
(4) Start address register
Register
Instruction register
Start address register
RD
WR
1
1
0
0
RS
1
0
DB7
0
0
DB6
0
DB5
0
DB4
DB3
DB2
0
1
0
Start Address (STAD)
DB1
0
DB0
0
- This register sets the value of display start line address.
- The display start line address shows the RAM line address of the data to be displayed in the top line on the LCD panel.
- The start address counter is a 7-bit down-counter with a preset function.
- The start address (STAD) is set to the start address counter as an initial value.
- The start address counter is decremented by 1 each time the display of a line in horizontal direction is completed on the
screen.
- The start address counter takes the value 7FH on the next decrement after 0.
(5) Lower cursor address register
Register
Instruction register
Cursor address counter
(lower byte)
RD
WR
1
1
0
0
RS
1
0
DB7
0
0
DB6
0
0
DB5
0
0
DB4
0
0
DB3
DB2
DB1
DB0
1
0
1
0
Lower cursor address (CAL)
- Set the lower address used to read/write data from/to the display RAM in this register.
- The lower cursor address counter is a 4-bit down-counter with a preset function.
- The lower cursor address (CAL) is set to the counter as an initial value.
- This counter is decremented by 1 each time the RAM is accessed.
- If RAM is accessed when the value of this counter is "0", then Dn-1 is automatically set.
- 0 to 9 (in decimal) can be set as a lower cursor address.
(6) Upper cursor address register
Register
Instruction register
Cursor address counter
(upper byte)
RD
WR
1
1
0
0
RS
1
0
DB7
0
0
DB6
0
DB5
DB4
DB3
DB2
DB1
0
0
1
0
1
Upper cursor address (CAH)
DB0
1
- Set the upper addresses used to read/write data from/to the display RAM in this register.
- The upper cursor address counter is a 7-bit down-counter with a preset function.
- This counter is decremented by 1 each time the lower cursor address counter generates the underflow.
- The cursor address is written to the cursor address counter by setting data to the lower and upper cursor address registers.
- The cursor address indicates the RAM address to access display data. The data of the address specified by the cursor
address is read /written from/to the display RAM.
- The cursor address consists of the 4-bit lower address and 7-bit upper address.
(7) Display RAM
a.) Writing data to Display RAM
Register
Instruction register
RAM
RD
WR
1
1
0
0
RS
1
0
DB7
0
MSB
DB6
0
DB5
DB4
DB3
DB2
0
0
1
1
Display pattern data
DB1
1
DB0
0
LSB
- Select the display data writing mode by setting "0EH" to the instruction register. Then set RS = 0 and write 8-bit data to
the display RAM.
The display pattern data is written to the RAM address specified by the cursor address. After writing data to RAM, the
cursor address counter is automatically decremented by 1.
No.6703-18/21
LC868920A
b.) Reading data from display RAM
Register
Instruction register
RAM
RD
WR
1
0
0
1
RS
1
0
DB7
0
MSB
DB6
0
DB5
DB4
DB3
DB2
0
0
1
1
Display pattern data
DB1
1
DB0
1
LSB
- Select the display data reading mode by setting ‘0FH’ to the instruction register. Then set RS=0 and select the display
RAM.
- The procedure of reading RAM data is as follows:
(1) The RAM data of the address specified by the cursor address is output to DB0 to DB7 terminals by setting as
shown above.
(2) The cursor address counter is decremented by 1.
The following figure indicates the procedure of reading RAM data.
Conditions
• Instruction register (IR) = OFH
• RS=0
• RD=0
DB0
(2)
-1
D0
Cursor
address
counter
RAM data
DB1
D1
A0 to A10
11 bits
DB7
D7
(1) RAM DATA is output to DB terminals
(1) Output control (OE)
e.x.) Writing (reading) data to (from) display RAM
• Lower cursor address (CAL) =03H
• Upper cursor address (CAH) =02H
• The number or horizontal bytes (Dn)=05H
• Internal RAM capacity =1280 bytes
00H
10H
20H
30H
01H
11H
21H
31H
02H
12H
22H
32H
03H
13H
23H
33H
If the writing operation is executed when the value of the
lower cursor address counter is ‘0’, the upper cursor address
counter is decremented by 1 after the completion of writing.
Then (Dn-1) is set to the lower cursor address counter.
04H
14H
24H
34H
Specified by the cursor address
First, data is written to this RAM address.
Decremented by 1 after the completion of writing.
7F0H
7F1H
7F2H
7F3H
7F4H
If the writing operation is executed when the cursor address is ‘00H’,
then "7FH" is set to the upper cursor address counter after the
completion of writing.
(Dn-1) is set to the lower cursor address counter.
Notes:
Don’t write to the Test Register.
The Test Register can be specified by writing ‘00H’ to the Instruction Register.
will cause malfunction since this register is only used for testing.
However, setting any bits in this register
No.6703-19/21
LC868920A
3. LCD driver
- 4 levels of the LCD driving voltage (V5, V3, V2, and VSS) are externally supplied. The LCD driving voltage level to be
output to the segment drivers S1 to S80 vary according to the contents of the display data latch and the synchronous signal (M
signal).
- The 8-bit data output from the display RAM is input to the display data latch. The input 8-bit data is latched in the display
data latch for the number of bytes specified by the horizontal byte count register. This operation is repeated for the number
of times that is determined by the divide ratio number.
- The LCD display voltage has to be supplied to V2, V3 and V5 terminals after all data is set to LCD display data registers and
the display RAM. After power is on, if the LCD display voltage is supplied to V2, V3, and V5 terminals without setting
data to the internal registers and the display RAM, uncertain display is appeared on LCD panel. Thus, supply the VSS level
to V2, V3 and V5 terminals until all data required to display is set to data registers and the display RAM.
(Actually, the LCD display voltage is supplied to this circuit from LC868364A microcontroller. Therefore, turn OFF the
LCD display in LC868364A until data is set to the internal registers and the display RAM in LC868920A)
Display examples
(1) Display mode control register=01H (LCD: ON)
The total number of horizontal dots=80 (Dn=5)
Divider ratio (Nx)=32
Start address register=1FH
S80 - - - - S73 S72 - - - -S65 S64- - - -S57 S56- - - -S49 S48- - - -S41 S40- - - -S33 S32- - - - -S25 S24- - - -S17 S16- - - -S9
↓
C1 →
↓
↓
MSB (1F0H)
LSB
↓ ↓
MSB (1F1H)
LSB
↓ ↓
MSB (1F2H)
LSB
↓ ↓
MSB (1F3H)
LSB
↓ ↓
MSB (1F4H)
LSB
↓
MSB (1F5H)
LSB
↓
↓
↓
MSB (1F6H)
LSB
↓ ↓
MSB (1F7H)
LSB
S8 - - - - -S1
↓ ↓
MSB (1F8H)
LSB
↓
MSB (1F9H)
LSB
C2 →
MSB (1E0H) LSB MSB (1E1H) LSB MSB (1E2H) LSB MSB (1E3H) LSB MSB (1E4H) LSB MSB (1E5H) LSB MSB (1E6H) LSB MSB (1E7H) LSB MSB (1E8H) LSB MSB (1E9H) LSB
C3 →
MSB (1D0H) LSB MSB (1D1H) LSB MSB (1D2H) LSB MSB (1D3H) LSB MSB (1D4H) LSB MSB (1D5H) LSB MSB (1D6H) LSB MSB (1D7H) LSB MSB (1D8H) LSB MSB (1D9H) LSB
---C28→
MSB (040H) LSB MSB (041H) LSB MSB (042H) LSB MSB (043H) LSB MSB (044H) LSB MSB (045H) LSB MSB (046H) LSB MSB (047H) LSB MSB (048H) LSB MSB (049H) LSB
C29→
MSB (030H) LSB MSB (031H) LSB MSB (032H) LSB MSB (033H) LSB MSB (034H) LSB MSB (035H) LSB MSB (036H) LSB MSB (037H) LSB MSB (038H) LSB MSB (039H) LSB
C30→
MSB (020H) LSB MSB (021H) LSB MSB (022H) LSB MSB (023H) LSB MSB (024H) LSB MSB (025H) LSB MSB (026H) LSB MSB (027H) LSB MSB (028H) LSB MSB (029H) LSB
C31→
MSB (010H) LSB MSB (011H) LSB MSB (012H) LSB MSB (013H) LSB MSB (014H) LSB MSB (015H) LSB MSB (016H) LSB MSB (017H) LSB MSB (018H) LSB MSB (019H) LSB
C32→
MSB (000H) LSB MSB (001H) LSB MSB (002H) LSB MSB (003H) LSB MSB (004H) LSB MSB (005H) LSB MSB (006H) LSB MSB (007H) LSB MSB (008H) LSB MSB (009H) LSB
(2) Display mode control register=01H (LCD: ON)
The total number of horizontal dots=80 (Dn=5)
Divider ratio (Nx)=32
Start address register=1EH
S80 - - - S73
S72 - - - S65 S64 - - - S57 S56 - - - S49
↓
↓
↓
↓ ↓
↓ ↓
S48 - - - S41 S40 - - - S33 S32 - - - S25
↓ ↓
↓ ↓
↓
↓
↓
S24 - - - S17 S16 - - - - S9 S8 - - - - S1
↓
↓ ↓
↓ ↓
↓
C1 →
MSB (1E0H) LSB MSB (1E1H) LSB MSB (1E2H) LSB MSB (1E3H) LSB MSB (1E4H) LSB MSB (1E5H) LSB MSB (1E6H) LSB MSB (1E7H) LSB MSB (1E8H) LSB MSB (1E9H) LSB
C2 →
MSB (1D0H) LSB MSB (1D1H) LSB MSB (1D2H) LSB MSB (1D3H) LSB MSB (1D4H) LSB MSB (1D5H) LSB MSB (1D6H) LSB MSB (1D7H) LSB MSB (1D8H) LSB MSB (1D9H) LSB
C3 →
MSB (1C0H) LSB MSB (1C1H) LSB MSB (1C2H) LSB MSB (1C3H) LSB MSB (1C4H) LSB MSB (1C5H) LSB MSB (1C6H) LSB MSB (1C7H) LSB MSB (1C8H) LSB MSB (1C9H) LSB
---C28→
MSB (030H) LSB MSB (041H) LSB MSB (042H) LSB MSB (043H) LSB MSB (044H) LSB MSB (045H) LSB MSB (046H) LSB MSB (047H) LSB MSB (048H) LSB MSB (049H) LSB
C29→
MSB (020H) LSB MSB (031H) LSB MSB (032H) LSB MSB (033H) LSB MSB (034H) LSB MSB (035H) LSB MSB (036H) LSB MSB (037H) LSB MSB (038H) LSB MSB (039H) LSB
C30→
MSB (010H) LSB MSB (021H) LSB MSB (022H) LSB MSB (023H) LSB MSB (024H) LSB MSB (025H) LSB MSB (026H) LSB MSB (027H) LSB MSB (028H) LSB MSB (029H) LSB
C31→
MSB (000H) LSB MSB (011H) LSB MSB (012H) LSB MSB (013H) LSB MSB (014H) LSB MSB (015H) LSB MSB (016H) LSB MSB (017H) LSB MSB (018H) LSB MSB (019H) LSB
C32→
MSB (7F0H) LSB MSB (7F1H) LSB MSB (7F2H) LSB MSB (7F3H) LSB MSB (7F4H) LSB MSB (7F5H) LSB MSB (7F6H) LSB MSB (7F7H) LSB MSB (7F8H) LSB MSB (7F9H) LSB
No.6703-20/21
LC868920A
(3) Display mode control register=01H (LCD: ON)
The total number of horizontal dots=80 (Dn=5)
Divider ratio (Nx)=16
Start address register=0FH
S80 - - - S73
↓
C1 →
↓
S72 - - - S65 S64 - - - S57 S56 - - - S49
S48 - - - S41 S40 - - - S33 S32 - - - S25
S24 - - - S17 S16 - - - - S9 S8 - - - - - S1
↓
↓
↓
↓
↓
↓ ↓
↓
↓ ↓
↓ ↓
↓
↓ ↓
↓
↓
↓
MSB (0F0H) LSB MSB (0F1H) LSB MSB (0F2H) LSB MSB (0F3H) LSB MSB (0F4H) LSB MSB (0F5H) LSB MSB (0F6H) LSB MSB (0F7H) LSB MSB (0F8H) LSB MSB (0F9H) LSB
C2 →
MSB (0E0H) LSB MSB (0E1H) LSB MSB (0E2H) LSB MSB (0E3H) LSB MSB (0E4H) LSB MSB (0E5H) LSB MSB (0E6H) LSB MSB (0E7H) LSB MSB (0E8H) LSB MSB (0E9H) LSB
C3 →
MSB (0D0H) LSB MSB (0D1H) LSB MSB (0D2H) LSB MSB (0D3H) LSB MSB (0D4H) LSB MSB (0D5H) LSB MSB (0D6H) LSB MSB (0D7H) LSB MSB (0D8H) LSB MSB (0D9H) LSB
---C12→
MSB (040H) LSB MSB (041H) LSB MSB (042H) LSB MSB (043H) LSB MSB (044H) LSB MSB (045H) LSB MSB (046H) LSB MSB (047H) LSB MSB (048H) LSB MSB (049H) LSB
C13→
MSB (030H) LSB MSB (031H) LSB MSB (032H) LSB MSB (033H) LSB MSB (034H) LSB MSB (035H) LSB MSB (036H) LSB MSB (037H) LSB MSB (038H) LSB MSB (039H) LSB
C14→
MSB (020H) LSB MSB (021H) LSB MSB (022H) LSB MSB (023H) LSB MSB (024H) LSB MSB (025H) LSB MSB (026H) LSB MSB (027H) LSB MSB (028H) LSB MSB (029H) LSB
C15→
MSB (010H) LSB MSB (011H) LSB MSB (012H) LSB MSB (013H) LSB MSB (014H) LSB MSB (015H) LSB MSB (016H) LSB MSB (017H) LSB MSB (018H) LSB MSB (019H) LSB
C16→
MSB (000H) LSB MSB (001H) LSB MSB (002H) LSB MSB (003H) LSB MSB (004H) LSB MSB (005H) LSB MSB (006H) LSB MSB (007H) LSB MSB (008H) LSB MSB (009H) LSB
(4) Display mode control register=01H (LCD: ON)
The total number of horizontal dots=64 (Dn=4)
Divider ratio (Nx)=16
Start address register=1FH
S64 - - - S57
↓
C1 →
S56 - - - S49 S48 - - - S41 S40 - - - S33
↓ ↓
↓ ↓
↓ ↓
↓
S32 - - - S25 S24 - - - S17 S16 - - - - S9
↓
↓
↓
↓ ↓
S8 - - - - S1
↓ ↓
↓
MSB (1F0H) LSB MSB (1F1H) LSB MSB (1F2H) LSB MSB (1F3H) LSB MSB (1F4H) LSB MSB (1F5H) LSB MSB (1F6H) LSB MSB (1F7H) LSB
C2 →
MSB (1E0H) LSB MSB (1E1H) LSB MSB (1E2H) LSB MSB (1E3H) LSB MSB (1E4H) LSB MSB (1E5H) LSB MSB (1E6H) LSB MSB (1E7H) LSB
C3 →
MSB (1D0H) LSB MSB (1D1H) LSB MSB (1D2H) LSB MSB (1D3H) LSB MSB (1D4H) LSB MSB (1D5H) LSB MSB (1D6H) LSB MSB (1D7H) LSB
---C12→
MSB (140H) LSB MSB (141H) LSB MSB (142H) LSB MSB (143H) LSB MSB (144H) LSB MSB (145H) LSB MSB (146H) LSB MSB (147H) LSB
C13→
MSB (130H) LSB MSB (131H) LSB MSB (132H) LSB MSB (133H) LSB MSB (134H) LSB MSB (135H) LSB MSB (136H) LSB MSB (137H) LSB
C14→
MSB (120H) LSB MSB (121H) LSB MSB (122H) LSB MSB (123H) LSB MSB (124H) LSB MSB (125H) LSB MSB (126H) LSB MSB (127H) LSB
C15→
MSB (110H) LSB MSB (111H) LSB MSB (112H) LSB MSB (113H) LSB MSB (114H) LSB MSB (115H) LSB MSB (116H) LSB MSB (117H) LSB
C16→
MSB (100H) LSB MSB (101H) LSB MSB (102H) LSB MSB (103H) LSB MSB (104H) LSB MSB (105H) LSB MSB (106H) LSB MSB (107H) LSB
PS No.6703-21/21