NEC UPD161622

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD161622
396 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM
DESCRIPTION
The µ PD161622 is a TFT-LCD source driver that includes display RAM.
This driver has 396 outputs, a display RAM capacity of 371,712 bits (132 pixels x 16 bits x 176 lines) and, can
provide a 65,536-color display.
FEATURES
• TFT-LCD driver with on-chip display RAM
• Logic power supply voltage: 2.5 to 3.6 V
• Driver power supply voltage: 4.3 to 5.5 V
• Display RAM: 132 x 16 x 176 bits
• Driver outputs: 396 output
• CPU interface: Serial, 8-bit/16-bit parallel interface selectable
• Colors: 65,536 colors/pixel
• On-chip VCOM generator
• On-chip timing generator
• On-chip oscillator
ORDERING INFORMATION
Part Number
Package
µ PD161622P
Chip
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15649EJ2V0DS00 (2nd edition)
Date Published August 2003 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001
µ PD161622
S395 S396
LCD drive circuit
VRL1
VRL2
S1 S2 S3 S4
V0 to V5
VRH
VSS
VS
VCC1
VCC2
1. BLOCK DIAGRAM
Gray scale generator
CVPH
CVPL
CVNH
CVNL
Decoder
Level shifter (2.5 V
5 V)
Display data latch
LCD timing control
Display data RAM
(132 x 16 x 176 bits)
Calibrator
Oscillator
OSCIN
OSCOUT
RSEL
Arbiter
BGR
BGRIN
Internal
timing
generator
Command
decoder
D/A converter
Address
decoder /
controller
Data
register
Remark
2
PS control
/xxx indicates active low signal.
Data Sheet S15649EJ2V0DS
VCOM
VCOUT1
VCOUT2
Gate control
LPMP
DCON
VCD11
VCD12
VCD2
VCE
RGONP
PSX
/CS
/RESET
/RD(E)
/WR(R, /W)
C86
D8 to D15
D7 (SI)
D6 (SCL)
D0 to D5
RS
IP0 to IP3
OP0 to OP7
CSTB
TOUT0 to
TOUT15
TSTx
TOSCx
TBSELx
TBGR
I/O buffer
LPMG
GOE1
GOE2
GSTB
GCLK
RGONG
VCOM generator
DAC0 to
DAC7
VCOMR
FBRSEL
µ PD161622
2. PIN CONFIGURATION (Pad Layout)
Chip size: 3.60 x 17.80 mm2 TYP.
Bump size (output type A): 35 x 94 µm2 TYP.
2
Bump size (input & dummy): 80 x 86 µm TYP.
Alignment mark (mark center, unit: µm)
X
Y
M1
−1615
8715
M2
−1615
−8715
M3
1435
−8715
562
Alignment mark reference (unit: µm)
559
558
204
72
60
72
1
60
72
41.5 µm
204
Y(+
X(+
130 µm
41.5 µm
72
146
141
142
145
Data Sheet S15649EJ2V0DS
3
µ PD161622
Table 2–1. Pad Layout (1/4)
PinNo.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
4
PinName PadType
DUMMY
B
DUMMY
B
DUMMY
B
TOUT15
B
TOUT14
B
TOUT13
B
TOUT12
B
TOUT11
B
TOUT10
B
TOUT9
B
TOUT8
B
TOUT7
B
TOUT6
B
TOUT5
B
TOUT4
B
TOUT3
B
TOUT2
B
TOUT1
B
TOUT0
B
VSS(MODE)
B
TSTVIHL
B
TSTRTST
B
TOSCSELO
B
TOSCSELI
B
TOSCI
B
TOSCO
B
VCC1(MODE B
RSEL
B
VSS(MODE)
B
OSCOUT
B
VSS(MODE)
B
OSCIN
B
VSS(MODE)
B
CSTB
B
D15
B
D14
B
D13
B
D12
B
D11
B
D10
B
D9
B
D8
B
D7(SI)
B
D6(SCL)
B
D5
B
D4
B
D3
B
D2
B
D1
B
D0
B
VSS(MODE)
B
/CS
B
/RESET
B
RS
B
/WR(R,/W)
B
/RD(E)
B
VCC2
B
PSX
B
C86
B
VSS(MODE) B
X[µm]
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
Y[µm]
8390.00
8270.00
8150.00
8030.00
7910.00
7790.00
7670.00
7550.00
7430.00
7310.00
7190.00
7070.00
6950.00
6830.00
6710.00
6590.00
6470.00
6350.00
6230.00
6110.00
5990.00
5870.00
5750.00
5630.00
5510.00
5390.00
5270.00
5150.00
5030.00
4910.00
4790.00
4670.00
4550.00
4430.00
4310.00
4190.00
4070.00
3950.00
3830.00
3710.00
3590.00
3470.00
3350.00
3230.00
3110.00
2990.00
2870.00
2750.00
2630.00
2510.00
2390.00
2270.00
2150.00
2030.00
1910.00
1790.00
1670.00
1550.00
1430.00
1310.00
PinNo.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PinName PadType
VCE
B
VCD2
B
VCD12
B
VCD11
B
LPMP
B
RGONP
B
DCON
B
VCOUT2
B
VSS
B
VCC2
B
VCC1
B
VSS
B
VSS
B
CVNL
B
CVNH
B
CVPL
B
CVPH
B
VS
B
VS
B
VSS
B
VCOUT1
B
VCOUT1
B
VCC1
B
VCC1
B
VCOM
B
DUMMY
B
DUMMY
B
VSS(MODE)
B
VCOMR
B
BGRIN
B
VCC1(MODE B
FBRSEL
B
VSS(MODE)
B
VRH
B
V0
B
V1
B
V2
B
V3
B
V4
B
V5
B
VRL1
B
VRL2
B
VSS(MODE)
B
TBSEL1
B
TBSEL2
B
TBGR
B
DAC7
B
DAC6
B
DAC5
B
DAC4
B
DAC3
B
DAC2
B
DAC1
B
DAC0
B
VSS(MODE)
B
OP0
B
OP1
B
OP2
B
OP3
B
OP4
B
X[µm]
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
Y[µm]
1190.00
1070.00
950.00
830.00
710.00
590.00
470.00
350.00
230.00
110.00
-10.00
-130.00
-250.00
-370.00
-490.00
-610.00
-730.00
-850.00
-970.00
-1090.00
-1210.00
-1330.00
-1450.00
-1570.00
-1690.00
-1810.00
-1930.00
-2050.00
-2170.00
-2290.00
-2410.00
-2530.00
-2650.00
-2770.00
-2890.00
-3010.00
-3130.00
-3250.00
-3370.00
-3490.00
-3610.00
-3730.00
-3850.00
-3970.00
-4090.00
-4210.00
-4330.00
-4450.00
-4570.00
-4690.00
-4810.00
-4930.00
-5050.00
-5170.00
-5290.00
-5410.00
-5530.00
-5650.00
-5770.00
-5890.00
Data Sheet S15649EJ2V0DS
PinNo.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
PinName PadType
OP5
B
OP6
B
OP7
B
VCC1(MODE B
IP0
B
VSS(MODE)
B
IP1
B
VCC1(MODE B
IP2
B
VSS(MODE)
B
IP3
B
VCC1(MODE B
GSTB
B
GCLK
B
GOE1
B
GOE2
B
RGONG
B
LPMG
B
DUMMY
B
DUMMY
B
DUMMY
B
DUMMY
B
DUMMY
B
DUMMY
B
DUMMY
B
DUMMY
B
DUMMY
A
DUMMY
A
S396
A
S395
A
S394
A
S393
A
S392
A
S391
A
S390
A
S389
A
S388
A
S387
A
S386
A
S385
A
S384
A
S383
A
S382
A
S381
A
S380
A
S379
A
S378
A
S377
A
S376
A
S375
A
S374
A
S373
A
S372
A
S371
A
S370
A
S369
A
S368
A
S367
A
S366
A
S365
A
X[µm]
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1674.00
-1350.00
-510.00
330.00
1170.00
1670.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
Y[µm]
-6010.00
-6130.00
-6250.00
-6370.00
-6490.00
-6610.00
-6730.00
-6850.00
-6970.00
-7090.00
-7210.00
-7330.00
-7450.00
-7570.00
-7690.00
-7810.00
-7930.00
-8050.00
-8170.00
-8290.00
-8410.00
-8774.00
-8774.00
-8774.00
-8774.00
-8600.00
-8520.00
-8478.50
-8437.00
-8395.50
-8354.00
-8312.50
-8271.00
-8229.50
-8188.00
-8146.50
-8105.00
-8063.50
-8022.00
-7980.50
-7939.00
-7897.50
-7856.00
-7814.50
-7773.00
-7731.50
-7690.00
-7648.50
-7607.00
-7565.50
-7524.00
-7482.50
-7441.00
-7399.50
-7358.00
-7316.50
-7275.00
-7233.50
-7192.00
-7150.50
µ PD161622
Table 2–1. Pad Layout (2/4)
PinNo.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
PinName
S364
S363
S362
S361
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
S308
S307
S306
S305
PadType
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X[µm]
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
Y[µm]
-7109.00
-7067.50
-7026.00
-6984.50
-6943.00
-6901.50
-6860.00
-6818.50
-6777.00
-6735.50
-6694.00
-6652.50
-6611.00
-6569.50
-6528.00
-6486.50
-6445.00
-6403.50
-6362.00
-6320.50
-6279.00
-6237.50
-6196.00
-6154.50
-6113.00
-6071.50
-6030.00
-5988.50
-5947.00
-5905.50
-5864.00
-5822.50
-5781.00
-5739.50
-5698.00
-5656.50
-5615.00
-5573.50
-5532.00
-5490.50
-5449.00
-5407.50
-5366.00
-5324.50
-5283.00
-5241.50
-5200.00
-5158.50
-5117.00
-5075.50
-5034.00
-4992.50
-4951.00
-4909.50
-4868.00
-4826.50
-4785.00
-4743.50
-4702.00
-4660.50
PinNo.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
PinName
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
PadType
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X[µm]
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
Data Sheet S15649EJ2V0DS
Y[µm]
-4619.00
-4577.50
-4536.00
-4494.50
-4453.00
-4411.50
-4370.00
-4328.50
-4287.00
-4245.50
-4204.00
-4162.50
-4121.00
-4079.50
-4038.00
-3996.50
-3955.00
-3913.50
-3872.00
-3830.50
-3789.00
-3747.50
-3706.00
-3664.50
-3623.00
-3581.50
-3540.00
-3498.50
-3457.00
-3415.50
-3374.00
-3332.50
-3291.00
-3249.50
-3208.00
-3166.50
-3125.00
-3083.50
-3042.00
-3000.50
-2959.00
-2917.50
-2876.00
-2834.50
-2793.00
-2751.50
-2710.00
-2668.50
-2627.00
-2585.50
-2544.00
-2502.50
-2461.00
-2419.50
-2378.00
-2336.50
-2295.00
-2253.50
-2212.00
-2170.50
PinNo.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
PinName
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
S198
S197
S196
S195
S194
S193
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
PadType
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X[µm]
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
Y[µm]
-2129.00
-2087.50
-2046.00
-2004.50
-1963.00
-1921.50
-1880.00
-1838.50
-1797.00
-1755.50
-1714.00
-1672.50
-1631.00
-1589.50
-1548.00
-1506.50
-1465.00
-1423.50
-1382.00
-1340.50
-1299.00
-1257.50
-1216.00
-1174.50
-1133.00
-1091.50
-1050.00
-1008.50
-967.00
-925.50
-884.00
-842.50
-801.00
-759.50
-718.00
-676.50
-635.00
-593.50
-552.00
-510.50
-469.00
-427.50
-386.00
-344.50
-303.00
-261.50
-220.00
-178.50
-137.00
-95.50
-54.00
-12.50
29.00
70.50
112.00
153.50
195.00
236.50
278.00
319.50
5
µ PD161622
Table 2–1. Pad Layout (3/4)
PinNo.
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
6
PinName
DUMMY
DUMMY
DUMMY
DUMMY
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
PadType
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X[µm]
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
Y[µm]
361.00
402.50
444.00
485.50
527.00
568.50
610.00
651.50
693.00
734.50
776.00
817.50
859.00
900.50
942.00
983.50
1025.00
1066.50
1108.00
1149.50
1191.00
1232.50
1274.00
1315.50
1357.00
1398.50
1440.00
1481.50
1523.00
1564.50
1606.00
1647.50
1689.00
1730.50
1772.00
1813.50
1855.00
1896.50
1938.00
1979.50
2021.00
2062.50
2104.00
2145.50
2187.00
2228.50
2270.00
2311.50
2353.00
2394.50
2436.00
2477.50
2519.00
2560.50
2602.00
2643.50
2685.00
2726.50
2768.00
2809.50
PinNo.
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
PinName
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
PadType
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X[µm]
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
Data Sheet S15649EJ2V0DS
Y[µm]
2851.00
2892.50
2934.00
2975.50
3017.00
3058.50
3100.00
3141.50
3183.00
3224.50
3266.00
3307.50
3349.00
3390.50
3432.00
3473.50
3515.00
3556.50
3598.00
3639.50
3681.00
3722.50
3764.00
3805.50
3847.00
3888.50
3930.00
3971.50
4013.00
4054.50
4096.00
4137.50
4179.00
4220.50
4262.00
4303.50
4345.00
4386.50
4428.00
4469.50
4511.00
4552.50
4594.00
4635.50
4677.00
4718.50
4760.00
4801.50
4843.00
4884.50
4926.00
4967.50
5009.00
5050.50
5092.00
5133.50
5175.00
5216.50
5258.00
5299.50
PinNo.
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
PinName
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
PadType
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X[µm]
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
Y[µm]
5341.00
5382.50
5424.00
5465.50
5507.00
5548.50
5590.00
5631.50
5673.00
5714.50
5756.00
5797.50
5839.00
5880.50
5922.00
5963.50
6005.00
6046.50
6088.00
6129.50
6171.00
6212.50
6254.00
6295.50
6337.00
6378.50
6420.00
6461.50
6503.00
6544.50
6586.00
6627.50
6669.00
6710.50
6752.00
6793.50
6835.00
6876.50
6918.00
6959.50
7001.00
7042.50
7084.00
7125.50
7167.00
7208.50
7250.00
7291.50
7333.00
7374.50
7416.00
7457.50
7499.00
7540.50
7582.00
7623.50
7665.00
7706.50
7748.00
7789.50
µ PD161622
Table 2–1. Pad Layout (4/4)
PinNo.
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
PinName
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
PadType
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
X[µm]
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1540.00
1670.00
1670.00
1220.00
380.00
-460.00
-1300.00
Data Sheet S15649EJ2V0DS
Y[µm]
7831.00
7872.50
7914.00
7955.50
7997.00
8038.50
8080.00
8121.50
8163.00
8204.50
8246.00
8287.50
8329.00
8370.50
8412.00
8453.50
8495.00
8575.00
8774.00
8774.00
8774.00
8774.00
7
µ PD161622
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Symbol
VCC1
Pin Name
Logic power supply
Pad No.
I/O
Function
71, 83, 84
−
Power supply pin for logic circuit
VCC2
I/O power supply
57, 70
−
Power supply pin for I/O buffer
VS
Driver power supply
78, 79
−
Power supply pin for driver circuit
Ground pin for logic and driver circuits
VSS
Ground
69, 72, 72, 80
−
V0 to V5
Power supply for
γ-curve correction
95 to 100,
−
VRH
VRL1, VRL2
The µ PD161622 includes power supplies and resistors for the γ-curve, so
94,
if the characteristics of the γ-curve and LCD panel in the µ PD161622
101, 102
match, leave V0 to V5, VRH, VRL1, VRL2 open.
If some kind of correction is required, adjust the γ-curve by connecting
resistors between the V0 to V5, VRH, VRL1, VRL2 pins (see 5.9 γ -Curve
Correction Power Supply Circuit for Cases of Unbalanced Driving).
VCC1(MODE) Mode setting pull-up
VSS(MODE)
27, 91, 124,
power-supply
128, 132
Mode setting pull-down
20, 29, 31, 33, 51,
power-supply
60, 88, 93, 103,
−
Pull-up power-supply pin for mode setting
−
Pull-down power-supply pin for mode setting
115, 126, 130
3.2 Logic System Pins
Symbol
PSX
Pin Name
CPU interface selection
(1/2)
Pad No.
58
I/O
Function
Input These pins are used to select the CPU interface mode.
PSX = H: Parallel interface
PSX = L: Serial interface
When the parallel interface is selected, this data but width can be changed
/CS
Chip select
52
between 8 bits and 16 bits by using BMD of index register 5 (R5).
Input This pin is used for chip select signals. When /CS = L, the chip is active
and can perform data input/output operations including command and data
I/O.
/RESET
Reset
53
Input When /RESET is low, an internal reset is performed. The reset operation
is executed at the /RESET signal level. Be sure to perform reset via this
pin at power application.
/RD
Read
(E)
(enable)
56
Input When i80 series parallel data transfer (/RD) has been selected, the signal
at this pin is used to enable read operations. Data is output to the data bus
only when this pin is low.
When M68 series parallel data transfer (E) has been selected, the signal at
this pin is used to enable read/write operations.
/WR
Write
(R, /W)
(read/write)
55
Input When i80 series parallel data transfer (/WR) has been selected, the signal
at this pin is used to enable write operations. Data is written at the rising
edge of this signal.
When M68 series parallel data transfer (R, /W) and serial data has been
selected, this pin is used to determine the direction of data transfer.
L: Write
H: Read
C86
Select interface
59
Input This pin is used to switch between interface modes (i80 series CPU or M68
series CPU).
L: Selects i80 series CPU mode
H: Selects M68 series CPU mode
8
Data Sheet S15649EJ2V0DS
µ PD161622
(2/2)
Symbol
D0 to D5,
Pin Name
Data bus
Pad No.
50 to 35
I/O
I/O
D8 to D15,
Function
These pins comprise 16-bit bi-directional data.
When the serial interface has been selected (PSX = L), D7 functions as
D6 (SCL),
(serial clock)
a serial data input pin (SI), D6 functions as a serial clock input pin (SCL).
D7 (SI)
(serial data input)
In either case, pins D0 to D7 and D8 to D15 are in high impedance mode.
RS
Index register/,
When the chip is not selected, D0 to D15 are in high impedance mode.
54
Input
data/command selection
When parallel data transfer has been selected, this pin is usually
connected to the least significant bit of the standard CPU address bus
and is used to distinguish between data from index registers and
data/commands.
RS = H: Indicates that data from D0 to D15 is data/command
RS = L: Indicates that data from D0 to D7 is index register contents
Also, when serial data transfer is selected, the level of the RS pin is
fetched at the rising edge of the eighth clock of the serial clock and
whether the data is index register contents or data/command is
distinguished.
RS = H: Indicates that the data input to SI is data/command.
RS = L: Indicates that the data input to SI is index register contents.
IP0 to IP3
Input port
125, 127,
Input
This is a general-purpose input port. The status of these pins (H or L)
can be read via a command.
129, 131
Because this is a CMOS input, do not leave open.
OP0 to
Output port
116 to 123
Output
This is a general-purpose output port. The status of these pins (H or L)
can be write via a command.
OP7
Leave open when in unused.
RSEL
Oscillation signal select
28
Input
This pin is for oscillation signal selection. When in used external
resistance connection oscillator circuit, this pin set H. When in used
internal oscillator circuit, this pin set L.
RSEL = H: External resistance connection oscillator circuit select
RSEL = L: CR internal oscillator circuit select
OSCIN
Oscillation signal
32
Input
This pin is for oscillation signal input.
RSEL = H: Connect 51 kΩ resistance between OSCIN and OSCOUT.
RSEL = L: Leave open
OSCOUT
Oscillation signal
30
Output
This pin is for oscillation signal input.
RSEL = H: Connect 51 kΩ resistance between OSCIN and OSCOUT.
RSEL = L: Leave open
CSTB
GSTB logic signal
34
Output
This pin outputs STB signal for gate driver leveled by interface power
supply voltage (VCC2). This output signal is reverse signal of GSTB.
Data Sheet S15649EJ2V0DS
9
µ PD161622
3.3 Gate Driver IC Control Pins
Symbol
LPMG
Pin Name
Low power mode signal
Pad No.
138
I/O
Function
Output This is an output pin for low power mode (for the gate driver).
GOE1
OE1 output for gate
135
Output This pin is an output pin for the low power mode (for the OE1).
Connect to the LPM pin of the gate driver.
driver
Connect to the OE1 pin of the gate driver.
Timing signal for output, refer to 5.4 Display timing generator.
GOE2
OE2 output for gate
136
Output This pin is the OE2 output for the gate driver.
Connect to the OE2 pin of the gate driver.
driver
Timing signal for output, refer to 5.4 Display timing generator.
GSTB
STB output for gate
133
Output This pin is the STB output for the gate driver.
driver
Connect to the STVR or STVL pin of the gate driver.
Timing signal for output, refer to 5.4 Display timing generator.
GCLK
CLK output for gate
134
Output This pin is the CLK output for the gate driver.
137
Output Regulator ON/OFF control of gate driver IC
driver
RGONG
Connect to the CLK pin of the gate driver.
Regulator control
Connect to the RGONG pin of the gate driver.
3.4 Power Supply Control Pins
Symbol
LPMP
Pin Name
Low power mode signal
Pad No.
65
I/O
Function
Output Low power mode control signal output pin (for power-supply IC).
This pin connects to LPM pin of power-supply IC.
DCON
DC/DC converter control 67
Output DC/DC converter ON/OFF signal pin for power-supply IC.
This pin connects DCON pin of power-supply IC.
RGONP
Regulator control
66
Output
Regulator ON/OFF control signal pin for power-supply IC.
VCD11, VCD12
VDD1 booster selection
64, 63
Output Control signal to select x4/x5/x6/x7 booster of power-supply IC for VCC1.
VCD2
VDD2 booster selection
62
Output Control signal to select x2/x3 booster of power-supply IC for VCC2.
This pin connects to RGONP pin of power-supply IC.
Connect to the VCD11 and VCD12 pins of the power-supply IC.
Connect to the VCD2 pin of the power-supply IC.
VCE
VO level selection
61
Output
Signal for selecting the level of the power-supply IC booster voltage, to
be used for the maximum voltage of VO. Selects that the booster
voltage level is either the same level as VDD1 or a multiple of minus 1.
Connect to the VCE pin of the power-supply IC.
10
Data Sheet S15649EJ2V0DS
µ PD161622
3.5 Driver-Related Pins
Symbol
S1 to S396
Pin Name
Source output
Pad No.
556 to 365,
I/O
Function
Output Source output pins
352 to 149
VCOM
COM adjustment
85
Output This pin is the common adjustment output.
VCOUT1
Center rectangle
81, 82
Output This pin is the center rectangle signal output (Vp-p) for common
modulation between 0 V to VS.
signal output
VCOUT2
Center rectangle
68
Output This pin is the center rectangle signal output (Vp-p) for common
modulation between 0 V to VCC1.
signal output
BGRIN
External-power-
90
Input
supply connect
This is an external-power-supply connect pin for VCOM.
This pin is valid when BGRS (power supply control register 1: R25) =
1. In this case, the reference voltage of the amplifier for setting the
common waveform center value is input from outside the µPD161622
When BGRS = 0, power supply with built-in the µPD161622 is set up
as a standard voltage for common waveform center value setup.
In this case, leave it open.
For more detail, refer to 5.5 Common Adjustment.
VCOMR
VCOM setting
89
Input
Connects an external feedback resistor for VCOM setting.
This pin is valid when FBRSEL = L. In this case, connect a feedback
resistor connection
resistor between the VCOM pin and GND.
When FBRSEL = H, the amplifier for setting the common waveform
center value operates as a voltage follower. In this case, leave it open.
For more detail, refer to 5.5 Common Adjustment.
FBRSEL
VCOM setting
92
Input
external circuit select
This pin is used to select the method of adjusting the amplifier for
setting the common waveform center value used to set the COMMON
drive waveform center level.
FBRSEL = H: Voltage follower circuit used (VCOMR connected to VCOM
internally)
FBRSEL = L: External feedback resistor used
CVPH,
Basis power supply
77,
CVPL,
for γ -corrected
76,
power supplies
75,
CVNH,
This is operational amplifier output pin for the γ -corrected power
supplies. Normally, this pin connects capacitor of 1 µF
74
CVNL
DAC0 to DAC7
−
D/A converter
value setting
114 to 107
Input
These pins set the reference voltage of the amplifier for setting the
VCOM value used to set the COMMON drive waveform center level.
These pins are valid when the VCOM output center value setting
register (R29) = 00H and BGRS (R25: D6) = 0.
This pin is pulled up to the inside IC, therefore, connect to only VSS
when in low level setting pin.
For more details, refer to 5.5 Common Adjustment Circuit.
Data Sheet S15649EJ2V0DS
11
µ PD161622
3.6 Test or Other Pins
Symbol
TOUT0 to TOUT15,
Pin Name
Source output
TOSCO
TSTRTST,
Pad No.
26
COM adjustment
21,
TOSCI,
25,
TOSCSELI,
24,
TOSCSELO,
23,
TBSEL1,
104,
TBSEL2
105
Test input/output
Function
Normally, leave it open.
Output These pins are to set up test mode of µ PD161622.
22,
TSTVIHL,
TBGR
I/O
Output This is output pin when µ PD161622 is in test mode.
19 to 4,
Normally, fixed it to VSS.
106
I/O
This is output pin when µ PD161622 is in test mode.
Normally, leave it open.
DUMMY
Dummy pin
1 to 3, 86, 87, 139
−
Dummy pin
to 148, 353 to 364,
The dummy pins of pads No. 1, 2, 557, and 558 are wired using
557 to 562
aluminum inside the µ PD161622.
The dummy pins of pads No. 140, 141, 146, and 147 are wired
using aluminum inside the µ PD161622.
12
Data Sheet S15649EJ2V0DS
µ PD161622
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit types of each pin and recommended connection of unused pins are described below.
Power
supply
Input Type
I/O
PSX
Schmitt trigger
Input
VCC2
Recommended Connection of Unused Pins
Parallel Interface
Serial Interface
Mode setting pin
/RESET
Schmitt trigger
Input
VCC2
Always reset on power application
−
/RD (E)
Schmitt trigger
Input
VCC2
C86
Schmitt trigger
Input
VCC2
Connect to VCC2
(when i80 series interface)
Mode setting pin
−
D0 to D5
D6 (SCL)
D7 (SI)
D8 to D15
RS
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
I/O
I/O
Input
VCC2
VCC2
VCC2
VCC2
VCC2
−
−
−
−
Register setting pin
Pin Name
I/O
I/O
Connect to VCC2 or VSS.
Notes
1
Connect to VCC2 or VSS.
1
Leave open
−
−
−
−
2
Leave open
Input
VCC1
Connect to VCC1 or VSS.
−
Output
VCC1
Leave open
−
CMOS
Input
VCC2
−
OSCOUT
CMOS
Output
VCC2
Input external clock (RSEL = H)
Leave open (RSEL = L)
Leave open (RSEL = H/L)
CSTB
−
Output
VCC2
Leave open
−
RSEL
Schmitt trigger
IP0 to IP3
Schmitt trigger
OP0 to OP7
−
OSCIN
−
Input
VCC1
Mode setting pin
3
VCC1
Leave open
−
LPMG
−
Output
GOE1
−
Output
VCC1
Always connect to the gate driver
−
GOE2
−
Output
VCC1
Always connect to the gate driver
−
GSTB
−
Output
VCC1
Always connect to the gate driver
−
GCLK
−
Output
VCC1
Always connect to the gate driver
−
RGONG
−
Output
VCC1
Always connect to the gate driver
−
LPMP
−
Output
VCC1
Leave open
−
DCON
−
Output
VCC1
Always connect to the power IC
−
RGONP
−
Output
VCC1
Always connect to the power IC
−
VCD11, VCD12
−
Output
VCC1
Always connect to the power IC
−
VCD2
VCE
−
Output
VCC1
Always connect to the power IC
−
−
Output
VCC1
Always connect to the power IC
−
VCOUT1
VCOUT2
BGRIN
−
−
−
Output
VS
VCC1
VS
Leave open
Leave open
Leave open (BGRS = L [R25])
−
−
−
VCOM
VCOMR
TOUT0 to TOUT15
TOSCO
TSTRTST
−
−
−
−
−
Output
Output
Input
VS
VS
VCC1
VCC1
VCC1
Leave open (FRBSEL = H)
Leave open (FRBSEL = H)
Leave open
Leave open
Connect to VSS.
−
−
−
−
−
TSTVIHL
−
Input
VCC1
Connect to VSS.
−
TOSCI
−
Input
VCC1
Connect to VSS.
−
TOSCSELI
−
Input
VCC1
Connect to VSS.
−
TOSCSELO
−
Input
VCC1
Connect to VSS.
−
TBSEL1
−
Input
VCC1
Connect to VSS.
−
TBSEL2
−
Input
VCC1
Connect to VSS.
−
TBGR
−
I/O
VCC1
Leave open
−
Output
Input
Input
Output
Notes 1. Connect to VCC2 or VSS, depending on the mode selected.
2. Input either H or L by CPU, depending on the register selected
3. Connect to VCC1 or VSS, depending on the mode selected.
Data Sheet S15649EJ2V0DS
13
µ PD161622
5. DESCRIPTION OF FUNCTIONS
5.1 CPU Interface
5.1.1 Selection of interface type
The µ PD161622 chip transfers data using a 16-bit bi-directional data bus (D15 to D0), 8-bit bi-directional data bus (D7
to D0) or a serial data input (SI). Setting the polarity of the PSX pin as either H or L enables the selections shown in
table 5–1 below.
Table 5–1.
PSX
BMD
Mode
/CS
RS
/RD (E)
/WR (R,/W)
C86
D15 to D8
D7
D6
D5 to D0
H
0
16-bit parallel
/CS
RS
/RD (E)
/WR (R,/W)
C86
D15 to D8
D7
D6
D5 to D0
D7
D6
D5 to D0
SI
SCL
H
L
1
X
8-bit parallel
Note2
Serial
Note3
Note1
/CS
RS
/RD (E)
/WR (R,/W)
C86
Hi-Z
/CS
RS
Note2
Note2
Note2
Hi-Z
Note1
Note1
Hi-Z
Notes 1. Hi-Z: High impedance
2. X: Don’t care (1 or 0)
3. In serial mode, read function is not available.
5.1.2 Parallel interface
When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct
connection to an i80 series or M68 series CPU (see table 5–2 below).
Table 5–2.
C86
Mode
/RD (E)
/WR (R,/W)
H
L
M68 series CPU
E
R, /W
i80 series CPU
/RD
/WR
The data bus signal is identified according to the combination of the RS, /RD (E), and /WR (R, /W) signals, as shown
in the following table 5–3.
Table 5–3.
14
Common
M68 series CPU
i80 series CPU
RS
R, /W
/RD
/WR
H
H
L
H
Read display data and registers
H
L
H
L
Write display data and registers
L
H
L
H
Prohibited
L
L
H
L
Write to control index register
Data Sheet S15649EJ2V0DS
Function
µ PD161622
Moreover, when using the parallel interface, it is possible to use the BMD flag (D7 of the data access control register
(R5) to select the length of the data to be transmitted as either 16 bits (BMD = 0) or 8 bits (BMD = 1). This setting is
valid for the display data written as DR data to the display memory register (R12).
The relationship between the command input and the data bus length is as follows.
⋅ Commands other than those of the display memory register (R12) are executed in 1-byte units regardless of
the value of BMD (bus length setting flag in data access control register (R5)).
⋅ Display memory register (R12) commands are executed in 1-byte units when BMD = 1, and in 1-word units
when BMD = 0.
(1) Commands other than those of the display memory register (R12)
BMD = 1 (8-bit data bus)
Pin
D7
D6
D5
D4
D3
D2
D1
D0
Data
D7
D6
D5
D4
D3
D2
D1
D0
BMD = 0 (16-bit data bus)
Pin
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data
Note
Note
Note
Note
Note
Note
Note
Note
D7
D6
D5
D4
D3
D2
D1
D0
Note 0 or 1
(2) Display memory register (R12)
BMD = 1 (8-bit data bus)
Pin
D7
D6
D5
D4
D3
D2
D1
D0
Data
D7
D6
D5
D4
D3
D2
D1
D0
BMD = 0 (16-bit data bus)
Pin
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Sheet S15649EJ2V0DS
15
µ PD161622
Relationship data bus and display RAM (16-bit parallel interface: BMD = 0)
Data bus side
16 bit
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Dot 1
Dot 2
Dot 3
1 pixel (= 1X address)
Display RAM side
Relationship data bus and display RAM (18-bit parallel interface: BMD = 1)
Data bus side
8 bit (1st byte)
DB7
DB6
D15
D14
8 bit (2nd byte)
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
Dot 1
Dot 2
1 pixel (= 1X address)
Display RAM side
16
Data Sheet S15649EJ2V0DS
DB2
DB1
DB0
D2
D1
D0
Dot 3
µ PD161622
Figure 5−1. Example of 16-bit Data Access (i80 series interface, BMD = 0)
/CS
RS
/WR
Invalid
Invalid
Invalid
D15
D15
Invalid
Invalid
Invalid
D14
D14
Invalid
Invalid
Invalid
D13
D13
Invalid
Invalid
Invalid
D8
D8
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
1st word (IR)
2nd word (DR)
D15
D14
D13
D8
D5
1st word (IR)
Registers other than Display memory register (R12)
2nd word (DR)
3rd word (DR)
Display memory register (R12)
Figure 5−2. Example of 8-bit Data Access (i80 series interface, BMD = 1)
/CS
RS
/WR
D7
D7
D7
D15
D7
D15
D6
D6
D6
D6
D14
D6
D14
D5
D5
D5
D5
D13
D5
D13
D15
D1
D0
D1
D0
1st byte (IR)
D1
D9
D1
D1
D0
D0
D8
D0
2nd byte (DR)
1st byte (IR)
2nd byte (DR)
3rd byte (DR)
1st pixel date
Registers other than Display memory register (R12)
D9
D8
4th byte (DR)
2nd pixel date
Display memory register (R12)
Data Sheet S15649EJ2V0DS
17
µ PD161622
(1) i80 Series Parallel Interface
When i80 series parallel data transfer has been selected, data is written to the µ PD161622 at the rising edge of the
/WR signal. The data is output to the data bus when the /RD signal is L.
Figure 5–3. i80 Series Interface Data Bus Status
/CS
/WR
/RD
Hi-Z
Hi-Z
Valid data
DBn
Data write
Data read
(2) M68 Series Parallel Interface
When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the
R,/W signal is L. In a data read operation, data is output at the rising edge of the E signal in a period when the R,/W
signal is H. The data bus is released (Hi-Z) at the falling edge of the E signal.
Figure 5–4. M68 Series Interface Data Bus Status (when data read)
/CS
R,/W
E
Hi-Z
Hi-Z
DBn
18
Hi-Z
Valid data
Data Sheet S15649EJ2V0DS
µ PD161622
5.1.3 Serial interface
When the serial interface has been selected (PSX = L), if the chip is active (/CS = L), serial data input (SI) and serial
clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial
clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted
to parallel data for processing.
RS input is used to judge serial input data as display data or command data when RS = H the data is display data
and when RS = L the data is command data. When the chip enters active mode, RS input is read at the rising edge
after every eighth serial clock and is then used to judge the serial input data. The serial interface signal chart is
shown below.
Figure 5–5. Serial Interface Signal Chart
/CS
SI
SCL
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RS
Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.
2. The data read function is disabled during serial interface mode.
3. When using SCL wiring, take care concerning the possible effects of terminating reflection and
noise from external sources. Our recommends checking operation with the actual device.
5.1.4 Chip select
The µ PD161622 has two chip select pins (/CS). The CPU parallel and serial interfaces can be used only when /CS
= L. When the chip select pin is inactive, D0 to D15 are set to high impedance (invalid) and input of RS, /RD, or /WR is
not active. If a serial interface mode has been set, the shift register and counter are both initialized.
Data Sheet S15649EJ2V0DS
19
µ PD161622
5.1.5 Access to display data RAM and internal registers
When the CPU accessed the µ PD161622, the CPU only has to satisfy the requirement of the cycle time (tCYC) and
can transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration.
A high-speed RAM write function, as well as the ordinary RAM write function, is provided for writing data to the
display data RAM. By using the high-speed write function, data can be written to the display RAM at an access speed
four times faster than that of the ordinary RAM write function. Therefore, applications, such as motion picture display
where the display data must be rewritten at high speeds, can be supported. For details, refer to 5.2.5 High-speed
RAM write mode
Dummy data is not required when either reading or writing data. In the µ PD161622, data of the display memory
register (R12) cannot be read. This relationship is shown in Figure 5–6.
Note that when in write mode of data at high speed for data read mode of read cycle time, this mode equals to
normal mode.
Figure 5–6. Image of internal access to display RAM
Writing
/WR
DATA
n
n+1
n+2
n+3
Dummy
n
n+1
Reading (display memory register)
/WR
/RD
DATA
n
Reading (registers other than display memory register)
/WR
/RD
DATA
20
IRn
IRn
Data
n
n+1
IR Address
Set #n
IRn Register
Data Read
IR Address
Set #n+1
IRn+1 Register
Data Read
Data Sheet S15649EJ2V0DS
µ PD161622
5.2 Display Data RAM
This RAM stores dot data for display and consists of 2,112 bits (132 x 16) x 176 bits. Any address of this RAM can
be accessed by specifying an X address and an Y address.
Display data D0 to D15 transmitted from the CPU corresponds to the pixels on the LCD (refer to Table 5−5).
Table 5−5. Display Data RAM
D15
D14
D13
Dot 1
D12
D11
D10
D9
D8
D7
D6
D5
D4
Dot 2
D3
D2
D1
D0
Dot 3
Pixel 1 (= 1 x address)
5.2.1 X address circuit
An X address of the display data RAM is specified by using the X address register as shown in Figure 5−8.
If the X address increment mode (INC = 0: data access control register: R5) is used, the specified X address is
incremented or decremented by one each time display data is written. Whether the address is incremented or
decremented is specified by the XDIR flag of data access control register (R5) as shown in Table 5−6.
In the increment mode, the X address is incremented up to 83H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 00H.
In the decrement mode, the X address is decremented to 00H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 83H.
5.2.2 Y address circuit
A Y address of the display data RAM is specified by using the Y address register as shown in Figure 5−8. If the Y
address increment mode (INC = 1: data access control register: R5) is used, the specified Y address is incremented
or decremented by one each time display is written. Whether the address is incremented or decremented is specified
by the YDIR flag of data access control register (R5) as shown in Table 5−6.
In the increment mode, the Y address is incremented up to AFH. If more display data is written, the X address is
incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to 00H.
In the decrement mode, the Y address is decremented to 00H. If more display data is written, the X address is
incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to AFH.
The relationship between the setting of INC, XDIR, and YDIR of data access control register (R5) and the address is
as follows:
Data Sheet S15649EJ2V0DS
21
µ PD161622
Table 5−6. Data Access Control Register (R5) Setting
INC
Setting
0
The address is successively incremented or decremented in the X direction when data is accessed.
1
The address is successively incremented or decremented in the Y direction when data is accessed.
XDIR
Setting
0
Increments the X address (+1) when data is accessed.
1
Decrements the X address (−1) when data is accessed.
YDIR
Setting
0
Increments the Y address (+1) when data is accessed.
1
Decrements the Y address (−1) when data is accessed.
Table 5−7. Combination of INC, XDIR, and YDIR, and Address Direction
INC
XDIR
YDIR
Image of Address Scanning
0
0
0
A-1
0
1
A-2
1
0
A-3
1
1
1
A-4
0
0
B-1
0
1
B-2
1
0
B-3
1
1
B-4
Caution If the access direction is changed by using INC, XDIR, or YDIR, be sure to set the X
address register (R6) and Y address register (R7) before accessing the display RAM.
22
Data Sheet S15649EJ2V0DS
µ PD161622
Figure 5−7. Combination of INC, XDIR, and YDIR, and Address Scanning Image
X address
00H
83H
00H
A-1
Y address
A-2
A-3
A-4
AFH
X address
83H
00H
Y address
00H
B-1
B-2
AFH
B-4
B-3
5.2.3 Column address circuit
When the contents of the display data RAM are displayed, column addresses are output to the SEG output pins as
shown in Figure 5−8.
The correspondence relationship between the column addresses of the display RAM and segment outputs can be
reversed by the ADC flag (segment driver direction select flag) of control register 1 (R0) as shown in Table 5−8. This
reduces the restrictions on chip layout when the LCD module is assembled.
Table 5−8. Relationship between Column Address of Display RAM and Segment Output
SEG Output
ADC
SEG1
→
SEG2
SEG385
SEG386
0
000H
000H
→
Column address
→
18AH
18BH
1
18BH
18AH
←
Column address
←
001H
000H
Data Sheet S15649EJ2V0DS
23
µ PD161622
Figure 5–8. µ PD161622 RAM Addressing
Source
output
ADC=0
ADC=1
S1
S396
S2
S395
000H
000H
001H
D15---D11
D10---D5
X-address
Column addres
Gate output
R,/L=H
R,/L=L
24
S3
S394
S4
S393
S5
S392
002H
003H
001H
004H
Y6
S391
005H
D4---D0
D15---D11
D10---D5
D4---D0
-----
-----
---
---
---
---
Y-address
O1
O176
00H
O2
O175
01H
|
|
|
|
|
O87
O90
56H
O88
O89
57H
O89
O88
58H
O90
O87
59H
|
|
|
|
|
|
|
O175
O176
O2
O1
AEH
AFH
Display area
Data Sheet S15649EJ2V0DS
S391
S6
S392
S5
186H
08EH
187H
D15---D11
D10---D5
S393
S4
S394
S3
S395
S2
188H
189H
08FH
18AH
S396
S1
18BH
D4---D0
D15---D11
D10---D5
D4---D0
µ PD161622
5.2.4 Arbitrary address area access (window access mode (WAS))
With the µPD161622, any area of the display RAM selected by the MIN.⋅·X/Y address registers (R8 and R10) and
MAX.⋅ X/Y address registers (R9 and R11) can be accessed.
A setup of data access control (R5): WAS = 1 chooses window access mode. And µPD161622 accesses only the
domain set up by MIN.⋅ X/Y address registers and MAX.⋅ X/Y address registers. The address scanning setting by
INC, XDIR, and YDIR of data access control register (R5) is also valid in window access mode, in the same manner
as when data is normally written to the display RAM. In addition, data can be written from any address by specifying
the X address register (R6) and Y address register (R7).
Note that the display RAM must be accessed after setting the X address register (R6) and Y address register (R7) if
the window access area has been set or changed by the MIN.⋅ X/Y address register or MAX.⋅ X/Y address register.
Figure 5−9. Example of Incrementing Address When INC = 0, XDIR = 0, and YDIR = 0
MIN. . X address
Start point
MAX. . X address
83H
00H
00H
MIN. . Y address
.
.
.
MAX. . Y address
AFH
End point
Cautions 1. When using the window access mode, the relationship between the start point and end point
shown in the table below must be established.
Item
Address Relation Ship
X address
00H ≤ MIN.⋅X address ≤ X address (R4) MAX.⋅X address ≤ 83H
Y address
00H ≤ MIN.⋅Y address ≤ Y address (R5) MAX.⋅Y address ≤ AFH
2. If invalid address data is set as the MIN./MAX.⋅address, operation is not guaranteed.
3. Do not specify any value other than the address value 4n−n (n = 1 to 33) for the X address in the
high-speed RAM access mode. The operation is not guaranteed if invalid address data is set.
4. Access the display RAM after setting the X address register (R6) and Y address register (R7) if
the window access area has been set or changed by the MIN.⋅ X/Y address register or MAX.⋅ X/Y
address register.
Data Sheet S15649EJ2V0DS
25
µ PD161622
Figure 5−10. Example of Sequence in Window Access Mode
Start
Data access control register (R5)
(WAS = 1)
Sets window access mode.
MIN. . X address register (R8)
Sets start point.
MIN. . Y address register (R10)
MAX. . X address register (R9)
Sets end point.
MAX. . Y address register (R11)
X address register (R6)
Y address register (R7)
Display memory register (R12)
Data
Writing complete?
No
Yes
End
26
Data Sheet S15649EJ2V0DS
µ PD161622
5.2.5 High-speed RAM write mode
With the µPD161622, two types of access modes can be selected for accessing the display RAM.
The µPD161622 has a high-speed RAM write function, as well as an ordinary RAM write function. By using the highspeed write function, data can be written to the display RAM at an access speed four times faster than that of the
ordinary RAM write function. Therefore, applications, such as motion picture display where the display data must be
rewritten at high speeds, can be supported.
When the high-speed RAM write mode is selected by using BSTR of the data access control register (R5), data is
temporarily stored in an internal register of the µPD161622.
When data of 64 bits (16 bits x 4) has been stored in the register, it is written to the display RAM. It is also possible to
write the next data to the internal register while the first data is being written to the RAM.
In the high-speed RAM write mode, however, the CPU must transmit data in units of 64 bits (4 pixels) have been
written to the internal register. If data of less than 64 bits is transmitted in the high-speed RAM write mode, this data is
not written to the display RAM. Therefore, CPU data is not reflected on the LCD display even if it is transmitted. In this
case, the data that is not reflected remains stored in the register. When the next data is transmitted, it is written to the
register from where the preceding data is stored. However, if the chip select signal is disserted inactive (/CS = H) in
the middle of data transfer, and then asserted active again and when the display data register (R12) is set, the register
is initialized. Consequently, the data stored in the register is lost.
It is therefore recommended to transmit display data in 64-bit units when using the high-speed RAM write mode.
Figure 5–11. Image of Operation in High-speed Write Mode
Display RAM
64-bit
64-bit
64
64-bit
64
64
64
64-bit register
8/16
Display
Data
8/16
8/16
8/16
Parallel / Serial
Interface circuit
Caution Do not specify any value other than the address value 4n−n (n = 1 to 33) for the X address (R6) in
the high-speed RAM access mode. The operation is not guaranteed if invalid address data is set.
Data Sheet S15649EJ2V0DS
27
µ PD161622
Figure 5−12. Example of Sequence in High-Speed RAM Write Mode (with 16-Bit Parallel Interface)
Start
High speed RAM write mode setting
(R5: BSTR[D6] = 1)
Sets the high-speed RAM write mode.
X address setting register (R6)Note
Y address setting register (R7)
Display memory register (R12)
1st word (4n − 4)
display data (16 bit)
2nd word (4n − 3)
display data (16 bit)
3rd word (4n − 2)
display data (16 bit)
Data write sequence
(writing data in 64-bit units)
4th word (4n − 1)
display data (16 bit)
No
End of data
Yes
Next processing
End
n: n ≥ 1
Note Do not specify any value other than the address value 4n−n (n = 1 to 33) for the X address (R6) in the
high-speed RAM access mode. The operation is not guaranteed if invalid address data is set.
28
Data Sheet S15649EJ2V0DS
µ PD161622
5.3 Oscillator
The µ PD161622 has a CR oscillator (with external R), which generate the display clock. When RSEL is L, an internal
CR oscillator is selected. Leave both OSCIN pin and OSCOUT open. When RSEL is H, an external oscillator is selected.
Connect 51 kΩ resistance between OSCIN and OCSOUT pin.
This oscillator also has a calibration function, which is available by itself to set the number of frame frequency of
display driving. Frame frequency calibration is set by calibration register (R45). The time to select one line is set by
the calibration start and stop commands.
Figure 5–13. Frame Frequency Calibration
Start/Stop
Calibration
command
Register
n-bit
counter
OSC
Internal
clock
The calibration function involves counting the number of oscillation clocks generated between the start and stop
signals and storing that number in a register. The number of oscillation clocks is then continually compared with this
register value in subsequent operations, and the time of the clock number stored in the register is set as 1 line
selection time, and used as the internal reference clock.
Using the time to set calibration (tcal) can be selected either tcal or tcal x 2 through control register (R1): LTS.
Figure 5–14. Calibration Function Timing (LTS [R1] = 0)
Calibration start
Calibration stop
tcal (1 line time)
1
2
3
5
4
6
tcal = 1/(fFRAME x n)
fFRAME = Frame frequency
n: Line numbers
7
OSC1
1
2
3
4
OSC2
Data Sheet S15649EJ2V0DS
29
µ PD161622
5.4 Display Timing Generator
5.4.1 Drive timing
The µ PD161622 generates the TFT-LCD drive timing inside the µ PD161622. The TFT-LCD panel is driven at the
timing of one line selection period generated based on the calibration time (tcal) set by the calibration function, as
shown in the figure below. One line selection period is made up of a pre-charge period, a source output period, and
the µ PD161622 output control clock. The pre-charge and source output periods are set by the pre-charge period
setting register (R46) and calibration register (R45), respectively, based on the following expressions.
1 line selection period = tcal
Pre-charge period = tpr
Source output period = tsout
tcal: Calibration setting time [R45]
tpr = (1/fOSC) x (CLKpr + 2 CLK)
tsout = tcal - (tpr + 3 CLK)
CLKcal: Calibration setting time (tcal) clock number = tcal ÷ (1fOSC)
CLKpr: Pre-charge peiod setting register clock number [R46: PLIMn] n
1 CLK = 1/fOSC
fOSC: Oscillator frequency
30
Data Sheet S15649EJ2V0DS
µ PD161622
Figure 5–15. 1-line Select Time
1 line select time
1 CLK
fOSC
Output control
basis clock
1
1
1
0
2
3
4
5
7
6
8
0
1
2
3
4
5
6
Source output time: tsout
Pre-charge time: tpr
CLKpr
1
1
1
2 CLK
1
9
2 CLK
CLsout
4 CLK
Sn
GCLK
GSTB
GOE1
Gn
VCOUT
Data Sheet S15649EJ2V0DS
31
µ PD161622
The display timing generator generates the timing signals for the internal timing of the source driver and for the gate
driver. The output timings for normal operation, for normal operation → stand-by mode, and for stand-by mode →
normal operation, are shown below.
Figure 5–16. During Normal Operation (during line inversion)
GSTB
Data output
line no.
176
dummy
1
2
3
4
5
GCLK
GOE1
GOE2
Sn
VCOUT
G176
G1
G2
G3
32
Data Sheet S15649EJ2V0DS
176
dummy
1
2
µ PD161622
Figure 5–17. Normal Operation → Stand-by Input (during line inversion)
(2)
(1)
GSTB
Data output
line no.
176
dummy
1
2
3
4
5
dummy
176
GCLK
GOE1
GOE2
Sn
VCOUT
G176
G1
G2
G3
G4
Stand-by
command input
Stand-by
mode start
Data Sheet S15649EJ2V0DS
Stand-by
statement
33
µ PD161622
Figure 5–18. Normal Operation → Stand-by Input (during line inversion) (1) Reference
1 line select time (3 line)
1 line select time (4 line)
1 CLK
fOSC
GSTB
GCLK
GOE1
GOE2
Sn
VSS
G2
G3
G4
VCOUT
VSS
Stand-by
command
34
Data Sheet S15649EJ2V0DS
Stand-by
mode start
µ PD161622
Figure 5–19. Normal Operation → Stand-by Input (during line inversion) (2) Reference
Stand-by time
1 line select time (dummy line)
1 CLK
fOSC
Oscillation stop
GSTB
GCLK
GOE1
GOE2
Sn
VSS
G176
G3
G4
All gate on
VCOUT
VSS
Stand-by
command
Data Sheet S15649EJ2V0DS
35
µ PD161622
Figure 5–20. Stand-by → Return to Normal Operation (during line inversion)
GSTB
Data output
line no.
dummy
1
2
GCLK
GOE1
GOE2
Sn
VCOUT
G176
G1
G2
G3
G4
Stand-by release
command input
36
Data Sheet S15649EJ2V0DS
3
4
5
µ PD161622
5.5 Common Adjustment Circuit
To generate common output, the center voltage of the common waveform is output from the VCOM pin along with
output of a 0 to VS (V) square waveform from the VCOUT1 pin and 0 to VCC1 (V) from VCOUT2. The level of the
VCOM output can be adjusted using as external resistor.
Figure 5–21. Common Adjustment Circuit
R29
VS
R25
(PVCOM)
D/A
converter
Rectangle waveform value
VCOUT1: Vp-p = VS
VCOUT2: Vp-p = VCC1
VBGR
R25
(BGRS)
BGRIN
DAC7
VCOMR
VCOUT1, VCOUT2
VCOM
FBRSEL
DAC0
C1
R1
R3
VCOMMON
VS,
VCC1
R2
0V
VCOMMON waveform center setting
The VCOM voltage formulas are shown below.
<When internal power supply is used 1 (BGRS [D6] of R25 = 0, PVCOM (D3) = 0)>
COM voltage = (1+R1/R2) x VBGR x (α ÷ 256)
VBGR = 3.0 V TYP.
α = VCOM electronic volume register [R29]
<When internal power supply is used 2 (BGRS [D6] of R25 = 0, PVCOM (D3) = 1)>
COM voltage = (1+R1/R2) x VS x (α ÷ 256)
α = VCOM electronic volume register [R29]
<When external power supply is used (BGRS [D6] of R25 = 1)>
COM voltage = (1+R1/R2) x VBGRIN
VBGRIN = external power supply voltage (voltage input from BGRIN)
<Recommended values for R1 to R3, and C1>
Use the values listed below as a guideline. The user is responsible for ultimately determining the resistance
values and recommended values based on careful evaluation on actual panels.
R1: 200 K
R2: 51 to 100 K
R3: 51 to 100 K
C1: 10 µF
Data Sheet S15649EJ2V0DS
37
µ PD161622
5.6 Rectangular Signal Generator
This circuit generates a common rectangular signal. A rectangular wave of 0 to VS (V) is output from the VCOUT1
pin, and a wave of 0 to VCC1 (V) is output from the VCOUT2 pin. The common output wave necessary for driving an
LCD can be generated by connecting an external circuit as shown in Figure 5–21.
5.7 Reference Voltage Generator (VBGR)
The µ PD161622 has a reference voltage generator for the voltage regulator. This reference voltage generator
generates a constant voltage from VCC1. The constant voltage generated by this circuit is connected to the input of the
operational amplifier that adjusts the center level of the COMMON drive output, via a D/A converter.
By using this voltage, therefore, the center level of the COMMON drive output can be kept constant, without being
affected by fluctuations in the supply voltage.
The common output waveform necessary for driving an LCD can be generated by connecting the external circuit
show in Figure 5–21.
When the internal reference voltage generator is not used (R25: BGRS = 1), directly input the reference voltage to
the operational amplifier that adjusts the center level of the COMMON drive output.
5.8 D/A Converter Circuit
The µ PD161622 is provided with an internal D/A converter to adjust the voltage of the reference voltage generator
for the voltage regulator. This D/A converter divides the constant voltage generated by the reference voltage
generator (VBFR) by 256, and a level of voltage between VBGR and VSS can be selected by setting the VCOM
electronic volume register (R29).
In addition, this D/A converter also has a function to select a level by using an external pin. If the set value of the
VCOM electronic volume register (R29) is 00H, the set statuses of the DAC7 to DAC0 pins are valid.
When DACn pin input is valid (R29 = 00H), these pins are pulled up internally , so only the pins that are to be set to L
should be connected to VSS.
Table 5–9. α Setting of VCOM Electronic Volume Register (R25: BGRS = 0)
00H
EV7
EV6
EV5
EV4
EV3
EV2
EV1
EV0
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
0
0
0
0
0
0
0
0
α
Remark
DACn set
R29
value
0
01H
0
0
0
0
0
0
0
1
2
02H
0
0
0
0
0
0
1
0
3
03H
0
0
0
0
0
0
1
1
4
FEH
1
1
1
1
1
1
1
0
255
FFH
1
1
1
1
1
1
1
1
256
↓
38
↓
↓
Data Sheet S15649EJ2V0DS
DACn
µ PD161622
5.9 γ-Curve Correction Power Supply Circuit
The µ PD161622 includes a γ-curve correction power supply circuit. If the internal γ-curve correction matches the
LCD characteristics, no external components are necessary. This power circuit has white level and black level
reference voltage generators on the positive and negative polarity sides, and also supports unbalanced driving. The
reference voltage generators consist of a D/A converter and an operational amplifier and divide VS to VSS by 256. One
level of voltage can be selected by using the contrast value setting registers (R36 to R39)
Figure 5–22. γ-Curve Correction Circuit
VS
D/A
(R36)
VPH
D/A
(R37)
VNH
custom γ
SR36
SR37
00H : SW ON
AMP OFF
SPH2
SNL2
VRH
VSS
SPH1
V0
SNL1
SNH1
V5
D/A
(R39)
VNL
00H : SW ON
AMP OFF
VRL1
VS
SR39
VPL
SR38
D/A
(R38)
SPL1
SNH2
SPL2
VRL2
VSS
Data Sheet S15649EJ2V0DS
39
µ PD161622
Figure 5–23. Relationship of TFT Drive Voltage (normally white)
VS
VPH
VNH
Black
White
VPL
VNL
VSS
Positive polarity
Negative polarity
Drive level
Setting register
VPH
Positive polarity, black
Contrast value setting register 1
R36
VNH
Negative polarity, white
Contrast value setting register 2
R37
VPL
Positive polarity, black
Contrast value setting register 3
R38
VNL
Negative polarity, white
Contrast value setting register 4
R39
The value of each amplifier output can be expressed as follows and the value of β can be set as shown in Table 5–
10 and 5−11by using the contrast value registers (R36 to R39)
VNL, BVPL, VNH, VPH = (β ÷ 256) x VS
Caution The usable range in which each output level of VPH, VNH, VPL, and VNL can be set depends on the
γ -curve.
Table 5–10. γ-Contrast Value Setting and Electronic Volume Register β Setting 1 (VPH, VNL)
R36
GPH7
GPH6
GPH5
GPH4
GPH3
GPH2
GPH1
GPH0
β value setting or
R37
GNH7
GNH6
GNH5
GNH4
GNH3
GNH2
GNH1
GNH0
status setting
00H
0
0
0
0
0
0
0
0
Fixed to VS (amplifier OFF)
01H
0
0
0
0
0
0
0
1
255
02H
0
0
0
0
0
0
1
0
254
03H
0
0
0
0
0
0
1
1
253
↓
40
↓
↓
FEH
1
1
1
1
1
1
1
0
2
FFH
1
1
1
1
1
1
1
1
1
Data Sheet S15649EJ2V0DS
µ PD161622
Table 5–11. γ-Contrast Value Setting and Electronic Volume Register β Setting 1 (VPL, VNL)
R36
GPL7
GPL6
GPL5
GPL4
GPL3
GPL2
GPL1
GPL0
β value setting or
R37
GNL7
GNL6
GNL5
GNL4
GNL3
GNL2
GNL1
GNL0
Statement setting
00H
0
0
0
0
0
0
0
0
Fixed to VS (amplifier OFF)
01H
0
0
0
0
0
0
0
1
255
02H
0
0
0
0
0
0
1
0
254
03H
0
0
0
0
0
0
1
1
253
FEH
1
1
1
1
1
1
1
0
2
FFH
1
1
1
1
1
1
1
1
1
↓
↓
↓
Relationship between Setting Value of R36 to R39 Registers and Switch Status (GSEL[R1] = 1)
Register
Setting value
Switch Status
00H
R36
00H
R37
SR37
Other than 00H
00H
R38
SR38
Other than 00H
00H
R39
ON
SR36
Other than 00H
SR39
Other than 00H
Amplifier
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
The relationship between the setting of the contrast value setting register and the driven waveform is explained next,
taking the γ-curve in Figure 5–22 as an example.
Table 5–12. Switch Status when γ-Curve Correction Power Supply Circuit is not used (GSEL[R1] = 0)
Polarity
Switch status
SPH1
SNL1
SNH1
SPL1
SPH2
SNL2
SNH2
SPL2
Positive
x
x
x
x
ON
OFF
OFF
ON
Negative
x
x
x
x
OFF
ON
ON
OFF
Remark x: Switch is normally OFF with the amplifier OFF.
Relationship of drive voltage (normally white)
VS
VPH
VNH
Black
White
VPL
VNL
VSS
Positive polarity
Negative polarity
Data Sheet S15649EJ2V0DS
41
µ PD161622
Table 5–13. Switch Status when γ-Curve Correction Power Circuit is used (GSEL[R1] = 1)
Polarity
Switch status
SPH1
SNL1
SNH1
SPL1
SPH2
SNL2
SNH2
SPL2
Positive
ON
OFF
OFF
ON
x
x
x
x
Negative
OFF
ON
ON
OFF
x
x
x
x
Remark x: Switch is normally OFF
Relationship of drive voltage (normally white)
VS
VPH
VNH
Black
White
VPL
VNL
VSS
Positive polarity
42
Negative polarity
Data Sheet S15649EJ2V0DS
µ PD161622
Figure 5–24. TFT Drive Voltage Level
VS
VPH
D/A
(R37)
VNH
SR36
SNL2
VRH
VSS
SPH1
V0
SNL1
Drive voltage range
D/A
(R36)
SR37
00H : SW ON
AMP OFF
SPH2
SNH1
V5
D/A
(R39)
VNL
00H : SW ON
AMP OFF
VRL1
VS
SR39
VPL
SR38
D/A
(R38)
SPL1
SNH2
SPL2
VRL2
VSS
Data Sheet S15649EJ2V0DS
43
µ PD161622
Table 5–14. γ-Curve Correction Circuit (γ-correction resistance)
Gray scale
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Display Data
D10 - D5
D15 - D11, D4 - D0
00H
00H
01H
−
02H
−
03H
01H
04H
−
05H
02H
06H
−
07H
03H
08H
−
09H
04H
0AH
−
0BH
05H
0CH
−
0DH
06H
0EH
−
0FH
07H
10H
−
11H
08H
12H
−
13H
09H
14H
−
15H
0AH
16H
−
17H
0BH
18H
−
19H
0CH
1AH
−
1BH
0DH
1CH
−
1DH
0EH
1EH
−
1FH
0FH
20H
−
21H
10H
22H
−
23H
11H
24H
−
25H
12H
26H
−
27H
13H
28H
−
29H
14H
2AH
−
2BH
15H
2CH
−
2DH
16H
2EH
−
2FH
17H
30H
−
31H
18H
32H
−
33H
19H
34H
−
35H
1AH
36H
−
37H
1BH
38H
−
39H
1CH
3AH
−
3BH
1DH
3CH
−
3DH
1EH
3EH
−
3FH
1FH
Total
44
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Resistance (kΩ)
1
1.587
2
1.226
3
2.453
4
3.390
5
4.112
6
4.905
7
1.731
8
1.443
9
1.587
10
1.515
11
1.082
12
1.082
13
1.154
14
1.226
15
1.298
16
1.082
17
0.649
18
0.721
19
0.794
20
0.721
21
0.794
22
0.505
23
0.577
24
0.577
25
0.577
26
0.505
27
0.433
28
0.433
29
0.433
30
0.433
31
0.505
32
0.361
33
0.433
34
0.433
35
0.433
36
0.433
37
0.433
38
0.433
39
0.505
40
0.433
41
0.433
42
0.433
43
0.505
44
0.361
45
0.433
46
0.433
47
0.361
48
0.361
49
0.361
50
0.361
51
0.433
52
0.433
53
0.433
54
0.505
55
0.505
56
0.505
57
0.721
58
0.721
59
0.866
60
0.866
61
1.587
62
2.597
63
2.597
64
12.047
65
7.719
80.000
Data Sheet S15649EJ2V0DS
Output Voltage (V)
Positive Voltage Negative Voltage
4.901
0.107
4.824
0.190
4.671
0.356
4.459
0.586
4.202
0.864
3.895
1.196
3.787
1.313
3.697
1.411
3.598
1.519
3.503
1.621
3.436
1.694
3.368
1.768
3.296
1.846
3.219
1.929
3.138
2.017
3.070
2.090
3.030
2.134
2.985
2.183
2.935
2.236
2.890
2.285
2.840
2.339
2.809
2.373
2.773
2.412
2.737
2.451
2.701
2.490
2.669
2.524
2.642
2.554
2.615
2.583
2.588
2.612
2.561
2.642
2.529
2.676
2.507
2.700
2.480
2.729
2.453
2.759
2.426
2.788
2.399
2.817
2.372
2.847
2.344
2.876
2.313
2.910
2.286
2.939
2.259
2.969
2.232
2.998
2.200
3.032
2.178
3.057
2.151
3.086
2.124
3.115
2.101
3.140
2.078
3.164
2.056
3.188
2.033
3.213
2.006
3.242
1.979
3.271
1.952
3.301
1.921
3.335
1.889
3.369
1.858
3.403
1.812
3.452
1.767
3.501
1.713
3.560
1.659
3.618
1.560
3.726
1.398
3.901
1.235
4.077
0.482
4.893
µ PD161622
Figure 5–25. γ-Curve Corrected Circuit (γ-corrected resistance value)
5.000
Level voltage [V]
4.000
3.000
2.000
1.000
0.000
0
10
20
30
40
50
60
Gray scale level
Positive Voltage
Negative Voltage
Data Sheet S15649EJ2V0DS
45
µ PD161622
Figure 5–26. Internal Connection of V0 to V5, VRH, VRL1, and VRL2
γ-correction
resister
VS
SPH2
SNL2
VSS
VPH
VRH
SPH1
r6
V1
r7
r1
V0
r2
r16
VNH
V2
r17
SNL1
r50
SNH1
V3
r63
r51
V5
VPL
SPL1
r64
VRL1
r60
V4
r61
VNL
r65
SNH2
VS
SPL2
VRL2
VSS
46
Data Sheet S15649EJ2V0DS
µ PD161622
5.10 Partial Display Mode
The µ PD161622 is provided with a function that allows sections within the screen to be displayed separately (partial
display mode). The start line of the area to be displayed in partial display mode is set using the partial display area
start line register (R20, R21), the number of lines in the area to be displayed is set using the partial display area line
count register (R22, R23), and the color of the area not to be displayed is set using the partial off area color register
(R19). If ”1” is set in the partial display area line count registers (R22, R23), the partial display areas each become 1
line. If “0” is set, there are no partial display areas but only normal display areas.
The non-display area indicated by R20 and R22 is called Partial 1, and the non-display area indicates by R21 and
R23 is called Partial 2. The Partial 2 setting is enabled only when the Partial 1 setting has been performed (when R22
≠ 0). Therefore, to set only one area as a non-display area, perform only the setting for Partial 1.
Low power consumption cannot be achieved if only the partial mode is set. If low power consumption is required, the
mode must be switched to the 8-clor mode.
Figure 5–26. Partial Display Mode
00H
01H
02H
03H
...
81H
82H
83H
Display
start line (00H)
Partial display area
line number(R22, R23)
Partial display start
line (R20, R21)
Section not displayed
Cautions 1. The "scroll step count register (R17)" command is ignored in the partial display mode.
2. The specified partial areas must not directly overlap, and the Partial 1 area and Partial 2 area
must be separated by at least one line. If the areas overlap, only the Partial 1 settings are valid,
and partial display is not performed for the Partial 2 area.
3. When setting the partial display areas, be sure to observe the following relationship.
“00H” ≤ R20 (R21)
R22 (R23) ≤ “AFH”
The following sequence is recommended to avoid display malfunction when switching from normal display mode to
partial display mode and vice versa.
Data Sheet S15649EJ2V0DS
47
µ PD161622
(1) Recommended sequence for switching from normal display mode to partial display mode
DISP1 = 1 or DISP1 = 0, DISP0 = 1
R0
D7
<1> Display off
↓
D2
PGDn setting
<2> Partial off area color register setting Note1
R19
D0
↓
<3> Display data overwrite Note1
Display data overwrite
(for partial display)
↓
D7
P1SLn, P2SLn setting
R20,
R21
<4> Partial display area start line setting Note1
D0
↓
D7
P1AWn, P2AWn setting
<5> Partial display area line count setting Note1
R22,
R23
D0
R0
D4, D2
R0
D7
↓
DTY = 1, COLOR = 1
<6> Partial display mode, 8-color mode Note2
↓
DISP1 = 0, DISP0 = 0
<7> Display on
Notes 1. <2> to <5> can be executed in any order.
2. <6> must be executed after <4> and <5> have been set.
48
Data Sheet S15649EJ2V0DS
µ PD161622
(2) Recommended sequence for switching from partial display mode to normal display mode
R0
DISP1 = 1 or DISP1 = 0, DISP0 = 1
D7
<1> Display off
↓
<2> Display data overwrite Note
Display data overwrite
(for normal display)
↓
DTY = 0, COLOR = 0
R0
D4, D2
R0
D7
<3> Partial display mode, 65,000-color mode Note
↓
DISP1 = 0, DISP0 = 0
<4> Display on
Note <2> to <3> can be executed in any order.
(3) Recommended sequence for switching from partial display mode to partial display mode (switching the
partial display area)
DISP1 = 1 or DISP1 = 0, DISP0 = 1
R0
D7
<1> Display off
↓
<2> Display data overwrite Notes Note1, 2
(display data overwrite)
↓
D7
P1SLn, P2SLn setting
R20,
R21
<3> Partial display area start line setting Note1
D0
↓
D7
P1AWn, P2AWn setting
<4> Partial display area line count setting Note1
R22,
R23
D0
R0
D4
<5> Partial display mode Note3
R0
D7
<6> Display on
↓
DTY = 1
↓
DISP1 = 0, DISP0 = 0
Notes 1. <2> to <4> can be executed in any order.
2. Execute <2> only when necessary.
3. <5> must be executed after <3> and <4> have been set.
Data Sheet S15649EJ2V0DS
49
µ PD161622
(4) Partial display setting examples
Setting A-1
Register
Setting Value
Details of Setting Value
Partial display area start line register (R20, R21)
00H
Sets Y address 00H
Partial display area line count register (R22, R23)
58H
Sets an area of 88 lines
Setting A-2
Register
Setting Value
Details of Setting Value
Partial display area start line register (R20, R21)
58H
Sets Y address 58H
Partial display area line count register (R22, R23)
58H
Sets an area of 88 lines
Setting A-3
Register
Setting Value
Details of Setting Value
Partial display area start line register (R20, R21)
84H
Sets Y address 84H
Partial display area line count register (R22, R23)
58H
Sets an area of 88 lines
Setting A-4
Register
50
Setting Value
Details of Setting Value
Partial display area start line register (R20, R21)
2CH
Sets Y address 2CH
Partial display area line count register (R22, R23)
58H
Sets an area of 88 lines
Data Sheet S15649EJ2V0DS
µ PD161622
Figure 5–28. Partial Display Setting Examples
Source
Gate
Setting A-1
1
Source
132
Gate
1
1
Area not displayed
88
89
88
89
Area not displayed
Partial display area
176
176
Source
Setting A-3
1
Source
132
1
Gate
Setting A-4
1
132
1
Partial display area
44
45
Area not displayed
44
45
Partial display area
Area not displayed
132
133
132
133
Area not displayed
Partial display area
176
132
1
Partial display area
Gate
Setting A-2
176
Data Sheet S15649EJ2V0DS
51
µ PD161622
5.11 Screen Scroll
The µ PD161622 has a screen scroll function. Any area of the screen can be scrolled by using the scroll area start
line register (R15), scroll area line count register (R16), and scroll step count register (R17) to set the Y address of the
top line of the area to be scrolled, the count of lines of the area to be scrolled, and the scroll step number,
respectively.
Note that in partial mode, the screen scroll function is disabled.
Table 5–15. Scroll Area Start Line Register (R15)
SSL7
SSL6
SSL5
SSL4
SSL3
SSL2
SSL1
SSL0
Start Line Y Address
0
0
0
0
0
0
0
0
00H
0
0
0
0
0
0
0
1
01H
0
0
0
0
0
0
1
0
02H
0
0
0
0
0
0
1
1
03H
↓
↓
1
0
1
0
1
1
0
1
ADH
1
0
1
0
1
1
1
0
AEH
1
0
1
0
1
1
1
1
AFH
Table 5–16. Scroll Area Line Count Register (R16)
SAW7
SAW6
SAW5
SAW4
SAW3
SAW2
SAW1
SAW0
Scroll Area Line Number
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
1
1
↓
4
↓
1
0
1
0
1
1
0
1
174
1
0
1
0
1
1
1
0
175
1
0
1
0
1
1
1
1
176
Table 5–17. Scroll Step Count Register (R17)
SST7
SST6
SST5
SST4
SST3
SST2
SST1
SST0
Scroll Step Number
0
0
0
0
0
0
0
0
0 (no scroll)
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
1
3
1
0
1
0
1
1
0
1
173
1
0
1
0
1
1
1
0
174
1
0
1
0
1
1
1
1
175
↓
↓
Scrolling must be set using the following sequence.
52
Data Sheet S15649EJ2V0DS
µ PD161622
(1) Recommended scroll sequence
D7
SSLn setting
<1> Scroll area start line setting Note1
R15
D0
↓
D7
SAWn setting
<2> Scroll area line count setting Note1
R16
D0
↓
D7
SSTn setting
<3> Scroll step count register setting Note2
R17
D0
Notes 1. <1> to <2> can be executed in any order.
2. <3> must be executed after <1> and <2> have been set.
Remark Set SSTn to 00H to disable the scroll operation. No particular sequence is required for this.
Cautions 1. If the sum of the values of SSLn and SAWn is 176 (AFH) or over, it is invalid (no scroll operation).
2. Set the step number SSTn so that it does not exceed the line number SAWn. If a value
exceeding SAWn is set, it will be invalid (no scroll operation).
Data Sheet S15649EJ2V0DS
53
µ PD161622
(2) Scroll setting examples
Setting A-1
Register
Setting Value
Details of Setting Value
Scroll area start line register (R15)
00H
Sets Y address 00H
Scroll area line count register (R16)
AFH
Sets an area of 176 lines
Setting A-2
Register
Setting Value
Details of Setting Value
Scroll area start line register (R15)
00H
Sets Y address 00H
Scroll area line count register (R16)
57H
Sets an area of 88 lines
Setting A-3
Register
Setting Value
Details of Setting Value
Scroll area start line register (R15)
58H
Sets Y address 58H
Scroll area line count register (R16)
57H
Sets an area of 88 lines
Setting A-4
Register
54
Setting Value
Details of Setting Value
Scroll area start line register (R15)
2CH
Sets Y address 2CH
Scroll area line count register (R16)
57H
Sets an area of 88 lines
Data Sheet S15649EJ2V0DS
µ PD161622
Figure 5–29. Display Scroll Setting Examples
Source
Gate
Setting A-1
1
Source
132
Gate
1
Setting A-2
1
132
1
Scroll area
88
89
Scroll area
Fixed display area
176
176
Source
Gate
Setting A-3
1
Source
132
1
Gate
Setting A-4
1
132
1
Fixed display area
44
45
Fixed display area
88
89
Scroll area
Scroll area
132
133
Fixed display area
176
176
Data Sheet S15649EJ2V0DS
55
µ PD161622
(3) Scroll setting flowchart example
Start
↓
Scroll area
start line register assignment
IR
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
0
1
1
1
1
↓
Scroll area
start line register setting
R15
D7 to D0 Scroll area start line register
RS
H
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Caution D7 to D0 are the data for Scroll area start line.
↓
Scroll area
line count register assignment
MSB
IR
D5 to D0 Index register
RS
L
MSB
X
LSB
0
0
1
0
0
0
D3
D2
D1
0
↓
Scroll area
line count register setting
R16
D7 to D0 Scroll area line count register
RS
H
MSB
D7
LSB
D6
D5
D4
D0
Caution D7 to D0 are the data for Scroll area line count
register.
↓
IR
Scroll step count register assignment
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
1
0
0
0
0
0
0
1
↓
Scroll step count register setting
(1 step)
R17
D7 to D0 Scroll step count register
RS
H
MSB
0
LSB
0
0
0
1
↓
IR
X address register assignment
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
0
0
1
1
0
↓
R6
X address register setting
D7 to D0 X address register
RS
H
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Caution D7 to D0 depend on application condition.
↓
IR
Y address register assignment
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
0
0
1
1
1
↓
R7
Y address register setting
D7 to D0 Y address register
RS
H
↓
56
MSB
D7
LSB
D6
D5
D4
D3
D2
Caution D7 to D0 depend on application condition.
Data Sheet S15649EJ2V0DS
D1
D0
µ PD161622
↓
IR
Display memory assignment
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
0
1
1
0
D4
D3
D2
D1
D2
D1
0
↓
Display data
Re-write scrolling area 1
(start)
R12
RS
H
↓
Display data
Re-write scrolling area 2
D7 to D0 Display memory
D7
LSB
D6
D5
D0
Caution D7 to D0 are display memory data.
R12
D7 to D0 Display memory
RS
H
↓
↓
↓
Display data
Re-write scrolling area n
(end)
MSB
MSB
D7
LSB
D6
D5
D4
D3
D0
Caution D7 to D0 are display memory data.
R12
D7 to D0 Display memory
RS
H
↓
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Caution D7 to D1 are display memory data.
IR
Scroll step count register assignment
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
1
0
0
0
0
0
1
1
↓
R17
Scroll step count register setting
(2 steps)
D7 to D0 Scroll step count register
RS
H
MSB
0
LSB
0
0
0
0
↓
IR
X address register assignment
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
0
0
1
1
0
↓
R6
X address register setting
D6 to D0 X address register
RS
H
↓
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Caution D7 to D0 depend on application condition.
IR
Y address register assignment
D6 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
0
1
1
D4
D3
D2
D1
1
↓
R70
Y address register setting
D7 to D0 Y address register
RS
H
↓
D7
LSB
D6
D5
D0
Caution D7 to D1 depend on application condition.
IR
Display memory assignment
MSB
D6 to D0 Index register
RS
L
MSB
X
LSB
0
0
0
1
1
0
0
↓
Data Sheet S15649EJ2V0DS
57
µ PD161622
↓
Display data
R12
Re-write scrolling area 1
RS
(start)
MSB
H
↓
Display data
D7 to D0 Display memory
D7
LSB
D6
D5
D4
D3
D2
D1
D2
D1
D2
D1
D0
Caution D7 to D0 are display memory data.
R12
D7 to D0 Display memory
RS
Re-write scrolling area 2
MSB
H
↓
D7
LSB
D6
D5
D4
D3
D0
Caution D7 to D0 are display memory data.
↓
↓
Display data
R12
Re-write scrolling area n
D7 to D0 Display memory
RS
(end)
MSB
H
D7
LSB
D6
D5
D4
D3
↓
Caution D7 to D0 are display memory data.
↓
(repeat)
↓
Next transaction
Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not
meant for use in mass-production design.
58
Data Sheet S15649EJ2V0DS
D0
µ PD161622
(4) Scroll function example
Scroll area start line register (R15): 2CH
Scroll area line count register (R16): 58H
(a) Scroll step count register setting (R17): 00H
Source
Gate 1
1
132
Y address
00H
Fixed display area
2BH
2CH
44
45
Scroll area
83H
84H
132
133
Fixed display area
176
AFH
(b) Scroll step count register setting (R17): 01H
Source
Gate 1
1
132
Y address
00H
Fixed display area
44
45
2BH
2DH
Scroll area
83H
2CH
84H
132
133
Fixed display area
176
AFH
Data Sheet S15649EJ2V0DS
59
µ PD161622
(c) Scroll step count register setting (R17): 02H
Source
Gate 1
1
132
Y address
00H
Fixed display area
2BH
2EH
44
45
Scroll area
83H
2CH
2DH
84H
132
133
Fixed display area
176
AFH
(d) Scroll step count register setting (R17): 57H
Source
Gate 1
1
132
Y address
00H
Fixed display area
44
45
2BH
83H
2CH
Scroll area
132
133
82H
84H
Fixed display area
176
60
AFH
Data Sheet S15649EJ2V0DS
µ PD161622
5.12 Stand-by
The µ PD161622 has a stand-by function. Input of a stand-by command is acknowledged when the STBY bit of the
control register 1 (R0) is set to 1.
When the stand-by command has been input, the µ PD161622 is forcibly placed in the VSS display status, and scans
the frame being display to the end. When scanning is complete, all gate outputs are turned on, the charge of the pixel
on the TFT panel is decreased to 0, and the output stage amplifier and internal oscillator are stopped.
The stand-by function is valid for only the source driver IC; the gate IC (µ PD161640) and power IC (µ PD161660)
connected to the µ PD161622 are not controlled by this function.
After executing the stand-by command, therefore, execute commands that turn off the regulator for the gate IC and
power IC an turn off the DC/DC converter.
When the stand-by status is released, turn on the DC/DC converter and the regulator of the gate IC and power IC,
and then issue an ordinary operation command (STBY = 0), in the reverse order to which the stand-by command was
input.
Data Sheet S15649EJ2V0DS
61
µ PD161622
(1) Stand-by sequence
Operating status (normal display)
↓
IR
Control register 1 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
↓
R0
Control register 1 setting
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
X
X
D5
X
X
X
X
D8
D0
X
0
1
0
0
0
D7: Don’t care
D6: Don’t care
D4: Normal display mode (not partial display mode)
D3: Stand-by ON
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
The source output is automatically fixed to the VSS level by standby, so D7 and D6 can be set to any value.
At least one frame period
↓
Wait time 1 (tOE2RG)
↓
<Power supply control sequence>
IR
Power supply control register 1 assignment
D5 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
↓
Wait time 2 (tRGRP)
X
D5
D4
D3
0
Note
1
1
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator ON
D0: DC/DC converter ON
Note This setting can be deleted from the sequence when using
an IC with no regulator circuit for the gate driver.
Although a setting of 0 ns has no negative effect in terms of the
device, be sure to finalize the timing after sufficient evaluation
with the LCD module.
↓
62
D6
D8
D0
Data Sheet S15649EJ2V0DS
µ PD161622
↓
IR
D5 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
RS
Power supply control register 1 assignment
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
X
D6
D5
D4
D3
D8
D0
0
0
1
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator OFF
D0: DC/DC converter ON
↓
Although a setting of 0 ns has no negative effect in terms of the
device, be sure to finalize the timing after sufficient evaluation
with the LCD module.
Wait time 3 (tRGRP)
↓
IR
D5 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
RS
Power supply control register 1 assignment
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
X
D6
D5
D4
D3
D8
D0
0
0
0
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator OFF
D0: DC/DC converter OFF
↓
Stand-by setting completed
Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not
meant for use in mass-production design.
Data Sheet S15649EJ2V0DS
63
µ PD161622
(2) Stand-by release sequence
Stand-by status
↓
IR
D6 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
RS
Control register 1 assignment
↓
R0
Control register 1 setting
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
1
0
D5
X
X
X
X
D8
D0
X
0
0
0
0
0
D7: All data “1” output (normally white: white output)
D6: Normal display
D4: Normal display mode (not partial display mode)
D3: Normal mode (stand-by release)
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
↓
<Power supply control sequence>
IR
D5 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
RS
Power supply control register 1 assignment
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
X
D6
D5
D4
D3
D8
D0
0
0
1
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator OFF
D0: DC/DC converter ON
↓
tDDRP is the output stable period of the DC/DC converter.
Although a setting of about 50 mS is the target, be sure to
finalize the timing after sufficient evaluation with the LCD module.
Wait time 1 (tDDRP)
↓
IR
Power supply control register 1 assignment
D5 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
↓
64
X
D6
D5
D4
D3
D8
D0
0
1
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator ON
D0: DC/DC converter ON
Data Sheet S15649EJ2V0DS
1
µ PD161622
↓
tRPRG is the output stable period of the DC/DC converter.
Although a setting of about 20 mS is the target, be sure to
finalize the timing after sufficient evaluation with the LCD module.
Wait time 2 (tRPRG)
↓
IR
Power supply control register 1 assignment
D5 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
X
D6
D5
D4
D3
D8
D0
1
Note
1
1
↓
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator ON
D1: Power supply IC regulator ON
D0: DC/DC converter ON
Note This setting can be deleted from the sequence when using
an IC with no regulator circuit for the gate driver.
Wait time 3 (tRGOE1)
Input DISP ON command after all power supply is set up.
Although a setting of about 1 mS is the target in tRPRG, be sure to
finalize the timing after sufficient evaluation with the LCD module.
↓
<Display ON>
IR
Control register 1 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
↓
R0
Control register 1 setting
↓
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
0
0
D5
X
X
X
X
D8
D0
X
0
0
0
0
0
D7: Normal display (all data “1” output → display ON)
D6: Normal display
D4: Normal display mode (not partial display mode)
D3: Normal mode (stand-by release)
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
Next transaction
Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not
meant for use in mass-production design.
Data Sheet S15649EJ2V0DS
65
µ PD161622
5.13 8-Color Dispaly Mode
The µ PD161622 contains an 8-color display function for low-power-consumption driving. The mode can be switched
to 8-color display mode by setting COLOR in control register 1 (R0) to 1.
As shown in the figure below, in 8-color display mode, the µ PD161622 controls ON/OFF of each dot using the MSB
of each dot data in the display RAM. It is therefore necessary to overwrite the display RAM data in accordance with
the screen of each mode when changing from 65,000-color display mode to 8-color mode, and vice versa.
In 8-color display mode, each source output is connected by switching the top and bottom grayscale voltages to
enable direct driving of the TFT panel, which results in low power consumption.
Figure 5–30.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Valid
Invalid
Invalid
Invalid
Invalid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Valid
Invalid
Invalid
Invalid
Invalid
Dot 1
Dot 2
1 pixel (= 1 x address)
66
Data Sheet S15649EJ2V0DS
Dot 3
µ PD161622
(1) 8-color display mode setting sequence example
Previous statement (65.000-color display mode)
↓
IR
Control register 1 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
↓
R0
Control register 1 assignment
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
0
1
D5
X
X
X
X
D8
D0
X
0
0
0
0
0
D7: Normal display
D6: All data “0” output (normally white: black output)
D4: Normal display mode (not partial display mode)
D3: Stand-by OFF
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
↓
<Data overwrite sequence>
In 8-color display mode, the value of the MSB of each dot data in
the internal display RAM is used as the color data, making it
necessary to overwrite the display RAM data when changing
from 65,000-color display mode to 8-color display mode.
IR
X address register assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
1
1
0
↓
R6
X address register setting
D7 to D0 X address register
D15
RS
D7
X
X
X
H
0
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
X address: 00H
↓
IR
Y address register assignment
D6 to D0 Index register
D15
RS
D7
L
D8
D0
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
↓
R7
Y address register setting
D7 to D0 Y address register
D15
RS
D7
H
↓
D8
D0
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
Y address: 00H
Data Sheet S15649EJ2V0DS
67
µ PD161622
↓
IR
Display memory register assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
0
X
1
X
1
X
0
D8
D0
X
0
↓
R12
D15 to D0 Display memory register
D15
D8
RS
D7
D0
D15
D10
X
X
X
X
X
X
H
D4
X
X
X
X
X
X
X
Caution D15, D10, and D4 are display memory data.
When in 8-color mode, only D15, D10, and D4 data are valid.
0: OFF, 1: ON, (normally white)
R12
D15 to D0 Display memory register
D15
D8
RS
D7
D0
D15
D10
X
X
X
X
X
X
H
D4
X
X
X
X
X
X
X
Caution D15, D10, and D4 are display memory data.
When in 8-color mode, only D15, D10, and D4 data are valid.
0: OFF, 1: ON, (normally white)
R12
D15 to D0 Display memory register
D15
D8
RS
D7
D0
D15
D10
X
X
X
X
X
X
H
D4
X
X
X
X
X
X
X
Caution D15, D10, and D4 are display memory data.
When in 8-color mode, only D15, D10, and D4 data are valid.
0: OFF, 1: ON, (normally white)
IR
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
Display data write 1
(start)
↓
Display data write 2
↓
Display data write n
(end)
↓
Control register 1 assignment
X
X
X
X
D8
D0
X
0
0
0
0
0
↓
R0
Control register 1 setting
↓
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
0
0
D5
X
X
X
X
D8
D0
X
0
0
1
D1
0
D7: Normal display
D6: Normal display (display ON [All data “0” display → normal
mode])
D4: Normal display mode (not partial display mode)
D3: Stand-by OFF
D2: 8-color display mode
D1: Power mode is set in accordance with the usage conditions.
D5 is set in accordance with the usage conditions.
Next transaction
Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not
meant for use in mass-production design.
68
Data Sheet S15649EJ2V0DS
µ PD161622
(2) Returning to 65,000-color display mode sequence
Previous statement (8-color display mode)
↓
IR
Control register 1 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
0
X
0
X
0
X
0
D8
D0
X
0
↓
R0
Control register 1 setting
↓
D7 to D0 Control register 1
D15
D8
RS
D7
D0
X
X
X
X
X
X
X
X
H
0
0
1
D1
0
0
0
D5
D7: Normal display
D6: All data “0” output (normally white: black output)
D4: Normal display mode (not partial display mode)
D3: Stand-by OFF
D2: 8-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
In 8-color display mode, the value of the MSB of each dot date in
the internal display RAM is used as the color data, making it
necessary to overwrite the display RAM data when returning to
65,000-color display mode from 8-color display mode.
<Data overwrite sequence>
IR
D6 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
1
D8
D0
X
0
X
0
D8
D0
X
0
X
1
D8
D0
X
1
X
0
D8
D0
X
0
RS
X address register assignment
X
0
X
0
X
1
↓
R6
X address register setting
↓
IR
Y address register assignment
D7 to D0 X address register
D15
RS
D7
X
X
X
H
0
0
0
X address: 00H
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
0
X
0
X
0
X
0
X
0
X
1
↓
R7
Y address register setting
↓
D7 to D0 Y address register
D15
RS
D7
X
X
X
H
0
0
0
Y address: 00H
Data Sheet S15649EJ2V0DS
X
0
X
0
X
0
69
µ PD161622
↓
IR
Display memory register assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
0
X
1
X
1
X
0
D8
D0
X
0
D9
D1
D8
D0
D8
D0
D9
D1
D8
D0
D8
D0
D9
D1
D8
D0
D8
D0
↓
R12
Display data write 1
(start)
↓
R12
Display data write 2
D15 to D0 Display memory register
D15
RS
D7
D15
D14
D13
D12
D11
D10
H
D7
D6
D5
D4
D3
D2
Caution D15 to D0 are display memory data.
D15 to D0 Display memory register
D15
RS
D7
D15
D14
D13
D12
D11
D10
H
D6
D5
D4
D3
D2
D7
Caution D15 to D0 are display memory data.
↓
R12
Display data write n
(end)
D15 to D0 Display memory register
D15
RS
D7
D15
D14
D13
D12
D11
D10
H
D7
D6
D5
D4
D3
D2
Caution D15 to D0 are display memory data.
↓
IR
Control register 1 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
↓
R0
Control register 1 setting
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
0
0
D5
X
X
X
X
D8
D0
X
0
0
0
0
0
D7: Normal display
D6: Normal display (display ON [All data “0” display → normal
mode])
D4: Normal display mode (not partial display mode)
D3: Stand-by OFF
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
↓
Next transaction
Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not
meant for use in mass-production design.
70
Data Sheet S15649EJ2V0DS
µ PD161622
5.14 Power ON/OFF
An example of the standard power ON/OFF sequence in a chipset for driving a TFT-LCD panel that uses µPD61622
is shown below. Note that this sequence diffes depending on the chipset configuration and TFT-LCD panel used.
(1) Power ON sequence
Power ON
Hard reset (/RESET = L)
↓
Hard reset release (/RESET =H)
↓
IR
Reset register assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
1
1
↓
R3
Reset register setting
D7 to D0 Reset register
D15
RS
D7
X
X
X
H
X
X
X
X
X
X
X
D8
D0
X
X
X
X
X
1
↓
<Initial status setting sequence>
IR
Power supply control register 1 assignment
D5 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
X
D6
D5
D4
D3
D8
D0
0
0
0
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator OFF
D0: DC/DC converter OFF
↓
IR
Power supply control register 2 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
1
0
↓
R26
Power supply control register 2 setting
D7 to D0 Power supply control register 2
D15
RS
D7
H
↓
X
X
X
X
X
D8
D0
X
D1
D0
D1 and D0 are set in accordance with the usage conditions.
Data Sheet S15649EJ2V0DS
71
µ PD161622
↓
IR
D6 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
X
X
D8
D0
X
1
1
1
RS
Power supply control register 1 assignment
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
X
X
X
X
X
H
D5
D4
D3
X
D6
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator ON
D1: Power supply IC regulator ON
D0: DC/DC converter ON
↓
IR
D6 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
1
0
1
X
X
D8
D0
X
1
1
1
RS
VCOM output center value setting register
assignment
↓
R29
VCOM output center value setting register setting
D7 to D0 Power supply control register 1
D15
RS
D7
X
X
X
X
X
H
D5
D4
D3
X
D6
D7 to D3 are set in accordance with the usage conditions.
This register setting is not required when VCOMC (D3) of the
output stage capacity setting register (R30) is 0.
↓
IR
Output stage capacity setting register assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
1
1
0
X
X
D8
D0
X
D2
D1
D0
↓
R30
Output stage capacity setting register setting
↓
72
D7 to D0 Power supply control register 1
D15
RS
D7
X
X
X
X
X
H
D5
D4
0
0
D6
D7: g-correction circuit reference voltage generation amplifier
drive/normal
D3: VCOM amplifier operation (when in used)
D6 to D4 are set in accordance with the usage conditions
(capacity setting for COMMON center value setting amplifier
(VCOM)).
D2 to D0 are set in accordance with the usage conditions (source
output capacity setting ).
Data Sheet S15649EJ2V0DS
µ PD161622
↓
IR
D6 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
RS
Control register 1 assignment
↓
R0
Control register 1 setting
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
1
0
D5
X
X
X
X
D8
D0
X
0
0
0
0
0
D7: All data “1” output (normally white: white output)
D6: Normal display
D4: Normal display mode (not partial display mode)
D3: Stand-by OFF
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
↓
IR
Control register 2 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
1
↓
R1
Control register 2 setting
D7 to D0 Control register 2
D15
RS
D7
X
X
X
H
X
X
D5
X
X
X
X
D8
D0
X
D4
0
0
0
0
D1: 1 line time = tcal (normal setting)
D0: Line inversion driving
D5 and D4 are set in accordance with the usage condtions.
Caution Always write 0 to D3 and D2.
↓
IR
Data access control register assignment
D6 to D0 Index register
D15
RS
D7
L
D8
D0
X
X
X
X
X
X
X
X
X
0
0
0
0
1
0
1
↓
R5
Data access control register setting
D7 to D0 Data access control register
D15
RS
D7
H
↓
D8
D0
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
D7: 16-bit data bus
D6: Normal write mode
D4: Normal operation (not window access mode)
D2: Access to X address direction
D1: X address increment
D0: Y address increment
Caution Always write 0 to D5 and D3.
↓
Data Sheet S15649EJ2V0DS
73
µ PD161622
↓
IR
D6 to D0 Index register
D15
D7
X
X
X
L
X
0
1
X
X
X
X
D8
D0
X
0
1
1
0
1
RS
Calibration register assignment
↓
R45
Calibration register setting
(calibration start)
D7 to D0 Calibration register
D15
RS
D7
X
X
X
H
X
X
X
X
X
X
X
D8
D0
X
X
X
X
X
1
↓
Calibration wait time (tcal)
tcal = 1 ÷ (frame frequency ×177)
Calibration time
↓
IR
Calibration register assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
1
X
X
X
X
D8
D0
X
0
1
1
0
1
X
X
D8
D0
X
0
↓
R45
Calibration register setting
(calibration stop)
D7 to D0 Calibration register
D15
RS
D7
X
X
X
H
X
X
X
X
X
X
X
X
X
↓
<Data write sequence>
IR
X address register assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
1
1
0
↓
R6
X address register setting
↓
IR
D7 to D0 X address register
D15
RS
D7
X
X
X
H
0
0
0
X address: 00H
X
X
X
0
0
0
0
0
X
1
D8
D0
X
1
X
0
D8
D0
X
0
D6 D0
RS
Y address register assignment
X
D8
D0
X
L
D15
D7
X
X
X
0
X
0
X
0
X
0
X
1
↓
R7
Y address register setting
↓
74
D7 to D0 Y address register
D15
RS
D7
X
X
X
H
0
0
0
Y address: 00H
Data Sheet S15649EJ2V0DS
X
0
X
0
X
0
µ PD161622
↓
IR
Display memory register assignment
D6 to D0 Index register
D15
RS
D7
L
D8
D0
X
X
X
X
X
X
X
X
X
0
0
0
1
1
0
0
↓
R12
Display data write 1
(start)
D15 to D0 Display memory register
D15
RS
D7
H
D8
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Caution D15 to D0 are display memory data.
↓
R12
Display data write 2
D15 to D0 Display memory register
D15
RS
D7
H
D8
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Caution D15 to D0 are display memory data.
↓
R12
Display data write n
(end)
D15 to D0 Display memory register
D15
RS
D7
H
D8
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Caution D15 to D0 are display memory data.
↓
IR
D6 to D0 Index register
D15
D7
D8
D0
RS
Control register 1 assignment
L
X
0
0
0
0
0
0
0
↓
R0
Control register 1 setting
↓
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
0
0
D5
X
X
X
X
D8
D0
X
0
0
0
0
0
D7: Normal display(display ON [All data “0” display → normal
mode])
D6: Normal display
D4: Normal display mode (not partial display mode)
D3: Stand-by OFF
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
Next transaction
Caution This sequence is shown only for the purpose of illustrating the sequence from power application to
display ON, and is not meant for use in mass production design. Note also that this sequence differs
depending on the configuration of the chipset and TFT-LCD module
Data Sheet S15649EJ2V0DS
75
µ PD161622
(2) Power OFF sequence
Operating status (normal display)
↓
IR
Control register 1 assignment
D6 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
0
0
0
0
0
↓
R0
Control register 1 setting
D7 to D0 Control register 1
D15
RS
D7
X
X
X
H
X
X
D5
X
X
X
X
D8
D0
X
0
1
0
0
0
D7: Don’t care
D6: Don’t care
D4: Normal display mode (not partial display mode)
D3: Stand-by ON
D2: 65,000-color display mode
D1: Normal power mode
D5 is set in accordance with the usage conditions.
The source output is automatically fixed to the VSS level by standby, so D7 and D6 can be set to any value.
↓
↓
Wait time 1 (tOE2RG)
↓
<Power supply control sequence>
At least one frame period
IR
Power supply control register 1 assignment
D5 to D0 Index register
D15
RS
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
↓
Wait time 2 (tRGRP)
X
D5
D4
D3
0
Note
1
1
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator ON
D0: DC/DC converter ON
Note This setting can be deleted from the sequence when using
an IC with no regulator circuit for the gate driver.
Although a setting of 0 ns has no negative effect in terms of the
device, be sure to finalize the timing after sufficient evaluation
with the LCD module.
↓
76
D6
D8
D0
Data Sheet S15649EJ2V0DS
µ PD161622
↓
IR
D5 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
RS
Power supply control register 1 assignment
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
X
D6
D5
D4
D3
D8
D0
0
0
1
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator OFF
D0: DC/DC converter ON
↓
Although a setting of 0 ns has no negative effect in terms of the
device, be sure to finalize the timing after sufficient evaluation
with the LCD module.
Wait time 3 (tRGRP)
↓
IR
D5 to D0 Index register
D15
D7
X
X
X
L
X
0
0
X
X
X
X
D8
D0
X
1
1
0
0
1
RS
Power supply control register 1 assignment
↓
R25
Power supply control register 1 setting
D7 to D0 Power supply control register 1
D15
RS
D7
H
↓
Hard reset (/RESET = L)
X
D6
D5
D4
D3
D8
D0
0
0
0
D6 to D3 are set in accordance with the usage conditions.
D2: Gate driver regulator OFF
D1: Power supply IC regulator OFF
D0: DC/DC converter OFF
Do not need to input RESET in source driver, however, when
power off, system reset is set up to /RESET = L by timing DCON
(R25: D0).
↓
Power OFF
Caution This sequence is shown only for the purpose of illustrating the sequence up to when the power is
turned off, and is not meant for use in mass-prodution design. Note also that this sequence differs
depending on the configuration of the chipset and TFT-LCD module.
Data Sheet S15649EJ2V0DS
77
µ PD161622
6. RESET
If the /RESET input becomes L or the reset command is input, the internal timing generator is initialized. The reset
command will also initialize each register to its default value. These default values are listed in the table below.
/RESET Pin
Note1
Reset Command
Default Value
Index register
IR
X
O
00H
Control register 1
R0
X
O
00H
Control register 2
R1
X
O
00H
Data access control register
R5
X
O
00H
X address register
R6
X
O
00H
Y address register
MIN. ⋅X address register
R7
X
O
00H
R8
X
O
00H
Register
Rn
MAX. ⋅X address register
R9
X
O
00H
MIN. ⋅Y address register
R10
X
O
00H
R11
X
O
00H
R12
X
X
−
Scroll area start line register
R15
X
O
00H
Scroll area line count register
R16
X
O
00H
Scroll step count register
R17
X
O
00H
Partial off area color register
R19
X
O
00H
Partial 1 display area start line register
R20
X
O
00H
Partial 2 display area start line register
R21
X
O
00H
Partial 1 display area line count register
R22
X
O
00H
Partial 2 display area line count register
R23
X
O
00H
Power supply control register 1
R25
X
O
00H
Power supply control register 2
R26
X
O
00H
VCOM output center value setting register
R29
X
O
00H
Output stage capacity setting register
γ-reference-voltage generator capacity setting register
R30
X
O
00H
R31
X
O
00H
γ-contrast value setting register 1
γ-contrast value setting register 2
γ-contrast value setting register 3
γ-contrast value setting register 4
R36
X
O
00H
R37
X
O
00H
R38
X
O
00H
R39
X
O
00H
Pre-charge direction setting data register
γ-correction input disconnect register
R40
X
O
00H
R42
X
O
00H
Calibration register
R45
X
O
00H
MIN. ⋅Y address register
Display memory register
Note2
Note 3
Pre-charge period supplement pulse setting register
R46
X
O
06H
Output port register
R49
X
O
00H
Input port register
R50
X
O
00H
Interface operating voltage setting register
R114
X
O
00H
Internal logic operating voltage setting register
R115
X
O
00H
X
O
00H
Test mode
Remark O: Default value set, X: Default value not set
Notes 1. The internal counters are initialized only by a reset from the /RESET pin. Be sure to perform reset via the
/RESET pin at power application.
2. The contents of RAM are saved in the case of both reset by /RESET pin and reset by reset command.
Note that the RAM contents are undifined. immediately after the power is turned on.
3. The following value is set as the calibration setting time, tcal, in a reset by reset command.
tcal = 1/fOSC x 37
78
Data Sheet S15649EJ2V0DS
µ PD161622
7. COMMAND
The µPD161622 identifies data bus signals by a combination of the RS, /RD (E), and /WR (R,/W) signals. It
interprets and executes commands only in accordance with the internal timing, without being dependent upon the
external clock. Therefore, the processing speed is extremely high and, usually, no busy check is necessary.
An i80 system CPU interface inputs a low pulse to the /RD pin when it reads data to issue a command. It inputs a
low pulse to the /WR pin when it writes data.
Data can be read from an M68 system CPU interface if a high-pulse signal is input to the R,/W pin, and written if a
low-pulse signal is input to the R,/W pin. A command is executed if a high-pulse signal is input to the E pin in this
status. Therefore, in the explanation of the commands and display commands after 7.2 Control Register 1 (R0) and
the sections that follow, the M68 system CPU interface uses H, instead of /RD (E), when reading status or display
data. This is how it differs from the i80 system CPU interface.
The commands of the µPD161622 are explained below, taking an i80 system CPU interface as an example. When
the serial interface is used, sequentially input data to the µPD161622, starting from D7.
The data bus length to input commands is as follows:
• Commands other than those that manipulate the display memory register (R12) are input in one byte unit,
regardless of the value of BMD (control register 2 (R1), bus length setting).
• The commands that manipulate the display memory register (R12) are input in 1-byte units when BMD = 1, or in
2-byte units when BMD = 0.
(1) Commands other than those that manipulate display memory register (R12)
BMD = 1 (8-bit data bus)
Pin
D7
D6
D5
D4
D3
D2
D1
D0
DATA
D7
D6
D5
D4
D3
D2
D1
D0
BMD = 0 (16-bit data bus)
Pin
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
Note
Note
Note
Note
Note
Note
Note
Note
D7
D6
D5
D4
D3
D2
D1
D0
Note 0 or 1
(2) Display Memory Register (R12)
BMD = 1 (8-bit data bus)
Pin
D7
D6
D5
D4
D3
D2
D1
D0
DATA
D7
D6
D5
D4
D3
D2
D1
D0
BMD = 0 (16-bit data bus)
Pin
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Sheet S15649EJ2V0DS
79
µ PD161622
7.1 Command List
CS
Index Register
RS
Rn
Register Name
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IR
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
1
0
R114 Interface operating voltage setting register
R115 Internal logic operating voltage setting register
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Remark
Index register
Control register 1
Control register 2
R/W
6
5
4
3
2
1
0
IR0
IR4
IR3
IR2
IR7
IR6
IR1
IR5
W
R/W DISP1 DISP0 ADC DTY STBY COLOR LPM GSM
R/W
VSEL GSEL
LTS INV
Reset register
W
CRES
BMD BSTR
XA7 XA6 XA5
YA7 YA6 YA5
WAS
XA4 XA3
YA4 YA3
Data access control register
X address register
Y address register
MIN. .X address register
MAX. . X address register
MIN. .Y address register
MAX. .Y address register
Display memory register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Scroll area start line register
Scroll area line count register
Scroll step count register
R/W SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0
R/W SAW7 SAW6 SAW5 SAW4 SAW3 SAW2 SAW1 SAW0
R/W SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0
Partial off area color register
Partial 1 display area start line register
Partial 2 display area start line register
Partial 1 display area line count register
Partial 2 display area line count register
R/W
R/W
R/W
R/W
R/W
Power supply control register 1
Power supply control register 2
R/W
R/W
VCOM output center value setting register
Output stage capacity setting register
-reference-voltage generator setting register
R/W EV7
R/W BPL
R/W WHP
γ-contrast value setting register 1
γ-contrast value setting register 2
γ-contrast value setting register 3
γ-contrast value setting register 4
Pre-charge direction setting data register
R/W
R/W
R/W
R/W
R/W
RDTP3 RDTP2 RDTP1 RDTP0 RDTN3 RDTN2 RDTN1 RDTN0
γ-correction input disconnect register
R/W
GHSW
Calibration register
Pre-charge period supplement pulse setting register
R/W
R/W
OC
PLIM6 PLIM5 PLIM4 PLIM3 PLIM2 PLIM1 PLIM0
Output port register
Input port register
R/W
R
R/W
R/W
: These registers cannot be used.
Cautions 1. If a write-only register is read, invalid data will be output.
2. A low level is output when an unused register is read.
80
Data Bits
7
Data Sheet S15649EJ2V0DS
INC XDIR YDIR
XA2 XA1 XA0
YA2 YA1 YA0
XMIN7 XMIN6 XMIN5 XMIN4 XMIN3 XMIN2 XMIN1 XMIN0
XMAX7 XMAX6 XMAX5 XMAX4 XMAX3 XMAX2 XMAX1 XMAX0
YMIN7 YMIN6 YMIN5 YMIN4 YMIN3 YMIN2 YMIN1 YMIN0
YMAX7 YMAX6 YMAX5 YMAX4 YMAX3 YMAX2 YMAX1 YMAX0
D7
D6
D5
D4
D3
D2
PGR
P1SL7
D1
D0
PGG PGB
P1SL6 P1SL5 P1SL4 P1SL3 P1SL2 P1SL1 P1SL0
P2SL7 P2SL6 P2SL5 P2SL4 P2SL3 P2SL2 P2SL1 P2SL0
P1AW7 P1AW6 P1AW5 P1AW4 P1AW3 P1AW2 P1AW1 P1AW0
P2AW7 P2AW6 P2AW5 P2AW4 P2AW3 P2AW2 P2AW1 P2AW0
BGRS VCE VCD2
PVCOM RGONG RGONP
DCON
VCD12 VCD11
GPH7
GNH7
GPL7
GNL7
OP7
EV6
CI2
WI2
EV5
CI1
WI1
EV4
CI0
WI0
VCOMC
GPH6
GNH6
GPL6
GNL6
GPH5
GNH5
GPL5
GNL5
GPH4
GNH4
GPL4
GNL4
OP6
OP5
OP4
EV3
BHP
EV2
SF2
BI2
EV1
SF1
BI1
EV0
SF0
BI0
GPH3
GNH3
GPL3
GNL3
GPH2
GNH2
GPL2
GNL2
GPH1
GNH1
GPL1
GNL1
GPH0
GNH0
GPL0
GNL0
OP3
IP3
OP2
IP2
OP1
IP1
OP0
IP0
RTSC1 RTSC0
RTSL1 RTSL0
µ PD161622
7.2 Command Explanation
(1/9)
Resistor
R0
Bit
D7
Symbol
DISP1
Function
This command performs the same output as when all data is 1, independently of the internal
RAM data (white display in the case of normally white).
This command is executed, after it has been transferred, when the next line is output.
0: Normal operation
1: Ignores data of RAM and outputs all data as 1.
DISP1 takes precedence over DISP0. When DISP1 = H, DISP0 = H is ignored.
D6
DISP0
This command performs the same output as when all data is 0, independently of the internal
RAM data (black display in the case of normally white).
This command is executed, after it has been transferred, when the next line is output.
0: Normal operation
1: Ignores data of RAM and outputs all data as 0.
D5
ADC
Column address direction
This command can be used to select the direction of source driver output. For more detail, refer
to 5.2.3 Column address circuit
D4
DTY
This pin selects the partial function.
When partial display mode is selected, partial off area color is displayed by setting partial off area
color register (R19).
The power consumption cannot be reduced with the partial function. To reduce the power
consumption, select the 8-color mode.
This command is executed following transfer from the time the next line data is output.
0: Normal display mode
1: Partial display mode
D3
STBY
This bit selects the stand-by function. When the stand-by function is selected, a display OFF
operation is executed and the amplifiers at each output stage and the operation of internal
oscillation circuit are stopped.
However, stand-by control cannot be performed for the gate IC (µ PD161640) connected to
µ PD161622 and the power-supply IC (µ PD161660). Therefore, after executing the stand-by
function using this bit, set both the regulator for the gate IC and power-supply IC to off and set
the DC/DC converter to OFF. For the sequence, refer to the preliminary product information
machine of the µ PD161660.
Note that when releasing stand-by, perform the opposite operation, i.e., after setting the DC/DC
converter to ON and setting the regulators of the gate IC and power-supply IC to ON, execute
the normal operation command.
0: Normal operation
1: Stand-by function
(display read off from RAM, stop both OSC and VCOM, display OFF = entire data is output as 1)
D2
COLOR
This pin switches the 65,000-color mode and the 8-color mode. When the 8-color mode is
selected, low power supply can be selected in order to stop the amplifier at each output stage.
In the 8-color mode, the value of the MSB of the internal RAM data is used as the color data.
This command is executed following transfer from the time the next line data is output.
0: 65,000-color mode (16 bits/pixels)
1: 8-color mode (3 bits/pixels)
Data Sheet S15649EJ2V0DS
81
µ PD161622
(2/9)
Resistor
R0
Bit
D1
Symbol
LPM
Function
This bit is used when setting the gate IC (µ PD161640) and power-supply IC (µ PD161660) to
the low-power mode. When the low-power mode is selected, the LPMG pin and the LPMP pin
signals change from low to high (output changes immediately following command execution.).
The LPMG pin must be connected to the LPM pin of the gate IC, and the LPMP pin must be
connected to the LPM pin of the power-supply IC.
0: Normal
1: Low power mode
D0
GSM
Sets output of the gate scanning signal during partial display.
When 1 is selected, gate scanning of the line set in the partial non-display area is stopped.
0: Normal mode
1: Stops gate scanning in partial non-display area
R1
D5
VSEL
Sets the potential of the pre-charge output of the LCD driver.
The maximum/minimum output potential of the pre-charge output is:
0: Power supply voltage (outputs VS and VSS)
1: Maximum output level of internal γ-output adjustment circuit (uses VPH, VNH, VPL, VNL)
IF VSEL = 0, VS or VSS is automatically output as the pre-charge output.
D4
GSEL
Sets the maximum/minimum output voltage of the γ-correction resistor.
If the internal γ-output adjustment circuit is selected, the maximum/minimum output potential of
the γ-correction resistor is:
0: Supply voltage (outputs VS and VSS).
1: Voltage of internal γ-output adjustment circuit (uses VPH, VNH, VPL, VNL) 8-color mode (3
bits/pixels)
D1
LTS
Selects set time of calibration.
The calibration function adjusts the frame frequency by setting time of one line. This command
can select the set time of a line from the following:
0: 1 line time = tcal
1: 1 line time = tcal x 2
(tcal: Calibration set time1 = 1 ÷ Frame frequency ÷ Number of displayed lines)
D0
INV
This bit selects between the line inversion function and the frame inversion function.
The mode selected by this command is executed from the start of the next scan after the gate
scan in progress when this command was executed has completed 176 lines. When the reset
command is input, the INV register is initialized. 0: Line inversion with same line.
0: Line inversion
1: Frame inversion
R3
D0
CRES
Command reset function. Be sure to execute this bit after power ON.
Command reset automatically clears this bit following execution (CRES = 01H). Therefore, it is
not necessary to set 0 (select normal operation) again by software. Moreover, since the time
required for the value of this bit to change (1 → 0) following command reset execution is
extremely short, it is not necessary to secure time until the next command is set following
command reset setting.
0: Normal operation
1: Command reset
82
Data Sheet S15649EJ2V0DS
µ PD161622
(3/9)
Resistor
R5
Bit
D7
Symbol
BMD
Function
Sets the bus width when the parallel interface is used.
0: 16-bit data bus
1: 8-bit data bus
This command is invalid when the serial interface is used.
D6
BSTR
Sets the write mode for writing data to the display RAM.
If the high-speed RAM write mode is selected, data is written to the display RAM in 64-bit units
inside the µ PD161622. When selecting the high-speed RAM write mode, be sure to write data
to the display RAM in 64-bit units.
0: Normal write mode (16-bit access)
1: High-speed RAM write mode (64-bit access)
D4
WAS
Window access mode setting
When the window access mode is set, the address is incremented/decremented only in the
range set by the MIN. ⋅X address setting register (R8), MAX. ⋅X address setting register (R9),
MIN. ⋅Y address setting register (R10), and MAX. ⋅Y address setting register (R11).
0: Normal operation
1: Window access mode
D2
INC
Selects the direction in which the display RAM address is to be incremented/decremented.
Whether the X address and Y address are incremented or decremented is specified by XDIR
(R5: D1) and YDIR (R5: D0), respectively.
0: Access in X address direction
1: Access in Y address direction
D1
XDIR
Specifies whether the display RAM address is incremented or decremented in the X address
direction.
0: Increments X address
1: Decrements X address
D0
YDIR
Specifies whether the display RAM address is incremented or decremented in the Y address
direction.
0: X address increment
1: X address decrement
R6
D7 to D0
XAn
This register sets the X address of the display RAM.
Set a value between 00H and 83H.
R7
D7 to D0
YAn
This register sets the Y address of the display RAM.
Set a value between 00H and AFH.
R8
D7 to D0
XMINn
Sets the minimum value of the X address in the window access mode.
The X address is incremented up to the maximum value set by the MAX. ⋅X address register
(R9), and then initialized to the address value set by this command. (R5: XDIR = 0)
Set a value between 00H to 82H.
R9
D7 to D0
XMAXn
Sets the maximum value of the X address in the window access mode.
The X address is incremented up to the maximum value set by the MIN. ⋅X address register
(R8), and then initialized to the address value set by this command. (R5: XDIR = 0)
Set a value between 01H to 83H.
R10
D7 to D0
YMINn
Sets the minimum value of the T address in the window access mode.
The Y address is incremented up to the maximum value set by the MAX. ⋅Y address register
(R11), and then initialized to the address value set by this command.
(R5: YDIR = 0)
Set a value between 00H to AEH.
Data Sheet S15649EJ2V0DS
83
µ PD161622
(4/9)
Resistor
R11
Bit
D7 to D0
Symbol
YMAXn
Function
Sets the maximum value of the Y address in the window access mode.
The Y address is incremented up to the address value set by this command, and then
initialized to the minimum address value set by the MIN. Y address register (R10)
(R5: YDIR = 0)
Set a value between 01H to AFH.
R12
D7 to D0
Dn
These bits are used for reading/writing data from/to display memory (internal RAM).
R15
D7 to D0
SSLn
Scroll area start line register (00H to AFH)
When the screen is scrolled, the screen of the number of lines set by the scroll area line count
register (R16) is scrolled up by the number of steps set by the scroll step count register (R17),
starting from the line set by this command.
R16
D7 to D0
SAWn
Scroll area line count register (00H to AFH)
When the screen is scrolled, the screen of the number of lines set by this command is scrolled
up by the number of steps set by the scroll step count register (R17), starting from the line set
by the scroll area start line register (R15)
R17
D7 to D0
SSTn
Scroll step count register (00H to AFH)
When the screen is scrolled, the screen of the number of lines set by the scroll area line count
register (R16) and the scroll step count register (R17) is scrolled up by the number of steps set
by this command.
Note that because this command is invalid in the partial display mode, the scroll function
cannot be used.
R19
D2
PGR
Partial off area color register
Sets the color of the screen other than the partial display area during partial display (R0: DTY
= 1). One of eight colors can be selected (RGB: 1 bit each) as the off color.
D1
PGG
The relationship between each color data and the bits of this register is as follows. This
relationship is not dependent upon the value of ADC.
D0
PGB
D7 to D0
P1SLn
PGR: R OFF= 0, ON = 1
PGG: G OFF= 0, ON = 1
PGB: B OFF= 0, ON = 1
R20
Partial 1 display area start line register (00H to AFH)
During partial display (R0: DTY = 1), the area starting from the line set by this command and
ending as set by the partial 1 display area line count register (R22) is the partial 1 display area.
R21
D7 to D0
P2SLn
Partial 2 display area start line register (00H to AFH)
During partial display (R0: DTY = 1), the area starting from the line set by this command and
ending as set by the partial 2 display area line count register (R23) is the partial 2 display area.
R22
D7 to D0
P1AWn
Partial 1 display area line count register (00H to AFH)
An area starting from the line set by the partial 1 display area start register (R20) and ending
as set by this command is the partial 1 display area.
If this register is 0, the values of the partial 2 display area start line register (R29) and the
partial 2 display area line count register (R31) are not valid.
R23
D7 to D0
P2AWn
Partial 2 display area line count register (00H to AFH)
An area starting from the line set by the partial 2 display area start register (R21) and ending
as set by this command is the partial 2 display area.
If the partial 1 display area line count register is 0, the values of the partial 2 display area start
line register (R21) and partial 2 display area line count register (R23) are not valid.
84
Data Sheet S15649EJ2V0DS
µ PD161622
(5/9)
Resistor
R25
Bit
D6
Symbol
BGRS
Function
This pin selects whether to use the internal power supply or an external power supply (input
from the BRGIN pin) for generation the common center voltage output from the VCOM pin.
0: The internal power-supply is selected as the VCOM power supply
1: Input from the external power-supply BGRIN is selected as the VCOM power supply
D5
VCE
Selects the VO output level of the power-supply IC (µ PD161660).
The VCE pin of the µ PD161622 and the VCE pin of the power-supply IC must be connected.
0: The Vo high-level booster voltage level is VDD1 minus 1 level
1: The Vo high-level booster voltage level is the same level as VDD1
D4
VCD2
Selects the VDD2 output level of the power-supply IC (µ PD161660).
The VCD2 pin of the µ PD161622 and the VCD2 pin of the power-supply IC must be connected.
0: VDD2 = VDC × 2
1: VDD2 = VCD × 3
D3
PVCOM
Sets the pre-charge time of a 1-line output period.
0: VBGR (3.0 V TYP.)
1: VS
D2
RGONG
Switches the internal regulator of the gate IC (µ PD161640) ON/OFF.
When OFF is selected, a low level is output from the RGONG pin, and when ON is selected, a
high level is output from the RGONG pin.
The RGONG pin of the µ PD161622 and the RGON pin of the gate IC must be connected.
0: Regulators of gate driver (VB) are OFF
1: Regulators of gate driver (VB) are ON
D1
RGONP
Switches the internal DC/DC converter of the power-supply IC (µ PD161660) ON/OFF.
When OFF is selected, a low level is output from the RGONP pin, and when ON is selected, a
high level is output from the RGONP pin.
The RGONP pin of the µ PD161622 and the RGON pin of the power-supply IC must be
connected.
0: Regulators of power-supply IC (VT, VS) are OFF
1: Regulators of power-supply IC (VT, VS) are ON
D0
DCON
Switches the internal DC/DC converter of the power-supply IC (µ PD161660) ON/OFF.
When OFF is selected, a low level is output from the DCON pin, and when ON is selected, a
high level is output from the DCON pin.
The DCON pin of this IC and the DCON pin of the power-supply IC must be connected.
0: DC/DC converter is OFF
1: DC/DC converter is ON
R26
D1
VCD12
Performs booster control for the DC/DC converter in the power-supply IC (µ PD161660)
The data set with this bit is output from the VCD11 pin and the VCD12 pin.
The VCD11 pin and VCD12 pin of µ PD161622 must be connected to the VCD11 pin and the VCD12
D0
VCD11
pin of the power-supply IC.
VCD12, VCD11 = 0, 0: VDD1 = VDC × 4
= 0, 1: VDD1 = VDC × 5
= 1, 0: VDD1 = VDC × 6
= 1, 1: VDD1 = VDC × 7
Data Sheet S15649EJ2V0DS
85
µ PD161622
(6/9)
Resistor
R29
Bit
D7 to D0
Symbol
EVn
Function
Sets the D/A converter circuit used to adjust the voltage of the reference voltage generator
circuit (VBGR) input to the voltage regulator that sets the center value of the panel common drive
output. The D/A converter divides the constant voltage generated by the reference voltage
generator (VBGR) by 256, and one level can be selected between VBGR and VSS by setting this
command.
For more detail, refer to 5.5 Common Adjustment Circuit and 5.8 D/A Converter Circuit.
R30
D7
BPL
Switched the capacity of the γ-correction circuit reference voltage generation amplifiers on the
side not being used (VPH, VPL, VNH, VNL) to the minimum value based on the polarity inversion
timing in order to reduce the current consumption.
Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used.
0: Normal
1: Reference voltage generation amplifier capacity switch drive
D6 to D4
CIn
Sets the bias current of the amplifier for setting the panel’s COMMON drive waveform center
value (VCOM), as shown in the table below.
Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used.
D3
VCOMC
CI2
CI1
CI0
0
0
0
0.20 µA
VCOM Center Value Setting Amplifier Bias Current Value
0
0
1
0.50 µA
0
1
0
0.10 µA
0
1
1
0.05 µA
1
0
0
1.00 µA
1
0
1
1.50 µA
1
1
0
2.00 µA
1
1
1
3.00 µA
Selects whether to use the amplifier for setting the panel’s COMMON drive waveform center
value (VCOM) or not.
This amplifier can be used under conditions such as when an external COMMON drive circuit is
being used.
0: VCOM amplifier operating
1: VCOM amplifier stopped
D2 to D0
SFn
Sets the capacity of the source output (S1 to S396), as shown in the table below.
Determine the output capacity after sufficient evaluation with the actual TFT panel to be used.
86
SF2
SF1
SF0
0
0
0
0.20 µA
Source Output Bias Current Value
0
0
1
0.15 µA
0
1
0
0.25 µA
0
1
1
0.10 µA
1
0
0
0.20 µA
1
0
1
0.30 µA
1
1
0
0.40 µA
1
1
1
0.05 µA
Data Sheet S15649EJ2V0DS
µ PD161622
(7/9)
Register
R31
Bit
D7
Symbol
WHP
Function
Sets the output mode of the reference voltage generator amplifier for setting the white level of
the positive-polarity and negative-polarity sides (when VPL and VNL are normally white), as
shown below.
Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used.
0: Normal mode
1: High-power mode (output stage capacity: twice that of normal mode)
D6 to D4
WIn
Sets the output bias current of the reference voltage generator amplifier for setting the white level
of the positive-polarity and negative-polarity sides (when VPL and VNL are normally white), as
shown below.
D3
BHP
WI2
WI1
WI0
0
0
0
0.20 µA
Amplifier Bias Current
0
0
1
0.50 µA
0
1
0
0.10 µA
0
1
1
0.05 µA
1
0
0
1.00 µA
1
0
1
1.50 µA
1
1
0
2.00 µA
1
1
1
3.00 µA
Sets the output mode of the reference voltage generator amplifier for setting the black level of
the positive-polarity and negative-polarity sides (when VPH and VNH are normally white), as
shown below.
Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used.
0: Normal mode
1: High-power mode (output stage capacity: twice that of normal mode)
D2 to D0
BIn
Sets the output bias current of the reference voltage generator amplifier for setting the black level
of the positive-polarity and negative-polarity sides (when VPH and VNH are normally white), as
shown below.
Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used.
R36
D7 to D0
GPHn
BI2
BI1
BI0
0
0
0
0.20 µA
Amplifier Bias Current
0
0
1
0.50 µA
0
1
0
0.10 µA
0
1
1
0.05 µA
1
0
0
1.00 µA
1
0
1
1.50 µA
1
1
0
2.00 µA
1
1
1
3.00 µA
Sets the voltage value of the black level of positive polarity.
For more det020ail, refer to 5.9 γ -Curve Correction Power Supply Circuit.
R37
D7 to D0
GNHn
Sets the voltage value of the white level of negative polarity.
For more detail, refer to 5.9 γ-Curve Correction Power Supply Circuit.
R38
D7 to D0
GPLn
R39
D7 to D0
GNLn
Sets the voltage value of the white level of positive polarity.
For more detail, refer to 5.9 γ-Curve Correction Power Supply Circuit.
Sets the voltage value of the white level of positive polarity.
For more detail, refer to 5.9 γ-Curve Correction Power Supply Circuit.
Data Sheet S15649EJ2V0DS
87
µ PD161622
(8/9)
Register
R40
Bit
D7 to D4
Symbol
RDTPn
Function
Sets the data value at which the pre-charge direction is switched during positive-polarity drive.
The value set to RDTPn corresponds to the higher 4bits of display RAM data DBn (6 bits for each
of RFB), as shown below.
D3 to D0
RDTNn
RDTP3
RDTP2
RDTP1
RDTP0
Dot 1 (R)
D15
D14
D13
D12
Dot 2 (G)
D10
D9
D8
D7
Dot 3 (B)
D4
D3
D2
D1
Sets the data value at which the pre-charge direction is switched during negative-polarity drive.
The value set to RDTNn corresponds to the higher 4 bits of display RAM data DBn (6 bits for
each of RGB), as shown below.
R42
D0
GHSW
RDTN3
RDTN2
RDTN1
RDTN0
Dot 1 (R)
D15
D14
D13
D12
Dot 2 (G)
D10
D9
D8
D7
Dot 3 (B)
D4
D3
D2
D1
Controls the γ-correction voltage input pins (V0 to V5) and the switch for connecting
the µ PD161622 internal γ-correction resistor.
0: Switch OFF (disconnected)
1: Switch ON (connected)
R45
D0
OC
This bit is used for calibration.
The time from calibration start command execution until calibration stop command execution
becomes the time for 1 line.
0: Calibration stop
1: Calibration start
R46
D7 to D0
PLIMn
Set the pre-charge time of a 1-line output period.
The number of clocks set in this register + 2 CLK (1/fOSC) becomes the pre-charge time when one
line is driven.
For details, refer to 5.4.1 Drive timing
R49
D7 to D0
OPn
Output port (OP7 to OP0) write
When after the output port register (R49) is specified in the index register, writing to the
γ-correction input disconnect register (R42) is performed, the values written to the OP7 to OP0
pins are output.
R50
D3 to D0
IPn
Input port (IP3 to IP0) read
To read the IP3 to IP0 inputs, use the following method.
<Read sequence>
<1> Specify the input port register (R50) from the index register.
↓
<2> Execute input port register (R50) read.
88
Data Sheet S15649EJ2V0DS
µ PD161622
(9/9)
Register
R114
Bit
D1, D0
Symbol
RTSCn
Function
Selects the optimum internal circuit operation based on the operating voltage of the interface
circuits. The following settings are recommended based on this register.
RTSC1
RTSC0
1
1
Caution Always set this register and internal logic operating voltage setting register
(R115) to the same value.
R115
D1, D0
RTSLn
Selects the optimum internal circuit operation based on the operating voltage of the internal logic
circuits. The following settings are recommended based on this register.
RTSC1
RTSC0
1
1
Caution Always set this register and interface operating voltage setting register (R114) to
the same value.
Data Sheet S15649EJ2V0DS
89
µ PD161622
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Symbol
Ratings
Unit
Power supply voltage
VS
–0.5 to +6.5
V
Power supply voltage
VCC1
–0.5 to +4.0
V
Power supply voltage
VCC2
–0.5 to VCC1 + 0.5
V
Power supply voltage for γ-curve correction
V1 to V5
–0.5 to VS + 0.5
V
Input voltage
VI
–0.5 to VCC1 + 0.5
V
Input current
II
±10
mA
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = –40 to +85°C, VSS = 0 V)
Parameter
Power supply voltage
Input voltage
Symbol
MIN.
TYP.
MAX.
Unit
VS
4.3
5.0
5.5
V
VCC1
2.5
2.7
3.6
V
VCC2
1.7
1.8
VCC1
V
0
VCC1
V
0
VCC2
V
VI1
VI2
Note1
Note2
Notes 1. Pins of VCC1 power-supply system: TOUT0 to TOUT15, IP0 to IP3, OP0 to OP7, LPMG, LPMP, GOE1, GOE2,
GSTB, GCLK, DCON, RGONP, RGONG, VCD11, VCD12, VCD2, VCE, RSEL,
TSTRTST, TSTVIHL, OSCIN
2. Pins of VCC2 power-supply system: /CS, /RD(E), /WR(R,/W), D0 to D5, D6(SCL), D7(SI), RS, /RESET, C86,
PSX
90
Data Sheet S15649EJ2V0DS
µ PD161622
Electrical Specifications (Unless Otherwise Specified, TA = –40 to +85°C, VCC1 = 2.5 to 3.6 V,
VCC2 = 1.7 V to VCC1, VS = 4.3 to 5.5 V)
Parameter
Symbol
Specification
Condition
MIN.
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
VCOM output voltage
High level input current
Low level input current
High level leakage current
Low level leakage current
High level driver output
MAX.
VIH1
0.8 VCC1
V
VIH2
VCC2
0.8 VCC2
V
VIL1
VCC1
0.2 VCC1
V
0.2 VCC2
V
VIL2
VCC2
VOH1
VCC1, IOUT = –100 µA
0.9 VCC1
V
VOH2
VCC2, IOUT = –1 mA
0.8 VCC2
V
VOH3
VCOUT1, VCOUT2, IOUT = –100 µA
VOL1
VCC1, IOUT = 100 µA
0.1 VCC1
V
VOL2
VCC2, IOUT = 1 mA
0.2 VCC2
V
VOL3
VCOUT1, VCOUT2, IOUT = 100 µA
0.1 VS
V
VCOMH
ISOURCE = 100 µA
VCOML
ISINK = –100 µA
VCOM + 0.3
mV
IIH1
Except D0 to D15
1
µA
IIL1
Except D0 to D15
–1
µA
ILIH
D0 to D15
10
µA
ILIL
D0 to D15
–10
µA
IVOH
VX = 3.5 V, VOUT = 4.5 V,
VS = 5.0 V
IVOL
V
0.9 VS
VCOM − 0.3
mV
µA
−85
Note2
VX = 1.5 V, VOUT = 0.5 V,
VS = 5.0 V
current
VCOM common output
Unit
VCC1
current
Low level driver output
TYP.
Note1
Note2
∆VCOM
−10
30
µA
10
%
voltage fluctuation parameter
Current consumption
ICC1
VCC1 (when non-access CPU)
140
240
µA
ICC2
VCC2 (when non-access CPU)
0.2
5
µA
ISTBY
VCC1 (stand-by mode)
1
10
µA
IS
VS (65,000-color mode)
600
1000
µA
45
100
µA
–0.14
–0.07
VS (8-color mode)
Note3
Note3
Driver output Current
IVOH
VS = 5.0 V, VOUT = VS – 0.1 V
(pre-charge)
IVOL
VS = 5.0 V, VOUT = VS + 0.1 V
Output voltage deviation
∆VO1
VOUT = 1.3 V to (VS − 1.3 V)
∆VO2
VOUT = 0.3 to 1.3 V
Note2
Note2
Note2
Note2
,
0.1
0.25
mA
mA
−20
20
mV
−30
30
mV
(VS − 1.3 V) to (VS − 0.3 V)
Notes 1. TYP. values are reference values when TA = 25°C
2. VX refers to the output voltage of analog output pins S1 to S396.
VOUT refers to the voltage applied to analog output pins S1 to S396
3. Frame frequency, line inversion mode selection, dot checkerboard input pattern, no load
Data Sheet S15649EJ2V0DS
91
µ PD161622
Switching characteristics (Unless Otherwise Specified, TA = –40 to +85°C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 V to
VCC1, VS = 5.0 V)
Pre-charge period
tPLH1
Driver output period
tPHL2
VO MAX. −200 mV
Goal voltage +200 mV
VOUT
Goal voltage −200 mV
VO MIN. +200 mV
tPHL1
tPLH2
Note
TYP.
MAX.
Unit
Driver output delay time 1
tPLH1
VS = 5.0 V,
VO MAX. –200 mV
40
µs
(pre-charge period)
tPHL1
4 kΩ +27 pF
VO MIN. +200 mV
70
µs
Driver output delay time 2
tPLH2
Pre-charge completed
50
µs
60
µs
Parameter
Symbol
Condition
→ goal voltage –200 mV
(driver output period)
tPHL2
Pre-charge completed
→ goal voltage +200 mV
Note TYP. values are reference values when TA = 25°C.
92
MIN.
Data Sheet S15649EJ2V0DS
µ PD161622
AC Characteristics (Unless Otherwise Specified, TA = –40 to +85°C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 V to VCC1)
(a) i80 series CPU interface
RS
tAS8
tf
tAH8
tr
/CS
tCYC8
tCCLW, tCCLR
/WR, /RD
tCCHR, tCCHW
tDS8
tDH8
D0 to D15 (D7)
(Write)
tACC8
tOH8
D0 to D15 (D7)
(Read)
Data Sheet S15649EJ2V0DS
93
µ PD161622
When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2 (normal write mode, R114 and R115 = 03H)
Parameter
Address hold time
Symbol
Condition
tAH8
RS
Address setup time
tAS8
RS
System cycle time
tCYC8
Control low-level pulse width (/WR)
tCCLW
Control low-level pulse width (/RD)
Control high-level pulse width (/WR)
MIN.
0
Note
TYP.
MAX.
0
Unit
ns
ns
250
ns
/WR
60
ns
tCCLR
/RD
140
ns
tCCHW
/WR
60
ns
Control high-level pulse width (/RD)
tCCHR
/RD
80
ns
Data setup time
tDS8
D0 to D15
60
ns
Data hold time
tDH8
D0 to D15
0
/RD access time
tACC8
D0 to D15, CL = 100 pF
Output disable time
tOH8
D0 to D15, CL = 5 pF
ns
10
110
ns
100
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 ≥ VCC2 (normal write mode, R114 and R115 = 03H)
Parameter
Address hold time
Symbol
Condition
tAH8
RS
Address setup time
tAS8
RS
System cycle time
tCYC8
Control low-level pulse width (/WR)
tCCLW
Control low-level pulse width (/RD)
tCCLR
MIN.
0
Note
TYP.
MAX.
Unit
ns
0
ns
333
ns
/WR
60
ns
/RD
160
ns
Control high-level pulse width (/WR)
tCCHW
/WR
100
ns
Control high-level pulse width (/RD)
tCCHR
/RD
140
ns
Data setup time
tDS8
D0 to D15
60
ns
Data hold time
tDH8
D0 to D15
0
ns
/RD access time
tACC8
D0 to D15, CL = 100 pF
Output disable time
tOH8
D0 to D15, CL = 5 pF
10
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
94
Data Sheet S15649EJ2V0DS
150
ns
150
ns
µ PD161622
When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2 (high-speed RAM write mode, valid only for writing data
R114 and R115 = 03H)
Symbol
Condition
Note
TYP.
MAX.
Unit
ns
Parameter
Address hold time
tAH8
RS
MIN.
0
Address setup time
tAS8
RS
0
System cycle time
tCYC8
62
ns
Control low-level pulse width (/WR)
tCCLW
/WR
35
ns
Control high-level pulse width (/WR)
tCCHW
/WR
25
ns
Data setup time
tDS8
D0 to D15
25
ns
Data hold time
tDH8
D0 to D15
0
ns
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 ≥ VCC2, (high-speed RAM write mode, valid only for writing data,
R114 and R115 = 03H)
Parameter
Address hold time
Symbol
Condition
tAH8
RS
Address setup time
tAS8
RS
System cycle time
tCYC8
Control low-level pulse width (/WR)
tCCLW
MIN.
0
0
Note
TYP.
MAX.
Unit
ns
ns
83
ns
/WR
35
ns
Control high-level pulse width (/WR)
tCCHW
/WR
30
ns
Data setup time
tDS8
D0 to D15
30
ns
Data hold time
tDH8
D0 to D15
0
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
Data Sheet S15649EJ2V0DS
95
µ PD161622
(b) M68 series CPU interface
RS
R,/W
tAS6
tf
tAH6
tr
/CS
tCYC6
tEWHR, tEWHW
E
tEWLR, tEWLW
tDS6
tDH6
D0 to D15 (D7)
(Write)
tACC6
D0 to D15 (D7)
(Read)
96
Data Sheet S15649EJ2V0DS
tOH6
µ PD161622
When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2 (normal mode, R114 and R115 = 03H)
Parameter
Address hold time
Symbol
tAH6
Condition
RS
Address setup time
tAS6
RS
System cycle time
tCYC6
Data setup time
tDS6
Data hold time
Access time
MIN.
0
Note
TYP.
MAX.
Unit
ns
0
ns
250
ns
D0 to D15
80
ns
tDH6
D0 to D15
0
tACC6
D0 to D15, CL = 100 pF
Output disable time
tOH6
D0 to D15, CL = 5 pF
10
Enable high pulse width
Read
tEWHR
E
140
ns
Write
tEWHW
E
120
ns
Read
tEWLR
E
80
ns
Write
tEWLW
E
60
ns
Enable low pulse width
ns
110
100
ns
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VCC2.
When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 ≥ VCC2 (normal mode, R114 and R115 = 03H)
Parameter
Address hold time
Symbol
tAH6
Condition
RS
Address setup time
tAS6
RS
System cycle time
tCYC6
Data setup time
tDS6
Data hold time
tDH6
MIN.
0
Note
TYP.
MAX.
Unit
ns
0
ns
333
ns
D0 to D15
100
ns
D0 to D15
0
ns
Access time
tACC6
D0 to D15, CL = 100 pF
Output disable time
tOH6
D0 to D15, CL = 5 pF
10
Read
tEWHR
E
160
Write
tEWHW
E
120
ns
Read
tEWLR
E
140
ns
Write
tEWLW
E
100
ns
Enable high pulse width
Enable low pulse width
150
ns
150
ns
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VCC2.
Data Sheet S15649EJ2V0DS
97
µ PD161622
When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2 (high-speed RAM write mode, valid only for writing data,
R114 and R115 = 03H)
Condition
Note
TYP.
MAX.
Unit
ns
Parameter
Address hold time
Symbol
tAH6
RS
MIN.
0
Address setup time
tAS6
RS
0
ns
System cycle time
tCYC6
62
ns
Data setup time
tDS6
D0 to D15
20
ns
Data hold time
tDH6
D0 to D15
0
ns
Enable high pulse width
tEWHR
E
35
ns
Enable low pulse width
tEWLR
E
20
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VCC2.
When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 ≥ VCC2 (high-speed RAM write mode, valid only for writing data)
Condition
MIN.
0
Note
TYP.
MAX.
Unit
ns
Parameter
Address hold time
Symbol
tAH6
RS
Address setup time
tAS6
RS
System cycle time
tCYC6
Data setup time
tDS6
D0 to D15
Data hold time
tDH6
D0 to D15
0
ns
Enable high pulse width
tEWHR
E
40
ns
Enable low pulse width
tEWLR
E
30
ns
0
ns
83
ns
30
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VCC2.
98
Data Sheet S15649EJ2V0DS
µ PD161622
(c) Serial interface
tCSS
tCSH
/CS
tSAS
tSAH
RS
tSCYC
tSLW
SCL
tSHW
tf
tSDS
tr
tSDH
SI
VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 ≥ VCC2
Parameter
Symbol
Condition
MIN.
TYP.
Note
MAX.
Unit
Serial clock cycle
tSCYC
SCL
250
ns
SCL high-level pulse width
tSHW
SCL
100
ns
SCL low-level pulse width
tSLW
SCL
100
ns
Address hold time
tSAH
RS
150
ns
Address setup time
tSAS
RS
150
ns
Data setup time
tSDS
SI
100
ns
Data hold time
tSDH
SI
100
ns
CS - SCL time
tCSS
/CS
150
ns
tCSH
/CS
150
ns
Note TYP. values are reference values when TA = 25°C.
VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2
Parameter
Serial clock cycle
Symbol
tSCYC
Condition
SCL
MIN.
TYP.
150
Note
MAX.
Unit
ns
SCL high-level pulse width
tSHW
SCL
60
ns
SCL low-level pulse width
tSLW
SCL
60
ns
Address hold time
tSAH
RS
90
ns
Address setup time
tSAS
RS
90
ns
Data setup time
tSDS
SI
60
ns
Data hold time
tSDH
SI
60
ns
CS - SCL time
tCSS
/CS
90
ns
tCSH
/CS
90
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
Data Sheet S15649EJ2V0DS
99
µ PD161622
(d) Common
Parameter
Oscillation frequency
Symbol
Condition
fOSC1
Internal oscillator (RSEL = L)
fOSC2
External resistance connection oscillator
(RSEL = H), R = 51 kΩ
Calibration setting time
tcal
(frame frequency)
(fFRAME0)
Frame frequency
fFRAME1
Note3
Uncalibrated
Note4
fFRAME2
Calibrated
Calibrated
Reset pulse width at power on
tVR
VCC1 or VCC2 to /RESET↑
Reset pulse width
tRW
tR
250
Note1
TYP.
450
MAX.
Unit
750
kHz
450
kHz
Note2
fFRAME3
Reset time
MIN.
Note5
/RESET↑ to interface operation
44
82.2
184
µs
(128.4)
(68.7)
(32.6)
(Hz)
38
70
115
Hz
72
80
88
Hz
77
80
83
Hz
100
ns
100
ns
100
ns
Notes 1. TYP. values are reference values when TA = 25°C.
2. The resistor value of “R” is depending on the characteristic of the parasitism capacity such as wiring. It is
recommended to determine this value after through evaluation with actual system.
3. The relationship between the frame frequency and the calibration setting time is as follows.
fFRAME0 = 1/tcal x 177
4. Measured at TA = –40 to +85°C, after calibration at frame frequency = 80 Hz, TA = 25°C exactly.
5. Measured at ±5°C, after calibration at frame frequency = 80 Hz exactly.
100
Data Sheet S15649EJ2V0DS
µ PD161622
9. µ PD161622, 161640, and 161660 CONNECTION DIAGRAM EXAMPLE
Connection diagram examples for the µ PD161622, 161640, and 161660 are show below.
1.7 V to VCC1
CPU
RESET
D0 to D15
/WR(R,/W)
/RD(E)
/CS
An
VDD
VCC1
VCC1
RS
VCC2
VS
VDC
DCON
DCON
RGONP
VCOM
µPD161622
VCE
VCE
µPD161660
VCD11
VCD11
VCD12
VCD12
VCD2
VCD2
LPMP
LPM
VSS
VO
RGONP
VCOMR
VCOUT
2.5 to 5.5 V
VS
VT
RESET
D0 to D15
/WR(R,/W)
/RD(E)
/CS
2.5 to 3.6 V
GND(0 V)
GCLK
GSTB
GOE1
GOE2
COMMON
O1
TFT-LCD Panel
132 x RGB x 176
O2
RGONG
OE1
OE2
STVR(STVL)
CLK
VT
VEE
VCC1
LPMP
LPM
Y1
Y2
FBRSEL
VSS
Y395
Y396
RGONG
µPD161640
O176
SB
VSS
Data Sheet S15649EJ2V0DS
101
µ PD161622
10. EXAMPLE of µ PD161622 and CPU CONNECTION
Examples of µ PD161622 and CPU connection are shown below.
In the example below, RS pin control in parallel interface mode is described for the case when the least significant bit
of the address bus is being used.
(1) i80 series format
(2) M68 series format
µ PD161622
CPU
µ PD161622
CPU
VDD2
VDD1
VDD
VDD1
/CS
/CS
/CS
/CS
A0
RS
A0
RS
D0 to D15
D0 to D15
D0 to D15
/RD
/RD
R,/W
/WR
/WR
E
/RESET
VSS
102
VDD2
VDD
/RESET
VSS
/RESET
VSS
Data Sheet S15649EJ2V0DS
D0 to D15
R,/W
E
/RESET
VSS
µ PD161622
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15649EJ2V0DS
103