SANYO LC868364A

Ordering number : ENN*6722
CMOS IC
LC868364A
8-Bit Single Chip Microcontroller with
64K-Byte ROM and 512-Byte RAM On Chip
Preliminary
Overview
The LC868364A microcontroller is an 8-bit single chip microcontroller with the following on-chip functional blocks:
- CPU: Operable at a minimum bus cycle time of 0.5µs
- On-chip ROM capacity: 64K bytes
- On-chip RAM capacity: 512 bytes
- Dot-matrix liquid crystal display (LCD) automatic display controller/driver
- External memory
- 16-bit timer/counter (or two 8-bit timers)
- 16-bit timer/PWM (or two 8-bit timers)
- 13-source 9-vectored interrupt function
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM):
65,280 × 8 bits
(2) Random Access Memory (RAM):
512 × 8 bits (calculation area)
128 × 8 bits (display area)
Ver.1.03
21700
91400 RM (IM) HO No.6722-1/29
LC868364A
(3) Bus Cycle Time/Instruction Cycle Time
Bus cycle time
Instruction Cycle Time
System Clock Oscillation
0.5µs
1µs
Ceramic (CF)
0.75µs
1.5µs
Ceramic (CF)
1.0µs
2µs
7.5µs
15.0µs
3.8µs
7.5µs
183µs
366µs
93µs
183µs
* Bus cycle time: ROM-read period
Oscillation Frequency
Ceramic (CF)
Internal RC
(or external RC)
Crystal (Xtal)
12MHz
6MHz
4MHz
6MHz
3MHz
Voltage
3.3-6.5V
2.7-6.5V
2.4-6.5V
800kHz
2.4-6.5V
32.768kHz
2.2-6.5V
Other
OCR7=0
OCR7=1
OCR7=1
OCR7=0
OCR7=1
OCR7=0
OCR7=1
OCR7=0
OCR7=1
OCR7: Oscillation control register bit-7
(4) Ports
- Input/output ports: 6 ports (48 terminals)
I/O programmable in nibble units:
I/O programmable for each bit individually:
- Input port: 1 port (4 terminals)
- LCD drive common output ports:
- LCD drive segment output ports:
1 port (8 terminals)
5 ports (40 terminals)
32 terminals/16 terminals (switched by mask option)
32 terminals/48 terminals (switched by mask option)
(5) External Program Memory Access Function
- Ports
1. Data input/output:
1 port (8 terminals)
2. Address output:
2 ports (16 terminals)
3. Bank address output: Use normal I/O ports as bank address output by program control.
- External program memory access function
External program memory space: 64K bytes
Internal/external program can be switched by program. (at initial: internal program operation mode)
Enabling/ disabling of switching from external program to internal program is provided.
- External data memory access function
By LDC instruction execution:
External data memory space: 64K bytes (Use normal I/O ports as bank address output by program control.)
1. When internal program is operating:
Access to the internal or external ROM data is selectable by program.
2. When external program is operating:
Only the external ROM data can be accessed.
(Only the external program memory space (64K bytes) can be referred.)
- External RAM memory access function (Able to be used when internal program is executed)
By LDX instruction/STX instruction execution:
External RAM space: 64K bytes (Use normal I/O ports as bank address output by program control.)
(When using the external RAM space in the external program operation mode, refer to the “LC868364 User’s Manual”
for details.)
(6) LCD Automatic Display Controller/Common Driver/Segment Driver
- Display duty:
1/32 duty, 1/16 duty
- Display bias:
1/5, 1/7 bias
- Graphic display
A maximum of 1,024 dots capability (without external segment driver)
32 × 80 dots display capability per each segment driver (LC868920A) can be expanded, when 1/32 duty is selected.
Note: If the display capability is expanded by the LC86920A when 1/16 duty is selected, only S1-S32 of the LC868364A can be
used, and S33-S48 can not be used. (Refer to the LC868920A specification sheet.)
No.6722-2/29
LC868364A
- LCD contrast
LCD display contrast is changeable by program.
- LCD power supply (max. 6V): externally boosted output terminal
(assigned at P40 terminal, The terminal function is selectable by program.)
- LCD driver
Following two kinds of combination can be switched by mask option.
Segment Output Terminals
Common Output Terminals
1
32
32
2
48
16
- LCD clock: Select the crystal oscillation circuit output
(in order to reduce the current consumption when LCD is on)
- LCD drive frequency: 102Hz (32.768kHz crystal oscillation)
(7) Serial Interface
- Synchronous 8-bit serial interface × 2 channels (built-in 8-bit baud rate generator)
(8) Timer
- Timer 0 (T0L, T0H)
16-bit timer/counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0: Two 8-bit timers with programmable prescaler
Mode 1: 8-bit timer with programmable prescaler + 8-bit counter
Mode 2: 16-bit timer with programmable prescaler
Mode 3: 16-bit counter
- Timer 1 (T1L, T1H)
16-bit timer/PWM
Mode 0: Two 8-bit timers
Mode 1: 8-bit timer + 8-bit PWM
Mode 2: 16-bit timer
Mode 3: Variable bit PWM (9-16 bits)
- Base Timer
Generates an overflow every 500ms for a clock application. (using a 32.768kHz crystal oscillation for the base timer
clock.)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0.
(9) Buzzer Output
- Built-in 4kHz and 2kHz buzzer generation function
(10) Remote Receiver Circuit (shares with P73/INT3/T0IN terminal)
- Noise rejection function
- Polarity switch function
(11) Watchdog Timer
- External RC circuit is required (connected to P70/INT0 terminal)
- Interrupt or system reset is activated when the timer overflows.
No.6722-3/29
LC868364A
(12) Interrupt
- 13-source and 9-vectored interrupt function:
1. External interrupt INT0 (including watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, timer/counter T0L (lower 8 bits of Timer 0)
4. External interrupt INT3, base timer
5. Timer/counter T0H (upper 8 bits of Timer 0)
6. Timer T1L (lower 8 bits of Timer 1), Timer T1H (upper 8 bits of Timer 1)
7. Serial interface SIO0
8. Serial interface SIO1
9. Port 0 or Port 3
- Built-in Interrupt Priority Control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the 11 interrupt sources, from the external interrupt INT2, Timer/Counter T0L (Timer 0,
lower 8 bits) to Port 0 or Port 3. For the external interrupt INT0 and INT1, low or highest priority can be set
regardless of the interrupt priority register.
(13) Sub-routine Stack Level
- A maximum of 128 levels: (sets stack inside RAM)
(14) Multiplication/Division Instruction
- 16 bits × 8-bit (7 instruction-cycle-times)
- 16 bits ÷ 8-bit (7 instruction-cycle-times)
(15) Three Types of Oscillation Circuit
- Built-in/external RC oscillation circuit used for the system clock
- CF oscillation circuit used for the system clock
- Xtal oscillation circuit used for the clock, system clock and LCD
* Crystal oscillation clock is also used as LCD display base clock. The current consumption of this microcontroller
becomes smaller than the Sanyo’s previous microcontrollers by this configuration.
Built-in/external RC oscillation circuit: switched by mask option
(16) Standby Function
- HALT mode
In this operation mode, the program execution is stopped. The mode can be released by a system reset or an
interrupt request.
- HOLD mode
The HOLD mode is used to stop the oscillations;
CF, RC, and Xtal oscillations. This mode can be released by the following conditions:
• System reset
• Feed the selected level to INT0 or INT1 terminals.
• Feed “L” level to the Port 0 or Port 3.
(17) Operating Supply Voltage Range
- VDD=2.4 to 6.5V
- VLCD=2.5 to 6.5V (LCD power supply)
(18) Shipping Form
- Chip
(19) Development Tool
- Evaluation (EVA) chip:
- Emulator:
LC868099
EVA86000(main) + ECB868300 (evaluation board)
No.6722-4/29
LC868364A
Pad Assignment
(Display duty: 1/32 duty)
5.38mm × 4.84mm
- Thickness of chip :
480µm
- Pad size
:
100µm × 100µm
- Pad pitch
:
120µm
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
V1
V2
V3
V4
V5
VLCD
RC1
RC2
- Chip size (X × Y):
35
30
25
20
15
10
5
2
1
135
40
130
45
125
50
120
55
115
60
110
65
105
70
103
75
80
85
90
95
100
VDD
CF2
CF1
VSS
XT2
XT1
RES
EROE
ADLC
P27
P26
P25
P24
P23
P22
P21
P20
P07
P06
P05
P04
P03
P02
P01
P00
P37
P36
P35
P34
P33
P32
P31
P30
VDD
102
VSS
P40
P41
P42
P43
P44
P45
P46
P47
P70
P71
P72
P73
P10
P11
P12
P13
P14
P15
P16
P17
P57
P56
P55
P54
P53
P52
P51
P50
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
No.6722-5/29
LC868364A
Pad Assignment
5.38mm × 4.84mm
480µm
100µm × 100µm
120µm
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
V1
V2
V3
V4
V5
VLCD
RC1
RC2
- Chip size (X × Y):
- Thickness of chip :
- Pad size
:
- Pad pitch
:
(Display duty: 1/16 duty)
35
30
25
20
15
10
5
2
1
135
40
130
45
125
50
120
55
115
60
110
65
105
70
103
VDD
CF2
CF1
VSS
XT2
XT1
RES
EROE
ADLC
P27
P26
P25
P24
P23
P22
P21
P20
P07
P06
P05
P04
P03
P02
P01
P00
P37
P36
P35
P34
P33
P32
P31
P30
VDD
VSS
P40
P41
P42
P43
P44
P45
P46
P47
P70
P71
P72
P73
P10
P11
P12
P13
P14
P15
P16
P17
P57
P56
P55
P54
P53
P52
P51
P50
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
No.6722-6/29
LC868364A
Application Circuit
(Display duty: 1/32 duty)
LCD Panel
32
32 × 112 dots
32 COM
32
80
SEGMENT DRIVER
80 SEG
LC868920A
Mask ROM
4M Byte
DATA
OE ADDRESS
COM1-32
SEG1-32
DATA
EROE
Control signal
Power supply for LCD
LC868364A
KEY MATRIX
8-bit single chip microcomputer
8×8
No.6722-7/29
LC868364A
Pad Name and Coordinates Table
Pad
No.
Name
Coordinates
1
VDD
2178
2
RC2
1967
3
RC1
4
5
(Display duty: 1/32 duty)
Pad
No.
Name
Pad
No.
Name
2330
47
COM27
-2179
2449
48
COM26
-2179
972
93
P16
797
852
94
P17
927
1836
2449
49
COM25
-2442
-2179
732
95
P57
1057
-2442
VLCD
1663
2449
50
V5
1543
2449
51
COM24
-2179
612
96
P56
1187
-2442
COM23
-2179
492
97
P55
1317
-2442
6
V4
1423
2449
7
V3
1303
2449
52
COM22
-2179
372
98
P54
1447
-2442
53
COM21
-2179
252
99
P53
1577
8
V2
1183
-2442
2449
54
COM20
-2179
132
100
P52
1707
9
V1
-2442
1063
2449
55
COM19
-2179
12
101
P51
1837
-2442
10
SEG1
942
2450
56
COM18
-2179
-108
102
P50
1967
-2442
Xµm
Yµm
Coordinates
Xµm
Yµm
Coordinates
Xµm
Yµm
-2442
11
SEG2
822
2450
57
COM17
-2179
-228
103
VDD
2178
-2294
12
SEG3
702
2450
58
COM16
-2179
-348
104
P30
2178
-2104
13
SEG4
582
2450
59
COM15
-2179
-468
105
P31
2178
-1974
14
SEG5
462
2450
60
COM14
-2179
-588
106
P32
2178
-1844
15
SEG6
342
2450
61
COM13
-2179
-708
107
P33
2178
-1714
16
SEG7
223
2450
62
COM12
-2179
-828
108
P34
2178
-1584
17
SEG8
103
2450
63
COM11
-2179
-948
109
P35
2178
-1454
18
SEG9
-17
2450
64
COM10
-2179
-1068
110
P36
2178
-1324
19
SEG10
-137
2450
65
COM9
-2179
-1188
111
P37
2178
-1194
20
SEG11
-257
2450
66
COM8
-2179
-1308
112
P00
2178
-1064
21
SEG12
-377
2450
67
COM7
-2179
-1428
113
P01
2178
-934
22
SEG13
-497
2450
68
COM6
-2179
-1548
114
P02
2178
-804
23
SEG14
-617
2450
69
COM5
-2179
-1668
115
P03
2178
-674
24
SEG15
-737
2450
70
COM4
-2179
-1788
116
P04
2178
-544
25
SEG16
-857
2450
71
COM3
-2179
-1908
117
P05
2178
-414
26
SEG17
-977
2450
72
COM2
-2179
-2028
118
P06
2178
-284
27
SEG18
-1097
2450
73
COM1
-2179
-2148
119
P07
2178
-154
28
SEG19
-1217
2450
74
VSS
-1673
-2442
120
P20
2178
-24
29
SEG20
-1337
2450
75
P40
-1543
-2442
121
P21
2178
106
30
SEG21
-1457
2450
76
P41
-1413
-2442
122
P22
2178
236
31
SEG22
-1577
2450
77
P42
-1283
-2442
123
P23
2178
366
32
SEG23
-1697
2450
78
P43
-1153
-2442
124
P24
2178
496
33
SEG24
-1817
2450
79
P44
-1023
-2442
125
P25
2178
626
34
SEG25
-1937
2450
80
P45
-893
-2442
126
P26
2178
756
35
SEG26
-2057
2450
81
P46
-763
-2442
127
P27
2178
886
36
SEG27
-2177
2450
82
P47
-633
-2442
128
2178
1216
37
SEG28
-2179
2172
83
P70
-503
-2442
129
ADLC
EROE
2178
1346
38
SEG29
-2179
2052
84
P71
-373
-2442
130
RES
2178
1476
39
SEG30
-2179
1932
85
P72
-243
-2442
131
XT1
2178
1606
40
SEG31
-2179
1812
86
P73
-113
-2442
132
XT2
2178
1736
41
SEG32
-2179
1692
87
P10
17
-2442
133
VSS
2178
1866
42
COM32
-2179
1572
88
P11
147
-2442
134
CF1
2178
1996
43
COM31
-2179
1452
89
P12
277
-2442
135
CF2
2178
2126
44
COM30
-2179
1332
90
P13
407
-2442
45
COM29
-2179
1212
91
P14
537
-2442
46
COM28
-2179
1092
92
P15
667
-2442
The values (X, Y) indicate the coordinates of each pad center with the center of the chip as the origin.
No.6722-8/29
LC868364A
Pad Name and Coordinates Table
Pad
No.
Name
Coordinates
1
VDD
2178
2
RC2
1967
3
RC1
4
5
(Display duty: 1/16 duty)
Pad
No.
Name
Pad
No.
Name
2330
47
SEG38
-2179
2449
48
SEG39
-2179
972
93
P16
797
852
94
P17
927
1836
2449
49
SEG40
-2442
-2179
732
95
P57
1057
-2442
VLCD
1663
2449
50
V5
1543
2449
51
SEG41
-2179
612
96
P56
1187
-2442
SEG42
-2179
492
97
P55
1317
-2442
6
V4
1423
2449
7
V3
1303
2449
52
SEG43
-2179
372
98
P54
1447
-2442
53
SEG44
-2179
252
99
P53
1577
8
V2
1183
-2442
2449
54
SEG45
-2179
132
100
P52
1707
-2442
9
V1
10
SEG1
1063
2449
55
SEG46
-2179
12
101
P51
1837
-2442
942
2450
56
SEG47
-2179
-108
102
P50
1967
-2442
Xµm
Yµm
Coordinates
Xµm
Yµm
Coordinates
Xµm
Yµm
-2442
11
SEG2
822
2450
57
SEG48
-2179
-228
103
VDD
2178
-2294
12
SEG3
702
2450
58
COM16
-2179
-348
104
P30
2178
-2104
13
SEG4
582
2450
59
COM15
-2179
-468
105
P31
2178
-1974
14
SEG5
462
2450
60
COM14
-2179
-588
106
P32
2178
-1844
15
SEG6
342
2450
61
COM13
-2179
-708
107
P33
2178
-1714
16
SEG7
223
2450
62
COM12
-2179
-828
108
P34
2178
-1584
17
SEG8
103
2450
63
COM11
-2179
-948
109
P35
2178
-1454
18
SEG9
-17
2450
64
COM10
-2179
-1068
110
P36
2178
-1324
19
SEG10
-137
2450
65
COM9
-2179
-1188
111
P37
2178
-1194
20
SEG11
-257
2450
66
COM8
-2179
-1308
112
P00
2178
-1064
21
SEG12
-377
2450
67
COM7
-2179
-1428
113
P01
2178
-934
22
SEG13
-497
2450
68
COM6
-2179
-1548
114
P02
2178
-804
23
SEG14
-617
2450
69
COM5
-2179
-1668
115
P03
2178
-674
24
SEG15
-737
2450
70
COM4
-2179
-1788
116
P04
2178
-544
25
SEG16
-857
2450
71
COM3
-2179
-1908
117
P05
2178
-414
26
SEG17
-977
2450
72
COM2
-2179
-2028
118
P06
2178
-284
27
SEG18
-1097
2450
73
COM1
-2179
-2148
119
P07
2178
-154
28
SEG19
-1217
2450
74
VSS
-1673
-2442
120
P20
2178
-24
29
SEG20
-1337
2450
75
P40
-1543
-2442
121
P21
2178
106
30
SEG21
-1457
2450
76
P41
-1413
-2442
122
P22
2178
236
31
SEG22
-1577
2450
77
P42
-1283
-2442
123
P23
2178
366
32
SEG23
-1697
2450
78
P43
-1153
-2442
124
P24
2178
496
33
SEG24
-1817
2450
79
P44
-1023
-2442
125
P25
2178
626
34
SEG25
-1937
2450
80
P45
-893
-2442
126
P26
2178
756
35
SEG26
-2057
2450
81
P46
-763
-2442
127
P27
2178
886
36
SEG27
-2177
2450
82
P47
-633
-2442
128
2178
1216
37
SEG28
-2179
2172
83
P70
-503
-2442
129
ADLC
EROE
2178
1346
38
SEG29
-2179
2052
84
P71
-373
-2442
130
RES
2178
1476
39
SEG30
-2179
1932
85
P72
-243
-2442
131
XT1
2178
1606
40
SEG31
-2179
1812
86
P73
-113
-2442
132
XT2
2178
1736
41
SEG32
-2179
1692
87
P10
17
-2442
133
VSS
2178
1866
42
SEG33
-2179
1572
88
P11
147
-2442
134
CF1
2178
1996
43
SEG34
-2179
1452
89
P12
277
-2442
135
CF2
2178
2126
44
SEG35
-2179
1332
90
P13
407
-2442
45
SEG36
-2179
1212
91
P14
537
-2442
46
SEG37
-2179
1092
92
P15
667
-2442
The values (X, Y) indicate the coordinates of each pad center with the center of the chip as the origin.
No.6722-9/29
LC868364A
System Block Diagram
Interrupt Control
IR
Standby Control
PLA
ROM
RC
X’tal
Base Timer
Clock
Generator
CF
PC
Base Timer
ACC
Port 1
B Register
Port 7
C Register
SI/O 0
Timer 0
ALU
Timer 1
Port 2
Port 3
PSW
INT0-3
Noise Rejection Filter
Port 4
RAR
LCD Display
Controller
Port 5
RAM
XRAM
Stack Pointer
LCD Driver
Port 0
Port 0
Watchdog Timer
No.6722-10/29
LC868364A
Pad Description
Name
VSS
VDD
VLCD
No.
74,133
1,103
4
I/O
-
V1 to V5
Port0
9-5
I/O
P00 to P07
112-119
Port1
P10 to P17
I/O
87-94
Port2
P20 to P27
I/O
120-127
Port3
P30 to P37
I/O
104-111
Function Description
Power terminal (-)
Power terminal (+)
Power terminal (+) for LCD driver
(for bleeder resistor)
Voltage supply terminals to LCD drivers
! 8-bit input/output port
! Data direction programmable in nibble units
! External memory mode
1. EXT register bit 2=0
Address output of lower 8 bits, input/output
of data
2. EXT register bit 2=1
! Input/output of data
! Input for key interrupt (P30INT=0) (Note 2)
! 8-bit input/output port
! Data direction programmable for each bit individually
! Other functions
P10 SIO0 data output
P11 SIO0 data input, bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input, bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM output)
! 8-bit input/output port
! Input/output can be specified in a bit
! External memory mode
Address output of upper 8 bits
! 8-bit input/output port
! Data direction programmable for each bit individually
! External memory mode
1. EXT register bit 2=0: input/output port
2. EXT register bit 2=1:
Option
! Pull-up resistor:
provided/not provided
! Output form:
CMOS/N-ch open drain
(Note 1)
! Output form:
CMOS/N-ch open drain
(Note 1)
! Output form:
CMOS/N-ch open drain
(Note 1)
! Pull-up resistor:
provided/not provided
! Output form:
CMOS/N-ch open drain
(Note 1)
address output of lower 8
bits for external memory
Port4
P40 to P47
I/O
75-82
! Input for key interrupt (P30INT=L) (Note 2)
! 8-bit input/output port
! Input/output can be specified each upper
2 bits and lower 6 bits
! Other functions
P40
Externally boosted clock
2KOUT
P41
Shift clock
CL2
System clock for expansion
P42
LCDP2
! Pull-up resistor:
provided/not provided
! Output form:
CMOS/N-ch open drain
(Note 1)
driver
P43
P44
P45
P46
Alternate signal
General output port
General output port
Read signal
M
P44
P45
P47
Write signal
WR
RD
(P40-P43: LCD expansion signal,
P46, P47: External RAM access signal)
No.6722-11/29
LC868364A
Name
Port5
P50 to P57
No.
I/O
I/O
102-95
I
Port7
P70 to P73
Function Description
⋅ 8-bit input/output port
⋅ Data direction programmable for each bit individually
83-86
⋅ 4-bit input port
⋅ Other functions
P70 INT0 input/HOLD release/N-ch Tr.
output for watchdog timer
P71 INT1 input/HOLD release input
P72 INT2 input/Timer 0 event input
P73 INT3 input with noise filter/Timer 0
event input
⋅ Interrupt detection style, vector address
Rising Falling
INT0
INT1
INT2
INT3
C1 to C32
(Note 3)
S1 to S32
RES
ADLC
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Option
⋅ Pull-up resistor:
provided/not provided
⋅ Output form:
CMOS/N-ch open drain
(Note 1)
⋅ Pull-up resistor:
provided/not provided
Rising/
H level L level Vector
Falling
No
Yes
Yes
03H
No
Yes
Yes
0BH
Yes
No
No
13H
Yes
No
No
1BH
73-42
O
LCD output terminals for common
10-41
130
O
I
LCD output terminals for segment
Reset
⋅ Segment output/
common output
-
EROE
XT1
128
129
O
O
Address control signal for external memory
Enable signal of external ROM output
-
131
I
-
XT2
132
O
CF1
134
I
CF2
135
O
RC1
3
I
RC2
2
O
Input terminal for 32.768kHz Xtal
When not in use, connect to VDD.
Output terminal for 32.768kHz Xtal
When not in use, leave open circuit.
Input terminal for ceramic resonator
When not in use, connect to VDD.
Output terminal for ceramic resonator
When not in use, leave open circuit.
Input terminal for RC oscillation (when external RC
oscillation is used)
Put a resistor between RC1 and RC2, and a capacitor
between RC1 and VSS externally.
Leave open when internal RC oscillation is used.
Output terminal for RC oscillation (when external RC
oscillation is used)
Put a resistor between RC1 and RC2 externally.
Leave open when internal RC oscillation is used.
Internal/external
Internal/external
(Note 1) Nch-OD: N-channel open-drain output
(Note 2) P30INT: Bit 0 of Port 3 interrupt control register (P3INT).
* Port options can be specified for each bit individually.
(Note 3) C1-C32 are the terminal names when 1/32 duty is selected.
C1-C16 and S48-S33 are the terminal names when 1/16 duty is selected.
Refer to “Pad Assignment” in pages 5-6.
* A state of port at initial
Pin Name
Input/output Mode
Port 0, 7
Ports 1, 2
Ports 3, 5
Port 4
Input
Input
Fixed pull-up resistor provided
Programmable pull-up resistor OFF
Input
Programmable pull-up resistor ON
Name
C1 to C32
S1 to S32
Style of pull-up resistors when pull-up option is enabled
Output Level
VSS (display OFF)
VSS (display OFF)
No.6722-12/29
LC868364A
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter
Supply Voltage
Input Voltage
Output Voltage
Symbol
VIO(1)
High
Level
Output
Current
Peak
Output
Current
Total
Output
Current
IOPH(1)
Low
Level
Output
Current
Peak
Output
Current
Operating
Temperature
Range
Storage
Temperature
Range
Conditions
VDDMAX VDD
VI(1)
·Ports 71,72,73
· RES
VI(2)
VLCD
VO(1)
·C1 to C32
·S1 to S32
VO(2)
ADLC, EROE
Input/output
Voltage
Total
Output
Current
Pins
ΣIOAH(1)
ΣIOAH(2)
IOPL(1)
IOPL(2)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
ΣIOAL(7)
Topr
Tstg
·Ports 0,1,2,3,4,5
·Port 70
·ADLC
·Ports 0,1,2,3,4,5
·ADLC, EROE
·Ports 0,2,3
·C1-C32,S1-S32
·ADLC, EROE
Ports 1, 4, 5
·Ports 0,1,2,3,4,5
·ADLC, EROE
Port 70
Port 0
·Port 2
·ADLC, EROE
Port 3
Ports 1, 5
Port 4
Port 70
C1-C32,S1-S32
VDD[V]
min.
-0.3
-0.3
Ratings
unit
typ.
max.
V
+7.0
VDD+0.3
-0.3
-0.3
-
+7.0
VLCD+0.3
-0.3
-
VDD+0.3
-0.3
-
VDD+0.3
·CMOS output
·For each pin
-4
Total of all pins
-25
Total of all pins
For each pin
-25
mA
20
For each pin
Total of all pins
Total of all pins
15
40
40
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
-30
-
40
40
40
15
30
+70
-55
-
+125
°C
Notes:
The specification above indicates the state when a die is mounted in a package, SQFC144.
However, we ship this product in a chip, not in a package.
Make sure that the operational characteristics may vary by the user’s package techniques.
No.6722-13/29
LC868364A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter
Symbol
Pins
VDD(1)
VDD(2)
VDD(3)
VDD
VHD
VDD
LCD Display
Voltage
VLCD
VLCD
Input High
Voltage
VIH(1)
Port 0
VIH(2)
·Ports 1,2,3,4,5
·Ports 72,73
(Schmitt)
·Port 70 for
Port input/interrupt
·Port 71
· RES (Schmitt)
Port 70 for watchdog
timer
Port 0 (Schmitt)
·Ports 1,2,3,4,5
·Ports 72,73
(Schmitt)
·Port 70
Port input/interrupt
·Port 71
· RES
Port 70 for watchdog
timer
VIH(4)
Input Low
Voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
Operation
Cycle Time
tCYC
Oscillation
Frequency
Range
(Note 1)
FmRC
VDD[V]
0.98µs ≤ tCYC ≤ 400µs
Operating
Supply
Voltage
Range
Hold Voltage
VIH(3)
Conditions
1.49µs ≤ tCYC ≤ 400µs
1.98µs ≤ tCYC ≤ 400µs
RAM and register
data are kept in
HOLD mode.
(Schmitt)
RC1, RC2
min.
3.3
2.7
2.4
Ratings
typ.
max.
6.5
6.5
6.5
2.0
6.5
6.5
6.5
6.5
VDD
unit
V
Output disable
2.4-2.5
2.5-3.0
3.0-6.5
2.4-6.5
Output disable
2.4-6.5
2.5
VDD
VDD
0.4VDD
+0.9
0.7VDD
Output N-channel
Tr. OFF
2.4-6.5
0.7VDD
VDD
Output N-channel
Tr. OFF
Output disable
Output disable
2.4-6.5
0.9VDD
VDD
2.4-6.5
2.4-6.5
VSS
VSS
0.2VDD
0.3VDD
Output N-channel
Tr. OFF
2.4-6.5
VSS
0.3VDD
Output N-channel
Tr. OFF
2.4-6.5
VSS
3.3-6.5
2.7-6.5
2.4-6.5
2.4-6.5
0.98
1.49
1.98
0.3
0.8VDD
-1.0
400
µs
400
400
3
MHz
·External RC
oscillation
·Refer to figure 3
VDD
(Note 1): Oscillation parameters are shown in “Recommended Oscillation Circuit and Characteristics” in page 20.
No.6722-14/29
LC868364A
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Input High
Current
Input Low
Current
Symbol
IIH(1)
·Ports 1,2,3,4,5
·Port 0 without
pull-up MOS Tr.
IIH(2)
Port 7 without
pull-up MOS Tr.
IIH(3)
RES
·Ports 1,2,3,4,5
·Port 0 without
pull-up MOS Tr.
IIL(1)
IIL(2)
Port 7 without
pull-up MOS Tr.
IIL(3)
RES
Port 0 of CMOS
output, P46,P47
·Ports 1,2,3,4(P40P45),5 of CMOS
output
·ADLC, EROE
·Ports 0,1,2,3,4,5
·ADLC, EROE
Output High
Voltage
VOH(1)
VOH(2)
VOH(3)
VOH(4)
Output Low
Voltage
VOL(1)
VOL(2)
VOL(3)
Pull-up MOS
Tr. resistor
Hysteresis
Voltage
Pin
Capacitance
Built-in RC
Oscillation
Frequency
Pins
VOL(4)
VOL(5)
Rpu
VHIS
CP
Port 70
·Ports 0,1,2,3,4,5
·Port 7
·Ports 0,1,2,3,4,5
·Port 7
· RES
All pins
Conditions
·Output disable
·Pull-up MOS Tr. OFF
·VIN=VDD
(including the offleak current of the
output Tr.)
·Output Nch Tr. OFF
·VIN=VDD
(including the offleak current of the
output Tr.)
VIN=VDD
VDD[V]
2.5-6.5
min.
Ratings
typ.
2.5-6.5
max.
1
2.5-6.5
1
2.5-6.5
-1
2.5-6.5
-1
2.5-6.5
-1
IOH=-10mA
IOH=-1mA
IOH=-1.0mA
IOH=-0.1mA
4.5-6.5 VDD-1.5
2.5-6.5 VDD-0.4
4.5-6.5 VDD-1
2.5-6.5 VDD-0.5
IOL=10mA
IOL=1.6mA
·IOL=1.0mA
·Every pin’s IOL≤1mA
IOL=1mA
IOL=0.5mA
VOH=0.9VDD
4.5-6.5
4.5-6.5
2.5-6.5
1.5
0.4
0.4
4.5-6.5
2.5-6.5
4.5-6.5
2.5-4.5
2.5-6.5
0.4
0.4
100
200
·f=1MHz
·All pins except the
measured terminal:
VIN=VSS
·Ta=25°C
50
60
2.5-6.5
2.5-6.5
µA
1
·Output disable
·Pull-up MOS Tr. OFF
·VIN=VSS
(including the offleak current of the
output Tr.)
·Output Nch Tr. OFF
·VIN=VSS
(including the offleak current of the
output Tr.)
VIN=VSS
Output disable
unit
V
70
100
0.1VDD
V
10
0.3
0.8
kΩ
pF
2
MHz
No.6722-15/29
LC868364A
4. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter
Symbol
Pins
High/low
Level
Pulse Width
tPIH(1)
tPIL(1)
·INT0, INT1
·INT2/T0IN
·Refer to figure 7
·INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
·Refer to figure 7
·INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
·Refer to figure 7
·Interrupt acceptable
·Timer 0-countable
· RES
·Refer to figure 7
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIL(4)
Conditions
VDD[V]
2.5-6.5
min.
1
·Interrupt acceptable
·Timer 0-countable
2.5-6.5
2
·Interrupt acceptable
·Timer 0-countable
2.5-6.5
128
Reset acceptable
2.5-6.5
200
Ratings
typ.
max.
unit
tCYC
µs
No.6722-16/29
LC868364A
5. Sample Current Consumption Characteristics at Ta=-30°C to +70°C, VSS=0V
The sample current consumption characteristics are the measurement result of Sanyo provided evaluation board. The currents
through the output transistors, the pull-up MOS transistors and the bleeder resistors for the LCD are not included.
Parameter
Current
Drain
During
Basic
Operation
(Note 2)
Symbol
Pins
IDDOP(1)
VDD
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
IDDOP(9)
IDDOP(10)
IDDOP(11)
IDDOP(12)
IDDOP(13)
Conditions
·FmCF=12MHz by ceramic resonator
·FsXtal=32.768kHz by Xtal
·System clock: 12MHz
·Internal RC oscillation stops.
·FmCF=6MHz by ceramic resonator
·FsXtal=32.768kHz by Xtal
·System clock: 6MHz
·Internal RC oscillation stops.
·FmCF=3MHz by ceramic resonator
·FsXtal=32.768kHz by Xtal
·System clock: 3MHz
·Internal RC oscillation stops.
·FmCF=0Hz
(when oscillation stops)
·FsXtal=32.768kHz by Xtal
·System clock: RC oscillation
·FmCF=0Hz
(when oscillation stops)
·FsXtal=32.768kHz by Xtal
·System clock: 32.768kHz
·Internal RC oscillation stops.
OCR7 VDD[V] min.
0
4.5-6.5
Ratings
unit
typ. max.
10
25 mA
1
4.5-6.5
10
25
0
1
0
4.5-6.5
3
6
1.5
9
15
5
0.7
1.2
0.4
0.8
30
50
10
20
3.4
4.5
2.8
3.6
45
80
20
30
0
1
0
1
0
1
0
1
2.5-4.5
4.5-6.5
2.5-4.5
5.0
3.0
µA
OCR7: Bit 7 of the oscillation control register.
No.6722-17/29
LC868364A
Ta=-30°C to +70°C, VSS=0V
Parameter
Current
Drain in
HALT
Mode
(Note 2)
Symbol
IDDHALT(1) VDD
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
Current
Drain in
HOLD
Mode
(Note 2)
Pins
Conditions
·HALT mode
·FmCF=12MHz
Ceramic resonator oscillation
·FsXtal=32.768kHz
Crystal oscillation
·System clock: 12MHz
·Internal RC oscillation stops.
·Refer to figure 8.
·HALT mode
·FmCF=6MHz
Ceramic resonator oscillation
·FsXtal=32.768kHz
Crystal oscillation
·System clock: 6MHz
·Internal RC oscillation stops.
·Refer to figure 8.
·HALT mode
·FmCF=3MHz
Ceramic resonator oscillation
·FsXtal=32.768kHz
Crystal oscillation
·System clock: 3MHz
·Internal RC oscillation stops
·Refer to figure 8.
OCR7 VDD[V] min.
0
5.0
1
5.0
4.0
7.0
0
1
0
5.0
1.5
2.3
0.5
2.6
4.0
0.9
400
600
200
300
1600
2400
1300
1500
20
35
30
50
7
13
10
18
0.05
0.02
30
20
3.0
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
IDDHALT(9)
·HALT mode
·FmCF=0Hz
(when oscillation stops)
·FsXtal=32.768kHz
crystal oscillation
·System clock: RC oscillation
·Refer to figure 8.
0
1
0
1
5.0
IDDHALT(10
)
IDDHALT(11
)
IDDHALT(12
)
IDDHALT(13
)
·HALT mode
·FmCF=0Hz
(when oscillation
stops)
·FsXtal=32.768kHz
crystal oscillation
·System clock:
32.768kHz
·Internal RC
oscillation stops
·Refer to figure 8.
0
5.0
IDDHOLD(1) VDD ·HOLD mode
·Refer to figure 8.
IDDHOLD(2)
·Ta≤50°C
Ratings
unit
typ. max.
4.0
7.0 mA
3.0
1
0
3.0
1
4.5-6.5
2.5-4.5
µA
(Note 2) The currents of the output transistors, pull-up MOS transistors, the LCD bleeder resistors and the LCD driver are
not included.
No.6722-18/29
LC868364A
6. LCD Voltage and LCD Driver Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Symbol
VX-Ci Drop Voltage
(X: 1 to 5)
(i: 1 to 32)
|VD1|
VX-Ci Drop Voltage
(X: 1 to 5)
(i: 1 to 32)
|VD2|
VX-Si Drop Voltage
(X: 1 to 5)
(i: 1 to 32)
|VD3|
VX-Si Drop Voltage
(X: 1 to 5)
(i: 1 to 32)
|VD4|
V4 Output Voltage
VV4
V3 Output Voltage
VV3
V2 Output Voltage
VV2
V1 Output Voltage
VV1
Pins, Conditions
·Only a Ci terminal for –15µA
·LCD display ON
·1/5 bias
·V5=VLCD=VDD
·Only a Ci terminal for +15µA
·LCD display ON
·1/5 bias
·V5=VLCD=VDD
·Only a Si terminal for -15µA
·LCD display ON
·1/5 bias
·V5=VLCD=VDD
VDD[V]
2.9
5.0
min.
2.9
5.0
-120
-200
Ratings
typ.
2.9
5.0
2.9
5.0
·Only a Si terminal for +15µA
·LCD display ON
·1/5 bias
·V5=VLCD=VDD
·LCD clock frequency=0Hz
·LCD display ON
·1/5 bias
·V5=VLCD=VDD
·Refer to figure 10
2.9
5.0
2.9
5.0
2.9
5.0
2.9
5.0
max.
120
200
unit
mV
120
200
-120
-200
0.75VDD 0.80VDD 0.85VDD
V
0.55VDD 0.60VDD 0.65VDD
0.35VDD 0.40VDD 0.45VDD
0.15VDD 0.20VDD 0.25VDD
7. Sample LCD Driver Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
LCD Display Current
Symbol
ILCD1
ILCD2
Contrast Current
ILC1
ILC2
ILC3
ILC4
ILC5
100kΩ
mode
50kΩ
mode
VDD[V]
2.9
5
2.9
5
min.
5
5
10
10
Ratings
typ.
10
10
20
20
max.
20
20
40
40
VCCR=1
VCCR=2
VCCR=4
VCCR=8
VCCR=10H
2.9
2.9
2.9
2.9
2.9
125
62
31
15
8
250
125
62
31
15
500
250
125
62
31
Pins, Conditions
·LCD display ON
·1/5 bias
·VLCD=5V
·V1-V5 are open.
·Refer to figure 9
·LCD display ON
·VLCD=5V
·V5=VLCD-0.5V
·Refer to figure 11
unit
µA
VCCR: LCD contrast control register
No.6722-19/29
LC868364A
Recommended Oscillation Circuit and Characteristics
The oscillation circuit characteristics in the table below are based on the following conditions:
• Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation
board.
• The characteristics are the results of the evaluation with the recommended circuit parameters connected externally.
Recommended Ceramic Oscillation Circuit and Characteristics (Ta = -30°C to +70°C)
Frequency
12MHz
MURATA
KYOCERA
6MHz
MURATA
KYOCERA
4MHz
MURATA
KYOCERA
3MHz
Oscillator
Manufacturer
MURATA
KYOCERA
CSA12.0MTZ
CST12.0MTW
KBR-12.0M
CSA6.00MG
CSTS0600MG03
KBR-6.0MSA
CSA4.00MG
CSTS0400MG03
KBR-4.0MSA
CSA3.00MG
CST3.00MGW
KBR-3.0MS
Operating
Oscillation
Recommended Circuit
supply Voltage Stabilizing Time
Parameter
Period
(typ.)
*
Range
C1
C2
Rd1
3.3 to 6.5V
0.06ms
30pF 30pF 0kΩ
3.3 to 6.5V
(30pF) (30pF) 0kΩ
0.06ms
3.3 to 6.5V
0.04ms
22pF 22pF 0kΩ
2.8 to 6.5V
0.08ms
30pF 30pF 0kΩ
2.4 to 6.5V
(15pF) (15pF) 0kΩ
0.04ms
2.4 to 6.5V
33pF 33pF 0kΩ
0.05ms
2.7 to 6.5V
30pF 30pF 0kΩ
0.05ms
2.4 to 6.5V
(15pF) (15pF) 0kΩ
0.03ms
2.4 to 6.5V
33pF 33pF 0kΩ
0.04ms
2.4 to 6.5V
0.06ms
30pF 30pF 0kΩ
2.4 to 6.5V
(30pF) (30pF) 0kΩ
0.06ms
2.4 to 6.5V
0.05ms
33pF 33pF 0kΩ
Notes
built-in capacitor type
built-in capacitor type
built-in capacitor type
built-in capacitor type
Recommended Crystal Oscillation Circuit and Characteristics (Ta = -30°C to +70°C)
Frequency
32.768kHz
Manufacturer
Oscillator
Seiko Instruments
Seiko Epson
VT-200
C-002RX/MC-306
Oscillation
Recommended Circuit Operating supply
Stabilizing Time
Parameter
Voltage Range Period (typ.)
*
C3
C4
Rd2
2.2 to 6.5V
12pF 12pF
0.6s
330kΩ
2.2 to 6.5V
0.8s
12pF 12pF
330kΩ
Notes
* The oscillation stabilizing time period is the time until the oscillation becomes stable after the VDD becomes higher than the
minimum operating voltage.
Notes: • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the
oscillation pins as possible with the shortest possible pattern length.
• If you use other oscillators herein, we provide no guarantee for the characteristics.
The oscillation circuit characteristics may differ by applications.
manufacturer with the following notes in your mind.
For further assistance, please contact with the oscillator
•
Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation
frequency on the production board.
•
The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -30°C to
+70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such
as car products, please consult with oscillator manufacturer.
Since the oscillation circuit characteristics are affected by the noise, wiring capacity, etc., refer to the following notices.
• The distance between the clock I/O terminal and external parts should be as short as possible.
• The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND.
• The signal lines with rapid state changes or the signal line with large amplitude such as middle withstand voltage port or
LCD driver output should be allocated away from the clock oscillation circuit.
• The signal lines with large current should be allocated away from the oscillation circuit.
No.6722-20/29
LC868364A
CF1
CF2
XT1
XT2
Rd1
C1
C2
CF
Figure 1
Ceramic Oscillation Circuit.
RC1
Figure 3
Rd2
C3
Figure 2
Xtal
C4
Crystal Oscillation Circuit.
RC2
RC Oscillation Circuit.
(when external RC oscillation is selected)
No.6722-21/29
LC868364A
VDD
VDD Limit
0V
Power Supply
Reset Time
RES
RC Oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation Mode
Unstable
Reset
Execution of Instructions
Reset Time and Oscillation Stabilizing Time Period
HOLD Release Signal
Valid
RC Oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation Mode
HOLD
Execution of Instructions
HOLD Release Signal and Oscillation Stabilizing Time Period (OCR6=1 at entering HOLD)
tmsCF:
tssXtal:
Oscillation stabilizing time period when using the ceramic resonator oscillator.
Oscillation stabilizing time period when using the Xtal oscillator.
Figure 4
Oscillation Stabilizing Time Period.
No.6722-22/29
LC868364A
VDD
RRES
RES
(Note) Determine the CRES, RRES value to
generate more than 200µs reset time.
CRES
Figure 5
Reset Circuit.
0.5VDD
<AC Timing Point>
VDD
tCKCY
tCKL
tCKH
SCK0
SCK1
1kΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 6
tPIL
Figure 7
<Test Load>
Serial Input/Output Test Condition.
tPIH
Pulse Input Timing Condition.
No.6722-23/29
LC868364A
VDD
VDD
A
VDD
VDD
V5
V4
V3
V2
V1
VLCD
CF1
CF2
VSS
XT1
V5
V4
V3
V2
V1
VLCD
OPEN
XT2
CF1
CF2
VSS
XT1
XT2
OPEN
A
5V
VSS
VSS
Figure 8
Current Consumption Measurement.
VDD
Figure 9
LCD Display Current Measurement.
VDD
5V
VDD
VDD
A
VDD
V5
V4
V3
V2
V1
VDD
VLCD
CF1
CF2
VSS
XT1
VLCD
V5
V4
V3
V2
V1
XT2
CF1
CF2
VSS
XT1
VLCD-0.5V
OPEN
XT2
V
VSS
Figure 10
Output Voltage of V1-V4 Measurement.
VSS
Figure 11
Contrast Current Measurement.
Notes: • Figure 8-11 indicate the measurement circuits when using the internal RC oscillator.
• When external RC oscillation is selected, an external circuit needs to be connected to RC1 and RC2 terminals.
No.6722-24/29
LC868364A
AC Characteristics at Ta=-30°C to +70°C, VSS=0V
Load capacity: 100pF
(Port 0, ADLC, EROE )
Load capacity: 80pF
(Output terminals except above)
*tCLCL=1tCYC/12
External Program Memory Timing
Parameter
Symbol
Pads and Conditions
ADLC Pulse Width
tLHLL
Address Settling Time
tAVLL
For ADLC
Address Hold Time
tLLAX
For ADLC
ADLC " Control Signal
tLLEL
For EROE
EROE Pulse Width
tELEH
Data Delay Time
tELIV
From EROE
Data Hold Time
tEHIX
For EROE
EROE " Address in
tEHAV
VDD[V]
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
Ratings
min.
max.
2tCLCL-40
2tCLCL-160
tCLCL-40
tCLCL-160
tCLCL-35
tCLCL-140
tCLCL-25
tCLCL-100
3tCLCL-35
3tCLCL-140
3tCLCL-125
3tCLCL-400
0
0
tCLCL-8
tCLCL-32
unit
ns
Refer to figure 12.
1 tCYC
SCLK
tCLCL tCLCL
tLHLL
ADLC
tLLEL
tELEH
EROE
tELIV
tEHAV
tLLAX
tAVLL
Port 0
tEHIX
A7-A0
Port 2
IR
A15-A8
Figure 12
A7-A0
A15-A8
Timing of the External Program Memory/Data Memory.
No.6722-25/29
LC868364A
External Data Memory Timing
Parameter
Symbol
RD Pulse Width
tRLRH
WR Pulse Width
tWLWH
Data Address Hold Time
tLLAX
Pads and Conditions
For ADLC (read)
For ADLC (write)
Data Delay Time
tRLDV
From RD
Data Hold Time
tRHDX
From RD
Data Floating Time
tRHDZ
From RD
Data Address Setting Time
tAVLL
For ADLC
ADLC " Control Signal
tLLRL
For RD
tLLWL
For WR
Data Settling Time
tQVWL
For WR
Data in WR =1
tQVWH
Data Hold Time
tWHQX
From WR
Control Signal " ADLC
tRHLH
For RD
tWHLH
For WR
VDD[V]
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
4.5 to 6.5
2.5 to 6.5
Ratings
min.
max.
6tCLCL-80
6tCLCL-320
6tCLCL-80
6tCLCL-320
3tCLCL-35
3tCLCL-140
2tCLCL-35
2tCLCL-140
5tCLCL-125
5tCLCL-400
0
0
2tCLCL-70
2tCLCL+70
2tCLCL-280
2tCLCL+280
2tCLCL-40
2tCLCL-160
3tCLCL-50
3tCLCL+50
3tCLCL-200
3tCLCL+200
3tCLCL-50
3tCLCL+50
3tCLCL-200
3tCLCL+200
tCLCL-60
tCLCL-240
7tCLCL-140
7tCLCL-560
tCLCL-50
tCLCL-200
tCLCL-50
tCLCL+50
tCLCL-200
tCLCL+200
tCLCL-50
tCLCL+50
tCLCL-200
tCLCL+200
unit
ns
Refer to figure 13.
tCLCL
1 tCYC
SCLK
ADLC
EROE
tLLRL
tRLRH
tRHLH
tRLDV
RD
tAVLL
tRHDZ
tLLAX
tRHDX
(at reading)
Port 0
DATA
tLLWL
tWLWH
Z
tWHLH
WR
tLLAX
tWHQX
tQVWL
(at writing)
Port 0
A7-A0
tQVWH
Figure 13
Timing of the External RAM.
No.6722-26/29
LC868364A
VDD=3V
Oscillation Frequency[MHz]
10
External Capacity=50pF
100pF
1
220pF
390pF
0.1
1
10
100
External Resistor (kΩ)
VDD=5V
Oscillation Frequency[MHz]
10
External Capacity=50pF
100pF
1
220pF
390pF
0.1
1
10
External Resistor (kΩ)
100
R=10kΩ
C=100pF
2.0
Oscillation Frequency[MHz]
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
1
2
Figure 14
3
4
Voltage (V)
5
6
7
8
External RC Oscillation Frequency Characteristics. (Ta=25°C)
No.6722-27/29
LC868364A
!
Evaluation Sample (ES)
Shipping Form:
LC868364: chip, Evaluation sample: SQFC144 (shown below) or chip
If you use the ES in the package to design and fabricate an evaluation board, refer to the following pin assignment.
VDD
NC
P50
P51
P52
P53
P54
P55
P56
P57
P17
P16
P15
P14
P13
P12
P11
P10
P73
P72
P71
P70
P47
P46
P45
P44
P43
P42
P41
P40
VSS
NC
NC
NC
NC
C1
• Pin Assignment of evaluation sample (Package type)
108
EROE
RES
XT1
XT2
VSS
CF1
CF2
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
105
100
98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
LC868364A-SQFC144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
S48/C17
S47/C18
S46/C19
S45/C20
S44/C21
S43/C22
S42/C23
S41/C24
S40/C25
S39/C26
S38/C27
S37/C28
S36/C29
S35/C30
S34/C31
S33/C32
S32
S31
S30
S29
S28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VDD
RC2
RC1
VLCD
V5
V4
V3
V2
V1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
P30
P31
P32
P33
P34
P35
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
P20
P21
P22
P23
P24
P25
P26
P27
NC
NC
NC
NC
ADLC
No.6722-28/29
LC868364A
memo:
PS No.6722-29/29