AD ADN8810ACP

12-Bit High Output Current Source
ADN8810
FUNCTIONAL BLOCK DIAGRAM
High precision 12-bit current source
Low noise
Long term stability
Current output from 0 mA to 300 mA
Output fault indication
Low drift
Programmable maximum current
24-lead 4 mm × 4 mm leadframe chip scale package
3-wire serial interface
ENCOMP
RESET
RESET
4.096V
VREF
CS
SERIAL
INTERFACE
5V
5V
3.3V
DVDD
AVDD
PVDD
FB
ADN8810
RSN
1.6V
IOUT
SCLK
RSN
1.6V
SDI
ADDRESS
APPLICATIONS
RSN
ADDR0-2
3
FAULT
SB
AVSS DVSS DGND
SB
FAULT
INDICATION
Tunable laser current source
Programmable high output current source
Automatic test equipment
D1
03195-0-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The ADN8810 is a 12-bit current source with an adjustable
full-scale output current of up to 300 mA. The full-scale output current is set with two external sense resistors. The output
compliance voltage is 2.5 V, even at output currents up to
300 mA.
The device is particularly suited for tunable laser control and
can drive tunable laser front mirror, back mirror, phase, gain,
and amplification sections. A host CPU or microcontroller
controls the operation of the ADN8810 over a 3-wire SPI®
interface. The 3-bit address allows up to eight devices to be
independently controlled while attached to the same SPI bus.
The ADN8810 is guaranteed with ± 4 LSB INL and ± 0.75 LSB
DNL. Noise and digital feedthrough are kept low to ensure low
jitter operation for laser diode applications. Full-scale and
scaled output currents are given in Equations 1 and 2,
respectively.
I FS ≈
VREF
10 × RSN
IOUT = Code ×
(1)
⎞
VREF
1 ⎛⎜ RSN
×
×
+ 0.1⎟⎟
4096 RSN ⎜⎝ 15k
⎠
(2)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADN8810
TABLE OF CONTENTS
ADN8810–Specifications ................................................................ 3
Serial Data Interface................................................................... 11
Timing Characteristics..................................................................... 5
Standby and Reset Modes ......................................................... 12
Absolute Maximum Ratings............................................................ 6
Power Dissipation ...................................................................... 12
ESD Caution.................................................................................. 6
Using Multiple ADN8810s for Additional Output Current . 12
Pin Configuration and Function Descriptions............................. 7
Adding Dither to the Output Current ..................................... 12
ADN8810 Terminology ................................................................... 8
Driving Common-Anode Laser Diodes ................................. 13
Typical Performance Characteristics ............................................. 9
PC Board Layout Recommendations ...................................... 13
Functional Description .................................................................. 11
Suggested Pad Layout for CP-24 Package ............................... 14
Setting Full-Scale Output Current ........................................... 11
Outline Dimensions ....................................................................... 15
Reference Voltage Source .......................................................... 11
Ordering Guide .......................................................................... 15
Power Supplies ............................................................................ 11
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADN8810
ADN8810–SPECIFICATIONS
Table 1. Electrical Characteristics (AVDD = DVDD = 5 V, PVDD = 3.3 V, AVSS = DVSS = DGND = 0 V, TA= 25°C, covering IOUT
from 2% IFS to 100% IFS, unless otherwise noted.)
Parameter
DC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Offset
Offset Drift
Gain Error
REFERENCE INPUT
Reference Input Voltage
Input Current
Bandwidth
ANALOG OUTPUT
Output Current Change vs. Output
Voltage Change
Max Output Current
Output Compliance Voltage
AC PERFORMANCE
Settling Time
Bandwidth
Current Noise Density @10 kHz
Standby Recovery
POWER SUPPLY1
Power Supply Voltage
Symbol
VREF
3.9
BWREF
VOUT = 0.7 V to 2.0 V
IMAX
VCOMP
RSN1 = 1.37 Ω
–40°C to +85°C; IFS=300 mA
IDVDD
±4
± 0.75
8
15
1
4.096
100
300
2.0
IFS = 250 mA
IFS = 100 mA
IFS= 50 mA
Bit
LSB
LSB
LSB
ppm/°C
%FS
V
µA
MHz
400
ppm/V
2.5
mA
V
3
5
7.5
3
1.5
6
µs
MHz
nA/√Hz
nA/√Hz
nA/√Hz
µs
AVDD = 4.5 V to 5.5 V; *
PVDD = 3.0 V to 3.6 V; *
IO = 0 mA, SB = DVDD
5
5
3.3
0.4
0.4
11
5.5
5.5
5.5
5
5
50
V
V
V
µA/V
µA/V
µA
1
2
mA
IPVDD
IO = 0 mA, SB = DVDD
IO = 0 mA, SB = DVDD
3
mA
IAVDD
SB = 0 V
1
mA
IPVDD
SB = 0 V
0.33
mA
PVDD – 0.6
AVSS + 0.2
V
V
V
IAVDD
3.0
4.5
3.0
Unit
4.3
1
2
∆IOUT/∆VOUT
τS
BW
iN
Max
12
4
Supply Current
Input High Voltage
Typ
RSN = 1.6 Ω; IOUT = 127 mA
Power Supply Rejection Ratio
LOGIC INPUTS
Input Leakage Current
Input Low Voltage
Min
N
INL
DNL
DVDD
AVDD
PVDD
PSRR
FAULT DETECTION
Load Open Threshold
Load Short Threshold
FAULT Logic Output
Condition
VOH
DVDD = 5.0 V
VOL
DVDD = 5.0 V
IIL
VIL
VIH
DVDD = 3.0 V
DVDD = 5 V
DVDD = 3.0 V
DVDD = 5 V
Rev. 0 | Page 3 of 16
4.5
2.4
4
0.5
V
1
0.5
0.8
µA
V
V
V
V
ADN8810
Parameter
INTERFACE TIMING2
Clock Frequency
RESET Pulsewidth
Symbol
Condition
fCLK
t11
Min
40
NOTES
1
With respect to AVSS.
2
See Timing Characteristics for timing specifications.
* RSN = 20 Ω
Rev. 0 | Page 4 of 16
Typ
Max
Unit
12.5
MHz
ns
ADN8810
TIMING CHARACTERISTICS1, 2
Table 2. Timing Characteristics
Parameter
fCLK
t1
t2
t3
t4
Description
SCLK Frequency
SCLK Cycle Time
SCLK Width High
SCLK Width Low
CS Low to SCLK High Setup
Min
Typ
Max
12.5
Unit
MHz
ns
ns
ns
ns
t5
CS High to SCLK High Setup
15
ns
t6
35
ns
t7
SCLK High to CS Low Hold
SCLK High to CS High Hold
20
ns
t8
t9
t10
Data Setup
Data Hold
CS High Pulsewidth
15
2
30
ns
ns
ns
t11
RESET Pulsewidth
40
ns
t12
CS High to RESET Low Hold
30
ns
80
40
40
15
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10%
to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
t1
SCLK
t6
t3
t4
CS
t2
t7
t5
t10
t8
t9
A3*
A2
A1
A0
D11
D10
D0
t12
RESET
* ADDRESS BIT A3 MUST BE LOGIC LOW
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 16
t11
03195-0-002
SDI
ADN8810
ABSOLUTE MAXIMUM RATINGS
Table 3. ADN8810 Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range CP
Package
Lead Temperature Range
(Soldering 10 sec)
Rating
6V
GND to VS+ 0.3 V
Indefinite
–65°C to +150°C
–40°C to +85°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 16
ADN8810
SDI
SCLK
CS
22 21 20 19
ADDR2 1
PIN 1
IDENTIFIER
RSN 2
18
DVSS
17
NC
FB 3
ADN8810
16
AVSS
ADDR1 4
TOP VIEW
15
AVDD
14
VREF
13
NC
(Not to Scale)
ADDR0 5
9
10 11 12
SB
IOUT
IOUT
ENCOMP
8
PVDD
7
PVDD
FAULT 6
NC = NO CONNECT
03195-0-003
24 23
RESET
DVDD
DGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Description
Pin No.
1
2
3
4
5
6
7
Mnemonic
ADDR2
RSN
FB
ADDR1
ADDR0
FAULT
SB
Type
Digital Input
Analog Input
Analog Input
Digital Input
Digital Input
Digital Output
Digital Input
Description
Chip Address, Bit 2
Sense Resistor RS2 Feedback
Sense Resistor RS1 Feedback
Chip Address, Bit 1
Chip Address, Bit 0
Load Open/Short Indication
Active Deactivates Output Stage (High Output Impedance State)
8, 11
9, 10
12
13
14
15
16
17
18
19
20
21
PVDD
IOUT
ENCOMP
NC
VREF
AVDD
AVSS
NC
DVSS
SDI
SCLK
CS
Power
Analog Output
Digital Input
Power Supply for IOUT (3.3 V Recommended)
Current Output
Connect to AVSS
No Connection
Input for High Accuracy External Reference Voltage (ADR292ER)
Power Supply for DAC
Connect to Analog Ground or Most Negative Potential in Dual-Supply Applications
No Connection
Connect to Digital Ground or Most Negative Potential in Dual-Supply Applications
Serial Data Input
Serial Clock Input
Chip Select; Active Low
Analog Input
Power
Ground
Ground
Digital Input
Digital Input
Digital Input
22
RESET
Digital Input
Asynchronous Reset to Return DAC Output to Code Zero; Active Low
23
24
DVDD
DGND
Power
Ground
Power Supply for Digital Interface
Digital Ground
Rev. 0 | Page 7 of 16
ADN8810
ADN8810 TERMINOLOGY
Relative Accuracy
Compliance Voltage
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in least significant bits (LSBs), from an
ideal line passing through the endpoints of the DAC transfer
function. Figure 5 shows a typical INL vs. code plot. The
ADN8810 INL is measured from 2% to 100% of the full-scale
(FS) output.
The maximum output voltage from the ADN8810 is a function
of output current and supply voltage. Compliance voltage
defines the maximum output voltage at a given current and
supply voltage to guarantee the device operates within its INL,
DNL, and gain error specifications.
Differential Nonlinearity
This is a measure of the ADN8810 output impedance and is
similar to a load regulation spec in voltage references. For a
given code, the output current changes slightly as output voltage
increases. It is measured as an absolute value in (ppm of fullscale range)/V.
Differential nonlinearity (DNL) is the difference between
the measured change and the ideal 1 LSB change between
any two adjacent codes. A specified differential nonlinearity
of ± 1 LSB maximum ensures monotonicity. The ADN8810
is guaranteed monotonic by design. Figure 6 shows a typical
DNL vs. code plot.
Output Current Change vs. Output Voltage Change
GAIN ERROR
PLUS
OFFSET ERROR
Offset Error
INTERPOLATED
OUTPUT VOLTAGE
Offset error, or zero-code error, is an interpolation of the output
voltage at code 0x000 as predicted by the line formed from the
output voltages at code 0x040 (2% FS) and code 0xFFF (100%
FS). Ideally, the offset error should be 0 V. Offset error occurs
from a combination of the offset voltage of the amplifier and
offset errors in the DAC. It is expressed in LSBs.
IDEAL
Offset Drift
ACTUAL
(EXAGGERATED)
This is a measure of the change in offset error with a change in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error
OFFSET
ERROR
Rev. 0 | Page 8 of 16
0x040
0xFFF
DAC CODE
Figure 4. Output Transfer Function
03195-0-004
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the output transfer characteristic from
ideal. The transfer characteristic is the line formed from the
output voltages at code 0x040 (2% FS) and code 0xFFF (100%
FS). It is expressed as a percent of the full-scale range.
ADN8810
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
1.2
1.0
0.15
0.8
∆DNL (LSB)
INL ERROR (LSB)
0.10
0.6
0.4
0.2
0
0.05
0
–0.05
–0.2
–0.10
–0.6
–0.8
0
500
03195-0-008
03195-0-005
–0.4
–0.15
–0.20
–40
1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500
CODE
–15
Figure 5. Typical INL Plot
10
35
TEMPERATURE (°C)
60
85
Figure 8. ∆ DNL vs. Temperature
0.4
0.258
0.257
0.2
0.256
0.1
0
–0.1
–0.3
03195-0-006
–0.2
0
500
0.255
0.254
0.253
0.252
03195-0-009
FULL-SCALE OUTPUT (A)
DNL ERROR (LSB)
RS = 1.6Ω
0.3
0.251
0.250
–40
1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500
CODE
Figure 6. Typical DNL Plot
–15
10
35
TEMPERATURE (°C)
60
85
Figure 9. Full-Scale Output vs. Temperature
0.20
20.765
0.15
20.760
0.05
0
–0.05
–0.10
03195-0-007
DINL (LSB)
0.10
–0.15
–0.20
–40
–15
10
35
TEMPERATURE (°C)
60
85
20.755
20.750
20.745
20.740
20.735
20.730
03195-0-010
FULL-SCALE OUTPUT (mA)
RS = 20Ω
20.725
20.720
–40
–15
10
35
TEMPERATURE (°C)
60
Figure 10. Full-Scale Output vs. Temperature
Figure 7. ∆ INL vs. Temperature
Rev. 0 | Page 9 of 16
85
ADN8810
0.50
105
CODE = x000
RS = 1.6Ω
0.45
0.40
OUTPUT IMPEDANCE (Ω)
104
0.25
0.20
0.15
0.10
0
–40
–15
10
35
TEMPERATURE (°C)
60
102
101
03195-0-011
0.05
103
03195-0-014
IPVDD (mA)
0.35
0.30
10
85
10
1k
10k
FREQUENCY (Hz)
100
100k
1M
Figure 14. Output Impedance vs. Frequency
Figure 11. PVDD Supply Current vs. Temperature
0
12
CODE: x700 TO xFFF
CODE = x000
0
10
5V/DIV
VOLTAGE (2.7V/DIV)
CS0
IDVDD (µA )
8
6
4
0
0
0
0
03195-0-012
0
–40
–15
10
35
60
03195-0-015
300mA/DIV
2
IOUT
0
0
85
0
0
TEMPERATURE (°C)
0 0 0
0
0
TIME (1µs/DIV)
0
0
0
Figure 15. Full-Scale Settling Time
Figure 12. DVDD Supply Current vs. Temperature
1.5
CODE: x7FF TO x800
RS = 1.6Ω
CODE = x000
5V/DIV
CS
1.3
IOUT
1.2
10mA/DIV
1.0
–40
–15
10
35
TEMPERATURE (°C)
60
85
03195-0-016
1.1
03195-0-013
IAVDD (mA)
1.4
0
0
0
0 0 0
0
0
TIME (200ns/DIV)
0
Figure 16. 1 LSB Settling Time
Figure 13. AVDD Supply Current vs. Temperature
Rev. 0 | Page 10 of 16
0
0
ADN8810
FUNCTIONAL DESCRIPTION
The ADN8810 is a single 12-bit current output D/A converter
with a 3-wire SPI interface. Up to eight devices can be
independently programmed from the same SPI bus.
The full-scale output current is set with two external resistors.
The maximum output current can reach 300 mA. Figure 17
shows the functional block diagram of the ADN8810.
DVDD AVDD FAULT
BIAS
GEN
SB
FB
AVDD provides power to the analog front end of the
ADN8810 including the DAC. Use this supply line to
power the external voltage reference. For best performance,
AVDD should be low noise.
•
DVDD provides power for the digital circuitry. This
includes the serial interface logic, the SB and RESET logic
inputs, and the FAULT output. Tie DVDD to the same
supply line used for other digital circuitry. It is not
necessary for DVDD to be low noise.
•
PVDD is the power pin for the output amplifier. It can
operate from as low as 3.0 V to minimize power dissipation
in the ADN8810. For best performance, PVDD should be
low noise.
ENCMP
FAULT
DETECTION
PVDD
1.5kΩ
PVDD
VREF
12-BIT
DAC
IOUT
IOUT
CONTROL
LOGIC
RSN
ADDRESS
DECODER
SDI
DGND
1.5kΩ
15kΩ
ADDR2 ADDR1 ADDR0 RESET
DVSS
Figure 17. Functional Block Diagram
SETTING FULL-SCALE OUTPUT CURRENT
Two external resistors set the full-scale output current from the
ADN8810. These resistors are equal in value and are labeled RSN
in the Functional Block Diagram on the front page. Use 1% or
better tolerance resistors to achieve the most accurate output
current and the highest output impedance.
Equation 1 shows the approximate full-scale output current.
The exact output current is determined by the data register code
as shown in Equation 2. The variable code is an integer from 0
to 4095, representing the full 12-bit range of the ADN8810.
4.096
10 × RSN
IOUT =
Code
1 ⎛ RSN
×
×⎜
+ 0.1⎞⎟
1,000 RSN ⎝ 15k
⎠
•
AVSS is the return path for both AVDD and PVDD. This
pin is connected to the substrate of the die as well as the
slug on the bottom of the LFCSP package. For singlesupply operation, this pin should be connected to a low
noise ground plane.
•
DVSS returns current from the digital circuitry powered by
DVDD. Connect DVSS to the same ground line or plane
used for other digital devices in the application.
•
DGND is the ground reference for the digital circuitry. In a
single-supply application, connect DGND to DVSS.
03195-0-017
SCLK
Current is returned through three pins:
AVSS
12-BIT
DATA LATCH
CS
I FS ≈
•
(1)
(2)
REFERENCE VOLTAGE SOURCE
The ADN8810 is designed to operate with a 4.096 V reference
voltage connected to VREF. The output current is directly
proportional to this reference voltage. A low noise precision
reference should be used to achieve the best performance. The
ADR292, ADR392, or REF198 is recommended.
POWER SUPPLIES
There are three principal supply current paths through the
ADN8810:
For single-supply operation, set AVDD to 5 V, set PVDD from
3.0 V to 5 V, and connect AVSS, AGND, and DGND to ground.
SERIAL DATA INTERFACE
The ADN8810 uses a serial peripheral interface (SPI) with three
input signals: SDI, CLK, and CS. Figure 2 shows the timing
diagram for these signals.
Data applied to the SDI pin is clocked into the input shift
register on the rising edge of CLK. After all 16 bits of the dataword have been clocked into the input shift register, a logic high
on CS loads the shift register byte into the ADN8810. If more
than 16 bits of data are clocked into the shift register before CS
goes high, bits will be pushed out of the register in first-in firstout (FIFO) fashion.
The four most significant bits (MSB) of the data byte are
checked against the device’s address. If they match, the next 12
bits of the data byte are loaded into the DAC to set the output
current. The first bit (MSB) of the data byte must be a logic zero,
and the following three bits must correspond to the logic levels
on pins ADDR2, ADDR1, and ADDR0, respectively, for the
Rev. 0 | Page 11 of 16
ADN8810
DAC to be updated. Up to eight ADN8810 devices with unique
addresses can be driven from the same serial data bus.
word correspond to the address. Note that the first bit loaded
(A3) must always be zero. The remaining bits set the 12-bit data
byte for the DAC output. Three example inputs are
demonstrated.
Table 5 shows how the 16-bit DATA input word is divided into
an address byte and a data byte. The first four bits in the input
Table 5. Serial Data Input Examples
Address Byte
A3
A2
0
1
0
0
0
1
A1
1
0
0
A0
1
0
0
Data Byte
D11
D10
0
0
1
0
1
1
Example 1: This SDI input sets the device with an address of
111 to its minimum output current, 0 A. Connecting the
ADN8810 pins ADDR2, ADDR1, and ADDR0 to VDD sets this
address.
Example 2: This input sets the device with an address of 000 to
a current equal to half of the full-scale output.
Example 3: The ADN8810 with an address of 100 is set to fullscale output.
D9
0
0
1
D8
0
0
1
D6
0
0
1
D5
0
0
1
D4
0
0
1
D3
0
0
1
D2
0
0
1
D1
0
0
1
D0
0
0
1
Example 4: A 300 mA full-scale output current is required to
drive a laser diode within an 85°C environment. The laser diode
has a 2 V drop and PVDD is 3.3 V.
Using Equation 3, the power dissipation in the ADN8810 is
found to be 267 mW. At TA = 85°C, this makes the junction
temperature 93.5°C, which is well below the 150°C limit. Note
that even with PVDD set to 5 V, the junction temperature would
increase to only 110°C.
USING MULTIPLE ADN8810S FOR ADDITIONAL
OUTPUT CURRENT
STANDBY AND RESET MODES
Applying a logic low to the SB pin deactivates the ADN8810 and
puts the output into a high impedance state. The device
continues to draw 1.3 mA of typical supply current in standby.
Once logic high is reasserted on the SB pin, the output current
returns to its previous value within 6 µs.
Applying logic low to RESET will set the ADN8810 data register
to all zeros, bringing the output current to 0 A. Once RESET is
deasserted, the data register can be reloaded. Data cannot be
loaded into the device while it is in Standby or Reset mode.
POWER DISSIPATION
Connect multiple ADN8810 devices in parallel to increase the
available output current. Each device can deliver up to 300 mA
of current. To program all parallel devices simultaneously, set all
device addresses to the same address byte and drive all CS, SDI,
and CLK from the same serial data interface bus. The circuit in
Figure 18 uses two ADN8810 devices and delivers 600 mA to
the pump laser.
CS
SERIAL
INTERFACE
(FROM µC
OR DSP)
FB
SCLK
IOUT
RSN
ADDR2 ADDR1 ADDR0
CS
(3)
FB
SCLK
The power dissipated by the ADN8810 will cause a temperature
increase in the device. For this reason, PVDD should be as low
as possible to minimize power dissipation.
While in operation, the ADN8810 die temperature, also known
as junction temperature, must remain below 150°C to prevent
damage. The junction temperature is approximately
TJ = TA + θ JA × PDISS
where TA is the ambient temperature in °C, and θJA is the
thermal resistance of the package (32°C/W).
(4)
RS
1.37Ω
RS
1.37Ω
ADN8810
SDI
The power dissipation of the ADN8810 is equal to the output
current multiplied by the voltage drop from PVDD to the
output.
PDISS = I OUT × (PVDD − VOUT ) − I OUT ² × RS
D7
0
0
1
IOUT
RS
1.37Ω
ADN8810
SDI
RS
1.37Ω
RSN
ADDR2 ADDR1 ADDR0
D1
ILD
600mA
Figure 18. Using Multiple Devices for Additional Output Current
ADDING DITHER TO THE OUTPUT CURRENT
Some tunable laser applications require the laser diode bias
current to be modulated or dithered. This is accomplished by
dithering the VREF voltage input to the ADN8810. Figure 19
demonstrates one method.
Rev. 0 | Page 12 of 16
03195-0-018
SDI Input
Ex. 1
Ex. 2
Ex. 3
ADN8810
R2
1.62kΩ
5V
5V
AD8605
D1
ADR292
5V
ENCOMP DVDD AVDD PVDD
VREF
VIN VOUT
GND
CS
ADN8810
IOUT
FDC633N
OR EQUIV
SCLK
TTL/CMOS
LOGIC LEVELS
3
SDI
RSN
ADDR0-2
RS
6.81Ω
AVSS DVSS DGND
03195-0-020
SB
The AD8605 is recommended as a low offset, rail-to-rail input
amplifier for this circuit.
NOTE: LEAVE FB WITH NO CONNECTION
DRIVING COMMON-ANODE LASER DIODES
Figure 20. Driving Common-Anode-to-VDD Laser Diodes
–5V
The ADN8810 can power common-anode laser diodes. These
are laser diodes whose anodes are fixed to the laser module
case. The module case is typically tied to either VDD or ground.
For common-anode-to-ground applications, a negative 5 V
supply must be provided.
D1
ADR292
ENCOMP DVDD AVDD PVDD
VREF
VIN VOUT
GND
In Figure 20, RS sets up the diode current by the equation
CS
I = 300mA
@ CODE 0x7F
NC
ADN8810
IOUT
FDC633N
OR EQUIV
SCLK
–5 TO 0V
LOGIC LEVELS
SDI
3
RSN
ADDR0-2
(5)
SB
where Code is an integer value from 0 to 4,095. Using the values
in Figure 20, the diode current is 300.7 mA at a code value of
2,045 (0x7FF), or one-half full-scale. This effectively provides
11-bit current control from 0 mA to 300 mA of diode current.
FB
RESET
–5V
⎛ 1
1 ⎞ Code
⎟×
+
I = 4.096 × 1.1⎜⎜
R
16
.5k ⎟⎠ 4096
⎝ S
I = 300mA
@ CODE 0x7F
NC
RESET
Figure 19. Adding Dither to the Reference Voltage
Set the gain of the dither by adjusting the ratio of R2 to R1.
Increase C to lower the cutoff frequency of the high-pass filter
created by C and R1. The cutoff frequency of Figure 19 is
approximately 10 Hz.
FB
RS
6.81Ω
AVSS DVSS DGND
–5V
–5V
NOTE: LEAVE FB WITH NO CONNECTION
Figure 21. Driving Common-Anode-to-Ground Laser Diodes with a Negative
Supply
+3V
The maximum output current of this configuration is limited by
the compliance voltage at the IOUT pin of the ADN8810. The
voltage at IOUT cannot exceed 1 V below PVDD, in this case
4 V. The IOUT voltage is equal to the voltage drop across RS plus
the gate-to-source voltage of the external FET. For this reason,
select a FET with a low threshold voltage.
100kΩ
NDC7003P
OR EQUIV
TTL/CMOS
LEVEL
NDC7002N
OR EQUIV
TO: RESET
CS
SCLK
SDI
10kΩ
In addition, the voltage across the RS resistor cannot exceed the
voltage at the cathode of the laser diode. Given a forward laser
diode voltage drop of 2 V in Figure 20, the voltage at the RSN pin
(I × RS) cannot exceed 3 V. This sets an upper limit to the value
of Code in Equation 5.
Although the configuration for anode-to-ground diodes is
similar, the supply voltages must be shifted down to 0 V and
–5 V, as shown in Figure. The AVDD, DVDD, and PVDD pins
are connected to ground with AVSS connected to –5 V. The
4.096 V reference must also be referred to the –5 V supply
voltage. The diode current is still determined by Equation 5.
03195-0-021
4.096V
5V
TO VREF
DITHER
–5V
–5V
03195-0-021
R1
1.62kΩ
03195-0-019
C
1µF
pins. Figure shows a simple method to level shift a standard
TTL or CMOS (0 V to 5 V) signal down using external FETs.
Figure 22. Level Shifting TTL/CMOS Logic
PC BOARD LAYOUT RECOMMENDATIONS
Although they can be driven from the same power supply
voltage, keep DVDD and AVDD current paths separate on the
PC board to maintain the highest accuracy; likewise for AVSS
and DGND. Tie common potentials together at a single point
located near the power regulator. This technique is known as
star grounding and is shown in Figure. This method reduces
digital crosstalk into the laser diode or load.
All logic levels must be shifted down to 0 V and –5 V levels as
well. This includes RESET, CS, SCLK, SDI, SB, and all ADDR
Rev. 0 | Page 13 of 16
ADN8810
SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE
5V
3V
GND
TO OTHER 5V
DIGITAL LOGIC
LOAD
GND
LOGIC GROUND
RETURN
PVDD
DVSS AVSS
DGND
ADN8810
LOAD
03195-0-023
DVDD AVDD
IOUT
shows the dimensions for the PC board pad layout for the
ADN8810. The package is a 4 mm × 4 mm, 24-lead LFCSP. The
metallic slug underneath the package should be soldered to a
copper pad connected to AVSS, the lowest supply voltage to the
ADN8810. For single-supply applications, this is ground. Use
multiple vias to this pad to improve the thermal dissipation of
the package.
0.027
(0.69)
Figure 23. Star Supply and Ground Technique
To improve thermal dissipation, the slug on the bottom of the
LFCSP package should be soldered to the PC board with
multiple vias into a low noise ground plane. Connecting these
vias to a copper area on the bottom side of the board will
further improve thermal dissipation.
Use identical trace lengths for the two output sense resistors.
These lengths are shown as X and Y in Figure 24. Differences in
trace lengths cause differences in parasitic series resistance.
Because the sense resistors can be as low as 1.37 Ω, small
parasitic differences can lower both the output current accuracy
and the output impedance. Application Note AN-619 shows a
good layout for these traces.
0.004
(0.10)
0.172
(4.36)
0.011
(0.28)
0.109
(2.78)
0.020
(0.50)
PACKAGE
OUTLINE
DIMENSIONS ARE SHOWN
IN INCHES AND (MM).
0.106
(2.68)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
ADN8810
Figure 25. Suggested PC Board Layout for CP-24 Pad Landing
FB
X
RSN
IOUT
Y
RSN
03195-0-024
TO LOAD
RSN
Figure 24. Use Identical Trace Lengths for Sense Resistors
Rev. 0 | Page 14 of 16
03195-0-025
POWER SUPPLY
ADN8810
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
TOP
VIEW
3.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
12° MAX
PIN 1
INDICATOR
19
18
24 1
2.25
2.10 SQ
1.95
BOTTOM
VIEW
13
12
7
6
0.25 MIN
2.50 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN8810ACP
ADN8810ACP- REEL7
ADN8810-EVAL
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
24-Lead LFCSP
24-Lead LFCSP
Evaluation Board
Rev. 0 | Page 15 of 16
Package Option
CP-24
CP-24
ADN8810
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03195-0-1/04(0)
Rev. 0 | Page 16 of 16