ETC MC33201

ⅢC33201ⅢC33202
ⅢC33204
干线至干线运算放大器
MC33201⒓ /4运 算放大器系列在输 入端和输 出端都提供干线
至干线工作 ◇输入可用高 出电源干线 200毫 伏的信号驱动而
保持输 出相位不反转 ,输 出则可在每个干线 的 50毫 伏 内摆
c
Cc输
Ncr川
输
出
ι
咖
vEE
嗍
典型增益带宽积 〓2.2兆 赫
ˉ
+125° C)
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鲡
动 。这 一 干线至干线运行使用户能充分利用有效的电源 电压
范围。它被设计 为工作在很低 的电源 电压下 (± 0.9伏 ),但
也能 工 作在 高达 +12伏 和地之间的电源下 。输 出电流提升技
术提供输 出大 电流能力 ,而 同时保持放大器的消耗 电流最小 。
还有 ,低 噪声和 失真与高转换速率和驱动能力的结合使之成
为音频应用的理想放大器 。
・ 低 电压 ,单 电源 工 作 (|1,8伏 对地至 +12伏 对地 )
输入 电压范围包括两个 电源干线
输 出电压摆动 围绕每个干线 50毫 伏
对过驱动 的输入信号在输 出端不会反相
高输 出电流 (Isc〓 80毫 安 ,典 型值 )
低 电源 电流 (lD〓 0.9毫 安 ,典 型值 )
600Ω 输 出驱动能力
扩 展 的 I作 温 度 范 围 (-00° C至 +105° C和 -s5° C至
安森美半导体
oⅡ sem:co"d"Ct● r
(单 运 放 ,俯 视 图 )
(sooB)
婶
D后 缀
^
1
:《〈讠h
i
(micro.B)
D"后 缀
外壳 846A
(双 运放,俯 视图)
llIllll刂
ll:、
1J。
1
1
P后 缀
外壳 s06
94<日
《
刂‘
(so"4)
D后 缀
外壳 7siA
:l甘
(TssoP丬 4)
砷
DTB斤衫旺
外壳 948G
1
入
"vEEP鼬
输出 1
vc
2
入
输出 2
(四 运放 ,俯 视 图 )
订购信息
见本数据表第 10页 封装尺 寸部分的详细订购和装运信
息。
◎半导体元件工业有限公司,2000
199θ 年 i0月 第 3次 怪 订版
出版 物 订 购 号
:
mc332o闸 cH`D
"C33201mC332o2mC332o4
图 1电 路原 理 图
(每 个放大器 )
这个器件包含 70个 有效晶体管 (每 个放大器 )
最大额定值
额定值
电源 电压lVcc至 VEE)
输 入差动 电压范围
共模输 入 电压 范 围 (注 2)
符号
值
单位
Vs
+13
V
VIDR
(注 1)
VcM
Vcc+0.5V至
V
V
VFFˉ 0.5V
(注 3)
输 出短 路 持 续 时 问
最 大 结温
保存温度
Tst。
+150
ˉ
65至 +150
最大 功 耗
PD
(注 3)
TJ
s
0c
0C
mW
注 :1每 个放大器 的差动输 入受 限于两个 内部并联 的背对背二极管 。需要 附加羌动输入 电压范围 ,则 在输 入管脚处使用限流 串联 电阻
2每 个放
输入电压范围受限于连在输入端与电源干线问的⊥极耸 。因此
夺镤 墅:(模
3必 须对功耗加以考虑 ,以 保证不超过最大结温 (TJ)
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2
,
任一输入端的电压不能超 过 任 一 电源 干 线 电压
ⅢC33201Ⅲ C33202Ⅲ C33204
〓z0ˇ △
直流 电
V^n〓 5.OV
Vcc〓 3.3V
Vcc=2.OV
特性
入
电压
失
调
输
单位
mV
MC33201
MC33202
M0332o4
ο・ο 2
出 LL
VI。 (max)
±8.o
±10
±12
±6.0
±8.0
±10
输出电压摆动
⒈9
VoH(RL〓 10kΩ )
VnlfRI〓 10kΩ )
3.15
o.15
o,10
485
Vmm
o.15
Vmnγ
mA
每个放大器的
电源电流(lD)
Vcc〓
沆 〓33V的 规,lg由 20V和 50V测 i式
1.125
1.125
1.125
VEE〓 地
直流 电气特性lVcc〓 +5.OVVEE〓 地,TA〓 2s° C,除 非另有规定 。)
C
TA〓 艹0° 至 +10s°
ˉ
TΔ 〓
55° 至 +125°
n
495.
4.75
4.85
5
RL=600Ω
RI〓 600Ω
o。
12
电源 电压 抑 制 比
CMR
PsRR
输 出短 路 电沉 (拉 才口
13,14
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3
dB
ILVA/
mA
80
ο
艹
o.25
25
99
ID
o15
90
ο
15
每 个 放 大 器 的 电源 电流 (V。 =OV)
TA〓 -40° 至 +105° C
TA〓 -55° 至 +125° C
60
500
50
Vnr/VFF=5.OV:歪 3.OV/M
05
o.15
VnI
共模抑制 (Vi泸 0V至 5,OV)
V
V
8,9,10
RL〓 10kΩ
RL〓 10kΩ
・
4.85
RL〓 600Ω
输 出 电压摆 动 lVD=± 0.2V)
32
V。 H
V。 L
V。 H
RL=10kΩ
nA
KX/A/
00
05
VFF
52
大信 号 电压 增 益
Vpc
VI。 R
Av。 L
ο
7
Α
入 电压 范 围
∞⑻猢
・
C
C
ο
|
5ο
°
ο
l丨
225
OV)
ο
ο
5。
ο ο
・
51
△:
⒛⑾・
T厶 〓ˉ
55° 至 +125°
C
ο
TA〓 ˉ
40° 至 +105°
5,6
C
C
输 入 失 调 电流 lVcM〓 OV至 0.5Ⅵ VcM〓 1。 OV全
TA=+25° C
uV/°
ο
TA〓 -40° 罕 +105°
TA〓 ˉ
55° 至 +125°
22
输入偏罴电流lVcM=OV至 0.5VVcM〓 1,OV至 5,OV)
C
ΔVl。 /AT
C
C
输 入 失调 电压温 度 系数 (Rs〓 50Ω )
TA=ˉ 40° 至 +105° C
〓ˉ
▲
55° 局
甬+125° C
TA〓 +25°
4
37
C
C
14ο
00° 至 +10s°
TA〓 ˉ
TA〓 -55° 罕 +125°
MC33204:TA〓 +25°
MC33202;TA〓 +25° C
ο
C
C
mV
3・
TA〓 -40° 至 +105°
TA〓 ˉ
55° 至 +125°
立
Vld
丨
ο
・ ・
MC3320⒈ TA=+25° C
于十
3
691811111
性
0,5Ⅵ VcM10V垒 5.OV)
(VcMOV至
ο
输入 失调 电压
mA
1.125
1,125
ⅢC33201"C33202Ⅲ C33204
〓地 ,TA=25° C,除 非另有规定 。
〓±2.5VV。 〓ˉ
2.OV至 +2,OVRL=2.0kΩ ,Av〓 +1.o
〓1,0VPP,Av=冂 .0)
Ⅳ°
OkHz
f〓 10kHz
f〓
1。
f〓
f〓
10Hz
f〓
1.OkHz
f〓
10Hz
f〓
1,OkHz
2.OMHz,Av=10
声电压(Rs=100Ω )
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4
ⅢC33201Ⅲ C33202Ⅲ C33204
Tss0R14封 装
Vcc〓 +50V
Vε
f地
TA〓 25°
ll卜
— △ — — 卜 — L⒑
ο
ο
.
50
■
■
■
-80 -60 -40 -2,0
0
20
田0
图 5.输 入偏置电流与温度关系曲线
图 4.输 入失调电压温度系数分布图
擗次
■甄
诧Jy肾 Ⅳ
g蟋
岔 ￠ˇ
烬 留婀喀
⌒
求ˇ
翌乐 肛
200
50
VEE〓 地
TA〓 25°
30
C
|
Vcc〓 +50V
VEE〓 地
160
120
<擤
Vρ
M
o Vto⒍
5V
丿
80
vGM
】,OV
.飞
■
10
■
o
二
骓 巛 揆 舶丶
姐
η苜
20
60
Vl。 ,输 入失调电压(mV)
TA,环 境温度(° C)
40
C
DlP封 装
m5・
25
测试 360个 放大器
廊 白 n个 品 片 Hl次
■
巧
ε°
⊥
^^秃
0
Γ — △ — — 卜 — LΓ — 卜
“
⒛
⒛
⒛
⌒
荃ˇ
彐 东 陋 黑睐 巛 揆 羽如
⌒
濯督巛嵴
Ξεˇ
8和 14管 脚 DIP封 装
-55 -40 -25
图 3.输 入失调电压分布图
硐
图 2.最 大功耗与温度关系曲线
; 40
■
-50 -40 -30 -20 -10
L
o△ -… ˉ
0
10
20
30
40
-55 -40 ˉ25
50
0
25
70
85
11
ω
TCⅥ 。
,输 入失调电压温度系数(uV/° c)
TA,环 境温度(° C)
图 6.输 入失调 电流与共模 电压关系 曲线
图 7.开 环电压增益与温度关系曲线
∞
⌒
之
∞
>吕
J。
Vcc〓 +50Vˉ
∞ ∞
2
・
.望
唰 璎以 型 咚 卡 〓 扌
ο
∞
丬
<樨
⒃ ∞
・ 丬
⌒<cˇ螟型嗣嫘
r
2・
VEE-地
300
260
220
/
/
180
40
60
80
I
l
Vcc〓 50V
140
TA=25° C
20
'
VEE〓 地
RL〓 600Ω
ΔV° =05VI至
100
-55
1Q
VcM,输 入共模 电压 lV)
I
-40
-25
45V
0
25
70
TA,环 境温度(° C)
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5
85
105
125
ⅢC3320闸
"C33202mc332o4
图 9.输 出饱和电压与负载电流关系曲线
图 8.输 出电压摆动与电源 电压关系 曲线
ˉ
r^〓
⒈
Vccˉ
±⒊0
±⒋0
02V
T
vCCˉ 0・ 4v
VEE+⒍ 4V
+0,2V
.甾
ハ
△α>ˇ 硐韶彐擤〓
>
⌒>ˇ 囤 型 展 寒 羽霪 〓 >
J-}5。
zsoσ
vCC
±⒌o
vcc,|vEE|,电 源电压lV)
图 iq,共 模抑制与频率关系曲线
图 10。 输出电压与频率关系曲线
100
12
窗 °ˇ
幂 嚣邺 枨
τα
δ田
θ,o
J钥
60
擤
丨 丨 |||
Σ°
\
30 ˉRL=6l,0Ω
\
AVˉ 1G
TA1251c|H
`
o
⒈Ok
sll
40
.∝
.。
>
vCC=△ θ・
Ov
VEE=ˉ 60V
80
10k
o
10M
100k
20
】Ok
100
10k
100k
f,频 率(Hzl
图 12.电 源 电压抑制与频率关系曲线
图 13,输 出短路电流与输出电压关系曲线
∞
⒛
f,频 率(Hzl
`'
⒛
m硐
ω
灌
//
∥
〃r
^~8二
⒛
亠
⒛
r∞
⒃
岔 已幂 屠 赆 型
⒛
岔 Eˇ螟型凿嘤彐擤
ο
ο
拉
vcc」 +6,Ov
VEE=-6,OV
ο
ο
TA=ls° c
1,Ok
1 0
10k
2,0
3,0
4,o
压lV)
|吒 “
|,输 出电
f,频 率(Hzl
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6
10M
MC33201Ⅲ C33202Ⅲ C33204
图 15。 无负载时,每 个放大器的电源 电流与电源
电压关系曲线
图 14,输 出短路 电流与温度关系 曲线
Eˇ
100
-^
、
50
・
濯
TA屮 zs° c
2B彳
苎
75
⒗
螟 留赆 型 ε骓 巛 揆
nd
螟 留 蜜 烈 钥擤
Eˇ
125
ο
岔
5・
ο
岔
∶
C
v
150
8三
(咿
^一
25
ο ±
^8一
o
-55 -40-25
o
25
70
85
10s
TA=25Ⅱ
/
125
褶
∷
c
姒
〃
±10
±20
vc注 |v∶ E|,电
TA,环 境温度(℃ )
40
Q工
vQ=± ⒎Ov
悱躅邱溆 〓
∝ω
>ˇ
30
+!转 换速率
-转 换速率
'
'
o,5
o
0
25
70
85
105
源电压lV)
f=100kHz
-55 -40 -25
125
o
85
105
12s
m
l
相位 Vs:± 60v
相位 Vs宝 ±6‘ OV
增益 Vs=± 10v
坼曾宝邕Vs=± 1,0v
酗
100k
10M
f,频 率(Hzl
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⒛喇
10k
f,频 率(Hzl
⒀
8AB
冖】
o
|l||||Il
2A
⌒
恻ˇu巽 酬 刺 〓
⑩
钔
-^
10
-30
7
m
|
F狃
1Ⅱ
CL`RL
、
刂
h
ο
ρΩ
ο
ο
δ
30
Α
10M
~i}、
丨 ||「 ltz
50
.
|
d扌
100k
⒛M
l | l|l llI
|
.⑩
1BΓ
岔υˇ
娟璎田梨渚卡〓
⌒
剿ˇu巽 酬刺
猢
仞
锏
|
t:|l∶ iF
l
| I ll
I Αˉ刂
扌
.J。
’
鏊∶
营
I
ⅢⅢ叩爿 "Ⅲ ⅢⅢⅢμⅢⅢⅢⅢm
30
R1=6lXlΩ
70
⒛
4
mm""Ⅲ
凵
TA=⒛ ℃
↓ 宋
岔 υˇ
涠 鹦 囤 型 旨肽
50
70
图 19.电 压增益和相位与频率关系曲线
m
mⅢ
vs=± ⒍Ov
|
z5
TA,环 境温度 (° C)
图 18。 电压增益和相位与频率关系曲线
10k
±6‘ o
1
70
-30
0
Vcc=衤 2,5V
TA,环 境温度(° C)
-10
5‘
2
⒈o
-5s -40 -25
10
±
VEE=-2,5V
〓∞
O
Σˇ癸 髁靼 娟 罂 〓
璧
⌒
v0C=i25v
vEE=^25v
15
±4,0
图 17.增 益带宽积与温度关系曲线
图 16。 电压增益和盯位与频率关系 曲线
20
±3,0
"C33201mC332o2mc332o4
乃
图 ni。 增益和相位余童与差动源电阻关系曲线
图 20.增 益和相位余量与温度关系
70
相位余量
相位余量
40
30
Ov
|
'CC=+6・
6000
`EE:-60V
RL±
.多
^泛
③
20
|||||||||
`
vGC=+θ ・
Ov
VEE=ˉ 6,OV
i^〓 25。 C
.虱
)L=100ρ F
6ο
50
⌒
恻酰巛u聊
u巽
岔 υˇ
喇巛 娟 哪 双
⌒
侧ˇ
酬巛
so
`
||
徐量
增
ο
10
喟盂笊星
o
-55 -40 -25
o
25
70
85
105
冂
00
10
125
冂
Ok
10k
100k
RT,差 动电阻ρ)
TA,环 境温度(° C)
图 23.通 道隔离度与频率关系 曲线
图 22.增 益余量和相位余量与 电容负载关系 曲线
150
⑾
⒛
`⒀
一 ∞
⌒
铡ˇ
酬 巛逻巽
.蛋
⒛
.Σ
.∞
Q
岔 υˇ
铡 腿 璺剩 嘲 °
岔 °ˇ
酬 巛娟 罂 双
Av=1∝
120
90
60
l
I
mο
vCC’ +6・ Ov
-60V
30 .VEE〓
Vo=80V¤ 。
T^〓 25° C
o
100
l
10k
f,频 率(Hzl
图 25.等 效输入噪声电压和 电流与频率关系 曲线
宙工
图 24,总 谐波失真度与频率关系 曲线
5.o
⑽
~'>cˇ
⑷
⒛
m
∶
言
<曝
|景
⒑
卜
揆鞭
d工
<ˇ
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10首皙
忄
^J
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⌒菸ˇ赋巛 祭靼 羽
4⒑
ⅢC33201Ⅲ C33202Ⅲ C33204
详细 工 作描述
电路信息
通用信息
通过在放大器 的输入端使用并联 NPNˉ PNP差 动输
运算放大器 的 MC3320侈 阳 家族在输 入端和输 出端
入级 ,实 现 了干线至十线性能 。当输入处于负干线的
均具有带完 全双极性设 计的十线至干线摆动 能力
800mV范 围内 ,PNP级 导通 。当输入超过 VEE800mV
这是它们所独有 的 。这 就提供 了低噪声 、 高输 出电
以上时 ,NPN级 导通 。输入对 的如此切换将导致输
r以 具有 的宽共模
流容量和 即使在低 电源 电压下也 自
入偏置 电流反 向 (见 图 6)。 而诅~,在 NPN和 PNP
输 入 电压范围 。在扩展的温度范围内和 2,OV、 33V、
对 间 ,可 以发现输入失调 电压有微小差别 。
5.0V对 地 电源 电压下 ,工 作均得到保证 。
除了它 的千线至干线性 能 ,输 出级具有 电流提
由于共模输入 电压范围扩展为从 Vcc至 VEE,lRl而
,可 以提供高达 80mA的 输 出电流 ,从 而使
。
工作
升能力
,它
在整个共
电源下
均
能够
电源或分离
在单
叮以驱动 600Ω 的负载 。由于如此高的输 出电
放大器
抑
证不锁定或相位反转
,MC3320侈
保
模范围内
,应
该注 意不要让结温超过 150° C的 最大纬
。
流容量
然丨
盯,输 入仍不应该超过最大额定值
氵
Ⅰ
云
,
,
,
l。
图 27,小 信号瞬态响应
图 26.同 相放大器转换速率
⌒
逸
⌒靼 氵
>E0s田
E0.s型
J钥
°
擤∽
>
>
型 钥蟑 δ
t,时
问(50us/格
t,时 问(10us/格 )
)
图 28.大 信号瞬态 响应
⌒
蝰
>°
.巳
。
型 型 彐擤 〓
>
t,时 间(10us/格 )
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9
MC3320日 ⅢC33202MC33204
订购信息
运算放大器功能
单运 放
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器件
MC33201D
MC33201DR2
MC33201P
MC33201VD
MC33201VDR2
MC33201VP
MC3202D
MC3202DR2
MC33202DMR2
MC33202P
MC33202VD
MC33202VDR2
MC33202VP
MC33204D
MC33204DR2
MC33204DTB
MC33204DTBR2
MC33204P
MC33204VD
MC33204VDR2
MC33204VP
工作温度范围
TA〓 ˉ
40° 至 +105°
C
封装
装运
so-8
so-8
98器 件 /轨
2500器 件 /卷 带
sO器 件/轨
98器 件 /轨
2500器 件/卷 带
50器 件/轨
98器 件/轨
2500器 件/卷 带
4000器 件 /卷 带
50器 件/轨
98器 件 /轨
2500器 件/卷 带
50器 件 /轨
55器 件 /轨
2500器 件/卷 带
96器 件 /轨
2500器 件/卷 带
25器 件 /轨
55器 件/轨
2500器 件/卷 带
25器 件/轨
塑料 DIP
TA〓 -40° 至 +125°
C
so-8
so-8
塑料 DIP
TA〓 ˉ
40° 阝
巨+105°
C
so-8
so-8
Micro-8
塑料 DIP
Soˉ 8
TA=-40° 至 +125°
C
s0ˉ 8
塑料 DlP
Soˉ 14
So-14
TA=-40° 至 +105°
C
Tss0P-14
TssOP-14
塑料 DIP
TA〓 -40° 罕 +125°
C
So-14
So-14
塑料 DIP
h“ p:〃 insem1,com。
10
cn
ⅢC33201MC33202"C33204
封装尺寸
P后 缀
塑料封装
夕卜
房己626-05
版本 K
注
;
2.
尺寸 L为 平行引线中心间距离 。
封装轮廓可选 (圆 角或直角 )。
3.
尺
1i
八寸
A
公差按
ANsl
趸寸
940
o370
445
C
D
0175
o040
F
G
H
J
5M, 1982
z bzIbt,△
o100BsC
o20
L
'0zbt,△
ˉˉ 1
o030
"N
10°
丨0040
(soˉ B)
D后 缀
塑料封装
夕卜
钴己751ˉ 05
版本 R
{:⑩
江 ⒈ ⒉⒊ ⒋ ⒌
扒
巽
◇|025①
尺 刂与公廾按 AsME Y冂 45M,1994。
尺 寸以毫米训 。
尺、
JD和 E不 包插模压突起 。
hR人 模压突起为 015每 边 。
尺 寸 B不 包括模压突出。在墩人+J料 条件 卜
挡块突出超过尺 刂 B,总 共为 0127。
,
尺寸
L
$拼
毫*
最小值 |最 大值
A
025
A1
B
C
D
E
127BSC
H
o25
o50
125
◇ 025⑩ |cB⑤ |A⑤
h“ p:″ insen,1,com。
11
Cn
允许
MC33201MC33202MC33204
封装尺寸
P后 缀
注 ⒈
塑 料封 装
夕卜蜃
毛646-06
版本 L
在最大材料条件下 ,引 线在安装面 应位于
其确切位置的 013(0005)半 径内。
尺 寸 L为 平行引线中心间距离 。
尺 寸 B不 包括模压毛边。
可选圆角。
l∶
⒉ ⒊ ⒋
尺寸
寸
B
C
D
o240
o145
o770
0260
o185
o0丬 5
o021
0040
o07Q
o052
o008
o20
o115
o095
0015
0135
o015
0039
o39
1956
369
o38
254BsC
o100BsC
G
H
K
z Vz
762BsC
o300BsC
Ⅲ
N
(s0丬 4)
D后 缀
塑料封装
外壳 751Aˉ 03
版本 F
注 ⒈ ⒉ ⒊ ⒋ ⒌
⑽01⑴ ①
o
B
JFL
01⑴
⑩ T|8⑤ A⑤
最 大值
最小值
最大值
A
B
o337
o150
C
D
o014
o016
o344
o157
o068
o019
0049
o25
025
o008
o0⒄
o009
620
V zzt,
o244
G
φ|0zs⒆
l+・
剐值
0西
尺寸
◇
尺 刂L9公 尧按 ANsl Y145M,1982。
控制尺 寸:毫 米 。
尺 寸A和 B不 包括模 突起 。
k突起为 0150lO006)每 边。
鼓大模丿
尺、
JD不 包括挡块突出。在墩人+d料 条
件 卜,允 许挡块突出超过尺 刂 D,总 共为
κ
o Os0
127BsC
o050BsC
)009
m
R
h“ p:〃 insen".com.cn
12
o010
o0丬 9
MC33201Ⅲ C33202MC33204
封装尺寸
(TssoP丬 4)
DTB后 缀
塑料封装
外壳 948Gˉ 01
版本 o
注
:
1尺 寸和公劳按按 ANsI Y145M,1982。
2.控 制尺寸 :毫 米 。
3~尺 寸A不 包括模压毛边 、模压突起或
14xK刍 分爿夸
ˉ 袒担嘤型唑坐⒛囵
△「
划佶
尺 寸
浇 凵毛边。模压毛边或浇 冂毛边不应
超过 015(0006)每 边 。
4尺 寸 B不 包括内引线造成的毛边和突
起 。内引线造成的毛边和突起不应超
过 025(0010)每 边。
5.尺 ・
JK不 包括挡块突出。在最人材料
条件 下,允 许挡块突出超过尺 寸 K,
总共为 00BlO003)°
6 所示端子数仪供参考。
7.尺 刂 A和 B在 基准 lHlˉ Wˉ ⒈测 薰。
t米
英寸
及大
设小值
玫大值
o193
o200
宿
A
B
C
D
F
G
Nˉ
N剖 面 图
J
二哪
匣晤禀叮JTⅠ ∶
L^口 辶
κ
nsem1.com.cn
http:″ ∶
13
450
o047
005
o002
o020
o65BsC
o Og
o Og
o60
o20
o30
o030
o026BsC
o020
o004
o004
o007
o024
o008
o006
0012
κ1
L
M
H
490
430
640BsC
o252BsC
o°
ⅢC33201"C33202Ⅲ C33204
封装尺寸
(m⒗ ro~B)
Dm后 缀
塑料封装
夕卜
毛846A-02
厉
版本 D
注
:
1.尺 寸和公差按按 ANsl Y145M,1982。
2.控 制尺寸 :亳 米 。
3.尺 寸 A不 包括模压毛边、模压突起或浇 口毛
边。模压毛边 、模压突起或浇 口毛边不应超过
o15(0006)每 边 。
4.尺 寸 B不 包括 内引线造成的毛边和突起 。 内
引线造成的毛边和突起不应超过 02slO010)
管脚 1
标志
◇|008⑩
lxl劭
A⑤
T|B⑤ 丨
④丨
酬
http:〃 ∶
nsθ nη I.com.cn
刂4
MC33201, MC33202,
MC33204
Rail-to-Rail Operational
Amplifiers
The MC33201/2/4 family of operational amplifiers provide
rail–to–rail operation on both the input and output. The inputs can be
driven as high as 200 mV beyond the supply rails without phase
reversal on the outputs, and the output can swing within 50 mV of each
rail. This rail–to–rail operation enables the user to make full use of the
supply voltage range available. It is designed to work at very low
supply voltages (± 0.9 V) yet can operate with a supply of up to +12 V
and ground. Output current boosting techniques provide a high output
current capability while keeping the drain current of the amplifier to a
minimum. Also, the combination of low noise and distortion with a
high slew rate and drive capability make this an ideal amplifier for
audio applications.
http://onsemi.com
PDIP–8
P, VP SUFFIX
CASE 626
8
1
8
1
SO–8
D, VD SUFFIX
CASE 751
• Low Voltage, Single Supply Operation
•
•
•
•
•
•
•
•
(+1.8 V and Ground to +12 V and Ground)
Input Voltage Range Includes both Supply Rails
Output Voltage Swings within 50 mV of both Rails
No Phase Reversal on the Output for Over–driven Input Signals
High Output Current (ISC = 80 mA, Typ)
Low Supply Current (ID = 0.9 mA, Typ)
600 Ω Output Drive Capability
Extended Operating Temperature Ranges
(–40° to +105°C and –55° to +125°C)
Typical Gain Bandwidth Product = 2.2 MHz
8
1
Micro–8
DM SUFFIX
CASE 846A
PDIP–14
P, VP SUFFIX
CASE 646
14
1
14
SO–14
D, VD SUFFIX
CASE 751A
1
14
1
TSSOP–14
DTB SUFFIX
CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 11 of this data sheet.
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 5
1
Publication Order Number:
MC33201/D
MC33201, MC33202, MC33204
PIN CONNECTIONS
CASE 646/751A/948G
CASE 626
NC 1
Inputs
8
2
7
Output 1 1
NC
VCC
Inputs 1
3
6
Output
VEE 4
5
NC
14 Output 4
1
4
3
12
11
5
10
6
2
3
2
1
3
VEE 4
8
VCC
7
Output 2
6
2
5
Inputs 4
VEE
Inputs 3
Output 3
(Quad, Top View)
CASE 751/846A
Inputs 1
9
8
Output 2 7
Output 1 1
13
VCC 4
Inputs 2
(Single, Top View)
2
Inputs 2
(Dual, Top View)
VCC
VCC
VEE
VCC
Vin-
Vout
VCC
Vin+
VEE
This device contains 70 active transistors (each amplifier).
Figure 1. Circuit Schematic
(Each Amplifier)
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2
MC33201, MC33202, MC33204
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+13
V
Input Differential Voltage Range
VIDR
Note 1.
V
Common Mode Input Voltage Range (Note 2.)
VCM
VCC + 0.5 V to
VEE – 0.5 V
V
Output Short Circuit Duration
ts
Note 3.
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
– 65 to +150
°C
Maximum Power Dissipation
PD
Note 3.
mW
Supply Voltage (VCC to VEE)
DC ELECTRICAL CHARACTERISTICS (TA = 25°C)
Characteristic
VCC = 2.0 V
VCC = 3.3 V
VCC = 5.0 V
Input Offset Voltage
VIO (max)
MC33201
MC33202
MC33204
± 8.0
±10
±12
± 8.0
±10
±12
± 6.0
± 8.0
±10
Output Voltage Swing
VOH (RL = 10 kΩ)
VOL (RL = 10 kΩ)
1.9
0.10
3.15
0.15
4.85
0.15
Power Supply Current
per Amplifier (ID)
1.125
1.125
1.125
Unit
mV
Vmin
Vmax
mA
Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = Gnd.
DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic
Figure
Symbol
Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V)
MC33201: TA = + 25°C
MC33201: TA = – 40° to +105°C
MC33201V: TA = – 55° to +125°C
MC33202: TA = + 25°C
MC33202: TA = – 40° to +105°C
MC33202V: TA = – 55° to +125°C
MC33204: TA = + 25°C
MC33204: TA = – 40° to +105°C
MC33204V: TA = – 55° to +125°C
3
VIO
Input Offset Voltage Temperature Coefficient (RS = 50 Ω)
TA = – 40° to +105°C
TA = – 55° to +125°C
4
Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
TA = + 25°C
TA = – 40° to +105°C
TA = – 55° to +125°C
5, 6
Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
TA = + 25°C
TA = – 40° to +105°C
TA = – 55° to +125°C
–
Common Mode Input Voltage Range
–
Min
Typ
Max
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6.0
9.0
13
8.0
11
14
10
13
17
–
–
2.0
2.0
–
–
–
–
–
80
100
–
200
250
500
–
–
–
5.0
10
–
50
100
200
VEE
–
VCC
mV
∆VIO/∆T
µV/°C
IIB
nA
IIO
VICR
Unit
nA
V
1. The differential input voltage of each amplifier is limited by two internal parallel back–to–back diodes. For additional differential input voltage
range, use current limiting resistors in series with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltage
on either input must not exceed either supply rail by more than 500 mV.
3. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See Figure 2)
http://onsemi.com
3
MC33201, MC33202, MC33204
DC ELECTRICAL CHARACTERISTICS (cont.) (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic
Large Signal Voltage Gain (VCC = + 5.0 V, VEE = – 5.0 V)
RL = 10 kΩ
RL = 600 Ω
Output Voltage Swing (VID = ± 0.2 V)
RL = 10 kΩ
RL = 10 kΩ
RL = 600 Ω
RL = 600 Ω
Figure
Symbol
Min
Typ
Max
7
AVOL
50
25
300
250
–
–
VOH
VOL
VOH
VOL
4.85
–
4.75
–
4.95
0.05
4.85
0.15
–
0.15
–
0.25
60
90
–
500
25
–
50
80
–
–
–
0.9
0.9
1.125
1.125
Unit
kV/V
8, 9, 10
V
Common Mode Rejection (Vin = 0 V to 5.0 V)
11
CMR
Power Supply Rejection Ratio
VCC/VEE = 5.0 V/Gnd to 3.0 V/Gnd
12
PSRR
Output Short Circuit Current (Source and Sink)
13, 14
ISC
Power Supply Current per Amplifier (VO = 0 V)
TA = – 40° to +105°C
TA = – 55° to +125°C
15
ID
dB
µV/V
mA
mA
AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic
Slew Rate
(VS = ± 2.5 V, VO = – 2.0 V to + 2.0 V, RL = 2.0 kΩ, AV = +1.0)
Gain Bandwidth Product (f = 100 kHz)
Figure
Symbol
16, 26
SR
Min
Typ
Max
0.5
1.0
–
Unit
V/µs
17
GBW
–
2.2
–
MHz
Gain Margin (RL = 600 Ω, CL = 0 pF)
20, 21, 22
AM
–
12
–
dB
Phase Margin (RL = 600 Ω, CL = 0 pF)
20, 21, 22
M
–
65
–
Deg
CS
–
90
–
dB
BWP
–
28
–
kHz
–
–
0.002
0.008
–
–
–
100
–
Rin
–
200
–
kΩ
Cin
–
8.0
–
pF
–
–
25
20
–
–
–
–
0.8
0.2
–
–
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100)
23
Power Bandwidth (VO = 4.0 Vpp, RL = 600 Ω, THD ≤ 1 %)
Total Harmonic Distortion (RL = 600 Ω, VO = 1.0 Vpp, AV = 1.0)
f = 1.0 kHz
f = 10 kHz
24
THD
%
ZO
Open Loop Output Impedance
(VO = 0 V, f = 2.0 MHz, AV = 10)
Differential Input Resistance (VCM = 0 V)
Differential Input Capacitance (VCM = 0 V)
Equivalent Input Noise Voltage (RS = 100 Ω)
f = 10 Hz
f = 1.0 kHz
25
Equivalent Input Noise Current
f = 10 Hz
f = 1.0 kHz
25
http://onsemi.com
4
Ω
en
in
nV/
Hz
pA/
Hz
2500
40
PERCENTAGE OF AMPLIFIERS (%)
PD(max) , MAXIMUM POWER DISSIPATION (mW
MC33201, MC33202, MC33204
8 and 14 Pin DIP Pkg
2000
TSSOP-14 Pkg
1500
SO-14 Pkg
1000
SO-8 Pkg
500
0
-55 -40 -25
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
30
25
20
15
10
5.0
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0
VIO, INPUT OFFSET VOLTAGE (mV)
125
Figure 2. Maximum Power Dissipation
versus Temperature
50
200
I IB , INPUT BIAS CURRENT (nA)
PERCENTAGE OF AMPLIFIERS (%)
30
120
10
-10
0
10
20
30
40
VCM = 0 V to 0.5 V
80
VCM > 1.0 V
40
0
-55 -40 -25
50
TCV , INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (µV/°C)
IO
25
70
85
125
Figure 5. Input Bias Current
versus Temperature
150
300
A VOL , OPEN LOOP VOLTAGE GAIN (kV/V)
I IB , INPUT BIAS CURRENT (nA)
0
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Input Offset Voltage
Temperature Coefficient Distribution
100
260
50
0
220
-50
180
-100
-150
VCC = 12 V
VEE = Gnd
TA = 25°C
-200
-250
10
VCC = +5.0 V
VEE = Gnd
160
20
0
-50 -40 -30 -20
8.0
Figure 3. Input Offset Voltage Distribution
360 amplifiers tested from
3 (MC33204) wafer lots
VCC = +5.0 V
VEE = Gnd
TA = 25°C
DIP Package
40
360 amplifiers tested from
3 (MC33204) wafer lots
VCC = +5.0 V
VEE = Gnd
TA = 25°C
DIP Package
35
0
2.0
4.0
6.0
8.0
10
VCM, INPUT COMMON MODE VOLTAGE (V)
140
VCC = +5.0 V
VEE = Gnd
RL = 600 Ω
∆VO = 0.5 V to 4.5 V
100
-55 -40 -25
12
Figure 6. Input Bias Current
versus Common Mode Voltage
0
25
70
85
TA, AMBIENT TEMPERATURE (°C)
105
Figure 7. Open Loop Voltage Gain versus
Temperature
http://onsemi.com
5
125
VO, OUTPUT VOLTAGE (Vpp )
12
VSAT, OUTPUT SATURATION VOLTAGE (V)
MC33201, MC33202, MC33204
RL = 600 Ω
TA = 25°C
10
8.0
6.0
4.0
2.0
0
±1.0
±2.0
±3.0
±4.0
±5.0
VCC,VEE SUPPLY VOLTAGE (V)
±6.0
TA = 125°C
VCC - 0.4 V
CMR, COMMON MODE REJECTION (dB)
VO, OUTPUT VOLTAGE (Vpp )
6.0
10
IL, LOAD CURRENT (mA)
VEE
20
15
VCC = +6.0 V
VEE = -6.0 V
RL = 600 Ω
AV = +1.0
TA = 25°C
100
80
60
40
VCC = +6.0 V
VEE = -6.0 V
TA = -55° to +125°C
20
0
1.0 M
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
Figure 11. Common Mode Rejection
versus Frequency
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)
PSR, POWER SUPPLY REJECTION (dB)
VEE + 0.2 V
TA = -55°C
5.0
Figure 10. Output Voltage
versus Frequency
120
100
100
PSR+
80
60
PSR-
40
VCC = +6.0 V
VEE = -6.0 V
TA = -55° to +125°C
20
0
TA = 25°C
TA = 125°C
Figure 9. Output Saturation Voltage
versus Load Current
9.0
10 k
100 k
f, FREQUENCY (Hz)
VEE + 0.4 V
VCC = +5.0 V
VEE = -5.0 V
0
12
0
1.0 k
VCC - 0.2 V
TA = 25°C
Figure 8. Output Voltage Swing
versus Supply Voltage
3.0
VCC
TA = -55°C
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
Source
80
60
Sink
40
VCC = +6.0 V
VEE = -6.0 V
TA = 25°C
20
0
0
1.0
2.0
3.0
4.0
5.0
Vout, OUTPUT VOLTAGE (V)
Figure 12. Power Supply Rejection
versus Frequency
Figure 13. Output Short Circuit Current
versus Output Voltage
http://onsemi.com
6
6.0
125
2.0
VCC = +5.0 V
VEE = Gnd
1.6
100
Source
75
TA = 125°C
1.2
Sink
TA = 25°C
0.8
50
TA = -55°C
0.4
25
0
-55 -40 -25
0
25
70 85
TA, AMBIENT TEMPERATURE (°C)
105
125
0
±0
±1.0
1.5
VCC = +2.5 V
VEE = -2.5 V
VO = ±2.0 V
+Slew Rate
1.0
-Slew Rate
0.5
0
25
70
85
105
1.0
0
-55 -40 -25
0
25
70
85
105
Figure 16. Slew Rate
versus Temperature
Figure 17. Gain Bandwidth Product
versus Temperature
40
VS = ±6.0 V
TA = 25°C
RL = 600 Ω
80
30
120
2A
10
A
2.0
TA, AMBIENT TEMPERATURE (°C)
50
-30
10 k
VCC = +2.5 V
VEE = -2.5 V
f = 100 kHz
TA, AMBIENT TEMPERATURE (°C)
70
-10
3.0
125
2B
1A - Phase, CL = 0 pF
1B - Gain, CL = 0 pF
2A - Phase, CL = 300 pF
2B - Gain, CL = 300 pF
100 k
1B
1.0 M
1A
160
200
, EXCESS PHASE (DEGREES)
, OPEN LOOP VOLTAGE GAIN (dB)
VOL
0
-55 -40 -25
4.0
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
SR, SLEW RATE (V/µ s)
2.0
±6.0
Figure 15. Supply Current per Amplifier
versus Supply Voltage with No Load
GBW, GAIN BANDWIDTH PRODUCT (MHz)
Figure 14. Output Short Circuit Current
versus Temperature
±2.0
±3.0
±4.0
±5.0
VCC, VEE, SUPPLY VOLTAGE (V)
70
30
1A
10
-10
1A - Phase, VS = ±6.0 V
1B - Gain, VS = ±6.0 V
2A - Phase, VS = ±1.0 V
2B - Gain, VS = ±1.0 V
f, FREQUENCY (Hz)
100 k
1B
2B
1.0 M
f, FREQUENCY (Hz)
Figure 18. Voltage Gain and Phase
versus Frequency
Figure 19. Voltage Gain and Phase
versus Frequency
http://onsemi.com
7
80
120
2A
-30
10 k
240
10 M
40
CL = 0 pF
TA = 25°C
RL = 600 Ω
50
125
160
200
240
10 M
, EXCESS PHASE (DEGREES)
150
I CC , SUPPLY CURRENT PER AMPLIFIER (mA)
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)
MC33201, MC33202, MC33204
MC33201, MC33202, MC33204
60
50
40
30
VCC = +6.0 V
VEE = -6.0 V
RL = 600 Ω
CL = 100 pF
40
30
20
20
10
10
Gain Margin
0
-55 -40 -25
0
25
70
85
105
60
60
VCC = +6.0 V
VEE = -6.0 V
TA = 25°C
45
30
15
0
0
125
10
100
60
Gain Margin
THD, TOTAL HARMONIC DISTORTION (%)
14
12
10
40
8.0
30
6.0
20
4.0
10
2.0
0
10
10
1.0
0
1.0 k
100
0.01
0.001
10
90
AV = 10
60
VCC = +6.0 V
VEE = -6.0 V
VO = 8.0 Vpp
TA = 25°C
30
0
100
1.0 k
10 k
f, FREQUENCY (Hz)
Figure 22. Gain and Phase Margin
versus Capacitive Load
Figure 23. Channel Separation
versus Frequency
VCC = +5.0 V
TA = 25°C
VO = 2.0 Vpp
VEE = -5.0 V
RL = 600 Ω
AV = 100
AV = 10
AV = 1.0
100
1.0 k
10 k
0
100 k
AV = 100
120
CL, CAPACITIVE LOAD (pF)
AV = 1000
0.1
10 k
150
100 k
en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
50
16
CS, CHANNEL SEPARATION (dB)
Phase Margin
1.0 k
Figure 21. Gain and Phase Margin
versus Differential Source Resistance
A , GAIN MARGIN (dB)
M
M , PHASE MARGIN (DEGREES)
70
15
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
Figure 20. Gain and Phase Margin
versus Temperature
VCC = +6.0 V
VEE = -6.0 V
RL = 600 Ω
AV = 100
TA = 25°C
30
Gain Margin
TA, AMBIENT TEMPERATURE (°C)
80
45
50
VCC = +6.0 V
VEE = -6.0 V
TA = 25°C
40
30
Noise Voltage
20
2.0
1.0
10
Noise Current
0
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
Figure 25. Equivalent Input Noise Voltage
and Current versus Frequency
http://onsemi.com
8
4.0
3.0
f, FREQUENCY (Hz)
Figure 24. Total Harmonic Distortion
versus Frequency
5.0
0
100 k
i n , INPUT REFERRED NOISE CURRENT (pA/ Hz)
50
75
Phase Margin
M , PHASE MARGIN (DEGREES)
60
75
A , GAIN MARGIN (dB)
M
M , PHASE MARGIN (DEGREES)
Phase Margin
A , GAIN MARGIN (dB)
M
70
70
MC33201, MC33202, MC33204
DETAILED OPERATING DESCRIPTION
Circuit Information
The MC33201/2/4 family of operational amplifiers are
unique in their ability to swing rail–to–rail on both the input
and the output with a completely bipolar design. This offers
low noise, high output current capability and a wide
common mode input voltage range even with low supply
voltages. Operation is guaranteed over an extended
temperature range and at supply voltages of 2.0 V, 3.3 V and
5.0 V and ground.
Since the common mode input voltage range extends from
VCC to VEE, it can be operated with either single or split
voltage supplies. The MC33201/2/4 are guaranteed not to
latch or phase reverse over the entire common mode range,
however, the inputs should not be allowed to exceed
maximum ratings.
Rail–to–rail performance is achieved at the input of the
amplifiers by using parallel NPN–PNP differential input
stages. When the inputs are within 800 mV of the negative
rail, the PNP stage is on. When the inputs are more than 800
mV greater than VEE, the NPN stage is on. This switching of
input pairs will cause a reversal of input bias currents (see
Figure 6). Also, slight differences in offset voltage may be
noted between the NPN and PNP pairs. Cross–coupling
techniques have been used to keep this change to a minimum.
In addition to its rail–to–rail performance, the output stage
is current boosted to provide 80 mA of output current,
enabling the op amp to drive 600 Ω loads. Because of this
high output current capability, care should be taken not to
exceed the 150°C maximum junction temperature.
VCC = +6.0 V
VEE = -6.0 V
RL = 600 Ω
CL = 100 pF
TA = 25°C
V , OUTPUT VOLTAGE (50 mV/DIV)
O
VCC = +6.0 V
VEE = -6.0 V
RL = 600 Ω
CL = 100 pF
TA = 25°C
t, TIME (5.0 µs/DIV)
t, TIME (10 µs/DIV)
Figure 26. Noninverting Amplifier Slew Rate
V , OUTPUT VOLTAGE (2.0 V/DIV)
O
V , OUTPUT VOLTAGE (2.0 mV/DIV)
O
General Information
Figure 27. Small Signal Transient Response
VCC = +6.0 V
VEE = -6.0 V
RL = 600 Ω
CL = 100 pF
AV = 1.0
TA = 25°C
t, TIME (10 µs/DIV)
Figure 28. Large Signal Transient Response
http://onsemi.com
9
MC33201, MC33202, MC33204
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self–align when subjected to a
solder reflow process.
Micro–8
0.208
5.28
0.041
1.04
0.126
3.20
0.015
0.38
0.0256
0.65
inches
mm
http://onsemi.com
10
MC33201, MC33202, MC33204
ORDERING INFORMATION
Operational
Amplifier Function
Operating
Temperature Range
Device
Package
Shipping
SO–8
98 Units / Rail
MC33201D
MC33201DR2
Single
SO–8
2500 Units / Tape & Reel
Plastic DIP
50 Units / Rail
SO–8
98 Units / Rail
SO–8
98 Units / Rail
SO–8
2500 Units / Tape & Reel
Micro–8
4000 Units / Tape & Reel
Plastic DIP
50 Units / Rail
TA= –40° to +105°C
MC33201P
MC33201VD
TA = –55° to 125°C
MC33202D
MC33202DR2
TA= –40
40 ° to +105°C
MC33202DMR2
MC33202P
Dual
MC33202VD
SO–8
98 Units / Rail
MC33202VDR2
SO–8
2500 Units / Tape & Reel
Plastic DIP
50 Units / Rail
MC33204D
SO–14
55 Units / Rail
MC33204DR2
SO–14
2500 Units / Tape & Reel
TSSOP–14
96 Units / Rail
MC33204DTBR2
TSSOP–14
2500 Units / Tape & Reel
MC33204P
Plastic DIP
25 Units / Rail
SO–14
55 Units / Rail
SO–14
2500 Units / Tape & Reel
Plastic DIP
25 Units / Rail
TA = –55° to 125°C
MC33202VP
TA= –40 ° to +105°C
MC33204DTB
Quad
MC33204VD
MC33204VDR2
TA = –55° to 125°C
MC33204VP
MARKING DIAGRAMS
8
8
3320x
ALYW
1
1
8
PDIP–14
VP SUFFIX
CASE 646
TSSOP–14
DTB SUFFIX
CASE 948G
14
MC33204VP
AWLYYWW
MC33
204
ALYW
14
MC33204P
AWLYYWW
1
3202
AYW
1
PDIP–14
P SUFFIX
CASE 646
MC33204VD
AWLYWW
Micro–8
DM SUFFIX
CASE 846A
MC33202VP
AWL
YYWW
1
1
14
14
MC33204D
AWLYWW
1
MC3320xP
AWL
YYWW
SO–14
VD SUFFIX
CASE 751A
SO–14
D SUFFIX
CASE 751A
14
8
8
320xV
ALYW
1
PDIP–8
VP SUFFIX
CASE 626
PDIP–8
P SUFFIX
CASE 626
SO–8
VD SUFFIX
CASE 751
SO–8
D SUFFIX
CASE 751
1
x
= 1 or 2
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
http://onsemi.com
11
1
MC33201, MC33202, MC33204
PACKAGE DIMENSIONS
PDIP–8
P, VP SUFFIX
CASE 626–05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
SO–8
D, VD SUFFIX
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
S
http://onsemi.com
12
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
MC33201, MC33202, MC33204
PACKAGE DIMENSIONS
PDIP–14
P, VP SUFFIX
CASE 646–06
ISSUE M
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
N
C
–T–
SEATING
PLANE
J
K
H
D 14 PL
G
M
0.13 (0.005)
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
--10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
--10
0.38
1.01
M
SO–14
D, VD SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
M
B
M
F
R X 45 C
–T–
SEATING
PLANE
0.25 (0.010)
M
T B
J
M
K
D 14 PL
S
A
S
http://onsemi.com
13
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.228
0.244
0.010
0.019
MC33201, MC33202, MC33204
PACKAGE DIMENSIONS
TSSOP–14
DTB SUFFIX
CASE 948G–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
–V–
ÉÉ
ÇÇ
ÇÇ
ÉÉ
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
G
H
DETAIL E
http://onsemi.com
14
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC33201, MC33202, MC33204
PACKAGE DIMENSIONS
Micro–8
DM SUFFIX
CASE 846A–02
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
–A–
–B–
K
PIN 1 ID
G
D 8 PL
0.08 (0.003)
–T–
M
T B
S
A
S
SEATING
PLANE
0.038 (0.0015)
C
H
L
J
http://onsemi.com
15
DIM
A
B
C
D
G
H
J
K
L
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
--1.10
0.25
0.40
0.65 BSC
0.05
0.15
0.13
0.23
4.75
5.05
0.40
0.70
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
--0.043
0.010
0.016
0.026 BSC
0.002
0.006
0.005
0.009
0.187
0.199
0.016
0.028
MC33201, MC33202, MC33204
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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For additional information, please contact your local
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16
MC33201/D
Order this document by MC33201/D
The MC33201/2/4 family of operational amplifiers provide rail–to–rail
operation on both the input and output. The inputs can be driven as high as
200 mV beyond the supply rails without phase reversal on the outputs, and
the output can swing within 50 mV of each rail. This rail–to–rail operation
enables the user to make full use of the supply voltage range available. It is
designed to work at very low supply voltages (± 0.9 V) yet can operate with a
supply of up to +12 V and ground. Output current boosting techniques
provide a high output current capability while keeping the drain current of the
amplifier to a minimum. Also, the combination of low noise and distortion with
a high slew rate and drive capability make this an ideal amplifier for audio
applications.
• Low Voltage, Single Supply Operation
(+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
•
•
•
•
•
•
•
•
LOW VOLTAGE
RAIL–TO–RAIL
OPERATIONAL AMPLIFIERS
8
NC 1
8
NC
2
7
VCC
3
6
Output
VEE 4
5
NC
Inputs
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
(Single, Top View)
Output Voltage Swings within 50 mV of both Rails
No Phase Reversal on the Output for Over–driven Input Signals
Output 1 1
8
VCC
7
Output 2
8
High Output Current (ISC = 80 mA, Typ)
1
2
1
Inputs 1
Low Supply Current (ID = 0.9 mA, Typ)
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
600 Ω Output Drive Capability
Extended Operating Temperature Ranges
(–40° to +105°C and –55° to +125°C)
Typical Gain Bandwidth Product = 2.2 MHz
3
6
Inputs 2
2
VEE 4
5
(Dual, Top View)
Offered in New TSSOP Package Including Standard SOIC and
DIP Packages
14
Operational
Amplifier Function
Operating
Temperature
Range
Device
MC33201D
MC33201P
TA= –40 ° to +105°C
14
1
1
ORDERING INFORMATION
Package
P SUFFIX
PLASTIC PACKAGE
CASE 646
SO–8
Plastic DIP
14
Si l
Single
MC33201VD
TA = –55 ° to
+125°C
MC33201VP
MC33202D
MC33202P
TA= –40 ° to +105°C
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
1
SO–8
Plastic DIP
DTB SUFFIX
PLASTIC PACKAGE
CASE 948G
(TSSOP–14)
SO–8
Plastic DIP
D l
Dual
MC33202VD
TA = –55 ° to
+125°C
MC33202VP
MC33204D
MC33204DTB
SO–8
Plastic DIP
SO–14
TA= –40
40 ° to +105°C
105°C
MC33204P
TSSOP–14
Plastic DIP
Q d
Quad
MC33204VD
MC33204VDTB
MC33204VP
TA = –55
55 ° to
+125°C
+125
C
SO–14
TSSOP–14
Output 1 1
2
Inputs 1
1
4
3
13
12
VCC 4
11
5
10
Inputs 2
6
2
3
Output 2 7
Plastic DIP
9
8
Inputs 4
VEE
Inputs 3
Output 3
(Quad, Top View)
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
14 Output 4
Rev 2
1
MC33201 MC33202 MC33204
DC ELECTRICAL CHARACTERISTICS (TA = 25°C)
Characteristic
VCC = 2.0 V
VCC = 3.3 V
VCC = 5.0 V
Input Offset Voltage
VIO (max)
MC33201
MC33202
MC33204
± 8.0
±10
±12
± 8.0
±10
±12
± 6.0
± 8.0
±10
Output Voltage Swing
VOH (RL = 10 kΩ)
VOL (RL = 10 kΩ)
1.9
0.10
3.15
0.15
4.85
0.15
Power Supply Current
per Amplifier (ID)
1.125
1.125
1.125
Unit
mV
Vmin
Vmax
mA
Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = Gnd.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+13
V
Input Differential Voltage Range
VIDR
(Note 1)
V
Common Mode Input Voltage Range (Note 2)
VCM
VCC + 0.5 V to
VEE – 0.5 V
V
Output Short Circuit Duration
ts
(Note 3)
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
– 65 to +150
°C
Maximum Power Dissipation
PD
(Note 3)
mW
Supply Voltage (VCC to VEE)
NOTES: 1. The differential input voltage of each amplifier is limited by two internal parallel back–to–back
diodes. For additional differential input voltage range, use current limiting resistors in series
with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs
to both supply rails. Therefore, the voltage on either input must not exceed either supply rail by
more than 500 mV.
3. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not
exceeded. (See Figure 2)
DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Figure
Symbol
Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V)
MC33201: TA = + 25°C
MC33201: TA = – 40° to +105°C
MC33201: TA = – 55° to +125°C
MC33202: TA = + 25°C
MC33202: TA = – 40° to +105°C
MC33202: TA = – 55° to +125°C
MC33204: TA = + 25°C
MC33204: TA = – 40° to +105°C
MC33204: TA = – 55° to +125°C
3
VIO
Input Offset Voltage Temperature Coefficient (RS = 50 Ω)
TA = – 40° to +105°C
TA = – 55° to +125°C
4
Characteristic
Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
TA = + 25°C
TA = – 40° to +105°C
TA = – 55° to +125°C
5, 6
Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
TA = + 25°C
TA = – 40° to +105°C
TA = – 55° to +125°C
–
Common Mode Input Voltage Range
–
2
Min
Typ
Max
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6.0
9.0
13
8.0
11
14
10
13
17
–
–
2.0
2.0
–
–
–
–
–
80
100
–
200
250
500
–
–
–
5.0
10
–
50
100
200
VEE
–
VCC
mV
∆VIO/∆T
µV/°C
IIB
nA
IIO
VICR
Unit
nA
V
MOTOROLA ANALOG IC DEVICE DATA
MC33201 MC33202 MC33204
DC ELECTRICAL CHARACTERISTICS (continued) (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic
Large Signal Voltage Gain (VCC = + 5.0 V, VEE = – 5.0 V)
RL = 10 kΩ
RL = 600 Ω
Output Voltage Swing (VID = ± 0.2 V)
RL = 10 kΩ
RL = 10 kΩ
RL = 600 Ω
RL = 600 Ω
Figure
Symbol
Min
Typ
Max
7
AVOL
50
25
300
250
–
–
VOH
VOL
VOH
VOL
4.85
–
4.75
–
4.95
0.05
4.85
0.15
–
0.15
–
0.25
60
90
–
500
25
–
50
80
–
–
–
0.9
0.9
1.125
1.125
Unit
kV/V
8, 9, 10
V
Common Mode Rejection (Vin = 0 V to 5.0 V)
11
CMR
Power Supply Rejection Ratio
VCC/VEE = 5.0 V/Gnd to 3.0 V/Gnd
12
PSRR
Output Short Circuit Current (Source and Sink)
13, 14
ISC
Power Supply Current per Amplifier (VO = 0 V)
TA = – 40° to +105°C
TA = – 55° to +125°C
15
ID
dB
µV/V
mA
mA
AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic
Slew Rate
(VS = ± 2.5 V, VO = – 2.0 V to + 2.0 V, RL = 2.0 kΩ, AV = +1.0)
Figure
Symbol
16, 26
SR
Min
Typ
Max
0.5
1.0
–
Unit
V/µs
Gain Bandwidth Product (f = 100 kHz)
17
GBW
–
2.2
–
MHz
Gain Margin (RL = 600 Ω, CL = 0 pF)
20, 21, 22
AM
–
12
–
dB
Phase Margin (RL = 600 Ω, CL = 0 pF)
20, 21, 22
OM
–
65
–
Deg
23
CS
–
90
–
dB
BWP
–
28
–
kHz
–
–
0.002
0.008
–
–
–
100
–
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100)
Power Bandwidth (VO = 4.0 Vpp, RL = 600 Ω, THD ≤ 1 %)
Total Harmonic Distortion (RL = 600 Ω, VO = 1.0 Vpp, AV = 1.0)
f = 1.0 kHz
f = 10 kHz
24
THD
%
ZO
Open Loop Output Impedance
(VO = 0 V, f = 2.0 MHz, AV = 10)
Ω
Differential Input Resistance (VCM = 0 V)
Rin
–
200
–
kΩ
Differential Input Capacitance (VCM = 0 V)
Cin
–
8.0
–
pF
–
–
25
20
–
–
–
–
0.8
0.2
–
–
Equivalent Input Noise Voltage (RS = 100 Ω)
f = 10 Hz
f = 1.0 kHz
25
Equivalent Input Noise Current
f = 10 Hz
f = 1.0 kHz
25
MOTOROLA ANALOG IC DEVICE DATA
en
in
nV/
Hz
pA/
Hz
3
MC33201 MC33202 MC33204
Figure 1. Circuit Schematic
(Each Amplifier)
VCC
VCC
VEE
VCC
Vin –
Vout
VCC
Vin +
VEE
This device contains 70 active transistors (each amplifier).
4
MOTOROLA ANALOG IC DEVICE DATA
Figure 2. Maximum Power Dissipation
versus Temperature
Figure 3. Input Offset Voltage Distribution
2500
40
PERCENTAGE OF AMPLIFIERS (%)
PD(max) , MAXIMUM POWER DISSIPATION (mW)
MC33201 MC33202 MC33204
8 and 14 Pin DIP Pkg
2000
TSSOP–14 Pkg
1500
SO–14 Pkg
1000
SO–8 Pkg
500
0
– 55 – 40 – 25
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
360 amplifiers tested from
3 (MC33204) wafer lots
VCC = + 5.0 V
VEE = Gnd
TA = 25°C
DIP Package
35
30
25
20
15
10
5.0
0
–10 – 8.0 – 6.0 – 4.0 – 2.0
0
2.0 4.0 6.0
VIO, INPUT OFFSET VOLTAGE (mV)
125
Figure 4. Input Offset Voltage
Temperature Coefficient Distribution
40
30
I IB , INPUT BIAS CURRENT (nA)
PERCENTAGE OF AMPLIFIERS (%)
200
360 amplifiers tested from
3 (MC33204) wafer lots
VCC = + 5.0 V
VEE = Gnd
TA = 25°C
DIP Package
20
10
0
– 50 – 40 – 30 – 20
–10
0
10
20
30
40
VCC = + 5.0 V
VEE = Gnd
160
120
VCM = 0 V to 0.5 V
80
VCM > 1.0 V
40
0
– 55 – 40 – 25
50
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (µV/°C)
A VOL , OPEN LOOP VOLTAGE GAIN (kV/V)
100
50
0
– 50
–100
VCC = 12 V
VEE = Gnd
TA = 25°C
– 200
0
2.0
4.0
6.0
8.0
10
VCM, INPUT COMMON MODE VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
25
70
85
125
Figure 7. Open Loop Voltage Gain versus
Temperature
150
–150
0
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Bias Current
versus Common Mode Voltage
I IB , INPUT BIAS CURRENT (nA)
10
Figure 5. Input Bias Current
versus Temperature
50
– 250
8.0
12
300
260
220
180
140
VCC = + 5.0 V
VEE = Gnd
RL = 600 Ω
∆VO = 0.5 V to 4.5 V
100
– 55 – 40 – 25
0
25
70
85
TA, AMBIENT TEMPERATURE (°C)
105
125
5
MC33201 MC33202 MC33204
Figure 8. Output Voltage Swing
versus Supply Voltage
RL = 600 Ω
TA = 25°C
10
8.0
6.0
4.0
2.0
0
±1.0
VCC
VSAT, OUTPUT SATURATION VOLTAGE (V)
VO, OUTPUT VOLTAGE (Vpp )
12
Figure 9. Output Saturation Voltage
versus Load Current
± 2.0
± 3.0
± 4.0
± 5.0
VCC,VEE SUPPLY VOLTAGE (V)
TA = – 55°C
TA = 125°C
VCC – 0.4 V
TA = – 55°C
CMR, COMMON MODE REJECTION (dB)
VCC = + 6.0 V
VEE = – 6.0 V
3.0 RL = 600 Ω
AV = +1.0
TA = 25°C
PSR, POWER SUPPLY REJECTION (dB)
VEE
20
15
80
60
40
120
100
PSR+
80
60
PSR–
40
VCC = + 6.0 V
VEE = – 6.0 V
TA = – 55° to +125°C
0
100 k
1.0 M
VCC = + 6.0 V
VEE = – 6.0 V
TA = – 55° to +125°C
20
1.0 M
Figure 12. Power Supply Rejection
versus Frequency
6
10
IL, LOAD CURRENT (mA)
100
0
10 k
100 k
f, FREQUENCY (Hz)
1.0 k
10 k
f, FREQUENCY (Hz)
5.0
0
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)
VO, OUTPUT VOLTAGE (Vpp )
6.0
100
VEE + 0.2 V
Figure 11. Common Mode Rejection
versus Frequency
9.0
10
TA = 25°C
TA = 125°C
± 6.0
12
20
VEE + 0.4 V
VCC = + 5.0 V
VEE = – 5.0 V
Figure 10. Output Voltage
versus Frequency
0
1.0 k
VCC – 0.2 V
TA = 25°C
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
Figure 13. Output Short Circuit Current
versus Output Voltage
100
Source
80
60
Sink
40
VCC = + 6.0 V
VEE = – 6.0 V
TA = 25°C
20
0
0
1.0
2.0
3.0
4.0
5.0
6.0
Vout, OUTPUT VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
MC33201 MC33202 MC33204
Figure 15. Supply Current per Amplifier
versus Supply Voltage with No Load
I CC , SUPPLY CURRENT PER AMPLIFIER (mA)
150
125
VCC = + 5.0 V
VEE = Gnd
100
Source
75
Sink
50
25
0
– 55 – 40 – 25
0
25
70 85
TA, AMBIENT TEMPERATURE (°C)
105
125
2.0
1.6
TA = 125°C
1.2
TA = 25°C
0.8
TA = – 55°C
0.4
0
±0
Figure 16. Slew Rate
versus Temperature
–Slew Rate
0.5
25
70
85
105
0
– 55 – 40 – 25
0
25
70
85
105
Figure 18. Voltage Gain and Phase
versus Frequency
Figure 19. Voltage Gain and Phase
versus Frequency
40
VS = ± 6.0 V
TA = 25°C
RL = 600 Ω
80
120
2
A2
B
1
B
10
A
1.0
125
30
– 30
10 k
2.0
TA, AMBIENT TEMPERATURE (°C)
50
–10
VCC = + 2.5 V
VEE = – 2.5 V
f = 100 kHz
TA, AMBIENT TEMPERATURE (°C)
70
1A – Phase, CL = 0 pF
1B – Gain, CL = 0 pF
2A – Phase, CL = 300 pF
2B – Gain, CL = 300 pF
100 k
± 6.0
3.0
1.0 M
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
1
A
160
200
240
10 M
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
, OPEN LOOP VOLTAGE GAIN (dB)
VOL
0
4.0
GBW, GAIN BANDWIDTH PRODUCT (MHz)
+Slew Rate
1.0
O , EXCESS PHASE (DEGREES)
SR, SLEW RATE (V/µ s)
VCC = + 2.5 V
VEE = – 2.5 V
VO = ± 2.0 V
0
– 55 – 40 – 25
± 2.0
± 3.0
± 4.0
± 5.0
VCC, VEE, SUPPLY VOLTAGE (V)
Figure 17. Gain Bandwidth Product
versus Temperature
2.0
1.5
±1.0
70
30
– 30
10 k
1A – Phase, VS = ± 6.0 V
1B – Gain, VS = ± 6.0 V
2A – Phase, VS = ± 1.0 V
2B – Gain, VS = ± 1.0 V
100 k
2
B
1.0 M
80
1
A
2
A
10
–10
40
CL = 0 pF
TA = 25°C
RL = 600 Ω
50
1
B
125
120
160
200
240
10 M
f, FREQUENCY (Hz)
7
O , EXCESS PHASE (DEGREES)
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)
Figure 14. Output Short Circuit Current
versus Temperature
MC33201 MC33202 MC33204
Figure 20. Gain and Phase Margin
versus Temperature
75
50
50
VCC = + 6.0 V
VEE = – 6.0 V
RL = 600 Ω
CL = 100 pF
40
30
40
30
20
20
10
10
Gain Margin
0
– 55 – 40 – 25
0
25
70
85
105
O M , PHASE MARGIN (DEGREES)
60
A , GAIN MARGIN (dB)
M
O M , PHASE MARGIN (DEGREES)
60
60
60
VCC = + 6.0 V
VEE = – 6.0 V
TA = 25°C
45
30
15
0
0
125
10
100
60
Gain Margin
50
14
12
10
40
8.0
30
6.0
20
4.0
10
2.0
0
10
AV = 100
120
90
AV = 10
60
30
VCC = + 6.0 V
VEE = – 6.0 V
VO = 8.0 Vpp
TA = 25°C
0
100
1.0 k
CL, CAPACITIVE LOAD (pF)
VEE = – 5.0 V
RL = 600 Ω
AV = 1000
0.1
0.01
AV = 100
AV = 10
AV = 1.0
0.001
10
100
1.0 k
f, FREQUENCY (Hz)
8
10 k
100 k
en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
THD, TOTAL HARMONIC DISTORTION (%)
1.0
VCC = + 5.0 V
TA = 25°C
VO = 2.0 Vpp
10 k
f, FREQUENCY (Hz)
Figure 24. Total Harmonic Distortion
versus Frequency
10
0
100 k
150
0
1.0 k
100
10 k
Figure 23. Channel Separation
versus Frequency
A , GAIN MARGIN (dB)
M
CS, CHANNEL SEPARATION (dB)
O M , PHASE MARGIN (DEGREES)
Phase Margin
1.0 k
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
16
70
15
Gain Margin
Figure 22. Gain and Phase Margin
versus Capacitive Load
VCC = + 6.0 V
VEE = – 6.0 V
RL = 600 Ω
AV = 100
TA = 25°C
45
30
TA, AMBIENT TEMPERATURE (°C)
80
75
Phase Margin
A , GAIN MARGIN (dB)
M
70
Phase Margin
Figure 25. Equivalent Input Noise Voltage
and Current versus Frequency
50
5.0
VCC = + 6.0 V
VEE = – 6.0 V
TA = 25°C
40
30
4.0
3.0
Noise Voltage
20
10
2.0
1.0
Noise Current
0
10
100
1.0 k
10 k
0
100 k
i n , INPUT REFERRED NOISE CURRENT (pA/ Hz)
70
Figure 21. Gain and Phase Margin
versus Differential Source Resistance
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
MC33201 MC33202 MC33204
General Information
Circuit Information
The MC33201/2/4 family of operational amplifiers are
unique in their ability to swing rail–to–rail on both the input
and the output with a completely bipolar design. This offers
low noise, high output current capability and a wide common
mode input voltage range even with low supply voltages.
Operation is guaranteed over an extended temperature
range and at supply voltages of 2.0 V, 3.3 V and 5.0 V and
ground.
Since the common mode input voltage range extends from
VCC to VEE, it can be operated with either single or split
voltage supplies. The MC33201/2/4 are guaranteed not to
latch or phase reverse over the entire common mode range,
however, the inputs should not be allowed to exceed
maximum ratings.
Rail–to–rail performance is achieved at the input of the
amplifiers by using parallel NPN–PNP differential input
stages. When the inputs are within 800 mV of the negative
rail, the PNP stage is on. When the inputs are more than 800
mV greater than VEE, the NPN stage is on. This switching of
input pairs will cause a reversal of input bias currents (see
Figure 6). Also, slight differences in offset voltage may be
noted between the NPN and PNP pairs. Cross–coupling
techniques have been used to keep this change to a
minimum.
In addition to its rail–to–rail performance, the output stage
is current boosted to provide 80 mA of output current,
enabling the op amp to drive 600 Ω loads. Because of this
high output current capability, care should be taken not to
exceed the 150°C maximum junction temperature.
VCC = + 6.0 V
VEE = – 6.0 V
RL = 600 Ω
CL = 100 pF
TA = 25°C
Figure 27. Small Signal Transient Response
VCC = + 6.0 V
VEE = – 6.0 V
RL = 600 Ω
CL = 100 pF
TA = 25°C
V , OUTPUT VOLTAGE (50 mV/DIV)
O
V , OUTPUT VOLTAGE (2.0 mV/DIV)
O
Figure 26. Noninverting Amplifier Slew Rate
t, TIME (5.0 µs/DIV)
t, TIME (10 µs/DIV)
V , OUTPUT VOLTAGE (2.0 V/DIV)
O
Figure 28. Large Signal Transient Response
VCC = + 6.0 V
VEE = – 6.0 V
RL = 600 Ω
CL = 100 pF
AV = 1.0
TA = 25°C
t, TIME (10 µs/DIV)
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA ANALOG IC DEVICE DATA
9
MC33201 MC33202 MC33204
OUTLINE DIMENSIONS
8
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B–
1
4
F
L
C
J
–T–
N
SEATING
PLANE
D
M
K
0.13 (0.005)
M
T A
B
M
M
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
D
A
8
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
0.25
H
E
M
B
M
1
4
e
h
A
C
X 45 _
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
h
L
q
0.10
A1
B
0.25
M
C B
14
8
1
7
S
A
L
S
q
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
B
A
F
L
C
J
N
H
10
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
–––
10_
0.030
0.040
G
H
B
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
–––
10_
0.76
1.01
DIM
A
B
C
D
F
G
H
J
K
L
M
N
–A–
NOTE 2
G
D
SEATING
PLANE
K
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.18
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
MOTOROLA ANALOG IC DEVICE DATA
MC33201 MC33202 MC33204
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
–A–
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
B
M
M
R X 45 _
C
F
–T–
0.25 (0.010)
M
T B
S
A
S
0.10 (0.004)
M
T U
V
S
N
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
0.15 (0.006) T U
N
F
7
1
S
DETAIL E
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K
A
–V–
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
G
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
S
2X
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
DTB SUFFIX
PLASTIC PACKAGE
CASE 948G–01
(TSSOP–14)
ISSUE O
14X K REF
0.15 (0.006) T U
J
M
K
D 14 PL
SEATING
PLANE
DIM
A
B
C
D
F
G
J
K
M
P
R
H
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
How to reach us:
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P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: [email protected] – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MOTOROLA ANALOG IC DEVICE
DATA
◊
11
MC33201/D
*MC33201/D*
MC33201, MC33202,
MC33204, NCV33202,
NCV33204
Low Voltage, Rail−to−Rail
Operational Amplifiers
http://onsemi.com
The MC33201/2/4 family of operational amplifiers provide
rail−to−rail operation on both the input and output. The inputs can be
driven as high as 200 mV beyond the supply rails without phase
reversal on the outputs, and the output can swing within 50 mV of each
rail. This rail−to−rail operation enables the user to make full use of the
supply voltage range available. It is designed to work at very low
supply voltages (± 0.9 V) yet can operate with a supply of up to +12 V
and ground. Output current boosting techniques provide a high output
current capability while keeping the drain current of the amplifier to a
minimum. Also, the combination of low noise and distortion with a
high slew rate and drive capability make this an ideal amplifier for
audio applications.
PDIP−8
P, VP SUFFIX
CASE 626
8
1
8
1
• Low Voltage, Single Supply Operation
•
•
•
•
•
•
•
•
•
•
(+1.8 V and Ground to +12 V and Ground)
Input Voltage Range Includes both Supply Rails
Output Voltage Swings within 50 mV of both Rails
No Phase Reversal on the Output for Over−driven Input Signals
High Output Current (ISC = 80 mA, Typ)
Low Supply Current (ID = 0.9 mA, Typ)
600 W Output Drive Capability
Extended Operating Temperature Ranges
(−40° to +105°C and −55° to +125°C)
Typical Gain Bandwidth Product = 2.2 MHz
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
Pb−Free Packages are Available
8
1
SOIC−8
D, VD SUFFIX
CASE 751
Micro8]
DM SUFFIX
CASE 846A
PDIP−14
P, VP SUFFIX
CASE 646
14
1
14
1
14
1
SOIC−14
D, VD SUFFIX
CASE 751A
TSSOP−14
DTB SUFFIX
CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 14
1
Publication Order Number:
MC33201/D
MC33201, MC33202, MC33204, NCV33202, NCV33204
PIN CONNECTIONS
MC33204
All Case Styles
MC33201
All Case Styles
NC 1
8
2
7
Output 1 1
NC
2
VCC
Inputs 1
Inputs
3
6
Output
VEE 4
5
NC
2
Inputs 1
1
3
VEE 4
4
13
12
11
5
10
6
2
3
Output 2 7
MC33202
All Case Styles
Output 1 1
1
3
VCC 4
Inputs 2
(Top View)
14 Output 4
9
8
Inputs 4
VEE
Inputs 3
Output 3
(Top View)
8
VCC
7
Output 2
6
2
Inputs 2
5
(Top View)
VCC
VCC
VEE
VCC
Vin−
Vout
VCC
Vin+
VEE
This device contains 70 active transistors (each amplifier).
Figure 1. Circuit Schematic
(Each Amplifier)
http://onsemi.com
2
MC33201, MC33202, MC33204, NCV33202, NCV33204
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+13
V
Input Differential Voltage Range
VIDR
Note 1
V
Common Mode Input Voltage Range (Note 2)
VCM
VCC + 0.5 V to
VEE − 0.5 V
V
Output Short Circuit Duration
ts
Note 3
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
− 65 to +150
°C
Maximum Power Dissipation
PD
Note 3
mW
Supply Voltage (VCC to VEE)
DC ELECTRICAL CHARACTERISTICS (TA = 25°C)
Characteristic
VCC = 2.0 V
VCC = 3.3 V
VCC = 5.0 V
Input Offset Voltage
VIO (max)
MC33201
MC33202, NCV33202
MC33204, NCV33204
± 8.0
±10
±12
± 8.0
±10
±12
± 6.0
± 8.0
±10
Output Voltage Swing
VOH (RL = 10 kW)
VOL (RL = 10 kW)
1.9
0.10
3.15
0.15
4.85
0.15
Power Supply Current
per Amplifier (ID)
1.125
1.125
1.125
Unit
mV
Vmin
Vmax
mA
Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = GND.
DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic
Figure
Symbol
Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V)
MC33201:
TA = + 25°C
MC33201:
TA = − 40° to +105°C
MC33201V: TA = − 55° to +125°C
MC33202:
TA = + 25°C
MC33202:
TA = − 40° to +105°C
MC33202V: TA = − 55° to +125°C
NCV33202V: TA = − 55° to +125°C (Note 4)
MC33204:
TA = + 25°C
MC33204:
TA = − 40° to +105°C
MC33204V: TA = − 55° to +125°C
NCV33204: TA = − 55° to +125°C
3
⎮VIO⎮
Input Offset Voltage Temperature Coefficient (RS = 50 W)
TA = − 40° to +105°C
TA = − 55° to +125°C
4
Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
TA = + 25°C
TA = − 40° to +105°C
TA = − 55° to +125°C
5, 6
DVIO/DT
⎮IIB⎮
Min
Typ
Max
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6.0
9.0
13
8.0
11
14
14
10
13
17
17
−
−
2.0
2.0
−
−
−
−
−
80
100
−
200
250
500
Unit
mV
mV/°C
nA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The differential input voltage of each amplifier is limited by two internal parallel back−to−back diodes. For additional differential input voltage
range, use current limiting resistors in series with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltage
on either input must not exceed either supply rail by more than 500 mV.
3. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See Figure 2)
4. NCV33202 and NCV33204 are qualified for automotive use.
http://onsemi.com
3
MC33201, MC33202, MC33204, NCV33202, NCV33204
DC ELECTRICAL CHARACTERISTICS (cont.) (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Figure
Symbol
Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
TA = + 25°C
TA = − 40° to +105°C
TA = − 55° to +125°C
Characteristic
−
⎮IIO⎮
Common Mode Input Voltage Range
−
VICR
Large Signal Voltage Gain (VCC = + 5.0 V, VEE = − 5.0 V)
RL = 10 kW
RL = 600 W
7
AVOL
Output Voltage Swing (VID = ± 0.2 V)
RL = 10 kW
RL = 10 kW
RL = 600 W
RL = 600 W
Min
Typ
Max
−
−
−
5.0
10
−
50
100
200
VEE
−
VCC
Unit
nA
V
kV/V
50
25
300
250
−
−
VOH
VOL
VOH
VOL
4.85
−
4.75
−
4.95
0.05
4.85
0.15
−
0.15
−
0.25
60
90
−
500
25
−
50
80
−
−
−
0.9
0.9
1.125
1.125
8, 9, 10
V
Common Mode Rejection (Vin = 0 V to 5.0 V)
11
CMR
Power Supply Rejection Ratio
VCC/VEE = 5.0 V/GND to 3.0 V/GND
12
PSRR
Output Short Circuit Current (Source and Sink)
13, 14
ISC
Power Supply Current per Amplifier (VO = 0 V)
TA = − 40° to +105°C
TA = − 55° to +125°C
15
ID
dB
mV/V
mA
mA
AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic
Slew Rate
(VS = ± 2.5 V, VO = − 2.0 V to + 2.0 V, RL = 2.0 kW, AV = +1.0)
Figure
Symbol
16, 26
SR
Min
Typ
Max
0.5
1.0
−
Unit
V/ms
Gain Bandwidth Product (f = 100 kHz)
17
GBW
−
2.2
−
MHz
Gain Margin (RL = 600 W, CL = 0 pF)
20, 21, 22
AM
−
12
−
dB
Phase Margin (RL = 600 W, CL = 0 pF)
20, 21, 22
OM
−
65
−
Deg
23
CS
−
90
−
dB
BWP
−
28
−
kHz
−
−
0.002
0.008
−
−
−
100
−
Rin
−
200
−
kW
Cin
−
8.0
−
pF
−
−
25
20
−
−
nV/
Hz
−
−
0.8
0.2
−
−
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100)
Power Bandwidth (VO = 4.0 Vpp, RL = 600 W, THD ≤ 1 %)
24
Total Harmonic Distortion (RL = 600 W, VO = 1.0 Vpp, AV = 1.0)
f = 1.0 kHz
f = 10 kHz
Open Loop Output Impedance
(VO = 0 V, f = 2.0 MHz, AV = 10)
THD
⎮ZO⎮
Differential Input Resistance (VCM = 0 V)
Differential Input Capacitance (VCM = 0 V)
Equivalent Input Noise Voltage (RS = 100 W)
f = 10 Hz
f = 1.0 kHz
25
Equivalent Input Noise Current
f = 10 Hz
f = 1.0 kHz
25
http://onsemi.com
4
en
in
%
W
pA/
Hz
2500
40
PERCENTAGE OF AMPLIFIERS (%)
PD(max) , MAXIMUM POWER DISSIPATION (mW
MC33201, MC33202, MC33204, NCV33202, NCV33204
8 and 14 Pin DIP Pkg
2000
TSSOP−14 Pkg
1500
SO−14 Pkg
1000
SOIC−8
Pkg
500
0
−55 −40 −25
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
30
25
20
15
10
5.0
0
−10 −8.0 −6.0 −4.0 −2.0
0
2.0 4.0 6.0
VIO, INPUT OFFSET VOLTAGE (mV)
125
Figure 2. Maximum Power Dissipation
versus Temperature
I IB , INPUT BIAS CURRENT (nA)
30
160
120
20
10
0
−50 −40 −30 −20
−10
0
10
20
30
40
VCC = +5.0 V
VEE = Gnd
VCM = 0 V to 0.5 V
80
VCM > 1.0 V
40
0
−55 −40 −25
50
TCV , INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (mV/°C)
IO
0
25
70
85
125
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Input Bias Current
versus Temperature
A VOL , OPEN LOOP VOLTAGE GAIN (kV/V)
Figure 4. Input Offset Voltage
Temperature Coefficient Distribution
150
I IB , INPUT BIAS CURRENT (nA)
10
200
360 amplifiers tested from
3 (MC33204) wafer lots
VCC = +5.0 V
VEE = Gnd
TA = 25°C
DIP Package
40
300
100
260
50
0
220
−50
180
−100
−150
VCC = 12 V
VEE = Gnd
TA = 25°C
−200
−250
8.0
Figure 3. Input Offset Voltage Distribution
50
PERCENTAGE OF AMPLIFIERS (%)
360 amplifiers tested from
3 (MC33204) wafer lots
VCC = +5.0 V
VEE = Gnd
TA = 25°C
DIP Package
35
0
2.0
4.0
6.0
8.0
10
VCM, INPUT COMMON MODE VOLTAGE (V)
140
VCC = +5.0 V
VEE = Gnd
RL = 600 W
DVO = 0.5 V to 4.5 V
100
−55 −40 −25
12
Figure 6. Input Bias Current
versus Common Mode Voltage
0
25
70
85
TA, AMBIENT TEMPERATURE (°C)
105
Figure 7. Open Loop Voltage Gain versus
Temperature
http://onsemi.com
5
125
VO , OUTPUT VOLTAGE (Vpp )
12
VSAT, OUTPUT SATURATION VOLTAGE (V)
MC33201, MC33202, MC33204, NCV33202, NCV33204
RL = 600 W
TA = 25°C
10
8.0
6.0
4.0
2.0
0
±1.0
±2.0
±3.0
±4.0
±5.0
VCC,⎮VEE⎮ SUPPLY VOLTAGE (V)
±6.0
VCC
TA = −55°C
TA = 125°C
VCC − 0.4 V
TA = −55°C
5.0
CMR, COMMON MODE REJECTION (dB)
VO, OUTPUT VOLTAGE (Vpp )
10
IL, LOAD CURRENT (mA)
VEE
20
15
6.0
VCC = +6.0 V
VEE = −6.0 V
RL = 600 W
AV = +1.0
TA = 25°C
100
80
60
40
VCC = +6.0 V
VEE = −6.0 V
TA = −55° to +125°C
20
0
1.0 M
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
Figure 11. Common Mode Rejection
versus Frequency
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)
Figure 10. Output Voltage
versus Frequency
PSR, POWER SUPPLY REJECTION (dB)
VEE + 0.2 V
Figure 9. Output Saturation Voltage
versus Load Current
9.0
10 k
100 k
f, FREQUENCY (Hz)
TA = 25°C
TA = 125°C
0
12
0
1.0 k
VEE + 0.4 V
VCC = +5.0 V
VEE = −5.0 V
Figure 8. Output Voltage Swing
versus Supply Voltage
3.0
VCC − 0.2 V
TA = 25°C
120
100
100
PSR+
80
60
PSR−
40
VCC = +6.0 V
VEE = −6.0 V
TA = −55° to +125°C
20
0
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
Source
80
60
Sink
40
VCC = +6.0 V
VEE = −6.0 V
TA = 25°C
20
0
0
Figure 12. Power Supply Rejection
versus Frequency
1.0
2.0
3.0
4.0
⎮Vout⎮, OUTPUT VOLTAGE (V)
5.0
Figure 13. Output Short Circuit Current
versus Output Voltage
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6
6.0
I CC , SUPPLY CURRENT PER AMPLIFIER (mA)
2.0
150
125
VCC = +5.0 V
VEE = Gnd
1.6
100
Source
75
TA = 125°C
1.2
Sink
TA = 25°C
0.8
50
TA = −55°C
0.4
25
0
−55 −40 −25
0
25
70 85
TA, AMBIENT TEMPERATURE (°C)
105
125
0
±0
±1.0
Figure 14. Output Short Circuit Current
versus Temperature
GBW, GAIN BANDWIDTH PRODUCT (MHz)
+Slew Rate
1.0
−Slew Rate
0.5
25
70
85
105
1.0
0
−55 −40 −25
0
25
70
85
105
TA, AMBIENT TEMPERATURE (°C)
Figure 16. Slew Rate
versus Temperature
Figure 17. Gain Bandwidth Product
versus Temperature
40
VS = ±6.0 V
TA = 25°C
RL = 600 W
50
80
120
30
1A
2A
10
−30
10 k
2.0
TA, AMBIENT TEMPERATURE (°C)
70
−10
VCC = +2.5 V
VEE = −2.5 V
f = 100 kHz
3.0
125
2B
1A − Phase, CL = 0 pF
1B − Gain, CL = 0 pF
2A − Phase, CL = 300 pF
2B − Gain, CL = 300 pF
100 k
1B
1.0 M
160
200
O , EXCESS PHASE (DEGREES)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
0
4.0
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
SR, SLEW RATE (V/μ s)
VCC = +2.5 V
VEE = −2.5 V
VO = ±2.0 V
0
−55 −40 −25
±6.0
Figure 15. Supply Current per Amplifier
versus Supply Voltage with No Load
2.0
1.5
±2.0
±3.0
±4.0
±5.0
VCC, ⎮VEE⎮, SUPPLY VOLTAGE (V)
70
30
1A
10
−10
1A − Phase, VS = ±6.0 V
1B − Gain, VS = ±6.0 V
2A − Phase, VS = ±1.0 V
2B − Gain, VS = ±1.0 V
f, FREQUENCY (Hz)
100 k
1B
120
Figure 18. Voltage Gain and Phase
versus Frequency
200
1.0 M
Figure 19. Voltage Gain and Phase
versus Frequency
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160
2B
f, FREQUENCY (Hz)
7
80
2A
−30
10 k
240
10 M
40
CL = 0 pF
TA = 25°C
RL = 600 W
50
125
240
10 M
O , EXCESS PHASE (DEGREES)
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)
MC33201, MC33202, MC33204, NCV33202, NCV33204
MC33201, MC33202, MC33204, NCV33202, NCV33204
75
60
50
50
30
VCC = +6.0 V
VEE = −6.0 V
RL = 600 W
CL = 100 pF
40
30
20
20
10
10
Gain Margin
0
−55 −40 −25
0
25
70
85
105
60
60
VCC = +6.0 V
VEE = −6.0 V
TA = 25°C
45
30
30
15
0
0
125
10
100
16
60
Gain Margin
12
10
40
8.0
30
6.0
20
4.0
10
2.0
0
10
THD, TOTAL HARMONIC DISTORTION (%)
14
10
1.0
AV = 10
60
VCC = +6.0 V
VEE = −6.0 V
VO = 8.0 Vpp
TA = 25°C
30
1.0 k
10 k
f, FREQUENCY (Hz)
Figure 22. Gain and Phase Margin
versus Capacitive Load
Figure 23. Channel Separation
versus Frequency
VCC = +5.0 V
TA = 25°C
VO = 2.0 Vpp
VEE = −5.0 V
RL = 600 W
AV = 100
AV = 10
0.01
0.001
10
90
CL, CAPACITIVE LOAD (pF)
AV = 1000
0.1
AV = 100
120
0
100
0
1.0 k
100
AV = 1.0
100
1.0 k
10 k
100 k
en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
50
0
100 k
150
CS, CHANNEL SEPARATION (dB)
Phase Margin
10 k
Figure 21. Gain and Phase Margin
versus Differential Source Resistance
A , GAIN MARGIN (dB)
M
O M , PHASE MARGIN (DEGREES)
70
1.0 k
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
Figure 20. Gain and Phase Margin
versus Temperature
VCC = +6.0 V
VEE = −6.0 V
RL = 600 W
AV = 100
TA = 25°C
15
Gain Margin
TA, AMBIENT TEMPERATURE (°C)
80
45
50
5.0
VCC = +6.0 V
VEE = −6.0 V
TA = 25°C
40
30
3.0
Noise Voltage
20
10
Noise Current
0
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
Figure 25. Equivalent Input Noise Voltage
and Current versus Frequency
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8
2.0
1.0
f, FREQUENCY (Hz)
Figure 24. Total Harmonic Distortion
versus Frequency
4.0
0
100 k
i n , INPUT REFERRED NOISE CURRENT (pA/ Hz)
40
75
Phase Margin
A , GAIN MARGIN (dB)
M
60
O M , PHASE MARGIN (DEGREES)
70
Phase Margin
A , GAIN MARGIN (dB)
M
O M , PHASE MARGIN (DEGREES)
70
MC33201, MC33202, MC33204, NCV33202, NCV33204
DETAILED OPERATING DESCRIPTION
Circuit Information
The MC33201/2/4 family of operational amplifiers are
unique in their ability to swing rail−to−rail on both the input
and the output with a completely bipolar design. This offers
low noise, high output current capability and a wide
common mode input voltage range even with low supply
voltages. Operation is guaranteed over an extended
temperature range and at supply voltages of 2.0 V, 3.3 V and
5.0 V and ground.
Since the common mode input voltage range extends from
VCC to VEE, it can be operated with either single or split
voltage supplies. The MC33201/2/4 are guaranteed not to
latch or phase reverse over the entire common mode range,
however, the inputs should not be allowed to exceed
maximum ratings.
Rail−to−rail performance is achieved at the input of the
amplifiers by using parallel NPN−PNP differential input
stages. When the inputs are within 800 mV of the negative
rail, the PNP stage is on. When the inputs are more than 800
mV greater than VEE, the NPN stage is on. This switching of
input pairs will cause a reversal of input bias currents (see
Figure 6). Also, slight differences in offset voltage may be
noted between the NPN and PNP pairs. Cross−coupling
techniques have been used to keep this change to a minimum.
In addition to its rail−to−rail performance, the output stage
is current boosted to provide 80 mA of output current,
enabling the op amp to drive 600 W loads. Because of this
high output current capability, care should be taken not to
exceed the 150°C maximum junction temperature.
VCC = +6.0 V
VEE = −6.0 V
RL = 600 W
CL = 100 pF
TA = 25°C
VCC = +6.0 V
VEE = −6.0 V
RL = 600 W
CL = 100 pF
TA = 25°C
V , OUTPUT VOLTAGE (50 mV/DIV)
O
V , OUTPUT VOLTAGE (2.0 mV/DIV)
O
General Information
t, TIME (5.0 ms/DIV)
t, TIME (10 ms/DIV)
V , OUTPUT VOLTAGE (2.0 V/DIV)
O
Figure 26. Noninverting Amplifier Slew Rate
Figure 27. Small Signal Transient Response
VCC = +6.0 V
VEE = −6.0 V
RL = 600 W
CL = 100 pF
AV = 1.0
TA = 25°C
t, TIME (10 ms/DIV)
Figure 28. Large Signal Transient Response
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self−align when subjected to a
solder reflow process.
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9
MC33201, MC33202, MC33204, NCV33202, NCV33204
ORDERING INFORMATION
Operational
Amplifier Function
Device
Operating
Temperature Range
MC33201D
SOIC−8
(Pb−Free)
MC33201DR2
SOIC−8
TA= −40° to +105°C
MC33201P
PDIP−8
(Pb−Free)
MC33201VD
SOIC−8
(Pb−Free)
SOIC−8
MC33202DG
SOIC−8
(Pb−Free)
MC33202DR2
SOIC−8
MC33202DR2G
MC33202DMR2
TA= −40 ° to +105°C
MC33202DMR2G
SOIC−8
(Pb−Free)
50 Units / Rail
98 Units / Rail
2500 / Tape & Reel
Micro−8
Micro−8
(Pb−Free)
MC33202P
4000 / Tape & Reel
PDIP−8
MC33202PG
PDIP−8
(Pb−Free)
MC33202VD
SOIC−8
MC33202VDG
SOIC−8
(Pb−Free)
MC33202VDR2
SOIC−8
MC33202VDR2G
NCV33202VDR2*
2500 / Tape & Reel
SOIC−8
TA = −55° to 125°C
MC33202D
Dual
SOIC−8
(Pb−Free)
98 Units / Rail
PDIP−8
MC33201PG
MC33201VDG
Shipping †
SOIC−8
MC33201DG
MC33201DR2G
Single
Package
TA = −55° to 125°C
NCV33202VDR2G*
SOIC−8
(Pb−Free)
SOIC−8
50 Units / Rail
98 Units / Rail
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC33202VP
PDIP−8
MC33202VPG
PDIP−8
(Pb−Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV33202 and NCV33204 are qualified for automotive use.
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10
MC33201, MC33202, MC33204, NCV33202, NCV33204
ORDERING INFORMATION (continued)
Operational
Amplifier Function
Device
Operating
Temperature Range
MC33204D
MC33204DG
SO−14
(Pb−Free)
MC33204DR2
SO−14
MC33204DTB
SO−14
(Pb−Free)
TA= −40 ° to +105°C
TSSOP−14*
MC33204DTBG
TSSOP−14*
MC33204DTBR2
TSSOP−14*
MC33204DTBR2G
TSSOP−14*
MC33204P
PDIP−14
MC33204PG
PDIP−14
(Pb−Free)
MC33204VD
SO−14
MC33204VDG
SO−14
(Pb−Free)
MC33204VDR2
SO−14
MC33204VDR2G
NCV33204DR2**
NCV33204DR2G**
Shipping †
SO−14
MC33204DR2G
Quad
Package
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
2500 / Tape & Reel
25 Units / Rail
55 Units / Rail
SO−14
(Pb−Free)
TA = −55° to 125°C
SO−14
SO−14
(Pb−Free)
NCV33204DTBR2**
TSSOP−14*
NCV33204DTBR2G**
TSSOP−14*
MC33204VP
PDIP−14
MC33204VPG
PDIP−14
(Pb−Free)
2500 / Tape & Reel
25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
**NCV33202 and NCV33204 are qualified for automotive use.
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11
MC33201, MC33202, MC33204, NCV33202, NCV33204
MARKING DIAGRAMS
SOIC−8
D SUFFIX
CASE 751
8
1
8
3320x
ALYW
G
1
320xV
ALYW
G
PDIP−8
VP SUFFIX
CASE 626
PDIP−8
P SUFFIX
CASE 626
SOIC−8
VD SUFFIX
CASE 751
*
8
8
MC3320xP
AWL
YYWWG
14
MC33204VDG
AWLYWW
1
*
MC33204P
AWLYYWWG
1
14
MC33204VP
AWLYYWWG
1
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12
MC33204DG
AWLYWW
1
TSSOP−14
DTB SUFFIX
CASE 948G
14
MC33
204
ALYWG
G
1
x
= 1 or 2
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This marking diagram applies to NCV3320x
14
1
PDIP−14
VP SUFFIX
CASE 646
14
SO−14
D SUFFIX
CASE 751A
3202
AYWG
G
1
PDIP−14
P SUFFIX
CASE 646
14
8
MC33202VP
AWL
YYWWG
1
SO−14
VD SUFFIX
CASE 751A
Micro−8
DM SUFFIX
CASE 846A
MC33
204V
ALYWG
G
1
*
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
PDIP−8
P, VP SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
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13
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
Micro8
DM SUFFIX
CASE 846A−02
ISSUE G
D
HE
PIN 1 ID
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
E
e
b 8 PL
0.08 (0.003)
M
T B
S
A
S
SEATING
−T− PLANE
0.038 (0.0015)
A
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
DIM
A
A1
b
c
D
E
e
L
HE
MIN
−−
0.05
0.25
0.13
2.90
2.90
L
c
SOLDERING FOOTPRINT*
8X
1.04
0.041
0.38
0.015
3.20
0.126
6X
8X
4.24
0.167
0.65
0.0256
5.28
0.208
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
http://onsemi.com
16
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC33201, MC33202, MC33204, NCV33202, NCV33204
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K
A
−V−
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
18
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC33201, MC33202, MC33204, NCV33202, NCV33204
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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19
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MC33201/D