This is trial version, If you want get full version, please register it, thank you. Web site: http://www.verypdf.com/ E-mail: [email protected] HX8801 Data Sheet TFT-LCD AV CONTROLLER Version 02 August, 2002 Himax Technologies, Inc. 1F, No.12, Nanke 8th Road, Tainan Science-Based Industrial Park, Tainan County, Taiwan 741, R.O.C. TEL: 886-6-505-0880 FAX: 886-6-505-0891 DOC No:HX8801-17 HX8801 TFT-LCD AV CONTROLLER August 2002, Version 02 1. General Description The HX8801 is a timing controller for small panel TFT-LCD. It provides horizontal and vertical control timing to TFT-LCD source and gate drivers. Built-in vertical synchronization detection generates vertical synchronization signal internally without the extra components. Built-in phase lock loop sub-function with external VCO and low pass filter circuits produces system clock which synchronizes input composite synchronization signal. 2. Features Support six display resolution mode, up to 1440 × 234. Master clock frequency: 30 MHz max. Built-in vertical sync. detection to omit the external sync. separator. Single supply voltage: +5.0V. Shift clock signals for the source driver (3-φ Clock). Line inversion driving scheme. Support NTSC/PAL TV system. Provides source and gate drivers control timing. Provides flip and mirror scan control. 48 pins LQFP. Version 02 Himax Technologies, Inc. 1 HX8801 TFT-LCD AV CONTROLLER 3. Block Diagram L.P.F. V.C.O. VCO_CLK_OUT HX8801 PLL NPC Source Driver Control Composite Sync. Processing CVS Sync. Separator VS DHS, CPH1~3 OEV CKV OEH STHL(R) LRC RSC1~3 NPC Gate Driver Control Vertical Sync. Processing DVS STVU(D) Q1H VCOM UDC EXT_VS Mode Detection EXT_NPC Version 02 Himax Technologies, Inc. NPC 2 HX8801 TFT-LCD AV CONTROLLER 4. Pin Assignment VCO_CLK_OUT 25 DVS 27 VCO_CLK_IN 26 N.C. 28 HWRESETZ 29 VS 30 GND 32 UDC_INV 31 24 VCC N.C. 38 23 GND LRC 39 22 RSC1 LRC_INV 40 21 PH2 N.C. 41 20 PH1 HX8801 EXT_VS 42 NPC 43 19 CPH3 18 CPH2 (48-pin LQFP) VCOM 44 17 CPH1 EXT_NPC 45 16 CKV HS_REF_FBO 46 15 PDO HS_REF_FBI 47 14 STHR VCC 48 13 STHL 12 VCC 11 STVU 10 STVD Technologies, Inc. 9 RSC3 Himax 8 Q1H 7 GND 6 N.C. 5 N.C. 4 OEV 3 OEH 2 INV_IN 1 INV_OUT Version 02 RSC2 33 CVS 35 DHS 34 GND 36 UDC 37 3 HX8801 TFT-LCD AV CONTROLLER 5. Pin Description Pin no. 1 2 3 4 5 6 7 Symbol INV_OUT INV_IN OEH OEV N.C.(1) N.C. (1) GND I/O O I O O 8 Q1H O 9 RSC3(2) I 10 STVD O 11 STVU O 12 VCC 13 STHL O 14 STHR O 15 16 17 18 19 20 21 22 23 24 25 PDO CKV CPH1 CPH2 CPH3 PH1(3) PH2(3) RSC1(2) GND VCC VCO_CLK_OUT O O O O O I I I O 26 VCO_CLK_IN I DVS O 28 29 N.C. (1) HWRESETZ(4) I 30 VS I 27 Version 02 Description Inverter output Inverter input Source driver output enable control signal Gate driver output enable control signal Ground R, G, B video signal sample & hold multiplexer control signal for source driver Resolution mode setting pin III Start pulse for gate driver. (1) STVD is “HiZ”, when UDC=”L” (2) STVD is ”Output”, when UDC=”H” Start pulse for gate driver. (1) STVU is ”HiZ”, when UDC=”H” (2) STVU is ”Output”, when UDC=”L” +5.0V for controller power Start pulse for source driver. (1) STHL is ”HiZ”, when LRC=”H” (2) STHL is ”Output”, when LRC=”L” Start pulse for source driver. (1) STHR is ”HiZ”, when LRC=”L” (2) STHR is ”Output”, when LRC=”H” Phase detector output Shift clock for gate driver Shift clock φ1 for source driver Shift clock φ2 for source driver Shift clock φ3 for source driver Phase compensation setting pin I Phase compensation setting pin II Resolution mode setting pin I Ground +5.0V for controller power Inverted system clock signal output System clock input. It connects with external VCO and low pass filter circuits to generate system clock which synchronizes input composite synchronization signal Negative polarity vertical synchronization signal output Active low global reset signal input Negative polarity vertical synchronization signal input which is from the external synchronization Himax Technologies, Inc. 4 HX8801 TFT-LCD AV CONTROLLER Pin no. Symbol I/O 31 32 33 UDC_INV GND RSC2(2) O 34 DHS O 35 CVS I 36 GND 37 UDC 38 N.C. (1) I I 39 LRC I 40 41 LRC_INV N.C. (1) O Description separator circuits UDC inverted signal output Ground Resolution mode setting pin II Horizontal synchronization signal output with negative polarity Composite synchronization signal input with positive polarity Ground Up / Down scan setting pin (1) Normal scan, when UDC=”L” (2) Reverse scan, when UDC=”H” Left / Right scan setting pin (1) Normal scan, LRC=”L” (2) Reverse scan, LRC=”H” LRC inverted signal output VS detection setting pin (1) VS is from external detection , when 42 EXT_VS I EXT_VS=”H” (2) VS is from internal detection , when EXT_VS=”L” 43 Video signal input format setting pin NPC I/O (1) Input format is ”PAL”, when NPC=”L” (2) Input format is ”NTSC, when NPC=”H” 44 Toggling signal for common electrode generation VCOM O circuits NPC I/O setting pin 45 EXT_NPC I (1) NPC is “Output”, when EXT_NPC =”L” (2) NPC is “Input”, when EXT_NPC =”H” 46 Reference signal output for phase lock loop HS_REF_FBO O operation 47 Reference signal input for phase lock loop HS_REF_FBI I operation 48 VCC +5.0V for controller power Note: (1) The N.C. pins should be set “OPEN” for normal operation. (2) Resolution mode setting: RSC1 RSC2 RSC3 H H L L H L H H H L H H L L H H L H Version 02 Resolution mode(H × V) 280 × 220 528 × 220 480 × 234 960 × 234 1152 × 234 1440 × 234 Himax Technologies, Inc. 5 HX8801 TFT-LCD AV CONTROLLER (3) Phase compensation setting: PH1 PH2 Description CPH1~3 phase lag as Q1H H L changes from ‘L’ to ‘H’ CPH1~3 phase lead as Q1H L L changes from ‘L’ to ‘H’ H H Normal phase operation L H Normal phase operation PH1=”H” and PH2=”L” STHL(R) Q1H=”L” Q1H=”H” CPH1 CPH2 CPH3 PH1=”L” and PH2=”L” STHL(R) Q1H=”L” Q1H=”H” CPH1 CPH2 CPH3 (4) Need external RC reset circuit. Version 02 Himax Technologies, Inc. 6 HX8801 TFT-LCD AV CONTROLLER 6. DC Characteristics 6.1 Absolute maximum ratings: Parameter Symbol Power supply VCC Input voltage VIN Output voltage VOUT Storage temperature TSTG 6.2 Recommended operating conditions: Parameter Symbol Min. Power supply VCC 4.5 Input voltage VIN 0 Operating TOPR TBD temperature Rating -0.3 to 6.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -40 to 125 Units V V V ºC Typ. 5.0 - Max. 5.5 VCC Units V V - 85 ºC 6.3 Electrical Characteristics: Parameter Symbol Condition Min Typ Max Units No pull-up or Input low current IIL -1 1 µA pull-down No pull-up or Input high current IIH -1 1 µA pull-down Tri-state leakage IOZ -10 10 µA current Input capacitance CIN 3 pF Output capacitance COUT 3 6 pF Logic input low VIL TTL 0.8 V voltage Schmitt input low (1) VSIL TTL TBD V voltage Logic input high TTL 2.0 V VIH voltage Schmitt input high (1) VSIH TTL TBD V voltage Output low voltage VOL IOL=4mA 0.2VCC V Output high voltage VOH IOH=-4mA 0.8VCC V (2) Output low voltage VOL1 IOL=8mA 0.2VCC V (2) Output high voltage VOH1 IOH=-8mA 0.8VCC V Input pull up/down VIL= 0V or RI 50 100 kΩ resistance VIH= VCC Note: (1) INV_IN, RSC3, HWRESETZ, VCO_CLK_IN, VS, CVS, HS_REF_FBI. (2) VCO_CLK_OUT. Version 02 Himax Technologies, Inc. 7 HX8801 TFT-LCD AV CONTROLLER 6.4 Current consumption for 5 Volts operating: Parameter Symbol Conditions Min Vcc=+5.0V, fOSC = 5.6 MHz Vcc=+5.0V, fOSC = 9.6 MHz Vcc=+5.0V, fOSC = Full Chip 11.3 MHz Current IIN Vcc=+5.0V, fOSC = Consumption 19.2 MHz Vcc=+5.0V, fOSC = 23.2 MHz Vcc=+5.0V, fOSC = 29.1 MHz Version 02 Himax Technologies, Inc. Typ Max Units - TBD mA - TBD mA - TBD mA - TBD mA - TBD mA - TBD mA 8 HX8801 TFT-LCD AV CONTROLLER 7. AC Characteristics 7.1 280 × 220 resolution mode a. Input signal characteristics PARAMETER Symbol VCO_CLK_IN period tOSC CVS period tH CVS pulse width tCVS CVS rising time tCr CVS falling time tCf VS pulse width tVS VS rising time tVr VS falling time tVf Horizontal lines per NTSC field PAL b. Output signal characteristics PARAMETER Symbol (1) Rising time tr Falling time(1) tf Clock high and low level tCPH (2) pulse width Clock pulse duty tCWH t t 3-φ clock phase difference C12, C23, tC31 STH setup time tSUH STH pulse width tSTH DHS pulse width tHS OEH pulse width tOEH Sample & hold disable tDIS1 time OEV pulse width tOEV CKV pulse width tCKV HS_REF_FBO period tCP HS_REF_FBO pulse duty tWCP DHS-OEH time t1 DHS-CKV time t2 DHS-OEV time t3 DHS-HS_REF_FBO time t4 STV setup time tSUV STV pulse width tSTV DVS-STVD NTSC tVS1 time(UDC=’H’) PAL tVS1 DVS-STVU NTSC tVS2 time(UDC=’L’) PAL tVS2 OEH-STV time tOES Note: (1) For all of the logic signals. (2) CPH1~3 Version 02 Min. 150 61.5 4 1 - Typ. 166 63.5 4.7 3 262.5 312.5 Max. 183 65.5 5.4 700 300 5 700 1.5 - Unit. ns us us ns ns tH ns us lines lines Min. - Typ. - Max. 10 10 Unit. ns ns - 3 - tOSC 40 50 60 % - tCPH/3 - ns - tCPH/2 1 9 2 - tCPH tCPH tCPH tCPH - 16 - tCPH - 10 11 1 1/2 7 4 3 6 2 1 19 27 19 27 2 - tCPH tCPH tH tH tCPH tCPH tCPH tCPH tCPH tH tH tH tH tH tH Himax Technologies, Inc. 9