ETC SPHE8281D

DATA SHEET
SPHE8281D
DVD Single Chip MPEG A/V
Processor
Preliminary
MAY 19, 2005
Version 0.1
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be
accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, Sunplus Technology products are not authorized for use as critical components in life
support systems or aviation systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without
the express written approval of Sunplus.
Preliminary
SPHE8281D/Dx
Table of Contents
PAGE
1. GENERAL DESCRIPTION............................................................................................................................................................................... 3
2. FEATURE .......................................................................................................................................................................................................... 4
3. BLOCK DIAGRAM ........................................................................................................................................................................................... 6
4. SIGNAL DESCRIPTION ................................................................................................................................................................................... 7
4.1. PIN MAP ..................................................................................................................................................................................................... 7
4.2. GROUP MAP ............................................................................................................................................................................................... 8
4.3. PIN DESCRIPTION........................................................................................................................................................................................ 9
5. FUNCTIONAL DESCRIPTIONS .................................................................................................................................................................... 22
5.1. PLL AND CLOCKGEN ................................................................................................................................................................................ 22
5.2. POWER CONTROL ..................................................................................................................................................................................... 22
5.3. EMBEDDED 32-BIT RISC CONTROLLER ..................................................................................................................................................... 22
5.4. ROM/FLASH/SRAM CONTROLLER ........................................................................................................................................................... 23
5.5. CSS DECRYPTION HARDWARE ................................................................................................................................................................. 24
5.6. MPEG VIDEO DECODER ........................................................................................................................................................................... 24
5.7. VIDEO POST PROCESSING ........................................................................................................................................................................ 24
5.8. PROGRAMMABLE AUDIO DECODER............................................................................................................................................................ 25
5.9. AUDIO INTERFACE ..................................................................................................................................................................................... 25
5.10. AUDIO DAC .............................................................................................................................................................................................. 25
5.11. I/O PROCESSOR ....................................................................................................................................................................................... 25
5.12. SDRAM CONTROLLER ............................................................................................................................................................................. 25
5.13. SUB- PICTURE DECODER ........................................................................................................................................................................... 25
5.14. ON SCREEN DISPLAY ................................................................................................................................................................................ 25
5.15. DISPLAY INTERFACE .................................................................................................................................................................................. 26
5.16. VIDEO DAC .............................................................................................................................................................................................. 26
5.17. GPIO........................................................................................................................................................................................................ 26
5.18. UART ....................................................................................................................................................................................................... 26
6. ELECTRICAL SPECIFICATIONS .................................................................................................................................................................. 27
6.1. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................................................. 27
6.2. DC OPERATING CONDITIONS .................................................................................................................................................................... 27
6.3. CAPACITANCE ........................................................................................................................................................................................... 27
6.4. AC CHARACTERISTICS .............................................................................................................................................................................. 28
6.4.1. SDRAM interface timing diagrams .............................................................................................................................................. 28
6.4.2. ROM / flash interface timing diagrams........................................................................................................................................ 29
6.4.3. Audio interface timing diagrams .................................................................................................................................................. 30
6.4.4. Video timing diagrams ................................................................................................................................................................. 31
7. PACKAGE/PAD LOCATION .......................................................................................................................................................................... 33
7.1. OUTLINE DIMENSIONS ............................................................................................................................................................................... 33
8. DISCLAIMER .................................................................................................................................................................................................. 34
9. REVISION HISTORY ...................................................................................................................................................................................... 35
© Sunplus Confidential
Contents are subject to change without Notice
2
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
DVD SINGLE CHIP MPEG A/V PROCESSOR
1.GENERAL DESCRIPTION
SPHE8281D A/V decoder is a single-chip integrated DVD A/V
ISO/IEC 11172 MPEG1, 13818 MPEG2 sources. Besides MPEG
decoder.
A/V decoding, it supports Dolby Digital and MPEGI/II Layer1/2,
It is designed to maximize system performance with
minimum cost.
It integrates DVD/CD controller, host processor,
PCM, LPCM audio playback.
A/V decoding hardware, audio quality DAC and a 6-channel
SPHE8281D also combines all the functions required for a
multi-format TV-encoder.
high-performance
progressive-scan
DVD
system.
Built-in
de-interlacing hardware allows high quality DVD playback. The
SPHE8281D supports DVD and CD physical formats. For logical
embedded digital audio decoder is able to support key control and
formats it supports DVD-Video, Super Video CD, Video CD,
audio sound effects for Karaoke.
CD-DA, OKO, and CD-ROM discs.
Development tools of SPHE8281D include complete compiler
SPHE8281D performs real-time decoding and playback of
tools, programming guide and system application libraries.
Application utilizing the SPHE8281D is presented below:
IR
VFD
front panel
4-ch video
output
SPHE8281D
DVD-loader
2-ch audio analog
output
2~8ch
Audio
DAC
Audio
amplifier
USB
devices
SDRAM
ROM
Figure 1-1 Sample SPHE8281D application
© Sunplus Confidential
Contents are subject to change without Notice
3
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
2.FEATURE
Single Chip Integrated DVD Servo and A/V Decoder
SDRAM controller
Integrated DVD/CD Servo Controller
— High Performance SDRAM controller
— Support 1x ~ 2x DVD format reading
— Support 16 or 32 bit operation
— Support 1x ~ 8x CD format reading
— Support up to 2 SDRAM devices
Embedded 32-bit RISC Processor without external host
— Support 16M/64M SDRAM devices
Video Display
controller
Embedded Audio Processor supports multiple audio standards
— De-interlacing of interlaced video source
Embedded
— Flexible vertical interpolation
8-bit
I/O
processor
supports
programmable
— Flexible horizontal interpolation with optional CIF filter
interface control
Embedded TV encoder with multi-channel built-in high-speed
— Powerful cropping and panning effect
— Support YUV422, 8-bit indexed color format
video DAC supports various display standards
Embedded 2-channel 24-bit audio DAC
OSD
Built-in system PLL and audio PLL generate all clock sources
— Multiple OSD regions with different formats
— Support 2/4/16 indexed color
required from single 27MHz crystal input
Support following disc format:
— Support 16/24-bit direct color
Embedded TV encoder
— DVD Navigation 1.0
— SVCD (Chaoji VCD)
— Simultaneous multi-channel output
— OKO disc
— Support 480i/480p/576i/576p format
— VCD 2.0/1.1/1.0
— Support CVBS and S-Video output
— CDDA / HDCD
— Support Component (YUV / YPbPr) or SCART-RGB output
— CDROM (game, WMA and JPEG disc)
— Support WSS and CGMS/A
TM
CSS/CPPM hardware
— Macrovision
— Built-in CSS hardware
3
7.1.D1 and Macrovision AGC v1.03
analog copy protection
Interface
— Built-in CPPM C2_DCBC and C2_D/C2_E function
Video Decoder
— 27MHz crystal driver
— Real time MPEG2 MP@ML decoding
— 16/32-bit SDRAM interface
— Real time MPEG4 ASP D1 resolution decoding
— 8-bit ROM/FLASH/SRAM interface
— Real time MPEG1 D1 (720x480x30 /720x576x25) decoding
— One UART port
— DivX 3.11, 4.0 and 5.x version compatible
— IR and VFD support
— Hardware accelerated JPEG decoding
— 4-channel 12-bit video DAC analog output
— Advanced decoding and display control
— Simultaneous 8-channel audio DAC output
Sub-picture Decoder
— IEC958/SPDIF digital input / output
— Advanced Sub-Picture Decoder for DVD SVCD and OKO
— 2-channel 24-bit audio DAC analog output
— Support hardware vertical scaling
— External ADC digital input interface (optional)
Audio Decoder
— Optional ATAPI and I2S interface support
— Flexible Programmable DSP Architecture
— Optional Parallel Port interface support
Low power
— Support CDDA
— Support LPCM, PCM, and WMA
TM 1
— Advanced low power design
playback
— Support MPEGI/II layer 1/2 and MPEG 2.5 playback (with
— Selective standby mode
— Programmable low speed operation
optional down-mixing)
TM 2
— Support Dolby
Technology
Digital AC3 playback
— Support Key Shift of 2 channels
— Advanced CMOS technology
— Support equalization, reverb and special sound field
— 216-pin LQFP package
— 3v (I/O) and 1.8v (kernel) power supplies
— 5v I/O tolerance
1
WMA is a trademark of Microsoft Corporation
2
Dolby is a trademark of the Dolby Laboratories
© Sunplus Confidential
Contents are subject to change without Notice
3
4
Macrovision is a trademark of Macrovision Corporation
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
■ Licensing Notice
 In order to take care of different royalties, Sunplus SPHE8281D series have different combinations for different royalties.
For detail information, please contact with Sunplus Sales.
 Supply of the implementation of Dolby, WMA, Macrovision … technologies do not imply of a right or convey a license
under any patent, or any Intellectual Property Right of each respective company. Companies plan to use the
implementations MUST obtain respective license from respective licensor. Additional royalties may be required and are to
be paid by purchaser to each respective licensor
 Dolby is a trademark of the Dolby Laboratories. “This product includes technology owned by Dolby Laboratories cannot be
used or further distributed without a license from Dolby Laboratories.”
 WMA is a trademark of Microsoft Corporation. “This product includes technology owned by Microsoft Corporation cannot
be used or further distributed without a license from Microsoft.”
 DivX is a trademark of the DivXNetworks Inc. “This product includes technology owned by DivXNetworks Inc. cannot be
used or further distributed without a license from DivXNetworks Inc.”
 Macrovision is a trademark of the Macrovision Corporation. “This product includes technology owned by Macrovision
Corporation cannot be used or further distributed without a license from Macrovision Corporation.”
 All other trademarks are owned and trademarks of their respective holders and companies, which are used for
identification purposed only
© Sunplus Confidential
Contents are subject to change without Notice
5
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
3.BLOCK DIAGRAM
EPROM/SRAM
USB1.1 bus
SDRAM /16 or /32
EPROM/
SRAM
interface
USB 1.1
host
SDRAM
controller
Video
encoder
Video output
PLLv PLLa
RISC
icache
Power control
dcache
Audio
DSP
Intr. control
Timer
icache
RISC DMA
HOST
DMA
Sub-picture
decoder
MPEG
video
decoder
Video DAC
Video postprocessing
loader inf.
RF
loader RF input
ECC
mem
Bootstrap
OSD
decoder
Servo
Control
I/O
processor
IR/VFD/(I2C)
GPIO
GPIO
UART
UART
DAC
DAC analog out
Audio
Interface
IEC 958 I/O
ADC digital in
Figure 3-1 SPHE8281D block diagram
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MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
4.SIGNAL DESCRIPTION
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
R_A12
R_A7
R_A6
R_A5
R_A4
R_A3
R_A2
R_A1
R_A0
R_D0
R_D1
R_D2
VSS_O5/VSS_K5
R_D3
R_D4
R_D5
R_D6
R_D7
R_OE_B
VDD_K4
M_DQM2/GPIO
M_DQM3/GPIO
R_A10
R_A11
R_A9
R_A8
VDD_O4
R_A13
R_A14
R_A17
R_WE_B
M_A3
M_A2
M_A1
VSS_O4/VSS_K4
M_A0
M_A10
M_BA1/GPIO
M_DQM0/GPIO
M_DQM1/GPIO
M_A4
VDD_K3
M_A5
M_A6
M_A7
M_A8
M_A9
M_CKE/GPIO
VSS_O3/VSS_K3
M_CLKO
VDD_O3
M_A11/GPIO
M_D8
M_D9
4.1. Pin Map
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
SPHE8281D
8202D-216P
216 PIN LQFP
24x24mm2
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
M_D10
M_D11
M_D12
VDD_K2
M_D13
M_D14
M_D15
M_BA0
M_CS0_B/GPIO
VSS_O2/VSS_K2
M_RAS_B
M_CAS_B
M_WE_B
M_D0
M_D1
M_D2
VDD_O2
M_D3
M_D4
M_D5
M_D6
M_D7
VDD_PLLV
VSS_PLLV
VDD_PLLA
VSS_PLLA
USB_DM
USB_DP
USB_VDD
USB_GND
CLKOUT
CLKIN
R_A19
R_A20/E_MX10
VFD_DATA/GPIO
VFD_STB/GPIO
VFD_CLK/GPIO
IR_IN/GPIO
RST_B
R_CS1_B/GPIO
R_CS2_B/GPIO
R_CS3_B/GPIO
R_CS4_B/GPIO
GPIO
VDD_O1
GPIO/ttio3_7
GPIO/ttio2_6
GPIO/ttio1_5
VSS_O1/VSS_K1
GPIO/ttio0_4
GPIO/TRAY_IS_OUT
GPIO/TRAY_IS_IN
VDD_K1
DFCT/GPIO
AGCON
AGCOP
RFIP
RFIS
RFSUM
DPDA
DPDB
DPDC
DPDD
DVDD
DVDC
DVDB
DVDA
CDB
CDA
CDF
CDE
RF_AVSS
APC_AVSS
DVDLDO
CDLDO
DVDMDI
CDMDI
APC_SRV_AVDD
V21
R33K
V165
SVOTST
RFRPPH
RFRPBH
RFRPMEAN
SBADPH
SBAD
FEO
TEO
TEOLP
OPVIP
OPVIN
OPVOP
SRV_AD_AVSS_VRGD
AD_DA_AVDD
DATEO
DAFEO
DA_AVSS
E_MX8
E_MX9
SPDC_OUT/GPIO
SC_OUT/GPIO
SC1_OUT/GPIO
TRAY_OUT/GPIO
DMEA/GPIO
FGIN/GPIO
HOMESW/GPIO
LDSW/GPIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
R_A15
DAC_REF
DAC_L
DAC_R
DAC_VDD
DAC_VSS
R_A16
R_A18
A_IEC_TX/GPIO
A_DATA0/GPIO
VDD_O5
A_DATA1/GPIO
A_DATA2/GPIO
A_DATA3/GPIO
A_LRCK/GPIO
VSS_K6/VSS_O6
A_BCK/GPIO
A_XCK/GPIO
UA0_RX/GPIO
UA0_TX/GPIO
V_COMP
V_BIAS
V_FSADJ
V_REFOUT
TV_DAC0
VDD_TVA0
VSS_TVA0
VDD_TVA1
VSS_TVA1
TV_DAC3
TV_DAC4
VDD_TVA2
TV_DAC5
VSS_TVA2
PLL_AVDD
LPFO
LPFN
VREFO
PDFLT
FDFLT
LPFNIN
LGIN
PLL_DS_AVSS
RFI
CNIN
SLVL
DS_AVDD
RF_AVDD
GMRES
AGCCAP
RFRP
RFO
FLTIP
FLTIN
Figure 4-1 SPHE8281D pin
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7
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
4.2. Group Map
System
Interface
VSS_*
LPFO LPFN
VDD_*
VREFO
CLKIN / CLKOUT
PDFLT
RSTB
FDFLT
LPFNIN
Audio
analog output
interface
DAC_VREF
LGIN
DAC_L
RFI
DAC_R
CNIN
SLVL
Audio
digital output
interface
AU_XCK
GMRES
AU_BCK
AGCCAP
AU_LRCK
RFRP
AU_DATA[3:0]
RFO
A_IEC_TX
FLTIP FLTIN
AGCON AGCOP
RFIP RFIS RFSUM
ROM/flash
interface
R_CS_B[3:0]
DPDA DPDB DPDC DPDD
R_OE_B
DVDA DVDB DVDC DVDD
R_WE_B
CDB CDA CDF CDE
R_A[19:0]
DVDLDO
SERVO
CDLDO
R_D[7:0]
DVDMDI
CDMDI
M_CLKO
SPHE8281D
(216pin)
M_RAS_B
M_CAS_B
M_WE_B
SDRAM
interface
M_CS0_B
R33K
V165
SVOTST
RFRPPH RFRPBH RFRPMEAN
M_BA0
SBADPH
M_BA1
SBAD
M_A11
FEO TEO
TEOLP
M_A[10:0]
M_D[15:0]
OPVIP
M_DQM[3:0]
OPVIN
OPVOP
VRGD
IR_IN
IR
VFD
UART
GPIOs
DATEO DAFEO
VFD_CLK
VFD_STB
VFD_DATA
SPDC_OUT
UA0_RX UA0_TX
SC_OUT
SC1_OUT
Other GPIOs
TRAY_OUT
V_COMP
DMEA
V_BIAS
Video
output
interface
FGIN
HOMESW
V_FSADJ
SERVO
LDSW
V_REFOUT
V_DAC0
DFCT
V_DAC3
TRAY_IS_OUT
V_DAC4
TRAY_IS_IN
V_DAC5
ttio*
Figure 4-2 SPHE8281D pin groups
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MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
4.3. Pin Description
Pin No.
I/O
AGCON
Symbol
1
O
Differential AGC output #N
AGCOP
2
O
Differential AGC output #P
RFIP
3
I
Differential RF signal input #P
RFIS
4
I
Single-ended RF equalizer input.
RFSUM
5
O
RF summing amplified output.
DPDA
6
I
AC coupled RF inputs for the DPD #A, from the main beam photo detector.
Description
DPDB
7
I
AC coupled RF inputs for the DPD #B, from the main beam photo detector.
DPDC
8
I
AC coupled RF inputs for the DPD #C, from the main beam photo detector.
DPDD
9
I
AC coupled RF inputs for the DPD #D, from the main beam photo detector.
DVDD
10
I
DVD RF inputs #A, from the main beam photo detector.
DVDC
11
I
DVD RF inputs #B, from the main beam photo detector.
DVDB
12
I
DVD RF inputs #C, from the main beam photo detector.
DVDA
13
I
DVD RF inputs #D, from the main beam photo detector.
CDB
14
I
CD RF inputs #B, from the main beam photo detector.
CDA
15
I
CD RF inputs #A, from the main beam photo detector.
CDF
16
I
CD tracking error inputs #F, from the sub-beam photo detector.
CDE
17
I
CD tracking error inputs #E, from the sub-beam photo detector.
RF_AVSS
18
S
Servo RF ground
APC_AVSS
19
S
Servo APC ground
DVDLDO
20
O
DVD APC output.
CDLDO
21
O
CD APC output.
DVDMDI
22
I
DVD APC input from monitor photo diode.
CDMDI
23
I
CD APC input from monitor photo diode.
APC_SRV_AVDD
24
S
Servo APC and analog 3.3V power (216pin only)
V21
25
-
Reference DC bias voltage.
R33K
26
-
External reference resistor input.
V165
27
-
Reference DC bias voltage.
SVOTST
28
O
RF peak hold external capacitor
RFRPPH
29
O
RFRP peak hold signal output.
RFRPBH
30
O
RFRP bottom hold signal output.
RFRPMEAN
31
O
RFRP mean signal output.
SBADPH
32
O
Sub-beam adds peak hold signal output.
SBAD
33
O
Sub-beam adds signal output.
FEO
34
O
Focus error signal output.
TEO
35
O
Tracking error signal output.
TEOLP
36
A
OPVIP
37
I
Op-amp 1 positive input.
OPVIN
38
I
Op-amp 1 negative input.
OPVOP
39
O
Op-amp output.
SRV_AD_VRGD_AV
40
S
Servo/ADC analog ground
AD_DA_AVDD
41
S
Servo ADC/DAC 3.3V power
DATEO
42
A
DAFEO
43
A
SS
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Contents are subject to change without Notice
9
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
Pin No.
I/O
DA_AVSS
44
S
E_MX8
45
I/O
Description
Servo DAC ground
GPIO [70]
Priority selection
sft_cfg2[5:4] =2'b01
Function
Dir
UA1_RXD
I
sft_cfg7[5:4]=2’b11
656_DATA[0]
O
sft_cfg1[11:9]=3’b110
RISC_INT1_11
I
sft_cfg7[1]= 1’b 0,
FM_GPIOB [12]
I/O
FM_GPIOB [29]
I/O
sft_cfg0[11]= 1’b 1,
fm_gpio_len[3:0]>8
sft_cfg0[11]= 1’b 0,
fm_gpio_len[3:0]=4'b1100
E_MX9
46
I/O
Sft_cfg8[5]= 1’b 1
TV_EXT_DATA_Cr[7]
(other)
GPIO[70](default)
I
I/O
GPIO[71]
Priority selection
Function
dir
sft_cfg2[5:4] =2'b01
UA1_TXD
O
sft_cfg7[5:4]=2’b11
656_DATA[1]
O
sft_cfg1[11:9]=3’b110
RISC_INT1_12
I
sft_cfg7[1]= 1’b 0,
FM_GPIOB [13]
I/O
FM_GPIOB [30]
I/O
sft_cfg0[11]= 1’b 1,
fm_gpio_len[3:0]>8
sft_cfg0[11]= 1’b 0,
fm_gpio_len[3:0]=4'b1100
SPDC_OUT/GPIO
47
I/O
Sft_cfg8[5]= 1’b 1
TV_EXT_DATA_Cr[6]
(other)
GPIO[71](default)
48
I/O
49
I/O
© Sunplus Confidential
dir
AT_RESET_B
O
sft_cfg4[0]=1’b1
SPDC_OUT (default)
I/O
Sft_cfg8[9]=1’b1
DAC_PDF
sft_cfg8[8]=1’b1
OTP_TEST_ADDR[0]
(other)
GPIO[0]
I
I
I/O
Servo SC_OUT
Function
dir
sft_cfg2[11:10]=2’b01,2’b10
AT_DIOR_B
O
sft_cfg4[1]=1’b1
SC_OUT (default)
I/O
Sft_cfg8[9]=1’b1
DAC_PDE
I
sft_cfg8[8]=1’b1
OTP_TEST_ADDR[1]
I
(other)
GPIO[1]
I/O
Servo SC1_OUT
Priority selection
Contents are subject to change without Notice
Function
sft_cfg2[11:10]=2’b01,2’b10
Priority selection
SC1_OUT/GPIO
I/O
Servo SPDC_OUT
Priority selection
SC_OUT/GPIO
I
Function
dir
sft_cfg2[11:10]=2’b01,2’b10
AT_DIOW_B
O
sft_cfg4[2]=1’b1
SC1_OUT (default)
I/O
Sft_cfg8[9]=1’b1
DAC_PDD
sft_cfg8[8]=1’b1
OTP_TEST_ADDR[2]
(other)
GPIO[2]
10
I
I
I/O
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
TRAY_OUT/GPIO
Pin No.
I/O
50
I/O
Description
Servo TRAY_OUT
Priority selection
DMEA_OUT/GPIO
51
I/O
sft_cfg4[3]=1’b1
TRAY_OUT (default)
Sft_cfg8[9]=1’b1
DAC_PDC
I
sft_cfg8[8]=1’b1
OTP_TEST_ADDR[3]
I
(other)
GPIO[3]
I/O
53
IO
IO
DMEA_OUT (default)
O
DAC_PDB
I
sft_cfg8[8]=1’b1
OTP_TEST_ADDR[4]
(other)
GPIO[4]
I
I/O
Servo FGIN
Function
dir
sft_cfg2[11:10]=2’b01,2’b10
AT_DMARQ
I
sft_cfg4[5]=1’b1
FGIN (default)
I
Sft_cfg8[9]=1’b1
DAC_PDA
I
sft_cfg8[8]=1’b1
OTP_TEST_PGM
I
(other)
GPIO[5]
I/O
Servo HOMESW
Function
UA0_RXD
dir
I
sft_cfg1[8:6]=3’b010
R_CSALL_B
O
sft_cfg7[7:6]=2’b11
PCMCIA_IOW_B
O
Sft_cfg8[1]=1’b1
DSP_FL0
O
Sft_cfg8[9]=1’b1
DAC_DATA_F[9]
I
sft_cfg9[14:13]=2’b01
EXT_CLK48
I
sft_cfg6[4]=1’b1
DELAY_CHAIN1
O
sft_cfg8[8]=1’b1
OTP_TEST_DATA
O
(other)
GPIO[6] (default)
I/O
Servo LDSW
Priority selection
© Sunplus Confidential
dir
Sft_cfg8[9]=1’b1
sft_cfg2[3:2]=2’b10
Contents are subject to change without Notice
Function
sft_cfg4[4]=1’b1
sft_cfg2[3:2]=2’b10
54
I/O
O
Priority selection
LDSW/GPIO
I/O
AT_DMACK
Priority selection
HOMESW/GPIO
I
Servo DMEA
sft_cfg2[11:10]=2’b01,2’b10
52
dir
AT_IORDY
Priority selection
FGIN/GPIO
Function
sft_cfg2[11:10]=2’b01,2’b10
Function
UA0_TXD
dir
O
sft_cfg2[5:4]=2’b10
UA1_RXD
I
sft_cfg7[7:6]=2’b11
PCMCIA_IOR_B
O
Sft_cfg8[2]=1’b1
DSP_FL1
O
Sft_cfg8[9]=1’b1
DAC_DATA_F[8]
I
sft_cfg7[15:14]=2’b11
CLK27_OUT
O
sft_cfg9[14:13]=2’b10
EXT_CLK48
I
sft_cfg6[4]=1’b1
DELAY_CHAIN2
O
(other)
GPIO[7] (default)
I/O
11
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
DFCT/GPIO
Pin No.
I/O
55
IO
Description
Servo DFCT
Priority selection
Function
AT_INTRQ
I
sft_cfg4[6]=1’b1
DFCT (default)
O
Sft_cfg8[9]=1’b1
DAC_DATA_F[7]
(other)
GPIO[8]
VDD_K1
56
S
Kernel logic power supply #1
GPIO/TRAY_IS_IN
57
IO
GPIO
Priority selection
GPIO/TRAY_IS_OUT
58
IO
Function
59
IO
I
I/O
dir
sft_cfg2[11:10]=2’b01,2’b10
AT_ADR[1]
Sft_cfg8[3]=1’b1
DSP_FL2
O
fm_gpio_len[3:0] > 0
FM_GPIOB[0]
I/O
Sft_cfg8[9]=1’b1
DAC_DATA_F[6]
I
O
(other)
GPIO[9] (default)
I/O
GPIO
Priority selection
GPIO/ttio0_4
dir
sft_cfg2[11:10]=2’b01,2’b10
Function
dir
sft_cfg2[11:10]=2’b01,2’b10
AT_ADR[2]
O
Sft_cfg8[4]=1’b1
DSP_FLAG_OUT
O
fm_gpio_len[3:0] > 0
FM_GPIOB[1]
I/O
Sft_cfg8[9]=1’b1
DAC_DATA_F[5]
(other)
GPIO[10] (default)
I
I/O
GPIO
Priority selection
Function
dir
sft_cfg2[11:10]=2’b01,2’b10
AT_ADR[0]
O
sft_cfg4[9]=1’b1
ttio4/ttio0
I/O
Sft_cfg1[11:9]=3’b001
RISC_INT1_11
Sft_cfg3[11:10]=2’b01
ADC_BCK, digital audio
I
I/O
input interface bit clock
fm_gpio_len[3:0] > 0
FM_GPIOB[2]
Sft_cfg8[9]=1’b1
DAC_DATA_F[4]
I
(other)
GPIO[11] (default)
I/O
VSS_O1/ VSS_K1
60
S
Kernel logic / I/O power shared ground supply #1
GPIO/ttio1_5
61
IO
GPIO
Priority selection
sft_cfg2[11:10]=2’b01,2’b10
Function
I/O
dir
AT_CS1
O
sft_cfg4[9]=1’b1
Ttio5/ttio1
I/O
sft_cfg4[15:13]=3’b001
HSYNC_PC
O
Sft_cfg1[11:9]=3’b001
RISC_INT1_12
I
Sft_cfg3[11:10]=2’b01
ADC_LRCK, digital
I/O
audio input interface L/R
strobe
© Sunplus Confidential
Contents are subject to change without Notice
fm_gpio_len[3:0] > 0
FM_GPIOB[3]
Sft_cfg8[9]=1’b1
DAC_DATA_F[3]
(other)
GPIO[12] (default)
12
I/O
I
I/O
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
GPIO/ttio2_6
Pin No.
I/O
62
IO
Description
GPIO
Priority selection
Function
dir
sft_cfg2[11:10]=2’b01,2’b10
AT_CS0
O
sft_cfg4[9]=1’b1
Ttio6/ttio2
I/O
sft_cfg4[15:13]=3’b001
VSYNC_PC
O
sft_cfg3[15:14]=2’b01
ISA_IOCHRDY
I
Sft_cfg1[11:9]=3’b001
RISC_INT1_13
I
Sft_cfg3[11:10]=2’b01
ADC_DATA, digital audio
I
input interface data
GPIO/ttio3_7
63
IO
fm_gpio_len[3:0] > 1
FM_GPIOB[4]
Sft_cfg8[9]=1’b1
DAC_DATA_F[2]
(other)
GPIO[13] (default)
sft_cfg4[9]=1’b1
Function
Ttio7/ttio3
dir
I/O
PCMCIA_WAIT_B
I
sft_cfg7[11:8]=4’b0001
EXT_CLK27
I
Sft_cfg1[11:9]=3’b001
RISC_INT1_14
I
fm_gpio_len[3:0] > 2
FM_GPIOB[5]
I/O
Sft_cfg8[9]=1’b1
DAC_DATA_F[1]
(other)
GPIO[14] (default)
64
S
I/O power supply #1
GPIO
65
IO
GPIO
Priority selection
IO
I/O
sft_cfg2[9:8]=2’b11
VDD_O1
66
I
GPIO
Priority selection
R_CS4_B/GPIO
I/O
Function
I
I/O
dir
sft_cfg2[5:4]=2’b10
UA1_TXD
O
sft_cfg1[8:6]=3’b001
R_CSALL_B
O
sysclk_sel[4]
EXT_SYSCLK
I
sft_cfg7[11:8]=4’b0010
EXT_CLK27
I
fm_gpio_len[3:0] > 3
FM_GPIOB[6]
I/O
sft_cfg8[9]=1’b1
DAC_DATA_F[0]
I
sft_cfg7[13:12]=2’b11
CLK54_OUT
O
sft_cfg9[14:13]=2’b11
EXT_CLK48
I
sft_cfg6[4]=1’b1
DELAY_CHAIN3
O
(other)
GPIO[15] (default)
I/O
ROM / SRAM / flash chip select #4 or GPIO
Priority selection
Function
dir
sft_cfg1[3]=1’b1
R_CS4_B (default)
O
sft_cfg1[7]=1’b1 &
FM_GPIOB[20]
I/O
fm_gpio_len[3:0] = 10,11,12
© Sunplus Confidential
Contents are subject to change without Notice
sft_cfg8[9]=1’b1
DAC_DATA_E[9]
(other)
GPIO[16]
13
I
I/O
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
R_CS3_B/GPIO
Pin No.
I/O
67
IO
Description
ROM / SRAM / flash chip select #3 or GPIO
Priority selection
R_CS2_B/GPIO
68
IO
Function
R_CS3_B (default)
O
sft_cfg8[9]=1’b1
DAC_DATA_E[8]
I
(other)
GPIO[17]
69
IO
Function
R_CS2_B (default)
O
sft_cfg8[9]=1’b1
DAC_DATA_E[7]
I
(other)
GPIO[18]
I
IR_IN/GPIO
71
IO
Function
R_CS1_B (default)
sft_cfg8[9]=1’b1
DAC_DATA_E[6]
(other)
GPIO[19]
Function
sft_cfg8[0]=1’b1
IR_IN,GPIO[20]
(other)
GPIO[20] (default)
72
IO
GPIO[21] for VFD_CLK
VFD_STB/GPIO
73
IO
GPIO[22] for VFD_STB
Priority selection
IO
Function
dir
I
I/O
dir
DAC_DATA_E[5]
I
(other)
GPIO[22] (default)
I/O
GPIO[23] for VFD_DATA
Function
dir
sft_cfg8[9]=1’b1
DAC_DATA_E[4]
I
(other)
GPIO[23] (default)
I/O
R_A20
75
IO
ROM / SRAM / flash address bus bit [20] (216pin package)
R_A19 (E_MX11)
76
IO
ROM / SRAM / flash address bus bit [19]
CLKIN
77
I
CLKOUT
78
O
Clock output / crystal out (XTALO)
RESERVED_N
79
A
Reserved
RESERVED_P
80
A
Reserved
RESERVED
81
A
Reserved
RESERVED
82
A
Reserved
VSS_PLLA
83
S
Ground pin for audio PLL
Clock input / crystal in (XTALI)
VDD_PLLA
84
S
3.3V power supply pin for audio PLL
VSS_PLLV
85
S
Ground pin for system PLL and audio PLL
VDD_PLLV
86
S
1.8V power supply pin for system PLL
M_DD[7]
87
IO
SDRAM data bus [7]
M_DD[6]
88
IO
SDRAM data bus [6]
M_DD[5]
89
IO
SDRAM data bus [5]
M_DD[4]
90
IO
SDRAM data bus [4]
© Sunplus Confidential
I
I/O
sft_cfg8[9]=1’b1
Priority selection
Contents are subject to change without Notice
O
GPIO
VFD_CLK/GPIO
74
dir
System reset (active low reset)
Priority selection
VFD_DATA/GPIO
I/O
ROM / SRAM / flash chip select #1 or GPIO
sft_cfg1[0]=1’b1
70
dir
sft_cfg1[1]=1’b1
Priority selection
RST_B
I/O
ROM / SRAM / flash chip select #2 or GPIO
Priority selection
R_CS1_B/GPIO
dir
sft_cfg1[2]=1’b1
14
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
Pin No.
I/O
Description
M_DD[3]
91
IO
SDRAM data bus [3]
VDD_O2
92
S
I/O power supply #2
M_DD[2]
93
IO
SDRAM data bus [2]
M_DD[1]
94
IO
SDRAM data bus [1]
M_DD[0]
95
IO
SDRAM data bus [0]
M_WE_B
96
IO
SDRAM write enable / row precharge
M_CAS_B
97
IO
SDRAM column address strobe (CASB)
M_RAS_B
98
IO
SDRAM row address strobe (RASB)
VSS_O2/ VSS_K2
99
S
Kernel logic / I/O power shared ground supply #2
M_CS0_B/GPIO
100
IO
SDRAM chip select 0, or GPIO[24]
Priority selection
sft_cfg0[0]=1’b1
Function
SDRAM chip select
dir
O
(default)
sft_cfg8[9]=1’b1
DAC_DATA_D[2]
(other)
GPIO[24]
M_BA0
101
IO
SDRAM bank select address [0]
M_DD[15]
102
IO
SDRAM data bus [15]
M_DD[14]
103
IO
SDRAM data bus [14]
M_DD[13]
104
IO
SDRAM data bus [13]
VDD_K2
105
S
Kernel logic power supply #2
M_DD[12]
106
IO
SDRAM data bus [12]
M_DD[11]
107
IO
SDRAM data bus [11]
M_DD[10]
108
IO
SDRAM data bus [10]
M_DD[9]
109
IO
SDRAM data bus [9]
M_DD[8]
110
IO
SDRAM data bus [8]
M_A[11]/ GPIO
111
IO
SDRAM address bus [11] or GPIO[25]
Priority selection
Function
sft_cfg1[4]=1’b1
SDRAM address bus
sft_cfg8[9]=1’b1
DAC_DATA_C[2]
(other)
GPIO[25]
I
I/O
dir
O
M_A[11] (default)
VDD_O3
112
S
I/O power supply #3
M_CLKO
113
O
SDRAM clock output
VSS_O3/ VSS_K3
114
S
Kernel logic / I/O power shared ground supply #3
M_CKE/GPIO
115
IO
SDRAM clock enable, or GPIO[26]
Priority selection
Function
sft_cfg0[1]=1’b1
DRAM clock enable
sft_cfg8[9]=1’b1
DAC_DATA_C[1]
(other)
GPIO[26]
I
I/O
dir
O
(default)
M_A[9]
116
IO
SDRAM address bus [9]
M_A[8]
117
IO
SDRAM address bus [8]
M_A[7]
118
IO
SDRAM address bus [7]
M_A[6]
119
I/O
SDRAM address bus [6]
M_A[5]
120
I/O
SDRAM address bus [5]
© Sunplus Confidential
Contents are subject to change without Notice
15
I
I/O
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
Pin No.
I/O
Description
VDD_K3
121
S
M_A[4]
122
I/O
SDRAM address bus [4]
M_DQM1/GPIO
123
I/O
SDRAM data input/output mask for M_DD[15:8], or GPIOA[27]
M_DQM0/GPIO
124
I/O
SDRAM data input/output mask for M_DD[7:0] or GPIOA[28]
Kernel logic power supply #3
Priority selection
sft_cfg0[2]=1’b1
Function
SDRAM data
dir
I/O
input/output mask for
M_DD[7:0] (default)
sft_cfg8[8]=1’b1
M_BA1/GPIO
125
I/O
ADC_MONO_D_R[5]
sft_cfg8[9]=1’b1
DAC_DATA_B[3]
(other)
GPIO[28]
O
I
I/O
SDRAM bank select address [1] or GPIOA[29]
Priority selection
sft_cfg0[6]=1’b1
Function
SDRAM bank select
dir
I/O
address [1] (default)
sft_cfg8[8]=1’b1
ADC_MONO_D_R[6]
O
sft_cfg8[9]=1’b1
DAC_DATA_B[2]
I
(other)
GPIO[29]
M_A[10]
126
O
SDRAM address bus [10]
M_A[0]
127
O
SDRAM address bus [0]
VSS_O4/ VSS_K4
128
S
Kernel logic / I/O power shared ground supply #4
M_A[1]
129
O
SDRAM address bus [1]
M_A[2]
130
O
SDRAM address bus [2]
M_A[3]
131
O
SDRAM address bus [3]
R_WE_B
132
I/O
ROM / SRAM / flash write strobe
R_A17
133
I/O
ROM / SRAM / flash address bus bit [17]
R_A14
134
I/O
ROM / SRAM / flash address bus bit [14]
R_A13
135
I/O
VDD_O4
136
S
I/O power supply #4
R_A8
137
O
ROM / SRAM / flash address bus bit [8]
R_A9
138
O
ROM / SRAM / flash address bus bit [9]
R_A11
139
I/O
ROM / SRAM / flash address bus bit [11]
R_A10
140
O
ROM / SRAM / flash address bus bit [10]
© Sunplus Confidential
Contents are subject to change without Notice
I/O
ROM / SRAM / flash address bus bit [13]
16
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
M_DQM3/GPIO
Pin No.
I/O
141
I/O
Description
SDRAM data input/output mask for M_DD[31:24] , or GPIO[38]
Priority selection
sft_cfg0[5]=1’b1
Function
SDRAM data
dir
O
input/output mask for
M_DD[31:24]
(default)
sft_cfg2[3:2]=2’b11
UA0_RXD
I
sft_cfg1[8:6]=3’b011
R_CSALL_B
O
sft_cfg3[13:12]=2’b10
TV_HSYNC
I/O
sft_cfg4[15:13]=3’b010
TV_HSYNC_PC
O
sft_cfg7[7:6]=2’b01
PCMCIA_IOW_B
O
sft_cfg0[13:12]=2’b01
TV_LCD_G[2]
O
sft_cfg7[1]= 1’b0,
FM_GPIOB[19]
I/O
sft_cfg8[8]=1’b1
ADC_MONO_D_L[5]
O
sft_cfg8[9]=1’b1
DAC_OPA[1]
I
sft_cfg8[10]=1’b1
OGT_BIST_FAIL
O
(other)
GPIO[38]
I/O
sft_cfg0[11]= 1’b 0,
fm_gpio_len[3:0]>9
M_DQM2/GPIO
142
I/O
SDRAM data input/output mask for M_DD[23:16] , or GPIO[39]
Priority selection
sft_cfg0[4]=1’b1
Function
SDRAM data
dir
O
input/output mask for
M_DD[23:16]
(default)
sft_cfg2[3:2]=2’b11
UA0_TXD
O
sft_cfg3[13:12]=2’b10
TV_VSYNC
I/O
sft_cfg4[15:13]=3’b010
TV_VSYNC_PC
O
sft_cfg7[7:6]=2’b01
PCMCIA_IOR_B
O
sft_cfg0[13:12]=2’b01
TV_LCD_G[3]
O
sft_cfg7[1]= 1’b 0,
FM_GPIOB[18]
I/O
sft_cfg8[8]=1’b1
ADC_MONO_D_L[6]
O
sft_cfg8[9]=1’b1
DAC_OPA[2]
I
BUF_CTRL_BIST_FAI
O
sft_cfg0[11]= 1’b 0,
fm_gpio_len[3:0]>9
sft_cfg8[10]=1’b1
L
(other)
GPIO[39]
VDD_K4
143
S
R_OE_B
144
I/O
ROM / SRAM / flash output enable
R_D7
145
I/O
ROM / SRAM / flash data bus bit [7]
R_D6
146
I/O
ROM / SRAM / flash data bus bit [6]
R_D5
147
I/O
ROM / SRAM / flash data bus bit [5]
R_D4
148
I/O
ROM / SRAM / flash data bus bit [4]
R_D3
149
I/O
ROM / SRAM / flash data bus bit [3]
VSS_O5/ VSS_K5
150
S
© Sunplus Confidential
Contents are subject to change without Notice
I/O
Kernel logic power supply #4
Kernel logic / I/O power shared ground supply #5
17
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
Pin No.
I/O
Description
R_D2
151
I/O
ROM / SRAM / flash data bus bit [2]
R_D1
152
I/O
ROM / SRAM / flash data bus bit [1]
R_D0
153
I/O
ROM / SRAM / flash data bus bit [0]
R_A0
154
O
ROM / SRAM / flash address bus bit [0]
R_A1
155
O
ROM / SRAM / flash address bus bit [1]
R_A2
156
O
ROM / SRAM / flash address bus bit [2]
R_A3
157
O
ROM / SRAM / flash address bus bit [3]
R_A4
158
O
ROM / SRAM / flash address bus bit [4]
R_A5
159
O
ROM / SRAM / flash address bus bit [5]
R_A6
160
O
ROM / SRAM / flash address bus bit [6]
R_A7
161
O
ROM / SRAM / flash address bus bit [7]
R_A12
162
I/O
ROM / SRAM / flash address bus bit [12]
R_A15
163
I/O
ROM / SRAM / flash address bus bit [15]
DAC_VREF
164
A
Audio DAC reference voltage, connect a 0.1uF to ground
DAC_L
165
A
Audio DAC left-channel output
DAC_R
166
A
Audio DAC right-channel output
DAC_VDD
167
S
3.3v power supply for on-chip audio DAC
DAC_VSS
168
S
Ground pin for on-chip audio DAC
R_A16
169
I/O
ROM / SRAM / flash address bus bit [16]
R_A18
170
I/O
ROM / SRAM / flash address bus bit [18]
A_IEC_TX/GPIO
171
I/O
IEC-958 transmit data
Priority selection
sft_cfg3[8]=1’b1
A_DATA[0] / GPIO
172
I/O
173
S
A_DATA[1] / GPIO
174
I/O
© Sunplus Confidential
O
ADC_MONO_C[0]
I
sft_cfg8[9]=1’b1
DAC_OPF[0]
I
(other)
GPIO[52]
I/O
Serial audio data output for channel 1/0 or GPIO
Function
Dir
sft_cfg3[1]=1’b1
A_DATA[0] (default)
O
sft_cfg8[8]=1’b1
ADC_MONO_C[1]
I
sft_cfg8[9]=1’b1
DAC_OPF[1]
I
(other)
GPIO[53]
I/O
I/O power supply #5
Serial audio data output for channel 3/2 or GPIO
Priority selection
Contents are subject to change without Notice
Dir
sft_cfg8[8]=1’b1
Priority selection
VDD_O5
Function
A_IEC_TX (default)
Function
Dir
sft_cfg3[2]=1’b1
A_DATA[1] (default)
O
sft_cfg8[8]=1’b1
ADC_MONO_C[2]
I
sft_cfg8[9]=1’b1
DAC_OPF[2]
I
(other)
GPIO[54]
18
I/O
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
A_DATA[2] / GPIO
Pin No.
I/O
175
I/O
Description
Serial audio data output for channel 5/4 or GPIO
Priority selection
A_DATA[3] / GPIO
176
I/O
Function
A_DATA[2] (default)
O
sft_cfg8[8]=1’b1
ADC_MONO_PWAD
I
sft_cfg8[9]=1’b1
DAC_PDALL
(other)
GPIO[55]
177
I/O
Function
178
S
A_BCK/GPIO
179
I/O
Dir
sft_cfg3[4]=1’b1
A_DATA[3] (default)
O
sft_cfg8[8]=1’b1
ADC_MONO_SPGA
I
sft_cfg8[9]=1’b1
DAC_TEST
I
(other)
GPIO[56]
I/O
PCM data output L/R strobe
Priority selection
VSS_O6/ VSS_K6
I
I/O
Serial audio data output for channel 7/6 or GPIO
Priority selection
A_LRCK/GPIO
Dir
sft_cfg3[3]=1’b1
Function
dir
sft_cfg3[6]=1’b1
A_LRCK (default)
sft_cfg8[8]=1’b1
ADC_MONO_MODE1
I/O
I
sft_cfg8[9]=1’b1
DAC_UD
I
(other)
GPIO[57]
I/O
Kernel logic / I/O power shared ground supply #6
PCM bit clock
Priority selection
sft_cfg3[0]=1’b1
Function
A_BCK (default)
sft_cfg8[8]=1’b1
ADC_MONO_MODE1
Dir
I/O
I
_1
A_XCK/GPIO
180
I/O
sft_cfg8[9]=1’b1
DAC_BGPD
(other)
GPIO[58]
Audio over-sampling clock
Priority selection
UA0_RX/GPIO
181
I/O
© Sunplus Confidential
Function
Dir
sft_cfg3[9]=1’b1
A_XCK (default)
sft_cfg8[8]=1’b1
ADC_MONO_MODE2
I
sft_cfg8[9]=1’b1
DAC_CLK
I
(other)
GPIO[59]
I/O
I/O
UART #0 data receive or GPIO
Priority selection
Contents are subject to change without Notice
I
I/O
Function
Dir
sft_cfg2[3:2] =2’b01
UART0_RX (default)
sft_cfg3[13:12]=2’b01
TV_HSYNC
sft_cfg4[15:13]=3’b011
HSYNC_PC
O
(other)
GPIO[60]
I/O
19
I
I/O
MAY. 19, 2005
Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
UA0_TX/GPIO
Pin No.
I/O
182
I/O
Description
UART #0 data transmit or GPIO
Priority selection
V_COMP
183
A
Function
Dir
sft_cfg2[3:2] =2’b01
UART0_TX (default)
O
sft_cfg3[13:12]=2’b01
TV_VSYNC
I/O
sft_cfg4[15:13]=3’b011
VSYNC_PC
O
(other)
GPIO[61]
I/O
(VDAC CBU) Compensation pin. Connect a 0.1pF ceramic capacitor to bypass this pin to
VSSA. The lead length must be kept as short as possible to avoid noise.
V_BIAS
184
(VDAC CBL) Bias voltage. Connect a 0.1pF ceramic capacitor to bypass this pin to VSSA.
The lead length must be kept as short as possible to avoid noise.
V_FSADJ
185
A
Full-Scale adjustment control pin. The full-scale current of D/A converters can be adjusted
by connecting a resistor (RSET) between this pin and ground.
V_REFOUT
186
A
(VDAC VREF/bandgap output) Voltage reference output. It generates typical 1.2V voltage
V_DAC[0]
187
A
Video DAC output #0. This is a high-impedance current source output. These outputs can
reference and may be used to drive V_REFIN pin directly.
drive a 37.5 load directly.
VDD_TVA0
188
S
TV DAC power supply #0
VSS_TVA0
189
S
TV DAC ground pin #0
VDD_TVA1
190
S
TV DAC power supply #1
VSS_TVA1
191
S
TV DAC ground pin #1
V_DAC[3]
192
A
Video DAC output #3. This is a high-impedance current source output. These outputs can
V_DAC[4]
193
A
Video DAC output #4. This is a high-impedance current source output. These outputs can
drive a 37.5  load directly.
drive a 37.5 load directly.
VDD_TVA2
194
S
TV DAC power supply #2
V_DAC[5]
195
A
Video DAC output #5. This is a high-impedance current source output. These outputs can
drive a 37.5 load directly.
VSS_TVA2
196
S
TV DAC ground pin #2
PLL_AVDD
197
S
Servo PLL 3.3V power
LPFO
198
A
NC pin
NC pin
LPFN
199
A
VREFO
200
A
PDFLT
201
A
FDFLT
202
A
LPFNIN
203
A
LGIN
204
A
PLL_DS_AVSS
205
S
RFI
206
A
CNIN
207
A
Servo PLL/Data-slicer ground
SLVL
208
A
DS_AVDD
209
S
Servo Data slicer 3.3V power
RF_AVDD
210
S
Servo RF 3.3V power
GMRES
211
A
External reference resistor input.
AGCCAP
212
A
External AGC capacitor connected to ground.
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol
Pin No.
I/O
Description
RFRP
213
O
RFRP signal output.
RFO
214
O
RF signal output.
FLTIP
215
I
Differential RF equalizer input #P
FLTIN
216
I
Differential RF equalizer input #N
Note: Please reference SPHE802D servo datasheet for servo related information.
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
5.FUNCTIONAL DESCRIPTIONS
Module-level stop-operation:
SPHE8281D is a highly integrated system-on-chip DVD player
SoC design. It includes DVD/CD front-end RF, read-channel, data
SPHE8281D provides a function to turn off specific module
decoder, servo controller, host controller, MPEG1/2 video decoder,
from operating. Without explicit wake-up, the hardware module
programmable audio decoder, programmable peripheral controller,
will remain static and consume little power.
System-level doze:
audio DAC and multi-format TV-encoder on a single chip.
For maximum power-saving, firmware could fine-tune system
5.1. PLL and ClockGen
performance according to system task.
SPHE8281D contains multiple PLLs to generate system clock and
audio reference clocks.
5.3. Embedded 32-bit RISC Controller
All the PLLs reference a single external
27MHz clock or crystal to generate the required clocks. System
SPHE8281D includes a powerful 32-bit RISC processor as the
clock is then derived from division of the system PLL output.
host controller. This host controller is utilized to manage servo
control, decoding tasks as well as UI tasks. It can access to all the
memory and devices, cooperate between processor systems.
Audio decoder and I/O processor handshake with RISC processor
CLKI
27MHz
PLLv
Fractional multiples
of CLKI
Optional video clock in
SYSCLK_GEN
/2, /4 ~ /65536
VIDCLK_GEN
through the mailbox registers.
SYSCLK
VIDCLK
mailbox
(16x16)
Audio
decoder
mailbox
(16x8)
I/O processor
RISC
controller
PLLa supports two center frequencies (for both 48kHz family and
44.1kHz family) and generates required audio clocks from the
audio system clock.
Figure 5-1 Communication between processors
The RISC processor is equipped with instruction and data caches.
CLKI
27MHz
PLLa #1
147.456MHz
135.4752MHz
These caches can accelerate accesses to the SDRAM or ROM
XCK
AUDCLK
GEN
cacheable regions.
ADCLK
IECCLK
CD_CLK
RISC32
core
SMMU
PLLa #2
BIU
D-CACHE
5.2. Power Control
Processor Local Bus
I-CACHE
Peripheral
Control bus
Other
modules
ROM/Flash
interface
ROM
FLASH
SRAM
System bus
Interface
SPHE8281D provides various levels of power-control mechanism
Memory
Interface
D-RAM
in order to achieve minimum power consumption.
DMA
Automatic power-save:
Most hardware modules are automatically power-saved when
Figure 5-2 RISC subsystem
not operating.
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Table: RISC processor local memory configuration
Memory
Table: Device interrupt controller sources
Specification
Symbol
Description
I-Cache
8kbyte (2-way set associated)
INT_WDOG
Watchdog interrupt (if reset disabled)
D-Cache
4kbyte (direct-mapped)
INT_VSYNC
Interrupt when enter vertical resync
D-RAM/DMA
1kbyte scratch buffer
INT_FLD_ACT
Interrupt when enter active region
INT_FLD_SYNC
Interrupt when leave active region
SDRAM, ROM and other devices are mapped to RISC memory
INT_HOST
Host device interrupt
spaces as in the following table:
INT_TIMER0
Timer 0 interrupt
INT_TIMER1
Timer 1 interrupt
INT_TIMER2A
Timer 2 scale interrupt
INT_TIMER2B
Timer 2 count interrupt
Timer 3 scale interrupt
Table: RISC memory mapping
Memory Range
Description
8000_0000~87ff_ffff
SDRAM (cached)
INT_TIMER3A
a000_0000~a7ff_ffff
SDRAM (uncached)
INT_TIMER3B
Timer 3 count interrupt
8800_0000~8fff_ffff
ROM/FLASH/SRAM (cached)
INT_TIMERW
Watchdog timer interrupt
a800_0000~afff_ffff
ROM/FLASH/SRAM (uncached)
INT_UART0
UART0 interrupt
bffe_8000~bffe_ffff
Peripheral control registers
INT_VDP0
Video decoder interrupt
bfff_0000~bfff_03ff
DMA buffer
INT_DSP
DSP interrupt
INT_EXT0
External interrupt #0
SPHE8281D includes following dedicated RISC peripherals to
INT_EXT1
External interrupt #1
assist the system tasks:
INT_EXT2
External interrupt #2
Device interrupt controller:
INT_EXT3
External interrupt #3
Device interrupt controller takes care of interrupt sources from
INT_IOP
IOP interrupt
on-chip devices and off chip sources. For each interrupt source
INT_AUD
Audio hardware interrupt
the firmware is able to configure the interrupt behavior between
edge-trigger and level-sensitive mode.
5.4. ROM/Flash/SRAM Controller
Watchdog:
The SPHE8281D provides flexible connections to external ROM,
Watchdog keeps monitoring RISC behavior and whenever
Flash or SRAM (RFS). It can support up to 4 external RFS devices
firmware is in a deadlock or ill-behaved, the watchdog would
by using different chip-selects (R_CS_B[3:0]). The firmware can
trigger system-wise reset and keep the application functioning
configure RFS memory anchor registers and map these devices
continuously.
into locations of RISC memory space.
Timers
can be in flash mode or in ISA mode.
There are 4-channel timers and 2 cascade counters for timed
the controller will reference external IO_CHRDY input.
to synchronize audio and video playback timing.
Device
interrupt
controller
peripheral control bus
to RISC interrupt
RISC
monitor
monitor
interrupt
Watchdog
watchdog
reset
Timers
timer
interrupt
In FLASH mode the
access timing is decided by wait-state setting, while in ISA mode
tasks. During A/V decoding, system time counters are utilized
RISC
subsystem
For each memory space it
Prefetch
buffer
Processor
local bus
Address
translator
External
ROM
interface
Address
sequencer
Wait state
generation
Figure 5-4 ROM/FLASH/SRAM controller
Figure 5-3 RISC dedicated hardware
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Advanced video decoding and display control mechanism is
ROM/Flash mode
included to prevent tearing effect.
CSB
wait
wait
ADDR[]
Address (read)
Address (write)
OEB
oe_setup
RISC
controller
oe_hold
WEB
we_setup
DATA[]
Data (read)
DATA (for write)
input
FIFO
Output
FIFO
Figure 5-5 ROM/FLASH/SRAM mode timing
Variable
length
decoder
Inverse
quantization
Motion
compensation
Inverse DCT
Memory
Interface
ISA MODE
wait
ADDR[]
OEB
Q matrix
we_hold
data is sampled at this point
CSB
Decoding
control
iochrdy_hold
wait
Address (read)
oe_setup
input
buffer
iochrdy_hold
Address (write)
output
buffer
oe_hold
WEB
we_setup
we_hold
IO_RDY
DATA[]
Data (read)
display
information
DATA (for write)
DCT
buffer
Decoding
control
data is sampled at this point
Figure 5-8 Architecture of video decoding pipeline
Figure 5-6 ISA mode timing
5.7. Video Post Processing
5.5. CSS Decryption Hardware
SPHE8281D includes powerful video-post-processing facilities to
(Optional) SPHE8281D has built-in CSS decryption hardware
provide high video quality. It perform following functions:
DMA support.
YUV411, YUV420, YUV422 and 8-bit indexed color
SIF to CCIR601 interpolation
5.6. MPEG Video Decoder
MPEG1 CIF filter
The system incorporates a powerful MPEG video decoding
MPEG1/2 chroma vertical interpolation
datapath and provides real-time video decoding of MPEGI/II
Up to 1/2x horizontal decimation
bitstream.
Up to 1/512x vertical decimation
The video decoder is a hardwired MPEG1/2 decoding datapath.
Powerful de-interlacing hardware
Up to 1024x horizontal and vertical expansion
The system architecture is as in the figure. RISC controller is in
Pan and scan function
charge of pre-process and buffering source into SDRAM buffers.
De-flicker during interlaced display
Upon correct timing video decoder will start to decode the
Video contrast/bright/color enhancement
bitstream and write back reconstructed video frame for playback.
During runtime video post-processing hardware will fetch video
sources from framebuffer and process the data as in the following
figure.
line
buffer
Reconstructed
Reference
Video
Decoder
Bitstream in
data-in
Control bus
de-muxed data
RISC
subsystem
Deinterlace
input
buffer
Vertical
filtering and
chroma
resample
CIF and
horizontal
expansion
display
interface
Memory
interface
Memory Interface
de-interlace
buffer
Figure 5-7 Interface between RISC and Video decoder
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
5.8. Programmable Audio Decoder
SPHE8281D support following audio DAC format combinations:
The SPHE8281D contains a high-performance 24-bit audio DSP
32k
44.1k
48k
64k
88.2k
96k
192k
optimized for embedded system applications. This audio DSP
256fs
Ok
Ok
Ok
Ok
Ok
Ok
Ok
processor can fetch operands from two memories and perform
384fs
Ok
Ok
Ok
Ok
Ok
Ok
Ok
multiplication-and-accumulation (MAC) in one cycle.
During
execution the DSP fetches instruction from main-memory or IROM,
Data alignment
at the same time the ICACHE will store the LRU instructions.
Data are loaded from and to main-memory by the cycle-stealing
DMA channels.
The DSP works closely with RISC processors by using mailbox
Left adjust, I2S, normal format
LRCK frame width
16b, 24b, 32b, 64b
Data bits
16b, 18b, 20b, 24b
Data sign extension
Zero-extended, sign-extended
5.10. Audio DAC
registers or shared-memory protocol. When downloaded with
different firmware the DSP could support multi-standard audio and
SPHE8281D includes a 2-channel 24-bit audio quality DAC for a
act as an accelerator for RISC in some case.
minimum DVD system.
IROM
5.11. I/O Processor
Inst.
Cache
The SPHE8281D includes an 8-bit micro-controller to help host
controller handling I/O jobs. IR, VFD and other slow devices can
Data
ROM
Audio
Core
be interfaced using this I/O processor.
Data
RAM
Memory
interface
BIU
5.12. SDRAM Controller
SDRAM controller in SPHE8281D is designed to meet both
flexible and powerful requirements. It can be programmed to use
Data
ROM
Data
RAM
1Mx16 and 4Mx16 SDRAM chips. For different grade of memory
chips it can support flexible timing select to meet different SDRAM
audio interface
controller
timing requirements while achieving maximum performance.
Audio
Hardware
The
actual speed of SDRAM interface depends on the system
configuration.
Figure 5-10 Audio DSP architecture
SPHE8281D supports SDRAM power-down modes to save
dynamic operating power.
5.9. Audio Interface
The audio interface is in charge of servicing DSP and maintaining
5.13. Sub-picture Decoder
all audio-related tasks. It would buffer the audio PCM samples and
For DVD and SVCD sub-picture content SPHE8281D includes an
format them to audio DAC and SPDIF formats. Up to 8 channel of
advanced multi-format sub-picture decoder. It supports real-time
digital audio are supported in I2S or normal mode.
vertical expansion for PAL/NTSC translation or special effect.
Buffer
control
Memory
Interface
5.14. On Screen Display
IEC958
IEC-958 input
The on screen display (OSD) function of the SPHE8281D provides
digital input
interface
digital audio input
an overlay bitmap graphics on the final TV display. Applications
ADC ctrl
ADC
can use this function to display specific information over the video
analog in
Audio
Work buffer
display plane without operating on the video source.
The SPHE8281D can display multiple OSD regions on a single
PCM
playback
digital audio output
display frame, where every OSD regions can be in different size,
IEC958
IEC-958 output
location and color format. The OSD hardware supports 4, 16,
256 indexed color or 16-bit direct color.
Figure 5-11 Audio Interface architecture
OSD regions are stored
in main memory before display. During display, OSD decoder
would read these header and data and interpret to be a graphic
data that overlay with video to be output to the display interface.
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Preliminary
SPHE8281D/Dx
5.15. Display Interface
5.16. Video DAC
The display interface of SPHE8281D mixes the video content
SPHE8281D integrates 4-channel 10-bit high-speed current
generated from video-post-processing, sub-picture-decoder and
source DACs operating from 27MHz to 108MHz. These DAC
on-screen-display modules. It also performs content cropping,
outputs can drive a 37.5-Ohm load directly. Half current, quarter
underflow and overflow correction and overall hue / brightness /
current modes are provided for low power operation using external
contrast adjustment.
current amplifiers.
Video
active?
5.17. GPIO
Sub-picture
blend-factor
Background
color
can serve as general-purpose input-output (GPIO) control function.
OSD
blend-factor
MUX
Video
framebuffer
In SPHE8281D almost every pin that related to selectable features
When a pin is programmed to this mode, the RISC controller or
the I/O processor can take full control over the direction and
output level by simple firmware programming.
MIX
Sub-picture
source data
MIX
TV data
output
5.18. UART
OSD
bitmap data
SPHE8281D provide one UART channel for debugging, firmware
upgrading and other user applications. This UART can support
standard serial port baud-rate and formats. It also supports auto
Figure 5-12 Display pipeline
baud-rate detection and hardware flow control (CTS/RTS pair).
The video enhancement process is show in following figure:
OSD
source
OSD
sub-picture
Video
source
Video
post processing
video source
enhancement and bright/
contrast/color control
Display
interface
analog
video
TV encoder
digital
output
DAC gain, linearity
adjustment
Figure 5-13 Display pipeline
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
6.ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pin relative to Vss
Value
Unit
VIN
-0.3 to 5.5
V
Voltage on VDDIO supply relative to VSS
VDDIO
-0.3 to 3.45
V
Voltage on VDDK supply relative to VSS
VDDK
-0.3 to 1.90
V
TSTG
-55 to 150
C
TSOLDER
240 (for 5 Sec. Max.)
C
IOS
50
mA
Storage Temperature
Soldering Temp. (Max. Time)
Short circuit current
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of this device at
these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
6.2. DC Operating Conditions
Recommended Operating Conditions (Voltage referenced to VSS=0V, TA=-0 to 70C)
Parameter
Symbol
Min.
Typ.
Max.
Units
Voltage on VDDK supply relative to VSS
VDDK
1.70
1.80
1.90
V
Voltage on VDDIO supply relative to VSS
VDDIO
3.15
3.30
3.45
V
VIH
2.0
-
5.5
V
Input logic low voltage
VIL
-0.3
-
0.8
V
Output logic high voltage
VOH
2.4
-
-
V
Output logic low voltage
VOL
-
-
0.4
V
IL
-10
-
10
uA
Symbol
Min.
Typ.
Max.
Units
Input pin capacitance
CIN
-
3.5
-
pF
Input pin capacitance
COUT
-
3.5
-
pF
Bidirectional pin capacitance
CBIDIR
-
3.5
-
pF
Input logic high voltage
Input leakage current
6.3. Capacitance
(VDDIO=3.3V, TA=24C, f=108MHz, VREF =1.4V+-200mV)
Parameter
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
6.4. AC Characteristics
6.4.1. SDRAM interface timing diagrams
tCH
0
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
CKE
tCC
tRAS
tRC
CS
tRP
tSH
RAS
tCCD
tRCD
tSS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
RAa
A10/AP
RBb
RAc
*Note 1
tRRD
tCDL
DQ CL=2
CAa0
CAa1
CAa2
CAa3
CAa0
CAa1
CAa2
DBb0
DBb1
DBb2
DBb3
DBb0
DBb1
DBb2
DBb3
CAc0
CAc1
CAc2
CAc0
CAc1
tSAC
CL=3
CAa3
tSLZ
DH
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Precharge
(A-Bank)
0
1
2
3
4
5
6
7
Read
(A-Bank)
Row Active
(A-Bank)
8
9
10
11
12
13
14
15
16
: Don't care
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
tBDL
DQ
DAa0
DAa1
DAa2
DAa3
tRDL
DAb0
DAa4
DAb1
DAb2
DAb3
DAb4
DAb5
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
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(A-Bank)
Burat Stop
28
Precharge
(A-Bank)
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Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
(Recommended condition for DVD playback is listed in typical condition with f=121.5MHz)
Parameter
Symbol
Min.
Typ.
Max.
Units
Row active to row active delay
tRRD
1
2
4 *1
System clock cycle
RAS to CAS delay
tRCD
1
2
4 *1
System clock cycle
Row precharge time
tRP
1
2
4 *1
System clock cycle
Row active time
tRAS
1
5
8 *1
System clock cycle
Row cycle time
tRC
1
8
32 *1
System clock cycle
Last data in to new column address delay
tCDL
1
1
4 *1
System clock cycle
Column address to column address delay
tCCD
1
1
1
System clock cycle
CLK cycle time *2
tCC
6
8.2
1000
ns
CLK to valid SDRAM output delay *2
tSAC
-
6.0
6.5
ns
SDRAM output data hold time *2
tOH
1
2
-
ns
CLK high pulse width *3
tCH
-
3
-
ns
CLK low pulse width *3
tCL
-
3
-
ns
CLK to SDRAM output Low-Z
tSLZ
-
1.0
(tCC)
ns
CLK to SDRAM output High-Z
tSHZ
-
6.0
(tSAC)
ns
Note: 1.Using maximum values may limit system performance.
2.Width of data window can be estimated from (tCC-tSAC+tOH).
3.Width of clock pulse depends on system clock cycle.
6.4.2. ROM / flash interface timing diagrams
ROM Compatible Mode
CSB
tACCESS
tACCESS
ADDR[]
Address (read)
Address (write)
OEB
tWES
WEB
tDS
DATA[]
tWEH
tDH
Data (read)
DATA (for write)
Figure 6-1 ROM / flash interface ROM mode access timing
Parameter
Symbol
Min.
Typ.
Max.
tACCESS
2
8 *1
31
Data setup time for read
tDS
5
-
-
ns
Data hold time for read
tDH
0
-
-
ns
Address/data setup time before write strobe
tWS
0
1
31
System clock cycle
Address/data setup time after write strobe
tWH
0
1
31
System clock cycle
ROM / SRAM / flash access time
Units
System clock cycle
Note: Recommended value when f=121.5MHz
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SPHE8281D/Dx
ISA Compatible Mode
CSB
tACCESS
ADDR[]
tACCESS
Address (read)
Address (write)
OEB
tWES
WEB
tWAIT
tOH
tWEH
tWAIT
tIH
tOH
tIH
IO_RDY
DATA[]
Data (read)
Data (write)
Figure 6-2 ROM / flash interface ISA mode access timing
Symbol
Min.
Typ.
Max.
ISA access time *1
Parameter
tACCESS
2
-
31
Units
IO_RDY wait time
tWAIT
0
-
1000
Output hold time
tOH
1
-
-
System clock cycle
Input hold time
tIH
0
-
-
ns
Address/data setup time before write strobe
tWS
0
1
31
System clock cycle
Address/data setup time after write strobe
tWH
0
1
31
System clock cycle
System clock cycle
ns
Note: After this period of time IO_RDY_B must be stable and indicates correct status of target device.
6.4.3. Audio interface timing diagrams
Some audio interface configuration timing diagrams are shown below.
0
1
22
23
0
1
2
22
23
BCK
LRCK
left channel
AUDATA[]
23
22
21
2
right channel
1
0
MSB
23
22
21
2
1
0
LSB MSB
LSB
Figure 6-3 Normal mode / 24bit data / 24bit frame / MSB first
0
1
8
9
30
31
0
1
30
31
1
0
0
BCK
LRCK
left channel
AUDATA[]
23
22
right channel
21
2
1
MSB
0
2
LSB
Figure 6-4 Right justified (normal) mode / 24bit data / 32bit frame / MSB first
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SPHE8281D/Dx
0
1
2
22
23
24
31
0
1
2
31
0
BCK
LRCK
left channel
AUDATA[]
23
22
21
right channel
1
MSB
0
23
22
21
LSB
Figure 6-5 Left justified mode / 24bit data / 32bit frame / MSB first
0
1
2
3
23
24
25
31
0
1
2
3
31
0
0
1
BCK
LRCK
D
left channel
AUDATA[]
23
22
21
D
2
1
right channel
0
MSB
23
22
LSB
2
Figure 6-6 I S mode / 24bit data / 32bit frame
0
1
2
22
23
0
1
2
22
23
2
1
BCK
LRCK
left channel
D
AUDATA[]
23
22
21
D
2
1
right channel
0
MSB
23
22
21
0
LSB MSB
LSB
2
Figure 6-7 I S mode / 24bit data / 24bit frame
Parameter
Symbol
Min.
Typ.
Max.
Units
BCK rising to LRCK / AUDATA transition
tS
-
0.5
-
System clock cycle
6.4.4. Video timing diagrams
Interlaced Modes
SP active period
SP active period
active line period
V blanking period (21)
active line period
Video line number
522 523 524 525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0
2
4
6
8
10
12
SP line number
473 475 477 479
Video line number
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291
SP line number
474 476 478
active line period
1
V blanking period (21)
SP active period
3
5
7
9
11
active line period
SP active period
Figure 6-8 NTSC (480i) timing diagram
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Preliminary
SPHE8281D/Dx
SP active period
SP active period
active line period
V blanking period (23.5)
active line period
Video line number
619 620 621 622 623 624 625
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
0
2
4
6
8
SP line number
567 569 571 573
Video line number
307 308 309 310 311 312 313 314 315 316
317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340
SP line number
474 476 478
1
active line period
V blanking period (24)
3
5
7
9
active line period
SP active period
SP active period
Figure 6-9 PAL (576i) timing diagram
Progressive Modes
SP active period
SP active period
active line period
521 522 523 524 525
active line period
1
2
3
4
5
6
7
8
9
10
11
12
13
14
44
476 477 478 479
45
46
47
48
49
50
51
0
1
2
3
4
5
6
Figure 6-10 NTSC (480p) timing diagram
SP active period
SP active period
active line period
617 618 619 620 621 622 623 624 625
active line period
1
2
3
4
5
6
7
8
9
572 573 574 575
43
44
45
46
47
48
49
50
51
0
1
2
3
4
5
6
Figure 6-11 PAL (576p) timing diagram
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Preliminary
SPHE8281D/Dx
7.PACKAGE/PAD LOCATION
7.1. Outline Dimensions
D
D1
D2
e
b
SUNPLUS
SPHE8281D
E E1 E2
YYWW
A2 A
c
L1
Symbol
A1
Min.
Nom.
Max.
A
-
-
1.60
A1
0.05
-
0.15
A2
1.35
1.40
1.45
D
26.00 BSC.
26.00 BSC.
26.00 BSC.
D1
24.00 BSC.
24.00 BSC.
24.00 BSC.
E
26.00 BSC.
26.00 BSC.
26.00 BSC.
E1
24.00 BSC.
24.00 BSC.
24.00 BSC.
R2
0.08
-
0.20
R1
0.08
-
-
θ
0O
3.5 O
7O
θ1
0O
-
-
θ2
11
θ3
c
O
O
13 O
11 O
12 O
13 O
0.09
-
0.20
12
L
0.45
0.60
0.75
L1
1.00 REF
1.00 REF
1.00 REF
S
0.20
-
-
Unit: Millimeter
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Preliminary
SPHE8281D/Dx
8.DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, expressed, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication
are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving
unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not
recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this
document are for reference purposes only.
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Preliminary
SPHE8281D/Dx
9.REVISION HISTORY
Date
Revision #
MAY. 19, 2005
0.1
Description
Original
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Contents are subject to change without Notice
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35
35
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Preliminary Version: 0.1