SPL31A Table of Contents PAGE 1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3. FEATURES.................................................................................................................................................................................................. 3 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5 5.1. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 5 5.2. ROM AREA ........................................................................................................................................................................................... 5 5.3. OPERATING STATES ............................................................................................................................................................................... 5 5.4. TIME-BASE-SETTING REGISTER ............................................................................................................................................................. 5 5.5. TIMER/COUNTER ................................................................................................................................................................................... 6 5.6. SPEECH AND MELODY ............................................................................................................................................................................ 6 5.7. LCD CONTROLLER/DRIVER .................................................................................................................................................................... 6 5.8. VOLTAGE DOUBLER/REGULATOR ............................................................................................................................................................ 6 5.9. PWM OUTPUT....................................................................................................................................................................................... 6 5.10. LOW VOLTAGE RESET ......................................................................................................................................................................... 6 5.11. WATCHDOG TIMER (WDT)................................................................................................................................................................... 7 5.12. LOW VOLTAGE DETECT ....................................................................................................................................................................... 7 5.13. MASK OPTIONS ................................................................................................................................................................................... 7 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 8 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 8 6.2. DC CHARACTERISTICS (VDD = 3.0V, TA = 25℃) ................................................................................................................................... 8 6.3. DC CHARACTERISTICS (VDD = 4.5V, TA = 25℃) ................................................................................................................................... 8 6.4. THE RELATIONSHIPS BETWEEN THE ROSC AND THE FCPU ........................................................................................................................... 9 6.5. THE RELATIONSHIPS BETWEEN THE FCPU AND THE IOP .............................................................................................................................. 9 6.6. THE RELATIONSHIPS BETWEEN THE FCPU AND THE VDD........................................................................................................................... 9 7. APPLICATION CIRCUITS......................................................................................................................................................................... 10 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 11 8.1. PAD ASSIGNMENT ................................................................................................................................................................................11 8.2. ORDERING INFORMATION ......................................................................................................................................................................11 8.3. PAD LOCATIONS .................................................................................................................................................................................. 12 9. DISCLAIMER............................................................................................................................................................................................. 13 10. REVISION HISTORY ................................................................................................................................................................................. 14 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 AUG. 10, 2001 Version: 1.2 SPL31A 64KB LCD CONTROLLER/DRIVER 1. GENERAL DESCRIPTION 3. FEATURES The SPL31A, an 8-bit CMOS single chip microprocessor, contains ! Built-in 8-bit CPU RAM, ROM, I/Os, interrupt/wakeup controller, timer, 8-bit PWM ― 160 bytes SRAM audio output and automatic display controller/ driver for LCD. ― 64K bytes ROM With a dual channel PWM driver, attractive sound effects can be ― Max. CPU clock: 3.0MHz @ 2.4V - 5.5V generated easily. ― Programmable CPU clock frequency, 1/2, 1/4, 1/8, 1/16, Built-in voltage doubler and voltage regulator 1/32 or 1/64 of R-oscillator’s clock frequency is available provide robust and adjustable (16-level) LCD supply voltage to get the best display quality for specific panels. ― Provides 7 interrupt sources Furthermore, a software controllable standby mode is also implemented for power ! Built-in 8-bit 2-channel PWM outputs saving. The SPL31A is designed with state-of-the-art technology ! Built-in 32.768KHz Crystal / R-oscillator to fulfill the requirements of LCD applications especially for ― Crystal or R-oscillator (mask option) hand-held products. ― Crystal oscillator switches from strong to Weak mode automatically ― Internal time base generator 2. BLOCK DIAGRAM ROSC ! Built-in System R-oscillator ― Only one resistor is needed 32.768KHz ! Two 16 bits timer/counters ! Low Voltage Reset / Low Voltage Detect 32.768KHz Oscillator & Time Base Low Voltage Reset 160 bytes RAM ― 2.4V/2.6V low voltage detect (Mask option) ! Low power consumption AUDN Two 16-bit Auto Reload Timers 8-bit RISC Processor LCD RAM 44 Segments X 5 Commons LCD Driver ― Operating current: 1.0mA/1.0MHz @ 3.0V IOCD3 - 0 (I/O) ― Very low standby current : ISTBY < 1.0µA @ 3.0V In standby mode: stop all oscillators 9 I/O ports 64K bytes ROM ― Provides 2.3V low voltage reset function AUDP PWM Interrup/wakeup Control ! Max. 12 general purpose I/O ― SEG[43:41] can be optioned to IOEF[7:5] ― 8 IO pins support Key wake-up mode IOEF4 - 0 (I/O) ! LCD controller / driver ― 44 segments x 5 commons, max. 220 dots COM4 - 0 ― Programmable bias option (1/2,1/3 bias) and duty option SEG43 - 0 (1/2,1/3,1/4,1/5 duty) ― Built-in voltage doubler and regulator to generate VLCD voltage for LCD driver ― Adjustable 16-level VLCD for various panels 1/3 bias: VLCD (3.0V - 6.0V) 1/2 bias: VLCD (2.0V - 4.0V) © Sunplus Technology Co., Ltd. Proprietary & Confidential 3 AUG. 10, 2001 Version: 1.2 SPL31A 4. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description SEG43 - 0 5 - 48 O LCD driver segment output COM4 - 0 49 - 53 O LCD driver common output IOEF1 - 0 74 - 73 I/O I/O port (provide key wake-up function) IOEF4 - 2 3-1 IOCD3 - 0 68 - 65 I/O I/O port ROSC 63 I System R-oscillator input, connect to VDD through resistor RESET 62 I System reset input AVDD 71 P PWM power supply input AUDP 70 O PWM audio output AUDN 72 O PWM audio output AVSS 69 P PWM ground input X32I 61 I 32.768KHz crystal input, or connect to VDD through resistor as R-oscillator input (Mask option) X32O 60 O 32.768KHz crystal output TEST 59 I Test mode input VDD 4 P Power supply voltage input VSS 64 P Ground input VLCD 54 I LCD voltage, connect to VSS through a capacitor VDD1 55 I Connect coupling capacitors for charge pump VDD2 58 CUP1 56 I Charge pump capacitor interconnection pins for LCD voltagegeneration CUP2 57 Note1: Legend: I = Input, O = Output, P = Power Note2: SEG43 - 41 can be optioned to IOEF7 - 5, IOEF7 - 0 provide key wake-up function Note3: Provides 220 bits read/writable LCD RAM buffer Note4: 32.768KHz Crystal oscillator can be optioned to R-oscillator (connect to VDD through resistor). © Sunplus Technology Co., Ltd. Proprietary & Confidential 4 AUG. 10, 2001 Version: 1.2 SPL31A 5. FUNCTIONAL DESCRIPTIONS 5.1. Map of Memory and I/Os *I/O PORT: * MEMORY MAP ― IOCD Port $0004 ― IOEF Port $0005 $0000 state is entered by writing the SLEEP register ($09). I/O & Registers $001F $0020 * I/O CONFIG ― IOCD_Config $0000 ― IOEF_Config $0019 wake-up, 4Hz/8Hz/ 16Hz/32Hz wake-up and 2Hz/1Hz wake-up. If any wake-up event occurs, execution of the next instruction LCD RAM Buffer $003D continues in the operating state. reserved SRAM states. $00FF ― INT1 ( from TIMER 1 ) reserved is in HALT state. Test Program ― INT0 ( from TIMER 0 ) ― T2Hz ( 2Hz /1Hz ) ― 128Hz $7FFA $7FFF remain active in the halt state. Write to SLEEP register, 32768 oscillator OFF Program ROM Bank #1 OPERATING STANDBY po ― T2 Hz ( 2Hz /1Hz ) , ter gis re N P rO EE ato SL ill to osc rite 68 W 327 et es rr se Wake-up or user reset NMI/Reset/IRQ Vector u eak W $FFFA $FFFF ― TIMER 0 Overflow ― T16Hz ( 4Hz /8Hz /16Hz /32Hz ) Following figure is a state diagram for the SPL31A. NMI/Reset/IRQ Vector * WAKEUP SOURCE ― IOEF Port Change CPU clock is halted while it waits for an event The 32768 related modules (timer/counter, LCD driver…) may Program ROM Bank #0 ― 2KHz ― EXTINT ( from IOCD0 pin ) By writing (key press, timer overflow) to generate a wake-up in HALT state. $05FF $0600 ― INT1 ( from TIMER 1 ) ― T16Hz ( 4Hz /8Hz /16Hz /32Hz ) Therefore current consumption is minimized. to SLEEP register but keeps 32768 oscillator running, the system $0200 * INT SOURCE In standby mode, all modules will be shut down, and RAM and I/Os remain in their previous $0060 * NMI SOURCE: There are four wake-up sources in SPL31A: port IOEF wake-up, TIMR0 ru 5.2. ROM Area SPL31A is a ROM based micro-controller with 220 dots LCD driver. HALT The large ROM space can be defined as a program ROM, LCD font and audio data continuously without any limitation. To State Diagram of SPL31A access the higher bank ROM area, user can program the BANK SELECT register ($07) to 1, then fetch the data from address After the chip is awakened from halt/standby state, CPU will $8000 to $FFFF. continue to execute the next instruction. The RAM and I/O status will not be changed by wake-up. 5.3. Operating States The SPL31A provides three operating states: standby, halt, and 5.4. Time-Base-Setting Register operating state. Writing to TIME-SETTING register can program the time source of Following table shows the differences between the three operating states. CPU wake-up and interrupt. For example, the programmer can change 2Hz wake-up and interrupt into 1Hz wake-up and interrupt by writing 80H into $0A. Operating Halt Standby CPU ON OFF OFF 32768 oscillator ON ON OFF Thus, the system will wake up to service every second. LCD driver ON ON/OFF OFF T16Hz (one of counter‘s clock source and wake-up & interrupt) Also, can be one of 4Hz, 8Hz, 16Hz or 32Hz by setting bit0 and bit1 of In operating state, all modules (CPU, timer/counter, LCD driver…) are activated. © Sunplus Technology Co., Ltd. Proprietary & Confidential 32768 TIME-SETTING register ($0A). oscillator, At power on state, the default value of T16Hz is 4Hz and T2Hz is 2Hz. The halt/standby 5 AUG. 10, 2001 Version: 1.2 SPL31A 5.5. Timer/Counter SPL31A contains two 16-bit timer/counters, TM0 and TM1 count continuously. respectively. In the timer mode, TM0 and TM1 are reloadable reset the counter by loading 0 into register $10 and $11 and up-counters. When the timer overflows from $FFFF to $0000, loading 0 into the counter by writing any data to $12. If TM0 is specified as a counter, the user can After the the carry signal will generate the INT signal if the corresponding counter is activated, the counter’s value can also be read from bit is enabled in INT ENABLE register ($0D). above registers ($10 and $11) and the read instruction will not The timer will automatically reload the value assigned by the program and up affect the counter's value or reset it. The clock source of the timer/counter are selected as the following: Timer/Counter Address Clock Source $0010 16-BIT Timer $0011 R-oscillator Output, the CARRY of timer 1 $0012 TM0 16-BIT Counter $0010 Clock source A: IOCD0, R-oscillator Output, VDD, 32768Hz. $0011 Clock source B: IOCD1, VDD, T16Hz, 128Hz. $0012 Note: T16Hz can be one of 4Hz, 8Hz, 16Hz and 32Hz by setting $0A (time-setting register) $0013 TM1 16-BIT Timer $0014 R-oscillator Output, 32768 Hz $0015 Mode Select Register $000B Select TM0 & TM1 configuration 5.6. Speech and Melody 5.8. Voltage Doubler/Regulator Since SPL31A can provide a large ROM size and wide CPU To get the best LCD quality, the LCD supply voltage should not operation speed, it is suitable for speech and melody synthesis. change with the system power. For speech synthesis, this chip can provide INT for precise and adjustable (16-level) LCD supply voltage. sampling frequency. desired VLCD to fit specific LCD panels by changing the output Users can record or synthesize the sound and digitize the data into the ROM. The sound can be played The SPL31A provides a robust reference voltage (program $16). back in the sequence designed by the internal user's program. Users can get The available VLCD voltage range are summarized as the following table: Several algorithms are recommended for high fidelity and good compression of sound: such as PCM and ADPCM. synthesis, SPL31A provides dual tone mode. For melody Once in the dual tone mode, users only need to program the tone frequency of each channel by writing to timer/counter TM0 and TM1, and set the envelope of each channel. Bias Min. VLCD ($16 = 00h) Max. VLCD ($16 = 0Fh) 1/2 bias 2.0V 4.0V 1/3 bias 3.0V 6.0V Note1: If the LCD display is uneven with a large panel load, connect a The hardware will toggle the tone resistor between the VDD1 pin and ground is suggested. Note2: To make sure the chip work properly, the following equation must be wave automatically without users’ care. satisfied. Min. (VLCD) > VDD, Otherwise, VDD will change the VLCD. 5.7. LCD Controller/Driver SPL31A contains a LCD controller and driver for 220dots LCD display. 5.9. PWM Output Users can set the LCD configuration (bias, duty, display mode) by writing LCD control register ($18). Internally, SPL31A has one pair of PWM outputs supporting two Once the LCD sound channels. configuration is initialized, the desired pattern can be displayed by filling the LCD buffer with appropriate data. individually. The LCD driver can drive speaker or buzzer directly without any buffer or amplification still operate during halt mode by keeping 32768 oscillator running. circuit. Furthermore, programmer can turn off the LCD display through LCD control register for power saving. The LCD driver in SPL31A is designed to fit most LCD's specifications. bias are available from the LCD driver. 5.10. Low Voltage Reset 1/2 or 1/3 The SPL31A provides a low voltage reset function. Meanwhile, The display Proprietary & Confidential The system will enter into LVRST state if and only if the power supply voltage duty can be programmed as 1/2, 1/3, 1/4 or 1/5 duty. © Sunplus Technology Co., Ltd. Each channel can be set to play speech or tone SPL31A uses Pulse Width Modulation that is able to VDD is lower than 2.3V. 6 AUG. 10, 2001 Version: 1.2 SPL31A 5.11. Watchdog Timer (WDT) An on chip watchdog timer is available on SPL31A. 5.13. Mask Options 5.13.1. 32768 crystal oscillator The WDT is designed for recovering from system abnormal operation. If the 1). X’TAL system is hanged, WDT will generate a system reset to restart system after 1 second. 2). R-oscillator If WDT is enabled, the WDT should be cleared every two seconds to avoid accidental reset. The WDT 5.13.2. Low voltage detect can be cleared by writing the specified value 0FH to port $0F. 1). 2.4V Note that the WDT only works when 32768 Hz clock is available. 2). 2.6V 5.12. Low Voltage Detect 5.13.3. SEG[43:41] can be optioned to IOEF[7:5] Furthermore, a Low Voltage Detect function is built in SPL31A. Once, the control register $17 bit7 is set to 1 (enable), the programmer can compare VDD voltage level with reference voltage 2.4V/2.6V from reading $17 bit0. Note1: 50us delay time is recommended for voltage detect circuit stabilization. Note2: Be sure to turn off voltage detect circuit if not needed to minimize power consumption. © Sunplus Technology Co., Ltd. Proprietary & Confidential 7 AUG. 10, 2001 Version: 1.2 SPL31A 6. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ TSTO -50℃ to +150℃ Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 6.2. DC Characteristics (VDD = 3.0V, TA = 25℃) Characteristics Operating Voltage Operating Current Standby Current Symbol Limit Unit Test condition Min. Typ. Max. VDD 2.4 - 3.6 V IOP - 0.8 - mA VDD = 3.0V, FCPU = 600KHz ISTBY - - 1.0 µA VDD = 3.0V - -50 - - -90 - - 60 - - 110 - IOH Audio output current IOL mA mA For 2-battery application VDD = 3.0V, VOH = 2.5V VDD = 3.0V, VOH = 2.0V VDD = 3.0V, VOL = 0.5V VDD = 3.0V, VOL = 1.0V Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High I IOH - -2.0 - mA VDD = 3.0V, VOH = 2.4V Output Sink I IOL - 2.5 - mA VDD = 3.0V, VOL = 0.8V 6.3. DC Characteristics (VDD = 4.5V, TA = 25℃) Characteristics Symbol Limit Min. Typ. Max. Unit Test condition Operating Voltage VDD 3.6 - 5.5 V Operating Current IOP - 1.6 - mA VDD = 4.5V, FCPU = 600KHz ISTBY - Standby Current Audio output current IOH For 3-battery application - 1.0 µA VDD = 4.5V -100 - mA VDD = 4.5V, VOH = 3.5V VDD = 4.5V, VOL = 0.8V IOL - 70 - mA VIH 3.0 - - V Input Low Level VIL - - 0.8 V Output High I IOH - -2.0 - mA VDD = 4.5V, VOH = 3.5V Output Sink I IOL - 2.5 - mA VDD = 4.5V, VOL = 0.8V Input High Level © Sunplus Technology Co., Ltd. Proprietary & Confidential 8 VDD = 4.5V VDD = 4.5V AUG. 10, 2001 Version: 1.2 SPL31A 6.4. The Relationships between the ROSC and the FCPU 6.5. The Relationships between the FCPU and the IOP o 6.4.1. VDD = 3.0V, TA = 25 C 3 VDD = 4.5V I OP ( m A ) F OSC ( MHz ) 6.0 4.0 2 1 VDD = 3V 2.0 0 0 2 0.0 4 6 F OSC ( MHz ) 0 200 400 600 800 Rosc ( Kohms ) 6.6. The Relationships between the FCPU and the VDD 6.4.2. VDD = 4.5V, TA = 25 oC F OSC ( MHz ) 6 F OSC ( MHz ) 6.0 4.0 Rosc = 51 Kohms 4 Rosc = 360 Kohms 2 0 2 2.0 3 4 5 VDD ( Volts ) 0.0 0 200 400 600 800 Rosc ( Kohms ) © Sunplus Technology Co., Ltd. Proprietary & Confidential 9 AUG. 10, 2001 Version: 1.2 SPL31A 7. APPLICATION CIRCUITS 0.1 µF Bias Circuit 1/2 Bias SPL31A TEST VDD1 0.1 µF 0.1 µF 0.1 µ F 0.1 µ F 0.1 µ F 0.1 µ F SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 COM3 AUDN AVDD AUDP AVSS RESET X32I X32O ROSC VDD VSS VDD2 CUP2 CUP1 VDD1 VLCD IOEF4 IOEF3 IOEF2 IOEF1 IOEF0 0.1 µF VDD 20P I/O VDD 0.1 µ F RESET 8 Ω ~ 64 Ω Bias Circuit 32768Hz 20P Rosc 0.1 µ F SPL31A Application Circuit COM0 VLCD CUP1 CUP2 1/3 Bias VDD1 VDD2 VLCD CUP1 CUP2 SEGs [ 43:0 ] LCD Module COMs [ 4:0 ] IOCD3 IOCD2 IOCD1 IOCD0 COM2 COM1 I/O DEVICE I/O Version: 1.2 Proprietary & Confidential COM4 AUG. 10, 2001 10 © Sunplus Technology Co., Ltd. SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 SPL31A 8. PACKAGE/PAD LOCATIONS 8.1. PAD Assignment Chip Size: 2270µm × 3020µm This IC substrate should be connected to VSS Note1: Chip size included scribe line. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 8.2. Ordering Information Product Number Package Type SPL31A-nnnnV-C Chip form Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z). © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 AUG. 10, 2001 Version: 1.2 SPL31A 8.3. PAD Locations PAD No. PAD Name X Y PAD No. PAD Name X Y 1 IOEF2 -921 1395 38 SEG10 1021 -1295 2 IOEF3 -921 1258 39 SEG9 1021 -1168 3 IOEF4 -921 1116 40 SEG8 1021 -1035 4 VDD -921 885 41 SEG7 1021 -908 5 SEG43 -921 765 42 SEG6 1021 -781 6 SEG42 -921 645 43 SEG5 1021 -654 7 SEG41 -921 525 44 SEG4 1021 -527 8 SEG40 -921 405 45 SEG3 1021 -400 9 SEG39 -921 285 46 SEG2 1021 -273 10 SEG38 -921 165 47 SEG1 1021 -146 11 SEG37 -921 45 48 SEG0 1021 -19 12 SEG36 -921 -75 49 COM4 1021 108 13 SEG35 -921 -195 50 COM3 1021 235 14 SEG34 -921 -315 51 COM2 1021 362 15 SEG33 -921 -435 52 COM1 1021 489 16 SEG32 -921 -555 53 COM0 1021 616 17 SEG31 -921 -675 54 VLCD 1021 743 18 SEG30 -921 -795 55 VDD1 1021 870 19 SEG29 -921 -915 56 CPU1 1021 997 20 SEG28 -921 -1035 57 CPU2 1021 1124 21 SEG27 -921 -1168 58 VDD2 1021 1258 22 SEG26 -921 -1295 59 TEST 1021 1395 23 SEG25 -784 -1295 60 X32O 884 1395 24 SEG24 -656 -1295 61 X32I 766 1395 25 SEG23 -538 -1295 62 RESET 647 1395 26 SEG22 -419 -1295 63 ROSC 529 1395 27 SEG21 -301 -1295 64 VSS 410 1395 28 SEG20 -182 -1295 65 IOCD0 292 1395 29 SEG19 -64 -1295 66 IOCD1 173 1395 30 SEG18 55 -1295 67 IOCD2 55 1395 31 SEG17 173 -1295 68 IOCD3 -64 1395 32 SEG16 292 -1295 69 AVSS -182 1395 33 SEG15 410 -1295 70 AUDP -301 1395 34 SEG14 529 -1295 71 AVDD -419 1395 35 SEG13 647 -1295 72 AUDN -538 1395 36 SEG12 766 -1295 73 IOEF0 -656 1395 37 SEG11 884 -1295 74 IOEF1 -784 1395 © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 AUG. 10, 2001 Version: 1.2 SPL31A 9. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Sunplus Technology Co., Ltd. Proprietary & Confidential 13 AUG. 10, 2001 Version: 1.2 SPL31A 10. REVISION HISTORY Date Revision # Description NOV. 17, 1999 0.1 Original SEP. 22, 2000 0.2 OSC Resistor Typ. 220K -> 177K OCT. 19, 2000 1.0 Delete “PRELIMINARY” APR. 30, 2001 1.1 1. Correct Min. (VLCD) - VDD > -0.5 to Min. (VLCD) > VDD Page 8 5 2. Renew to a new document format AUG. 10, 2001 1.2 1. Update “6. ELECTRCIAL SPECIFICATIONS” 8-9 2. Correct chip size 11 3. Add Note1 in the “8.1 PAD Assignment” 11 4. Renew to a new document © Sunplus Technology Co., Ltd. Proprietary & Confidential 14 AUG. 10, 2001 Version: 1.2 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com