SPC21A1 20KB SOUND CONTROLLER GENERAL DESCRIPTION The SPC21A1 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 20K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 6 sec speech duration @ 7KHz sampling rate) and 64-byte working SRAM. It includes two Timer/Counters, 10 Software Selectable I/Os, and one 8-bit current D/A output. For audio processing, melody and speech can be mixed into one output. It operates over a wide voltage range of 2.4V - 5.5V and includes Low Voltage Reset function. The Low Voltage Reset automatically resets when the working voltage is less than 2.2V. In addition, SPC21A1 has a Clock Stop mode for power savings. The power savings mode saves the RAM contents, but freezes the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 6.0MHz. It has an Instruction Cycle Rate of 2 clock cycles (min.) – 6 clock cycles (max.). The SPC21A1 includes, not only the latest technology, but also the full commitment and technical support of Sunplus. FEATURES BLOCK DIAGRAM 8-bit microprocessor Provides 20K-byte ROM for program and 20K-byte ROM 8-bit microprocessor audio data Two Timers TimeBase INT control 64-byte SRAM 64-byte working SRAM Software-based audio processing Wide operating voltage: 2.4V – 3.4V @ 4.0MHz XI 3.6V – 5.5V @ 6.0MHz One 8-bit D/A (current) Low Voltage Reset CLK OSC 10 PINS GENERAL I/O AUD PORT Supports Rosc only IOC3-0 (I/O) IOD5-0 (I/O) Max. CPU clock: 4.0MHz @ 3V, 6.0MHz @ 5V Standby mode (Clock Stop mode) for power Savings. Max. 2A @ 5V APPLICATION FIELD 500ns instruction cycle time @ 4.0MHz CPU clock Intelligent education toys Provides 10 general I/Os Ex. Pattern to voice (animal, car, color, etc.) Two 12-bit timer/counters Spelling (English or Chinese) 6 INT sources Math Key wake -up function High end toy controller Approx. 6 sec speech Talking instrument controller General speech synthesizer @ 7KHz sampling rate with ADPCM One D/A output Industrial controller Low Voltage Reset Sunplus Technology Co., Ltd. 1 Rev.: 1.1 1999.11.19 SPC21A1 FUNCTION DESCRIPTIONS CPU The SPC21A1 8-bit microprocessor is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). SPC21A1 is able to perform with 6.0MHz (max.) depending on the application specifications. ROM AREA The SPC21A1 provides a 20K-byte ROM that can be defined as the program area, audio data area, or both. RAM AREA The SPC21A1 total RAM consists of 64-bytes (including Stack) at locations from $C0 through $FF. MAP OF MEMORY AND I/Os *I/O PORT: *MEMORY MAP (From ROM view) - PORT IOC $0004 IOD $0005 - I/O CONFIG $0000 $00000 Hardware register, I/Os $000C0 USER RAM and STACK $0001 *NMI SOURCE: $00100 UNUSED - INTA (from TIMER A) $00200 *INT SOURCE: - INTA (from TIMER A) SUNPLUS TEST PROGRAM $00600 - INTB (from TIMER B) USER’S PROGRAM & DATA AREA - CPU CLK / 1024 - CPU CLK / 8192 $03FFF DUMMY AREA - CPU CLK / 65536 - EXT INT $07000 USER‘S PROGRAM & DATA AREA $07FFF Sunplus Technology Co., Ltd. 2 Rev.: 1.1 1999.11.19 SPC21A1 I/O PORT CONFIGURATION* Input/Output IOC port : IOC3 - IOC0 V DD logic_2 control 60K output data buffer or OD-NMOS input data OD : Open Drain Input/Output IOD port : IOD3 - IOD0 Input/Output IOD port : IOD5 - IOD4 input data output input data OD-PMOS or buffer output data logic_3 OD-PMOS or buffer data 60K logic_4 control control OD : Open Drain OD : Open Drain 60K *Values shown are for VDD = 5.0V test conditions only. Sunplus Technology Co., Ltd. 3 Rev.: 1.1 1999.11.19 SPC21A1 POWER SAVINGS MODE The SPC21A1 provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. RAM and I/Os will remain in their previous states until being awakened. source in the SPC21A1. In such a mode, Port IOD7-0 is the only wake-up After the SPC21A1 is awakened, the internal CPU will go to the RESET State (Tw 65536 x T1) and then continue processing the program. Wakeup Reset will not affect RAM or I/Os (FIG.1). Sleep Wake-up T1 CPU CLK Tw Reset FIG. 1 T1 = 1 / ( FCPU ), Tw 65536 x T1 LOW VOLTAGE RESET The SPC21A1 includes a Low Voltage Reset (LVR) function. Below the minimum power-supply voltage of 2.2V, the CPU system will become unstable and malfunction. Low Voltage Reset will reset all functions into the initial operational (stable) state if the VDD power-supply voltage drops below 2.2V (FIG.2). T1 CPU CLK VDD 2.2V T2 TW RESET T2 2 * T1 (The LVR function is the same as Power ON Reset or External Reset.) FIG. 2 Sunplus Technology Co., Ltd. 4 Rev.: 1.1 1999.11.19 SPC21A1 TIMER/COUNTER The SPC21A1 contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be specified as a timer or a counter, but TMB can only be used as a timer. In the timer mode, TMA and TMB are re-loaded upcounters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user’s pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time. The read instruction will not affect the value of the counter or reset it. Clock source of Timer/Counter can be selected as follows: Timer/Counter TMA TMB Clock Source 12-BIT TIMER CPU CLOCK (T) or T/4 12-BIT COUNTER T/64, T/8192, T/65536 or EXT CLK 12-BIT TIMER T or T/4 MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4 SPEECH AND MELODY Since the SPC21A1 provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis. For speech synthesis, the SPC21A1 can provide NMI for accurate sampling frequency. Users can record or synthesize the sound and digitize it into the ROM. The sound data can be played back in the sequence of the control functions as designed by the user's program. Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM. For melody synthesis, the SPC21A1 provides the dual tone mode. After selecting the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to generate expected frequency for each channel. The hardware will toggle the tone wave automatically without entering into an interrupt service routine. Users are able to simulate musical instruments or sound effects by simply controlling the envelope of tone output. Sunplus Technology Co., Ltd. 5 Rev.: 1.1 1999.11.19 SPC21A1 PIN DESCRIPTION* Mnemonic PIN No. Type Description VDD 8 I Supply voltage input VSS 7 I Ground XI 9 I Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) RESET 2 I RESET TEST 11 I TEST MODE AUD 10 O AUDIO OUTPUT Port C is an 4-bit bi-directional programmable Input / Output port with IOC0 6 I/O Pull-high or Open-drain option. As inputs, Port C can be in either IOC1 5 I/O the Pure or Pull-high states. IOC2 4 I/O Open-drain NMOS type (sink current). IOC3 3 I/O IOC1:EXT INT IN As outputs Port C can be a Buffer or IOC2:EXT COUNT IN **See note 1 and 2 below. Port D is an 6-bit bi-directional programmable Input / Output port with IOD0 17 I/O Pull-low or Open-drain option. As inputs, Port D can be either Pure IOD1 16 I/O or Pull-low states. IOD2 15 I/O drain PMOS type (send current). IOD3 14 I/O (Key change, Wake up I/O) IOD4 13 I/O IOD5 12 I/O As outputs, Port D can be either Buffer or Open- **See note 1 and 2 below. * Refer to SPC Programming Guide for complete information. **Note: 1.) Two input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified as Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output (sink). ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Ratings DC Supply Voltage V+ < 7V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0 to +60 TSTO -50 to +150 Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. Sunplus Technology Co., Ltd. 6 Rev.: 1.1 1999.11.19 SPC21A1 AC CHARACTERISTICS ( TA = 25 ) Characteristics OSC Frequency Symbol Limit Unit Test Condition Min. Typ. Max. - 2.0 4.0 MHz VDD = 3V - 4.0 6.0 MHz VDD = 5V FOSC2 DC CHARACTERISTICS (TA = 25 C, VDD = 3 V) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition Operating Voltage VDD 2.4 - 3.4 V Operating Current IOP - 1.5 2.0 mA FCPU = 3.0MHz @ 3V, no load Standby Current ISTBY - - 2.0 A VDD = 3V Audio output current IAUD - -1.5 - mA VDD = 3V,one-channel Input High Level VIH 2.0 - - V VDD = 3V Input Low Level VIL - - 0.8 V VDD = 3V IOH -1.0 - - mA IOL 2.0 - - mA RIN - 110 - Kohm Output High I IOC,IOD Output Sink I IOC,IOD Input Resistor IOD For 2-battery VDD = 3V VOH = 2V VDD = 3V VOL = 0.8V Pull Low VDD = 3V DC CHARACTERISTICS (TA = 25 C, VDD = 5 V) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition Operating Voltage VDD 3.6 - 5.5 V Operating Current IOP - 4.0 5.0 mA FCPU = 4.0MHz @ 5V, no load Standby Current ISTBY - - 2.0 A VDD = 5V Audio output current IAUD - -3.0 - mA VDD = 5V, one-channel Input High Level VIH 3.0 - - V VDD = 5V Input Low Level VIL - - 0.8 V VDD = 5V IOH -1.0 - - mA IOL 4.0 - - mA RIN - 60 - Kohm Output High I IOC,IOD Output Sink I IOC,IOD Input Resistor IOD Sunplus Technology Co., Ltd. 7 For 3-battery VDD = 5V VOH = 4.2V VDD = 5V VOL = 0.8V Pull Low VDD = 5V Rev.: 1.1 1999.11.19 SPC21A1 The relationship between the Rosc and the FCPU VDD = 3.0V , Ta = 25 VDD = 4.5V , Ta = 25 6.0 Fosc ( MHz ) Fosc ( MHz ) 4.0 3.0 2.0 1.0 5.0 4.0 3.0 2.0 1.0 0.0 0 200 400 600 0.0 800 0 200 Rosc ( Kohms ) 400 600 800 Rosc ( Kohm s ) Frequency vs. Temperature Frequency vs. VDD Frequency normalized to 25 Fosc ( MHz ) FCPU/FCPU(25) 1.04 Rosc=200Kohms 1.02 VDD=5.0V 1.00 0.98 5.0 4.0 3.0 2.0 1.0 0.0 Rosc = 100 Kohms Rosc = 200 Kohms 2.0 0.96 0 10 20 30 40 50 60 Temperature () 3.0 4.0 5.0 VDD ( Volts ) 70 Operating current vs. Frequency vs. VDD IOP ( mA ) 4 3 VDD = 4.5V 2 1 VDD = 3V 0 0 1 2 3 4 5 6 Fosc ( MHz ) Sunplus Technology Co., Ltd. 8 Rev.: 1.1 1999.11.19 1999.11.19 SPC21A1 VDD R2 150K R1 50K RESET 0.1 3 4 5 6 SPC21A1 VDD 8 C3 + C4 220 F 0.1 IOC3 IOC2 IOC1 IOC0 VDD AUD IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS TEST Speaker 9 Q1 8050 10 C2 12 13 14 15 16 17 0.1 R3 680 9 C1 RESET XI 1,7 11 Sunplus Technology Co., Ltd. 2 APPLICATION CIRCUIT NOTE Rev.: 1.1 VDD SPC21A1 Current Mode DAC Speaker Driver RB1: 10K ~ 50K RB2: 820 ~ 1.5K C1: 0.1 F ~ 1 F VDD C1: 0.1 F ~ 1 F RB1: 680 ~ 1.5K ~ 8 32 ~ 64 AUD RB1 AUD 8050 RB1 C1 VDD 8050 RB2 C1 Figure 1 Figure 2 VDD RB1: 2K~10K; C1: 1 F~10 F RB2: ~1K; C2: ~0.1 F VDD RB1: 2K~10K; C1: 1 F~10 F RB2: ~1K; C2: ~0.1 F ~ 64 C2 ~ 8 RB1 Enable C2 AUD RB1 AUD 8050 C1 RB2 8050 C1 RB2 Figure 3 Figure 4 VDD Power ~ 64 AUDP 3 220 F 6 5 LM386 2 AUD 8050 7 10 4 RB1 1N4148 + RB1: ~ 360 (Vol) RB2: ~ 4.7 0.1 F 20K RE1 0.01 F RB1 Figure 5 Figure 6 Figure 1:The simplest CKT uses with low impedance speaker. It has high operation current, but low cost. Figure 2:It is the same as Figure 1 but a high impedance speaker is used. Figure 3:The CKT contains a low pass filter. It is capable of providing higher speech quality, but it takes higher operation current. Figure 4:Improved version of Figure 3. The standby current can be controlled by the enable pin. Figure 5:The current mirror mode. It is able to control the volume. In addition, it is more stable and has lower operation current than Figure 1-3. Figure 6:High quality, low operation current CKT, but more expensive. Sunplus Technology Co., Ltd. 10 Rev.: 1.1 1999.11.19 SPC21A1 PAD ASSIGNMENT AND LOCATIONS PAD Assignment Chip Size: 1980m x 1420m This IC substrate should be connected to VSS Note: To ensure that the IC functions properly, bond all VDD, VSS, AVDD and AVSS pins. Ordering Information Product Number Package Type SPC21A1-nnnnV-C Chip form Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999) ; version (A = A - Z). NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance and to supply the best possible product. Sunplus Technology Co., Ltd. 11 Rev.: 1.1 1999.11.19 SPC21A1 PAD Locations Pad No Pad Name X Y 1 VSS -822 -509 2 RESET -604 -498 3 IOC3 -431 -509 4 IOC2 -276 -509 5 IOC1 -125 -509 6 IOC0 30 -509 7 VSS 187 -509 8 VDD 327 -509 9 XI 482 -498 10 AUD 648 -498 11 TEST 803 -498 12 IOD5 788 -316 13 IOD4 788 -157 14 IOD3 788 -6 15 IOD2 788 153 16 IOD1 788 305 17 IOD0 788 464 DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. Sunplus Technology Co., Ltd. 12 Rev.: 1.1 1999.11.19