TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 FEATURES Input Port Ÿ RGB analog input port Ÿ Full SOG and composite sync support, including copy protected signals Ÿ High-speed 8-bit triple-ADC with low jitter PLL operates up to 220 MHz n Display Processing Engine Ÿ Patent-pending Hybrid Image Resolution Converter Ÿ Variable sharpness control Ÿ Interlaced to progressive conversion Ÿ Patent-pending Dynamic Frame-Rate generator (DFR) – short line storage frame extension technique eliminates short lines in output frames Ÿ Media Window Enhancement (MWE)Note Ÿ Peaking and coring functions for sharpness enhancement and noise reduction Ÿ Brightness and contrast control Ÿ Programmable 10-bit gamma correction Ÿ sRGB support n Auto-Detection / Auto-Tune Support Ÿ Auto input signal format (SOG, composite, separated HSYNC, and VSYNC) Ÿ Input mode detection support analyzes input video signal (H/V polarity, H/V frequency, interlace/field detect) – extensive status registers support robust detection of all VESA and IBM modes n n n n n Ÿ Auto-tuning function including support for phase selection, image position, offset & gain and jitter detection Ÿ Smart screen-fitting On-screen display controller (OSD) Ÿ Built-in OSD generator with 291 character font programmable RAM Ÿ Internal OSD rotation degree of 90 and 270 Ÿ Supports 2/4/8 multi-color fonts Ÿ Supports 8/16/256 color palette Ÿ Supports 1K code attributes Ÿ Gradient color function Ÿ Hardware button animation function Ÿ Pattern generator for production test Ÿ Supports OSD MUX and alpha blending capability Output Display Interface Ÿ Supports 6/8-bit LVDS panel interface Ÿ Supports up to SXGA display resolution with up to 135 MHz dot clock Ÿ Spread spectrum output frequency for EMI suppression Ÿ PWM backlight intensity control DPMS Support Ÿ Full green mode DPMS support Ÿ Low standby power (< 16mA) External Connection/Component Ÿ Supports DDR direct bus (up to 40MHz) and serial bus (up to 400Kbit/sec) Note: The optional MWE function is available with TSU16AWK. Version 0.3 -1Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 BLOCK DIAGRAM Display Processing Engine Analog RGB Analog Interface Engine Analog HSYNC/VSYNC HOST OSD LVDS Panel Interface To Panel Clock Gen interface MCU XTAL/EXT CLK GENERAL DESCRIPTION The TSU16AK is total solution graphics processing IC for LCD monitors with panel resolutions up to SXGA. It is configured with a high-speed integrated triple-ADC/PLL, a high quality display processing engine, and an integrated output display interface that can support LVDS panel interface format. To further reduce system costs, the TSU16AK also integrates intelligent power management control capability for green-mode requirements and spread-spectrum support for EMI management. The TSU16AK incorporates the world’s first coherent oversampled RGB graphics ADC in a monitor controller system1. The oversampling ADC samples the input RGB signals at a frequency that is much higher than the signal source pixel rate. This can preserve details in the video signal that ordinarily would be lost due to input signal jitter or bandwidth limitations in non-oversampled systems. The TSU16AK also incorporates a new Dynamic Frame Rate (DFR) generator 2 for the digital output video to the display panel that preserves the advantages of a fixed output clock rate, while eliminating the output end of frame short-line. 1,2 Patent Pending Version 0.3 -2Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 103 104 105 106 107 108 109 110 111 112 114 115 116 117 118 119 120 121 122 123 124 125 126 113 LVA3P NC 100 NC 99 NC 98 NC 97 VDDC 96 GND 95 GND 94 VDDP 93 NC 92 NC 91 NC 90 NC 89 NC 88 NC 87 VDDC 86 GND 85 GND 84 VDDP 83 NC 82 NC 81 NC 80 NC 79 NC 78 AD2 77 AD1 76 NC 75 NC 74 PWM1 73 PWM0 72 INT 71 RDZ/SCL 70 WRZ/SDA 69 ALE/CS 68 GND 67 REFM 66 REFP 65 AVDD_ADC 1 102 2 101 Pin 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TSU16AK XXXXXXXXXXX XXXXX 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND NC NC GND NC NC AVDD_ADC NC NC GND NC NC AVDD_ADC REXT AVDD_PLL GND AVDD_ADC GND BIN0M BIN0P GIN0M GIN0P SOGIN0 RIN0M RIN0P GND 40 38 39 LVB0M GND BYPASS NC NC BUSTYPE NC NC NC GND VDDP NC NC NC NC NC NC VDDC GND GND VDDP NC NC NC NC NC NC NC NC AD0 AD3 HWRESET XIN XOUT AVDD_MPLL GND HSYNC0 VSYNC0 127 128 LVB0P GND VDDP LVB1M LVB1P LVB2M LVB2P LVBCKM LVBCKP LVB3M LVB3P VDDC GND GND VDDP LVA0M LVA0P LVA1M LVA1P LVA2M LVA2P LVACKM LVACKP GND VDDP LVA3M PIN DIAGRAM (TSU16AK) Version 0.3 -3Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 PIN DESCRIPTION CPU Interface Pin Name Pin Type Function Pin HWRESET Schmitt Trigger Input Hardware reset; active high w/ 5V-tolerant 32 CS Input w/ 5V-tolerant 3 Wire Serial Bus Chip Select; active high 69 SDA I/O w/ 5V-tolerant 3 Wire Serial Bus Data; 4mA driving strength 70 SCL Input w/ 5V-tolerant 3 Wire Serial Bus Clock 71 INT Output CPU interrupt; 4mA driving strength 72 AD3 I/O w/ 5V-tolerant DDR direct bus AD3; 4mA driving strength 31 AD2 I/O w/ 5V-tolerant DDR direct bus AD2; 8mA driving strength 78 AD1 I/O w/ 5V-tolerant DDR direct bus AD1; 8mA driving strength 77 AD0 I/O w/ 5V-tolerant DDR direct bus AD0; 4mA driving strength 30 ALE I w/ 5V-tolerant DDR direct bus ALE; active high 69 RDZ I w/ 5V-tolerant DDR direct bus RDZ; active low 71 WRZ I w/ 5V-tolerant DDR direct bus WRZ; active low 70 BUSTYPE Input (not 5V-tolerant) Bus type Ÿ Low : Serial bus Ÿ High : DDR Direct bus 6 Analog Interface Pin Name Pin Type Function Pin HSYNC0 Schmitt Trigger Input Analog HSYNC input w/ 5V-tolerant 37 VSYNC0 Schmitt Trigger Input Analog VSYNC input w/ 5V-tolerant 38 REFP Internal ADC top de-coupling pin 66 REFM Internal ADC bottom de-coupling pin 67 RIN0P Analog Input Analog red input 63 RIN0M Analog Input Reference ground for analog red input 62 SOGIN0 Analog Input Sync-on-green input 61 GIN0P Analog Input Analog green input 60 GIN0M Analog Input Reference ground for analog green input 59 BIN0P Analog Input Analog blue input 58 BIN0M Analog Input Reference ground for analog blue input 57 External resistor 390 ohm to AVDD_ADC 52 REXT Version 0.3 -4Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 LVDS Interface Pin Name Pin Type Function Pin LVA0M Output A-Link Negative LVDS Differential Data Output 113 LVA0P Output A-Link Positive LVDS Differential Data Output 112 LVA1M Output A-Link Negative LVDS Differential Data Output 111 LVA1P Output A-Link Positive LVDS Differential Data Output 110 LVA2M Output A-Link Negative LVDS Differential Data Output 109 LVA2P Output A-Link Positive LVDS Differential Data Output 108 LVA3M Output A-Link Negative LVDS Differential Data Output 103 LVA3P Output A-Link Positive LVDS Differential Data Output 102 LVACKM Output A-Link Negative LVDS Differential Clock Output 107 LVACKP Output A-Link Positive LVDS Differential Clock Output 106 LVB0M Output B-Link Negative LVDS Differential Data Output 1 LVB0P Output B-Link Positive LVDS Differential Data Output 128 LVB1M Output B-Link Negative LVDS Differential Data Output 125 LVB1P Output B-Link Positive LVDS Differential Data Output 124 LVB2M Output B-Link Negative LVDS Differential Data Output 123 LVB2P Output B-Link Positive LVDS Differential Data Output 122 LVB3M Output B-Link Negative LVDS Differential Data Output 119 LVB3P Output B-Link Positive LVDS Differential Data Output 118 LVBCKM Output B-Link Negative LVDS Differential Clock Output 121 LVBCKP Output B-Link Positive LVDS Differential Clock Output 120 Pin Name Pin Type Function Pin PWM1 Output PWM1; 4mA driving strength 74 PWM0 Output PWM0; 4mA driving strength 73 Pin Type Function Pin For External Bypass Capacitor 3 GPO Interface Misc. Interface Pin Name BYPASS XIN Crystal Oscillator Input Xin 33 XOUT Crystal Output 34 Version 0.3 Oscillator Xout -5Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Power Pins Pin Name Pin Type Function Pin AVDD_ADC 3.3V Power ADC Power 45, 51, 55, 65 AVDD_PLL 3.3V Power PLL Power 53 AVDD_MPLL 3.3V Power MPLL Power 35 VDDP 3.3V Power Digital Output Power 11, 21, 84, 94, 104, 114, 126 VDDC 1.8V Power Digital Core Power 18, 87, 97, 117 GND Ground Ground 2, 10, 19, 20, 36, 39, 42, 48, 54, 56, 64, 68, 85, 86, 95, 96, 105, 115, 116, 127 Pin Type Function No Connects Pin Name NC Version 0.3 Pin No Connect. Floating. Leave These Pins 4, 5, 7-9, 12-17, 22-29, 40, 41, 43, 44, 46, 47, 49, 50, 75, 76, 79-83, 88-93, 98-101 -6Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 ELECTRICAL SPECIFICATIONS Analog Interface Characteristics Parameter Min Resolution Typ Max 8 Unit Bits DC ACCURACY Differential Nonlinearity ±0.5 Integral Nonlinearity +1.50/-1.0 ±1 No Missing Codes LSB LSB Guaranteed ANALOG INPUT Input Voltage Range Minimum 0.5 Maximum 1.0 V p-p V p-p Input Bias Current 1 uA Input Full-Scale Matching 1.5 %FS Brightness Level Adjustment 62 %FS SWITCHING PERFORMANCE Maximum Conversion Rate 220 MSPS Minimum Conversion Rate 12 MSPS HSYNC Input Frequency 15 200 kHz PLL Clock Rate 12 220 MHz PLL Jitter 500 ps p-p Sampling Phase Tempco TBD ps/°C DIGITAL INPUTS Input Voltage, High (VIH) 2.5 V Input Voltage, Low (VIL) 0.8 V Input Current, High (IIH) -1.0 uA Input Current, Low (IIL) 1.0 uA Input Capacitance 5 pF DIGITAL OUTPUTS Output Voltage, High (VOH) VDDP-0.1 V Output Voltage, Low (VOL) 0.1 V DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Channel to Channel Matching 250 MHz 0.5% Full-Scale Specifications are subjected to change without notice. Version 0.3 -7Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Absolute Maximum Ratings Parameter Symbol Min 3.3V Supply Voltages VVDD_33 1.8V Supply Voltages Input Voltage (5V tolerant inputs) Typ Max Units -0.3 3.6 V VVDD_18 -0.3 1.98 V VIN5Vtol -0.3 5.0 V Input Voltage (non 5V tolerant inputs) VIN -0.3 VVDD_33 V Ambient Operating Temperature TA 0 70 °C Storage Temperature TSTG -40 150 °C Junction Temperature TJ 150 °C Thermal Resistance (Junction to Air) Natural Conversion θJA 34 °C/W Thermal Resistance (Junction to Case) Natural Conversion θJC 6.0 °C/W Note: Stress above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Model MARKING INFORMATION Temperature Package Package Range Description Option TSU16AK 0°C to +70°C PQFP 128 TSU16AWK 0°C to +70°C PQFP 128 TSU16AK-LF 0°C to +70°C PQFP 128 TSU16AWK-LF 0°C to +70°C PQFP 128 TSU16AK Part Number Lot Number Operation Code A Operation Code B Date Code (YYWW) Note: Product suffix “LF” represents lead-free version, and “W” represents MWE function. DISCLAIMER MSTAR SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO RESPONSIBILITY IS ASSUMED BY MSTAR SEMICONDUCTOR ARISING OUT OF THE APPLICATION OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. Electrostatic charges accumulate on both test equipment and human body and can discharge without detection. TSU16AK comes with ESD protection circuitry, however, the device may be permanently damaged when subjected to high energy discharges. The device should be handled with proper ESD precautions to prevent malfunction and performance degradation. Version 0.3 -8Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 REVISION HISTORY Document Description Date TSU16AK_ds_v01 Ÿ Initial release Aug 2004 TSU16AK_ds_v02 Ÿ Updated Register Table Sep 2004 TSU16AK_ds_v03 Ÿ Updated MWE related information Ÿ Added lead-free information to Ordering Guide Ÿ Updated Register Table Oct 2004 Version 0.3 -9Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 MECHANICAL DIMENSIONS Symbol Inch Symbol Min. Nom. Max. Min. Nom. Max. A - - 3.40 - - 0.134 A1 0.25 - - 0.010 - - A2 Version 0.3 Millimeter 2.50 2.72 23.20 0.913 D1 20.00 0.787 D2 18.50 0.728 E 17.20 0.677 E1 14.00 0.551 E2 12.50 0.492 R1 0.13 - R2 0.13 - - θ 0° - 7° 0° - 7° θ1 0° - - 0° - - (Alloy) θ2, θ2 (Copper) - - 0.30 0.005 - 0.012 7° Ref 7° Ref 15° Ref 15° Ref b 0.170 0.200 0.270 0.007 0.008 0.011 c 0.11 e 0.005 Inch Min. Nom. Max. Min. Nom. Max. θ2, θ2 2.90 0.098 0.107 0.114 D Millimeter L 0.73 L1 S 0.15 0.23 0.004 0.006 0.009 0.50 BSC. 0.88 0.020 BSC. 1.03 0.029 0.035 0.041 1.60 Ref 0.20 - 0.063 Ref - - 10 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 0.008 - - 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 REGISTER DESCRIPTION General Control Register Index 00h Mnemonic REGBK PORR Bits 7:0 7 AINC 6:4 3 BUST 2 REGBK[1:0] 1:0 Description Default : Access : R/W Power On Reset Ready (read only). 0: Not ready. 1: Ready. Reserved. Serial bus address auto increase. 0: Enable. 1: Disable. BUS type (read only). 0: Direct bus. 1: Serial bus. Register Bank Select. 00: Register of digital image processor. 01: Register of internal ADC, DVI/HDCP receiver. 10: Register of timing controller. 11: Register of MWE function. ADC Register (Bank = 01) ADC Register (Bank=01) Index Mnemonic Bits Description 01h DBFC 7:0 Default : 0x00 - 7:1 Reserved. DBVB 02h 03h Double Buffer load at Vertical Blanking. 0: Disable. 1: Enable. PLLDIVM 7:0 Default : 0x69 PLLDIV[11:4] 7:0 PLL Divider ratio. When bank 1 register 3Dh[4] = 0 ADC PLL will multiply the horizontal line frequency by PLLDIV[11:0] + 3 to generate the ADC sampling clock. When bank 1 register 3Dh[4] = 1 ADC PLL will multiply the horizontal line frequency by (PLLDIV[11:0] +3)*2 to generate the ADC sampling clock. PLLDIVL 7:0 Default : 0x50 PLLDIV[3:0] 7:4 PLL Divider ratio. Please see the description of PLLDIV[11:4]. STAT[2:0] Version 0.3 0 Access : R/W 3 2:0 Access : R/W Access : R/W Reserved. Status select. Selects 1/8 internal PLL status values to read from register 16h. - 11 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 ADC Register (Bank=01) 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Version 0.3 REDGAIN 7:0 Default : 0x80 Access : R/W REDGAIN 7:0 Red channel Gain adjust. GRNGAIN 7:0 Default : 0x80 GRNGAIN 7:0 Green channel Gain adjust. BLUGAIN 7:0 Default : 0x80 BLUGAIN 7:0 Blue channel Gain adjust. REDOFST 7:0 Default : 0x80 REDOFST 7:0 Red channel Offset adjust. GRNOFST 7:0 Default : 0x80 GRNOFST 7:0 Green channel Offset adjust. BLUOFST 7:0 Default : 0x80 BLUOFST 7:0 Blue channel Offset adjust. CLPACE 7:0 Default: 0x05 CLPACE 7:0 Clamp Placement based on ADC clock. CLDUR 7:0 Default : 0x05 CLDUR 7:0 Clamp Duration based on ADC clock. GCTRL 7:0 Default : 0x82 Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W HSP 7 Input HSYNC Polarity. 0: Active low. 1: Active high. ECLK 6 External Clock. 0: ADC clock from internal ADC PLL. 1: ADC clock from external clock. HSLE 5 HS Lock Edge. Determines which edge of HSYNC the ADC PLL will lock to, assuming HSP is set correctly. 0: Leading edge of HSYNC. 1: Trailing edge of HSYNC. CLPE 4 Clamp reference Edge. 0: Trailing edge of HSYNC. 1: Leading edge of HSYNC. CCDIS 3 Disable PLL watchdog timer. 0: Always enable clamp. 1: Disable clamp during active coast. WDIS 2 Disable watchdog timer. 0: Enable PLL watchdog timer. A watchdog timer is used to reset the ADC PLL when the PLL remains much higher than PLLDIV*HSYNC_FREQ for a predetermined period. See WDTOL (Register 30h). - 12 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 ADC Register (Bank=01) 1: Disable PLL watchdog timer (should only be used when DPL_S = 0). 0Dh 0Eh OFh 10h CSTP 1 Coast Polarity. 0: Active low. 1: Active high. DRBS 0 DVI input Red/Blue swap (DVI features only). 0: Normal. 1: Swap. BWCOEF 7:0 Default : 0x02 DMODE[1:0] 7:6 Damping coefficient mode control. 00: Default value – backward compatibility mode. 01: Reserved. 10: Automatic DCOEF control (recommended mode). 11: Reserved. BWCOEF[5:0] 5:0 PLL loop filter control. FCOEF 7:0 Default : 0x09 7:5 Reserved. FREQCOEF[4:0] 4:0 PLL loop filter control. DCOEF 7:0 Default : 0x05 7:4 Reserved. DAMPCOEF[3:0] 3:0 PLL loop filter control. CLKCTRL1 7:0 Default : 0x08 11h Access : R/W Access : R/W Reserved. 6:0 Clock Phase adjust (should be always set to PHASECC + 8). CLKCTRL2 7:0 Default : 0x00 7 Access : R/W Reserved. PHASECC[6:0] 6:0 Clock phase adjust for ADC sampling time point. adjustable between 0 and 360° in 5.6° steps. VCOCTRL 7:0 Default : 0x15 PDGT Version 0.3 Access : R/W PHASE[6:0] - 12h 7 Access : R/W 7 Phase is Access : R/W Phase digitizer frequency compensation disable. DPL_S[2:0] 6:4 VCO range. Sets ADC SETCNT[3:0] 3:0 Setting time for ADC PLL phase detector, in ADC clock periods. - 13 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. PLL frequency range. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 ADC Register (Bank=01) 13h 14h 15h 16h RT_CTL 7:0 Default : 0x10 Access : R/W SFTF 7 DVI error correction enable (DVI feature only). 0: Error correction disable. 1: Error correction enable. DEFE 6 DVI R/G/B alignment edge on DE (DVI feature only). 0: DE leading edge. 1: DE trailing edge. WDF 5 DVI word alignment edge on DE (DVI feature only). 0: Disable. 1: Enable. RT_CTL[4:0] 4:0 Resistor termination control for DVI (DVI feature only). SOG_LVL 7:0 Default : 0x10 Access : R/W RMID 7 Middle clamp of Red Channel. 0: Disable. 1: Enable (used when YPbPr input). BMID 6 Middle clamp of Blue Channel. 0: Disable. 1: Enable (used when YPbPr input). SOGFLT 5 SOG Filter (low-pass filter on SOG input). 0: Disable. 1: Enable. SOG_LVL[4:0] 4:0 SOG trigger level. 5‘b00000: 10mV; 5‘b00001: 20mV; … … 5‘b11110: 310mV; 5‘b11111: 320mV. HS_LVL 7:0 Default: 0x00 ADCBW[2:0] 7:5 ADC Bandwidth. - 4 Reserved. - 3 Reserved. HL_LVL[2:0] 2:0 HSYNC trigger level. STATUS1 7:0 Default: - Access : R/W Access : RO Note: PLL status is read based on STAT[2:0] (Reg_03h). 7 Version 0.3 When STAT[2:0] = 000: LOCK: PLL Lock status. If 1, PLL is in lock. 6 IQ: PLL Lock status. If 1, PLL is in stable lock, and now capable of filtering spurious HSYNC inputs. 5 SLOW. - 14 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 ADC Register (Bank=01) 4 17h 18h 19h 3:0 Reserved. - 7:0 Default : - - 7:0 Reserved. STATUS5 7:0 Default: - RCMP[7:0] 7:0 DVI termination resistor status in 2’s complement (DVI feature only). Positive value represents resistor value on low side, and RT_CTL needs to adjust to higher values for compensation. Negative value represents resistor value on high side, and RT_CTL needs to adjust to lower values for compensation. STATUS4 7:0 Default: PH_STAT[7:0] 1Ah 7 STATUS5 7:0 PH_STAT[15:8] 1Bh 7 DVI_PHR 7:0 OVPR 1Ch 7 1Fh DVI phase status indicator in 2’s complement (DVI feature only). Default : - Access : RO DVI phase status indicator in 2’s complement (DVI feature only). Default : 0x80 Access : R/W DVI_PHG 7:0 Default : 0x80 7 Access : R/W OVPHG 6:0 Freeze and override DVI red channel PLL phase selection with OVPHG[6:0]. DVI_PHB 7:0 Default : 0x80 7 Access : R/W OVPHB 6:0 Freeze and override DVI red channel PLL phase selection with OVPHB[6:0]. DVI_ERST 7:0 Default : 0x00 DRR_ST[7:0] 7:0 DVI bit error status indicator. DVI_ERTH 7:0 Default : 0x00 7:0 DVI bit error tolerance threshold. / Clamp skipping on/select in ADC mode. CLPSKIP[7] Version 0.3 Access : RO 6:0 ERR_TH[7:0] CLPSKIP[7:0] 20h Access : RO OVPHR OVPB 1Eh Access : - Freeze and override DVI red channel PLL phase selection with OVPHR[6:0]. OVPG 1Dh FAST. / 7 Access : R/W Access : R/W Clamp skipping on. CLPSKIP[3:0] 3:0 Clamping skipping select. TESTEN 7:0 Default : 0x00 TESTEN 7 Access : R/W Enable Test Mode. 0: Disable. 1: Enable. - 15 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 ADC Register (Bank=01) ERRCHSEL[1:0] Channel select for DVI error status indicator (DVI feature only). 00: Red channel. 01: Green channel. 10: Blue channel. 11: Reserved. ERRD 3 DVI bit error status indicator (ERR_ST) enable (DVI feature only). 0: Normal. 1: Read status. RDST 2 Terminator resistance status (RCMP) and DVI phase status enable (DVI feature only). 0: Normal. 1: Read status. 1:0 Channel Select for DVI phase status (DVI feature only). 00: Red channel. 01: Green channel. 10: Blue channel. 11: Reserved. ~ - 7:0 Default : - - 7:0 Reserved. TESTMOD 7:0 Default : 0x06 2Dh 2Eh 2Fh Access : Access : R/W - 7 Reserved. - 6:5 Reserved. TESTMOD[4:0] 4:0 LVDS/RSDS differential output swing control. 5’b01000: 5.0mA for LVDS/ 2.5mA for RSDS 5’b00111: 4.6mA for LVDS/ 2.3mA for RSDS 5’b00110: 4.2mA for LVDS/ 2.1mA for RSDS ~ - 7:0 Default : - - 7:0 Reserved. PLLCTRLV 7:0 Default : 0xC6 WDTOL[1:0] 7:6 PLL Watchdog threshold. IQCLR_TH[2:0] 5:3 PLL unstable lock threshold. IQSET_TH[2:0] 2:0 PLL stable lock threshold. ~ - 7:0 Default : - - 7:0 Reserved. DAC_CTRL 7:0 Default : 0x00 - 7:5 Reserved 30h 31h 3Ch Reserved. 5:4 PHSEL[1:0] 21h 2Ch 6 3Dh Version 0.3 Access : Access : R/W Access : Access : R/W - 16 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 ADC Register (Bank=01) CMPATEN 31h FFh 4 Compatible bit. - 3:0 Reserved. ~ - 7:0 Default : - - 7:0 Reserved. Access : - Digital Image Processor Register (Bank = 00) Digital Image Processor Register (Bank=00) Index Mnemonic Bits Description 01h DBFC 7:0 Default : 0x80 7:3 Reserved. 2:1 Double buffer load. 00: Keep old register value. 01: Load new data (auto reset to 00 when load finish). 10: Automatically load data at VSYNC blanking. 11: Reserved. DBL[1:0] DBC 02h ISELECT NIS STYPE[1:0] Version 0.3 0 7:0 7 6:5 Access : R/W Double buffer control. 0: Double buffer disable. 1: Double buffer enable. Default : 0x00 Access : R/W Output lock mode. 0: Lock input (input signal exits). 1: Free-run (no input signal). Input Sync Type. 00: Auto detected. 01: Input is separated HSYNC and VSYNC. 10: Input is Composite sync. 11: Input is sync-on-green (SOG). COMP 4 CSYNC/SOG select (only useful when STYPE = 00). 0: CSYNC. 1: SOG. CSC 3 CSC function. 0: Disable (RGB -> RGB). 1: Enable (YCbCr -> RGB). IHSU 2 Input Sync Usage. When ISEL=00 or 01: 0: Use HSYNC to perform mode detection, HSOUT from ADC to sample pixel. 1: Use HSYNC only. When ISEL=10: - 17 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Normal. 1: Enable DE Ahead/Delay adjust. When ISEL=11: 0: Normal. 1: Output Black at blanking. 03h 04h 05h Version 0.3 ISEL[1:0] 1:0 00: 01: 10: 11: Analog 1. Analog 2. DVI. Video. - 7:0 Default : - - 7:0 Reserved. IPCTRL2 7:0 Default : 0x18 Access : Access : R/W DHSR 7 Digital Input Horizontal Sample Range. 0: Use DE as sample range, only V position can be adjusted. 1: Use SPRHST and SPRHDC as sample range, both H and V position can be adjusted. DEON 6 DE Only. HSYNC and VSYNC are ignored. 0: Disable. 1: Enable. IVSD 5 Input VSYNC Delay select. 0: Delay 1/4 input HSYNC (recommended). 1: No delay. HSE 4 Input HSYNC reference edge select. 0: From HSYNC leading edge, default value. 1: From HSYNC tailing edge. VSE 3 Input VSYNC reference edge select. 0: From VSYNC leading edge, default value. 1: From VSYNC tailing edge. ESLS 2 Early Sample Line Select. 0: 8 lines. 1: 16 lines. VWRP 1 Input image Vertical wrap. 0: Disable. 1: Enable. HWRP 0 Input image Horizontal wrap. 0: Disable. 1: Enable. SPRVST-L 7:0 Default : 0x10 Access : R/W, DB SPRVST[7:0] 7:0 Image vertical sample start point, count by input HSYNC. - 18 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 06h 07h 08h SPRVST-H 7:0 Default : 0x00 Access : R/W, DB 7:3 Reserved. SPRVST[10:8] 2:0 Image vertical sample start point, count by input HSYNC. When Reg. 52, 51, 50 < 90 00 00, SPRHST is multiplied by 2 internally. SPRHST-L 7:0 Default : 0x01 SPRHST[7:0] 7:0 Image horizontal sample start point, count by input dot clock. SPRHST-H 7:0 Default : 0x00 SPRHSTLSB 7 Back 1 LSB, sample range will move 1 pixel left. - 6 Reserved. - 5 Reserved. - 4 Reserved. Access : R/W, DB Access : R/W, DB SPRGST[11:8] 3:0 Image horizontal sample start point, count by input dot clock. SPRVDC-L 7:0 Default : 0x10 SPRVDC[7:0] 7:0 Image vertical resolution (vertical display enable area count by line). SPRVDC-H 7:0 Default: 0x00 7:3 Reserved. SPRVDC[10:8] 2:0 Image vertical resolution (vertical display enable area count by line). When Reg. 52, 51, 50 < 90 00 00, SPRVST is multiplied by 2 internally. SPRHDC-L 7:0 Default : 0x10 SPRHDC[7:0] 7:0 Image horizontal resolution (horizontal display enable area count by pixel). SPRHDC-L 7:0 Default : 0x00 7:4 Reserved. 3:0 Image horizontal resolution (horizontal display enable area count by pixel). 0Dh ~ 0Eh - 7:0 Default : - 7:0 Reserved. 0Fh 7:0 Default : 0x00 7:5 Reserved. 09h 0Ah 0Bh 0Ch SPRHDC[11:8] 10h Version 0.3 LYL 3LVRCEN 4 LYL[3:0] 3:0 Lock Y Line. DEVST-L 7:0 Default : 0x00 Access : R/W, DB Access : R/W Access : R/W Access : R/W Access : Access : R/W 3 Line Vertical Resolution Conversion Enable. Access : R/W - 19 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh Version 0.3 DEVST[7:0] 7:0 Output DE Vertical Start. DEVST-H 7:0 Default : 0x00 7:3 Reserved. DEVST[10:8] 2:0 See description for DEVST[7:0]. DEHST-L 7:0 Default : 0x03 DEHST[7:0] 7:0 Output DE Horizontal Start. DEHST-H 7:0 Default : 0x00 7:3 Reserved. DEHST[10:8] 2:0 See description for DEHST[7:0]. DEVEND-L 7:0 Default : 0x06 DEVEND[7:0] 7:0 Output DE Vertical END. DEVEND-H 7:0 Default : 0x00 7:3 Reserved. DEVEND[10:8] 2:0 See description for DEVEND[7:0]. DEHEND-L 7:0 Default : 0x00 DEVEND[7:0] 7:0 Output DE Horizontal END. DEHEND-H 7:0 Default : 0x00 7:3 Reserved. DEVEND[10:8] 2:0 See description for DEVEND[7:0]. OIHST-L 7:0 Default : 0x00 OIHST[7:0] 7:0 Output Image window Horizontal Start. OIHST-H 7:0 Default : 0x00 7:3 Reserved. OIHST[10:8] 2:0 See description for OIHST[7:0]. OIVEND-L 7:0 Default : 0x06 OIVEND[7:0] 7:0 Output Image window Vertical END. OIVEND-H 7:0 Default : 0x00 7:3 Reserved. OIVEND[10:8] 2:0 See description for OIVEND[7:0]. OIHEND-L 7:0 Default : 0x00 OIHEND[7:0] 7:0 Output Image window Horizontal END. OIHEND-H 7:0 Default : 0x00 7:3 Reserved. OIHEND[10:8] 2:0 See description for OIHEND[7:0]. VDTOT-L 7:0 Default : 0x03 Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 20 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 1Fh 20h 21h VDTOT[7:0] 7:0 Output Vertical Total. VDTOT-H 7:0 Default : 0x00 7:3 Reserved. VDTOT[10:8] 2:0 See description for VDTOT[7:0]. VSST-L 7:0 Default : 0x03 VSST[7:0] 7:0 Output VSYNC start (only useful when AOVS=1). VSST-H 7:0 Default : 0x00 7:4 Reserved. VSRU 22h 23h 24h 25h 26h 27h Version 0.3 3 Access : R/W Access : R/W Access : R/W VSYNC Register Usage. 0: Registers 20h – 23h are used to define output VSYNC. 1: Registers 20h and 21h are used to define No signal VSYNC. Registers 22h and 23h are used to define minimum H total. VSST[10:8] 2:0 See description for VSST[7:0]. VSEND-L 7:0 Default : 0x06 VSEND[7:0] 7:0 Output VSYNC END (only useful when AOVS=1). VSEND-H 7:0 Default : 0x00 7:3 Reserved. VSEND[10:8] 2:0 See description for VSEND[7:0]. HDTOT-L 7:0 Default : 0x03 HDTOT[7:0] 7:0 Output Horizontal Total. HDTOT-H 7:0 Default : 0x00 7:4 Reserved. HDTOT[11:8] 3:0 See description for HDTOT[7:0]. HSEND 7:0 Default : 0x00 HSEND[7:0] 7:6 Output HSYNC Pulse width. OSCTRL1 7:0 Default : 0x4C Access : R/W Access : R/W DB Access : R/W DB Access : R/W Access : R/W Access : R/W AOVS 7 Auto Output VSYNC. 0: OVSYNC is defined automatically. 1: OVSYNC is defined manually (register 0x20 – 0x23). - 6 Reserved. HRSM 5 HSYNC Remove Mode. 0: Normal. 1: Remove HSYNC when GPOA (Bank 2 register 0x62 – 0x6A) is low. VSGP 4 VSYNC use GPO9. 0: Disable. 1: Enable (using Bank 2 register 0x59 – 0x61 to define - 21 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) OVSYNC). 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh EHTT 3 Even H Total. 0: Enable, Output H Total always be even pixels. 1: Disable, Output H Total always be odd pixels. - 2 Reserved. AHRT 1 Auto H total and Read start Tuning enable. 0: Disable. 1: Enable. CTRL 0 0: Disable. 1: Enable. OSCTRL2 7:0 Default : 0x00 - 7:0 Reserved. - 7:0 Default : - - 7:0 Reserved. BRC 7:0 Default : 0x00 - 7:1 Reserved. Access : Access : R/W BRC 0 BCR 7:0 Default : 0x80 BCR[7:0] 7:0 Brightness Coefficient – Red color. 00h: -128. 80h: 0, default value. FFh: +127. BCG 7:0 Default : 0x80 BCG[7:0] 7:0 Brightness Coefficient – Green color. 00h: -128. 80h: 0, default value. FFh: +127. BCB 7:0 Default : 0x80 BCB[7:0] 7:0 Brightness Coefficient – Blue color. 00h: -128. 80h: 0, default value. FFh: +127. CNTR 7:0 Default : 0x00 CNREN[6:5] Version 0.3 Access : R/W 7 6:5 Brightness function, reference to register 2Bh, 2Ch, and 2Eh. 0: Off. 1: On. Access : R/W Access : R/W Access : R/W Access : R/W Reserved. Contrast Noise Rounding Enable. 11: Enable. - 22 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 2Fh 30h 31h 32h 33h 34h 35h 36h Version 0.3 CCLR 4 Contrast Coefficient LSB – Red color. CCLG 3 Contrast Coefficient LSB – Green color. CCLB 2 Contrast Coefficient LSB – Blue color. CNTT 1 Contrast Type select. 0: Use 0 as center point. 1: Use 128 as center point. CNTR 0 Contrast function. 0: Off. 1: On. CCR 7:0 Default : 0x80 CCR[7:0] 7:0 Contrast Coefficient – Red color. 00h: 0.0000000. 80h: 1.0000000. Default value. FFh: 1.1111111. CCG 7:0 Default : 0x80 CCG[7:0] 7:0 Contrast Coefficient – Green color. 00h: 0.0000000. 80h: 1.0000000. Default value. FFh: 1.1111111. CCB 7:0 Default : 0x80 CCB[7:0] 7:0 Contrast Coefficient – Blue color. 00h: 0.0000000. 80h: 1.0000000. Default value. FFh: 1.1111111. FWC 7:0 Default : 0x00 - 7:1 Reserved. FWC 0 FCR 7:0 Default : 0x00 FCR[7:0] 7:0 Border Color – Red channel. FCG 7:0 Default : 0x00 FCG[7:0] 7:0 Border Color – Green channel. FCR 7:0 Default : 0x00 FCB[7:0] 7:0 Border Color – Blue channel. DITHCTRL 7:0 Default : 0x02 DITHG[1:0] 7:6 Dither coefficient for G channel. DITHB[1:0] 5:4 Dither coefficient for B channel. Access : R/W Access : R/W Access : R/W Access : R/W Border Color (will be used when output is in free-run mode). 0: Off. 1: On. Access : R/W Access : R/W Access : R/W Access : R/W - 23 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 37h 38h Version 0.3 SROT 3 Spatial coefficient Rotate. 0: Disable. 1: Enable. TROT 2 Temporal coefficient Rotate. 0: Disable. 1: Enable. OBN 1 Output Bits Number (used for 8/10-bit gamma). 0: 8-bit output. 1: 6-bit output (power on default value). DITH 0 Dither function. 0: Off. 1: On. DITHCOEF 7:0 Default : 0x20 TL[1:0] 7:6 Top – Left dither coefficient. TR[1:0] 5:4 Top – Right dither coefficient. BL[1:0] 3:2 Bottom – Left dither coefficient. BR[1:0] 1:0 Bottom – Right dither coefficient. TRFN 7:0 Default : 0x00 PSRD 7 Pseudo Random, resets every 4 frames. 0: Enable. 1: Disable. NDMD 6 Noise Dithering Method. DATP 5 Dither based on Auto Phase threshold. 0: Disable. 1: Enable. DRT 4 Dither Rotate Type. 0: EOR. 1: Rotate. DT3 3 Dither Type 2 control. 0: Disable dither type 2. 1: Enable dither type 2. DT2 2 Dither Type 2. 0: Output data bits 1 and 0 according to input pixel value. 1: Output data bits 2, 1 and 0 according to input pixel value. DT1 1 Dither Type 1. 0: Normal. 1: Output data bits 1 and 0 are always 00. TDFNC 0 Tempo-Dither Frame Number Control. 0: Tempo-dither every frame. Access : R/W Access : R/W - 24 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 1: Tempo-dither every 2 frames. 39h DITHCTRL2 7:0 Default : 0x00 - 7:5 Reserved. GAMMAPR GATECLK 3Ah 3:1 0 Gamma Protection Reserved. Gated clock. BFRACDIV_L 7:0 BFRACDIV[7:0] 0 BFRACDIV_H 7:0 Default : 0x00 - 7:3 Reserved. BFRACDIV[15:8] 7:0 See description for BFRACDIV[7:0]. BFRACV_L 7:0 Default : 0x00 BFRACV[7:0] 0 BFRACV_H 7:0 Default : 0x00 - 7:3 Reserved. BFRACV[10:8] 2:0 See description for BFRACV[7:0]. ~ - 7:0 Default : - - 7:0 Reserved. GAMMAC 7:0 Default : 0x00 - 7:6 Reserved. 3Bh 3Ch 3Dh 3Eh 3Fh 4 Access : R/W 40h 42h Version 0.3 Access : R/W Access : RO Blanking fraction value. 5 Dither function Minus Type GNREN 4 Gamma Noise Round Enable. 3:2 Access : R/W Blanking fraction divider. DITHMTYPE BTCS[1:0] 41h Default : 0x00 Access : RO Access : Access : R/W Gamma Table Channel Select. 00: Write red channel. 01: Write green channel. 10: Write blue channel. 11: Write red/green/blue channel. GTIO 1 Gamma Table I/O access. 0: Disable. 1: Enable. GCFE 0 Gamma correction function enable. 0: Off. 1: On. GAMMAP 7:0 Default : 0x00 GAMMAP[7:0] 7:0 Gamma data Port. OCTRL1 7:0 Default : 0x00 Access : R/W Access : R/W - 25 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 43h Version 0.3 LCPS 7 LVDS Channel Polarity Swap (P/N swap). 0: Disable. 1: Enable. LCS 6 LVDS Channel Swap. 0: Disable. 1: Enable. When enabled in dual LVDS: LVA0M/LVA3M swap, LVA0P/LVA3P swap, LVA1M/LVACKM swap, LVA1P/LVACKP swap, LVB0M/LVB3M swap, LVB0P/LVB3P swap, LVB1M/LVBCKM swap, LVB1P/LVBCKP swap. When enabled in single LVDS: LVA0M/LVA3M swap, LVA0P/LVA3P swap, LVA1M/LVACKM swap, LVA1P/LVACKP swap. MLXT 5 MSB/LSB Exchange Type. 0: Always reverse bit[7:0]. 1: Reverse bit[7:2] when 6-bit panel. LTIM 4 LVDS TI Mode. 0: Normal. 1: TI Mode. OMLX 3 Odd channel MSB/LSB Exchange. 0: Normal. 1: Exchange. EMLX 2 Even channel MSB/LSB Exchange. 0: Normal. 1: Exchange. ORBX 1 Odd channel Red/Blue bus Exchange. 0: Normal. 1: Exchange. ERBX 0 Even channel Red/Blue bus Exchange. 0: Normal. 1: Exchange. OCTRL2 7:0 Default : 0x00 Access : R/W TCOP 7 TCON Control Pin port select (only used when )BN=1, 6-bit output). 0: Use output data port. 1: Use video in port. DOT 6 Differential Output Type. 0: LVDS/RSDS. 1: Reduced-swing LVDS/increased-swing RSDS. WHTS 5 White Screen (screen off). - 26 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Disable. 1: Enable. 44h BLSK 4 Black Screen (screen off). 0: Disable. 1: Enable. REV 3 Reverse luminosity. 0: Off. 1: On. STO 2 Stagger Output (only used when DPO=1). 0: Disable. 1: Enable. DPX 1 A/B Port Swap (only used when DPO=1). 0: Disable. 1: Enable. DPO 0 Dual Pixel Output. 0: Single pixel. 1: Dual pixel. OCTRL3 7:0 Default : 0x00 - 7:5 Reserved. CKSEL[4:0] 4:0 Enable clock of internal control. Supposed input interface (ADC/DVI) as the left-side. CKSEL[4] CKSEL[3] CKSEL[2] CKSEL[1] CKSEL[0] 45h 4Ah 4 3 2 1 0 Enable clock of down-side GPO. Enable clock of up-side channel. Enable clock of down-side channel. Enable clock of right-side GPO. Enable clock and output current of right-side channel. Please use ADC bank register 0x2D bit 7 to control LVDS internal clock. 01h: LVDS output. 1Dh: Dual-Link RSDS output with down-side GPO. 0Fh: Dual-Link RSDS output with right-side GPO. 15h: Single-Link RSDS output with down-side GPO. 07h: Single-Link RSDS output with right-side GPO. 00h: TTL output. ~ - 7:0 Default : - - 7:0 Reserved. BLENDC 7:0 Default : 0x00 4Bh CKIND[3:0] Version 0.3 7 6:3 Access : R/W Access : Access : R/W Reserved. Color Index of Color Key. 0000: Color index 0. - 27 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0001: Color index 1. … … 1111: Color index 15. When OSD register 0x10[7]=1, OSD is not backward compatible. When OSD register 0x10[7]=0, OSD is backward compatible. When 8-color palette is selected, only CKIND[2:0] are used. When 16-color palette is selected, OSD0xE0 bit[6] is color key bit[3] instead of using CKIND[3]. 4Ch ABM[2:0] 2:0 Alpha Blending Mode. 000: No alpha blending. 001: Background alpha blending. 010: Foreground alpha blending. 011: Color key alpha blending. 100: Not color key alpha blending. 101: Entire OSD alpha blending. 11x: Reserved. BLENDL 7:0 Default : 0x00 - 7:6 Reserved. NBM 5 Access : R/W New Blending Level. 0: Original blending level (BLENDL = 000 means 0% transparency). 1: New blending level (BLENDL = 000 means 12.5% transparency). - 4:3 Reserved. BLENDL[2:0] 2:0 OSD alpha blending Level. 000: 12.5% transparency. 001: 25.0% transparency. 010: 37.5% transparency. 011: 50.0%% transparency. 100: 62.5% transparency. 101: 75.0% transparency. 110: 87.5% transparency. 111: 100% transparency. 4Dh ~ 4Fh - 7:0 Default : - 7:0 Reserved. 50h RDCRH-L 7:0 Default : 0x00 RDCRH[7:0] 7:0 Horizontal resolution down-conversion ratio (4 bits integer, 19 bits fraction), support to 1/15.9999. (don’t support horizontal resolution up-conversion) xxxx.xxxxxxxxxxxxxxxxxxx Version 0.3 Access : Access : R/W - 28 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 51h 52h RDCRH-M 7:0 Default : 0x00 RDCRH[15:8] 7:0 See description for RDCRH[7:0]. RDCRH-H 7:0 Default : 0x00 RDCENH 53h 54h 55h 56h 57h 58h 59h Version 0.3 7 Access : R/W Access : R/W Horizontal Resolution Down-conversion Enable. (don’t support horizontal resolution up-conversion) 0: Disable. 1: Enable. RDCRH[22:16] 6:0 See description for RDCRH[7:0]. RCRV-L 7:0 Default : 0x00 RCRV[7:0] 7:0 Vertical Resolution conversion ratio (2 bits integer, 20 bits fraction), support to 1/2.9999. xx.xxxxxxxxxxxxxxxxxxxx RCRV-M 7:0 Default : 0x00 RCRV[15:8] 7:0 See description for RCRV[7:0]. RCRV-H 7:0 Default : 0x00 Access : R/W Access : R/W Access : R/W RCENV 7 Vertical Resolution Conversion Enable. 0: Disable. 1: Enable. VFMD 6 Vertical Resolution conversion Factor Mode. 0: N-1/M-1 for vertical resolution conversion factor. 1: N/M for vertical resolution conversion factor. RCRV[21:16] 5:0 See description for RCRV[7:0]. RDCFH 7:0 Default : 00x0 RDCFH1[3:0] 7:4 Horizontal resolution down-conversion Filter for Edge. RDCFH2[3:0] 3:0 Horizontal resolution down-conversion Filter for No Edge. RCFV 7:0 Default : 0x00 RCFV[7:0] 7:0 Vertical 57h 00 11 11 11 22 33 55 Access : - Access : resolution 59h X 00 22 33 33 11 00 conversion Description BI BI BG (2) BG (1.5) BM (1.5) BS (0.75) CB (0) Filter. HDSUSG 7:0 Default : 0x00 Access : - HDSUSG[7:0] 7:0 Horizontal DSUS resolution down-conversion Parameter. HDSUSL 7:0 Default : 0x00 Access : - - 29 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 5Ah 5Bh 5Ch - 7 Reserved. HFMD 6 Horizontal resolution down-conversion Factor Mode. 0: N-1/M-1 for horizontal resolution down-conversion factor. 1: N/M for horizontal resolution down-conversion factor. GSR 5 Gray scale Sensitive Register IO. 0: Disable. 1: Enable. TSR 4 Text Sensitive Register IO. 0: Disable. 1: Enable. TXTJL[3:0] 3:0 Text Judge Level. VDSUSG 7:0 Default: 0x00 M_CSC_EN 7 Main window CSC enable (RGB-> YUV) S_CSC_EN 6 MWE window CSC enable (RGB-> YUV) VDSUSG[5:0] 5:0 Vertical DSUS resolution conversion Parameter. VDSUSL 7:0 Default: 0x01 Access : - MCKS 7 Manual Clock Select. 0: Auto select. 1: Manual select. IOCK 6 Input / FIX Clock Select (when MCKS=1). 0: FIXCLK faster, FIXCLK defined by Reg_D1h, bit[7]. 1: IDCLK faster. GSE 5 Gray scale Sensitive Function Enable. 0: Disable. 1: Enable. TSE 4 Text Sensitive function Enable. 0: Disable. 1: Enable. DSUSL[3:0] 3:0 DSUS resolution conversion Parameter Level. PFEN 7:0 Default: 0x00 - 7:6 Reserved. Access : R/W PFCOEF-H[4] 5 1: Add 2 to coefficient values of PFCOEF-H[3:0] (see below). PFCOEF-L[4] 4 1: Add 2 to coefficient values of PFCOEF-L[3:0] (see below). MWE_EN 3 MWE function Enable 0: Disable 1: Enable PFEN Version 0.3 Access : - 2:1 0 Reserved. Post Filter Enable. - 30 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Disable. 1: Enable. 5Dh 5Eh PFCOEF 7:0 Default: 0x00 PFCOEF-H[3:0] 7:4 Post Filter H Coefficient for edge part. 0000: Blur – 0.0; 0001: 0.125; 0010: 0.25; 0011: 0.375; 0100: 0.5; 0101: 0.625; 0110: 0.75; 0111: 8.875; 1000: No action – 1.0; 1001: 1.125; 1010: 1.25; 1011: 1.375; 1100: 1.5; 1101: 1.625; 1110: 1.75; 1111: Sharp – 1.875. PFCOEF-L[3:0] 3:0 Post Filter L Coefficient for edge part. 0000: Blur – 0.0; 0001: 0.125; 0010: 0.25; 0011: 0.375; 0100: 0.5; 0101: 0.625; 0110: 0.75; 0111: 0.875; 1000: No action – 1.0; 1001: 1.125; 1010: 1.25; 1011: 1.375; 1100: 1.5; 1101: 1.625; 1110: 1.75; 1111: Sharp – 1.875. - 7:0 Default: 0x00 CTHRD[7:4] 7:4 Coring threshold. STP[2:1] Version 0.3 3 2:1 Access : R/W Access : R/W Reserved. Step. - 31 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) VDEN 5Fh 64h Video Enable. ~ - 7:0 Default : - - 7:0 Reserved. FTAPEN 7:0 Default : 0x00 - 7:6 Reserved. 65h sRGBNE 5 sRGB Noise round Enable. 0: Disable. 1: Enable. sRBGP 4 sRGB Precision. 0: Normal. 1: Shift 2 bits. sRGBG 3 sRGB go through Gamma. 0: Bypass gamma. 1: Go to gamma. TPP 2 Test Pattern Position. 0: After sRGB. 1: Before sRGB. FFSEL[1:0] 1:0 Filter Function Select. 00: Disable. 01: Enable 3 tap function. 1x: Enable sRGB function. sRGB12 7:0 Default : 0x00 sRGB12[7:0] 7:0 Coefficient 12, 1 sign bit, 7 bits. sRGB13 7:0 Default : 0x00 sRGB13[7:0] 7:0 Coefficient 13, 1 sign bit, 7 bits. sRGB21 7:0 Default : 0x00 sRGB21[7:0] 7:0 Coefficient 21, 1 sign bit, 7 bits. sRGB23 7:0 Default : 0x00 sRGB23[7:0] 7:0 Coefficient 23, 1 sign bit, 7 bits. sRGB31 7:0 Default : 0x00 sRGB31[7:0] 7:0 Coefficient 31, 1 sign bit, 7 bits. sRGB32 7:0 Default : 0x00 sRGB32[7:0] 7:0 Coefficient 32, 1 sign bit, 7 bits. ~ - 7:0 Default : - - 7:0 Reserved. INTMDS 7:0 Default : 0x00 - 7:5 Reserved. 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Eh 0 6Fh Version 0.3 Access : Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : Access : R/W - 32 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) ILIM 4 Insert Line when Interlace Mode. 0: Do not insert. 1: Insert. ODDF 3 Shift Odd Field. 0: Shift even field. 1: Shift odd field. SLN[2:0] 71h 77h 2:0 Shift Line Numbers. 000: Shift 0 line between odd and even fields. 001: Shift 1 line between odd and even fields. 010: Shift 2 line between odd and even fields. 011: Shift 3 line between odd and even fields. 1xx: Shift 4 line between odd and even fields. ~ - 7:0 Default : - - 7:0 Reserved. ATGCTRL 7:0 Default : 0x00 78h Version 0.3 Access : R/W Access : R/W MAXR 7 Max value flag for red channel (read only). 0: Normal. 1: Max value (255) value when AGR = 0. Output over max value (255) when AGR = 1. MAXG 6 Max value flag for green channel (read only). 0: Normal. 1: Max value (255) value when AGR = 0. Output over max value (255) when AGR = 1. MAXB 5 Max value flag for blue channel (read only). 0: Normal. 1: Max value (255) value when AGR = 0. Output over max value (255) when AGR = 1. ACE 4 ADC Calibration Enable. 0: Disable. 1: Enable. AGR 3 Auto Gain Result selection. 0: Output has max/min value. 1: Output is overflow/underflow. ATGM 2 Auto Gain Mode. 0: Normal mode (result will be cleared every frame). 1: History mode (result remains not cleared till ATGE = 0). ATGR 1 Auto Gain Result Ready. 0: Result not ready. 1: Result ready. ATGE 0 Auto Gain Function Enable. - 33 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Disable. 1: Enable. 79h 7Ah ATGST Default : - Access : RO VCLP 7 Video auto gain mode. 0: RGB mode. 1: YPbPr Mode. - 6 Reserved. CALR 5 Calibration value flag for Red channel. 0: Normal. 1: Calibration result (needs to increase offset) when ACE = 1. CALG 4 Calibration value flag for Green channel. 0: Normal. 1: Calibration result (needs to increase offset) when ACE = 1. CALB 3 Calibration value flag for Blue channel. 0: Normal. 1: Calibration result (needs to increase offset) when ACE = 1. MINR 2 Min value flag for Red channel. 0: Normal. 1: Min value (0) present when AGR = 0, ACE = 0. Output under min value (0) when AGR = 1, ACE = 0. Calibration result (needs to decrease offset) when ACE = 1. MING 1 Min value flag for Green channel. 0: Normal. 1: Min value (0) present when AGR = 0, ACE = 0. Output under min value (0) when AGR = 1, ACE = 0. Calibration result (needs to decrease offset) when ACE = 1. MINB 0 Min value flag for Blue channel. 0: Normal. 1: Min value (0) present when AGR = 0, ACE = 0. Output under min value (0) when AGR = 1, ACE = 0. Calibration result (needs to decrease offset) when ACE = 1. ATFCHSEL 7:0 Default: 0x00 - 7:6 Reserved. ATPCHSEL[1:0] 5:4 Auto Phase R/G/B channel select 00: R/G/B 3 channels 01: only R channel 10: only G channel 11: only B channel ATGCHSEL[2:0] Version 0.3 7:0 3 2:0 Access : R/W Reserved. Auto Gain R/G/B channel min/max value select. - 34 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 000: R min value 001: G min value 010: B min value 011: R max value 100: G max value 101: B max value 11x: Reserved 7Bh 7Ch Version 0.3 ATOCTRL 7:0 Default : 0x00 Access : R/W JITLR 7 Jitter function Left / Right result for 86h and 87h. 0: Left result. 1: right result. JITS 6 Jitter Software clear. 0: Not clear. 1: Clear. - 5 Reserved. JITM 4 Jitter function Mode. 0: Update every frame. 1: Keep the history value. JITR 3 Jitter function Result. 0: No jitter. 1: Jitter present. ATOM 2 Auto position function Mode. 0: Update every frame. 1: Keep the history value. ATOR 1 Auto position result Ready. 0: Result ready. 1: Result not ready. ATOE 0 Auto position function Enable. 0: Disable. 1: Enable. Disable-to-enable needs at least 2 frame apart for ready bit to settle. AOVDV 7:0 Default : 0x00 Access : R/W AOVDV[3:0] 7:5 Auto position Valid Data Value. 0000: Valid if data >= 0000 0000. 0001: Valid if data >= 0001 0000. 0010: Valid if data >= 0010 0000. … … 1111: Valid if data >= 1111 0000. - 4:0 Reserved. - 35 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h Version 0.3 ATGVALUE 7:0 Default: - Access : RO ATGVALUE[7:0] 7:0 Auto Gain result based on 7Ah[2:0]. AOVST-L 7:0 Default : - AOVST [7:0] 7:0 Auto position detected result Vertical Starting point. AOVST-H 7:0 Default : - - 7:3 Reserved. AOVST[10:8] 2:0 See description for AOVST [7:0]. AOHST-L 7:0 Default : - AOHST[7:0] 7:0 Auto position detected result Horizontal Starting point. AOHST-H 7:0 Default : - 7:3 Reserved. SPRGST[10:8] 2:0 Image horizontal sample start point, count by input dot clock. AOVEND-L 7:0 Default : - AOVEND[7:0] 7:0 Auto position detected result Vertical End point. AOVEND-H 7:0 Default : - - 7:3 Reserved. AOVEND[10:8] 2:0 See description for AOVEND[7:0]. AOHEND-L 7:0 Default : - AOHEND[7:0] 7:0 Auto position detected result Horizontal End point. AOHEND-H 7:0 Default : - - 7:4 Reserved. AOHEND[11:8] 2:0 See description for AOHEND[7:0]. JLR-L 7:0 Default : - JLR[7:0] 7:0 Jitter function detected Left/Right most point state (previous frame) depend on Reg_7Bh[7]. JLR-H 7:0 Default : - - 7:3 Reserved. JLR[10:8] 2:0 See description for JLR[7:0]. ANRF 7:0 Default : - - 7:6 Reserved. Access : RO Access : RO Access : RO Access : R/W DB Access : RO Access : RO Access : RO Access : RO Access : RO Access : RO Access : RO HNEN 5 High level Noise reduction Enable. 0: Disable. 1: Enable. BGEN 4 Background Noise reduction Enable. 0: Disable. 1: Enable. - 36 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) - 89h 8Ah 8Bh 8Dh 8Eh 8Fh 90h 2:0 Auto Noise Level. 111: Noise level = 16. ATPGTH 7:0 Default : 0x01 ATPGTH[7:0] 7:0 Auto Phase Gray scale Threshold for ATPV3 when ATPN4 = 0. ATPTTH 7:0 Default : 0x10 ATPTTH[7:0] 7:0 Auto Phase Text Threshold for ATPV4. ATPCTRL 7:0 Default : 0x00 - 7 Reserved. GRY 6 Gray scale detect (read only). TXT 5 Text detect (read only). 4:2 Nose Mask. 000: Mask 0 001: Mask 1 010: Mask 2 011: Mask 3 100: Mask 4 101: Mask 5 110: Mask 6 111: Mask 7 Access : R/W Access : R/W Access : R/W bit, default value. bit. bit. bit. bit. bit. bit. bit. ATPR 1 Auto Phase Result ready. 0: Result not ready. 1: Result ready. ATPE 0 Auto Phase function Enable. 0: Disable. 1: Enable. ATPV1 7:0 Default : - ATPVALUE[7:0] 7:0 Auto Phase Value. ATPV2 7:0 Default : - ATPVALUE[15:8] 7:0 See description for ATPVALUE[7:0]. ATPV3 7:0 Default : - ATPVALUE[23:16] 7:0 See description for ATPVALUE[7:0]. ATPV4 7:0 Default : - ATPVALUE[31:24] 7:0 See description for ATPVALUE[7:0]. ASCTRL 7:0 Default : 0x90 IVB Version 0.3 Reserved. ANLV[2:0] APMASK[2:0] 8Ch 3 7 Access : RO Access : RO Access : RO Access : RO Access : R/W Input VSYNC Blanking Status. 0: In display. 1: In blanking. - 37 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) - 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah Version 0.3 6 Reserved. DLINE[1:0] 5:4 Delay Line. - 3:2 Reserved. UNDER 1 Under run status. OVER 0 Over run status. LPVP-L 7:0 Default : - LPVP[7:0] 7:0 Locking Point Vertical Position. LPVP-H 7:0 Default : - - 7:3 Reserved. LPVP[10:8] 2:0 See description for LPVP[7:0]. IFRACW-L 7:0 Default : - IFRACW[7:0] 7:0 Insert Fraction Width. IFRACW-H 7:0 Default : - - 7 Reserved. - 6 Reserved. FIELD 5 Field select.. SFRACU 4 Stop Fraction Update. - 3 Reserved. Access : RO Access : RO Access : RO Access : R/W IFRACW[10:8] 2:0 See description for IFRACW[7:0]. (read only) LVSST-L 7:0 Default : - LVSSTAT[7:0] 7:0 Locking Vertical Total line number. LVSST-H 7:0 Default : - Access : RO Access : RO - 7 Reserved. - 6:3 Reserved. LVSSTAT[10:8] 2:0 See description for LVSSTAT[7:0]. LHTST-L 7:0 Default : - LHTSTAT[7:0] 7:0 Locking HTotal Status. LHTST-H 7:0 Default : - - 7:3 Reserved. LHTSTAT[10:8] 2:0 See description for LHTSTAT[7:0]. LFRST-L 7:0 Default : 0x00 LFTSTAT[7:0] 7:0 Locking Fraction Status. LFRST-H 7:0 Default : 0x00 - 7:3 Reserved. LFTSTAT[10:8] 2:0 See description for LFTSTAT[7:0]. Access : RO Access : RO Access : R/W Access : R/W - 38 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h LMARGIN 7:0 Default : 0x00 LHTTMGN[7:0] 7:0 Locking H Total Margin. LRSV-L 7:0 Default : 0x00 LRSVALUE[7:0] 7:0 Locking Read Start Value. LRSV-H 7:0 Default : 0x00 - 7:3 Reserved. LRSVALUE[10:8] 2:0 See description for LRSVALUE[7:0]. LMARGIN 7:0 Default : 0x00 LSSCMGN[7:0] 7:0 Locking SSC Margin. - 7:0 Default : - - 7:0 Reserved. OSDIOA 7:0 Default : 0x10 Version 0.3 Access : R/W Access : R/W Access : R/W Access : Access : R/W OSBM 7 OSD SRAM I/O Access Burst Mode. 0: Disable. 1: Enable. CLR 6 OSD Clear Bit (write only). 0: Normal. 1: Clear code with 00h, attribute with 00h. CP 5 OSD 256 Color Palette I/O access. 0: Disable. 1: Enable. RF 4 OSD RAM Font I/O access. 0: Disable. 1: Enable. DC 3 OSD Display Code I/O access. 0: Disable. 1: Enable. DA 2 OSD Display Attribute I/O access. 0: Disable. 1: Enable. ORBW 1 OSD Register Burst Write mode. 0: Disable. 1: Enable. - 0 Reserved. OSDRA - A2h Access : R/W 7:0 7 Default : 0x00 Access : R/W Reserved. OSDRA[6:0] 6:0 OSD Register Address port. OSDRD 7:0 Default : 0x00 Access : R/W - 39 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) A3h A4h A5h A6h A7h A8h A9h AAh ABh OSDRD[7:0] 7:0 OSD Register Data port. RAMFA 7:0 Default: RAMFA[7:0] 7:0 OSD RAM Font Address port. RAMFD 7:0 Default : 0x00 RAMFD[7:0] 7:0 OSD RAM Font Data port. DISPCA-L 7:0 Default : 0x00 DISPCA[7:0] 7:0 OSD Display Code Address code. DISPCA-H 7:0 Default : 0x00 - 7:2 Reserved. DISPCA[9:8] 1:0 See description for DISPCA[7:0]. DISPCD 7:0 Default : 0x00 DISPCD[7:0] 7:0 OSD Display Code Data port. DISPAA-L 7:0 Default : 0x00 DISPAA[7:0] 7:0 OSD Display Attribute Address port. DISPAA-H 7:0 Default : 0x00 - 7:3 Reserved. DISPAA[10:8] 2:0 See description for DISPAA[7:0]. DISPAD 7:0 Default : 0x00 DISPAD 7:0 OSD Display Attribute Data Port. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Bank 0 register 0xD0[0] = 0 FSM FSMEN 7:0 7 Default : 0x00 Access : R/W Frame rate control Enable. 0: Disable. 1: Enable. FSMRATIO[3:0] 6:3 Output frame rate / input frame rate. Bit[3]: 1/2; Bit[2]: 1/4; Bit[1]: 1/8; Bit[0]: 1/16. - 2:0 Reserved. Bank 0 register 0xD0[0] = 1 ACh Version 0.3 TSTDATA 7:0 Default : 0x00 Access : R/W TSTDATA[7:0] 7:0 LVDS/RSDS Test mode Data. When LVDS output, use TSTDATA[7:1]. When RSDS output, use TSTDATA[7:0]. 256CPA 7:0 Default : - Access : WO - 40 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) ADh AEh 256CPA[7:0] 7:0 OSD 256 Color Palette Address port. 256CPD 7:0 Default : - 256CPD[7:0] 7:0 OSD 256 Color Palette Data port. OSDDF 7:0 Default : 0x00 RAMFA[8] DISPCD[8] - B1h B2h B3h Version 0.3 6:4 3 Access : R/W See description for RAMFA[7:0]. Reserved. See description for DISPCD[7:0]. 2:0 Reserved. 7:0 Default : DDC2BI_EN 7 0: Disable. 1: Enable. DDC2BI_ID 6:0 DDC2BI ID. WDTEN 7:0 Default : 0x01 - 7:2 Reserved. AFH B0h 7 Access : WO Access : WO Access : R/W WDTC 1 Watchdog Timer Clear (protected by WDTKEY). 0: Normal. 1: Clear. WDTE 0 Watchdog Timer Enable (protected by WDTDEY). 0: Disable. 1: Enable. WDTKEY 7:0 Default : 0x00 WDTKEY 7:0 Watchdog Timer Enable Key. To disable/clear watchdog timer, you must first write the WDTKEY with 55h, AAh to unlock. WDTCNT 7:0 Default : 0x03 WDTCNT 7:0 Watchdog Timer Counter. The clock of Watchdog timer is frequency of XTAL/(256*1024). DDCEN 7:0 Default : 0x1E GPOU[1:0] 7:6 GPO Usage. 00: GPO. 01: MPU bypass. 10: DDC bypass. 11: ISP bypass (use I2C protocol). DMEN 5 DDC Master function Enable. 0: Disable. 1: Enable. CSOK 4 DDC Check sum (read only). 0: Check sum not okay. Access : R/W Access : R/W Access : R/W - 41 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 1: Check sum okay. B4h B5h DMST 3 DDC Master function Status (read only). 0: Busy. 1: Not busy. DMF 2 DDC Master Finish. Already access 128 or 256 byte data (read only). 0: Not finish. 1: Finish. GPO[1:0] 1:0 GPO. DDCEN 7:0 Default : 0x8A D_EN1 7 DDC function Enable. 0: Disable. 1: Enable. DFLT 6 DDC Filter. 0: Enable. 1: Disable. DIWP 5 DDC I2C bus Write Protect. 0: Enable. 1: Disable. ISPT 4 ISP using RS-232 type. 0: Disable. 1: Enable. CSOK1 3 DDC Check Sum for input 1 (read only). 0: Check sum not okay. 1: Check sum okay. D_BSY1 2 DDC Busy (read only). 0: Not busy. 1: Busy. D_RW1 1 DDC last Read/Write status (read only). 0: Write. 1: Read. D_DTY1 0 DDC SRAM Dirty status (read/clear). 0: Not dirty. 1: Dirty. DDC_LAST DDCTS DDC_LAST1[6:0] Version 0.3 7:0 7 6:0 Default : - Access : R/W Access : RO DDC Type Select. 0: DDC. 1: DDC2BI. DDC Last R/W address. - 42 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) B6h DDCADDR 7:0 S_RW1 B7h B8h B9h 7 6:0 DDC Address Port. DDCDATA 7:0 Default : 0x00 DDCDATAP1[7:0] 7:0 DDC Data Port. DDCEN 7:0 Default : 0x82 D_EN2 7 See description for D_EN1. 1: Enable. D_1A_INT 6 Enable 1st DDC2BI Interrupt. D_1D_INT 5 Enable 2nd DDC2BI Interrupt. 1A_STA 4 1st Status. 1D_STA 3 2nd Status. D_BSY2 2 See description for D_BSY1. D_RW2 1 See description for D_RW1. D_DTY2 0 See description for D_DTY1. DDC_LAST 7:0 7 BCh Version 0.3 Default : - Access : R/W Access : R/W Access : RO DDC Type Select. 0: DDC. 1: DDC2BI. DDC_LAST2[6:0] 6:0 See description for DDC_LAST1[6:0]. DDCADDR 7:0 Default : 0x86 S_RW2 BBh Access : R/W DDC SRAM Read/Write. 0: Write. 1: Read. DDC_ADDRP1[6:0] DDCTS BAh Default : 0x8A 7 Access : R/W See description for S_RW1. DDC_ADDRP2[6:0] 6:0 See description for DDC_ADDRP1[6:0]. DDCDATA 7:0 Default : 0x00 DDCDATAP2[7:0] 7:0 See description for DDCDATAP1[7:0]. MISCFC 7:0 Default : 0x00 Access : R/W Access : R/W AFT 7 ATP Filter for Text (4 frames). 0: Disable. 1: Enable. IDHTT 6 DE only mode HTT count by IDCLK. 0: Disable. 1: Enable. VSGR 5 VSYNC glitch removal with line less than 2 (DE only). 0: Disable. 1: Enable. - 43 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) BDh BEh BFh C0h Version 0.3 VSP 4 VSYNC Protect with V total (DE only). 0: Disable. 1: Enable. LBGC 3 LB Clock no gating mode. 0: Disable. 1: Enable. DEGP 2 DE only mode Glitch Protect for position. 0: Disable. 1: Enable. - 1:0 Reserved. HDCPCTRL 7:0 Default : 0x00 OVER2PIN 7:6 0: Not toggling (default). 1: Toggling. - 5:4 Reserved. - 3 Reserved. - 2 Reserved. Access : R/W HDCPADR[9:8] 1:0 HDCP address port (default=0), bit 9 is reserved. HDCPADR 7:0 Default : 0x16 HDCPADR[7:0] 7:0 HDCP address port (default=0), bit 9 is reserved. HDCPDAT 7:0 Default : 0x00 HDCPDAT[7:0] 7:0 HDCP Data port. DPMSTATUS 7:0 Default : 0x08 Access : R/W Access : R/W Access : R/W VS 7 VSYNC toggling Status. 0: Not toggling. 1: Toggling. HS 6 HSYNC toggling Status. 0: Not toggling. 1: Toggling. SCDT 5 SCDT Status. 0: No SCDT. 1: SCDT valid. DEV 4 DE with Valid blanking. 0: Not valid. 1: Valid. AutoOn 3 Hardware power on upon detecting valid DVI input. 0: Disable. 1: Enable. Auto 2 Hardware Auto detection on DVI input. - 44 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Disable. 1: Enable. Manual 1 Manual detection on DVI input. 0: Off. 1: On. ManualGo 0 Manual detection trigger, auto clear to 0 if finish. 0: Off. 1: On. Note: This register is only valid when F0h[1:0] = 2’b10. C1h DPMCTL 7:0 Default : 0x00 Access : R/W DPMPrd 7:6 Hardware auto detection cycle time. 00: Default. 01: Short. 10: Shortest. DMPPulse 5:3 Hardware auto Detection Pulse Width Manual detection pm DVI input. 000: Shortest. … 111: Longest. DEMon 2 DVI DE Monitor enable. 0: Disable. 1: Enable. HVMon 1 DVI HSYNC and VSYNC Monitor enable. 0: Disable. 1: Enable. HMon 0 DVI HSYNC Monitor enable. 0: Disable. 1: Enable. Note: This register is only valid when F0h[1:0] = 2’b10. C2h Version 0.3 PWMCLK 7:0 Default : 0x00 Access : R/W DB_EN 7 Double Buffer Enable. 0: Disable. 1: Enable. P1REN 6 PWM1 Reset every frame Enable. 0: Disable. 1: Enable. P0REN 5 PWM1 Reset every frame Enable. 0: Disable. 1: Enable. - 45 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) C3h C4h C5h C6h C7h C8h C9h CAh Version 0.3 P1POL 4 PWM 1 Polarity when enhance PWM1 enable. EP1EN 3 Enhance PWM1 Enable. 0: Disable. 1: Enable. P0POL 2 PWM0 Polarity when enhance PWM0 enable. EP0EN 1 Enhance PWM0 Enable. 0: Disable. 1: Enable. PCLK 0 PWM base Clock select. 0: 14.318MHz. 1: 14.318MHz / 4. PWM0C 7:0 Default : 0x00 PWM0C[7:0] 7:0 PWM0 Coarse adjustment. PWM1C 7:0 Default : 0x00 PWM1C[7:0] 7:0 PWM1 Coarse adjustment. PWM0EP 7:0 Default : 0x00 EPWM0P[7:0] 7:0 Enhance PWM0 Period. PWM0EP 7:0 Default : 0x00 EPWM0P[7:0] 7:0 Enhance PWM0 Period. PWM1EP 7:0 Default : 0x00 EPWM1P[7:0] 7:0 Enhance PWM1 Period. PWM1EP 7:0 Default : 0x00 EPWM1P[7:0] 7:0 Enhance PWM1 Period. - 7:0 Default : 0x00 - 7:0 Reserved. INTCTROL 7:0 Default : 0x00 Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : Access : R/W HCHGM 7 HSYNC Changing detect Method. 0: Interrupt only occurred at start and end of transition. 1: interrupt occurred at every line. DCMD 6 DVI Clock Missing Detected (read only; DVI feature only, independent of bank 0 register 0x02h, ISEL[1:0]). 0: DVI clock is OK, Freq(dvi)>Freq(xtal)*EBh/128. 1: DVI clock is missing, Freq(dvi)<Freq(xtal)*EBh/128. Where EBh default to 0x1E(30). HSPM 5 ADC Mode: HSYNC Pin Monitor (read only); DVI mode: SCDT value. When input is analog: 0: HSYNC pin is low. - 46 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 1: HSYNC pin is high. When input is DVI: 0: SCDT is missing. 1: SCDT is OK. CBh CCh CDh Version 0.3 HSST 4 HS Status (read only). 0: Stable. 1: Not stable. IVSI 3 Input VSYNC Interrupted generated by: 0: Leading edge. 1: Tailing edge. OVSI 2 Output VSYNC interrupt generated by: 0: Leading edge. 1: Tailing edge. TRGC 1 Trigger Condition. 0: Active low for level trigger / tailing edge trigger. 1: Active high for level trigger / leading edge trigger. INTT 0 Interrupt Trigger. 0: Generate an edge trigger interrupt. 1: Generate a level trigger interrupt. INTPULSE 7:0 Default : 0x0F Access : R/W INTPULSE[7:0] 7:0 Interrupt Pulse Width by reference clock. INTSTA 7:0 Default : 0x00 INTSTA[7:0] 7:0 Interrupt Status byte A. Bit 7: Input VSYNC changed (co-work with register E7h). Bit 6: Input HSYNC changed (co-work with register E6h). Bit 5: Input VSYNC disappear. Bit 4: Input HSYNC disappear. Bit 3: Input VSYNC edge. Bit 2: Input HSYNC edge. Bit 1: ADC0 HSYNC0 pin toggling (independent with Reg_02h, ISEL[1:0]). Bit 0: Composite sync / SOG status change. INTSTB 7:0 Default : 0x06 INTSTB[7:0] 7:0 Interrupt Status control byte B. Bit 7: Auto phase ready. Bit 6: Auto position ready. Bit 5: Auto gain ready. Bit 4: Jitter detected. Bit 3: ADC1 HSYNC1 pin toggling. Bit 2: DVI clock status change; no clock <-> with clock. Access : R/W Access : R/C - 47 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) Bit 1: Watchdog timer. Bit 0: Under-run / Over-run occurred. CEh CFh D0h D1h INTENA 7:0 Default : 0x00 INTENA[7:0] 7:0 Interrupt Enable control byte A. 0: Disable interrupt. 1: Enable interrupt. INTENB 7:0 Default : 0x00 INTENB[7:0] 7:0 Interrupt Enable control byte A. 0: Disable interrupt. 1: Enable interrupt. PLLCTRL1 7:0 Default : 0x00 Access : R/W Access : R/W XOUT 7 Enable PWM1 as XTAL clock output. 0: Disable. 1: Enable. EOCK 6 Use External Clock (pin #) as Output Dot Clock. 0: Disable (use internal dot clock). 1: Enable (use external dot clock). XDIV 5:4 BPM 3 Bypass clock Mode (IDCLK as ODCLK). 0: Disable. 1: Enable. TSTM 2 Test Mode. 0: Disable. 1: Enable. PTEN 1 PLL Test register protect bit. 0: Disable. 1: Enable. LRTM 0 LVDS/RSDS Test Mode enable. 0: Disable. 1: Enable. PLLCTRL2 MPPDIV Version 0.3 Access : R/C 7:0 7 XTAL clock Divided by: 00: 16; 01: 08; 10: 04; 11: 01. Default : 0x00 Access : R/W Master PLL Post Divider. 0: div 3 (143 MHz). 1: div 2.5 (172 MHz), for output dot clock higher than 143 MHz (vertical = 85 MHz). - 48 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) D2h D3h LP_POR 6 Output PLL Power On Reset. LP_RST 5 Output PLL Reset. LP_PD 4 Output PLL Power Down. MP_K 3 Master PLL output frequency divided by 2. MP_PORT 2 Master PLL Power On Reset. MP_RST 1 Master PLL Reset. MP_PD 0 Master PLL Power Down. MPLL_M 7:0 Default : 0x6F MP_ICTRL[2:0] 7:5 Master PLL Current Control. MPLL_M[4:0] 4:0 Master PLL divider. LPLL_M 7:0 Default : 0x02 - 7:6 Reserved. SDMD D4h 4:0 Output PLL divider 1. LPLL_CTL2 7:0 Default : 0x0B - 7:6 Reserved. D6h D7h D8h D9h Version 0.3 5 Access : R/W Output PLL spread spectrum Mode. 0: Normal. 1: Reverse for mode 1. LPLL_M[4:0] LP_TP D5h 5 Access : R/W Access : R/W Output PLL Type. 0: LVDS. 1: RSDS/TTL. LP_K[1:0] 4:3 Output PLL divider 2. 00: 8; 01: 4; 10: 2; 11: 1. LP_ICTROL[2:0] 2:0 Output PLL Current Control. LPLL_SET 7:0 Default : 0x44 LP_SET[7:0] 7:0 Output PLL Set. LPLL_SET 7:0 Default : 0x55 LP_SET[15:8] 7:0 See description for LP_SET[7:0]. LPLL_SET 7:0 Default : 0x24 LP_SET[23:16] 7:0 See description for LP_SET[7:0]. LPLL_STEP 7:0 Default : 0x20 LPLL_STEP[7:0] 7:0 Output PLL spread spectrum Step. LPLL_STEP 7:0 Default : 0x00 Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB - 49 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) DAh DBh DCh DDh DEh - 7:3 Reserved. LPLL_STEP[10:8] 2:0 See description for LPLL_STEP[7:0]. LPLL_SPAN 7:0 Default : 0x00 LP_SPAN[7:0] 7:0 Output PLL spread spectrum Span. LPLL_SPAN 7:0 Default : 0x00 - 7:3 Reserved. LP_SPAN[10:8] 2:0 See description for LP_SPAN[7:0]. MPLL_TST 7:0 Default : 0x00 Access : R/W MP_TEST[7:0] 7:0 LPLL_TSTA 7:0 Default : 0x00 Access : R/W LP_TESTA[7:0] 7:0 LPLL_TSTD 7:0 Default : 0x00 Access : R/W 7 LPLL Lock Status. LP_LSTA DFh E0h E1h Version 0.3 LP_TESTD[7:0] 6:0 - 7:0 Default : - 7:0 Reserved. STATUS1 7:0 Default : - - 7:4 Reserved. Access : R/W, DB Access : R/W, DB Access : Access : RO IHSM 3 Input normalized HSYNC pin Monitor. Show input HSYNC pin directly. IVSM 2 Input normalized VSYNC pin Monitor. Show input VSYNC pin directly. OHSM 1 Output normalized HSYNC pin Monitor. Show output HSYNC pin directly. OVSM 0 Output normalized VSYNC pin Monitor. Show output VSYNC pin directly. STATUS2 7:0 Default : - Access : RO VSACT 7 Input VSYNC Active. 0: Not detected. 1: Detected. HSACT 6 Input HSYNC Active. 0: Not detected. 1: Detected. CSD 5 Composite Sync Detected status. 0: Input is not composite sync. 1: Input is detected as composite sync. SOGD 4 Sync-On-Green Detected status. - 50 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Input is not SOG. 1: Input is detected as SOG. E2h E3h E4h E5h INTM 3 Interlace / Non-interlace detecting result by this chip. 0: Non-interlace. 1: Interlace. INTF 2 Input odd/even field detecting result by this chip. 0: Even. 1: Odd. IHSP 1 Incoming input HSYNC polarity detecting result by this chip. 0: Active low. 1: Active high. IVSP 0 Incoming input VSYNC polarity detecting result by this chip. 0: Active low. 1: Active high. VTOTAL-L 7:0 Default : - VTOTAL[7:0] 7:0 Input Vertical Total, count by HSYNC. VTOTAL-H 7:0 Default : - - 7:3 Reserved. VTOTAL[10:8] 2:0 See description for VTOTAL[7:0]. HSPRD-L 7:0 Default : - HSPRD[7:0] 7:0 Input Horizontal Period, count by reference clock. HSPRD-H 7:0 Default : - IHDM E6h E7h Access : RO Access : RO Access : RO Input HSYNC period Detect Mode. 0: One line. 1: 16 lines. - 6:5 Reserved. HSPRD[12:8] 4:0 See description for HSPRD[7:0]. HSTOL 7:0 Default : 0x05 VS2HS 7 Input VSYNC too close to input HSYNC. DEF 6 DE Follow mode (for DE to DE period is not fixed). HSTOL[5:0] 5:0 HSYNC Tolerance. 5: Default value. VSTOL 7:0 Default : 0x01 - 7:6 Reserved. ANGF 5 Auto No signal Filter mode. ANG 4 Auto No signal. VSTOL[3:0] Version 0.3 7 Access : RO 3:0 Access : R/W Access : R/W VSYNC Tolerance. - 51 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 1: Default value. E8h E9h ISOVRD Default : 0x00 Access : R/W SL 7 Shift Line. 0: Shift line method 0. 1: Shift line method 1 for interlace mode. CSHS 6 HSYNC in coast. 0: HSOUT (recommended). 1: Re-shaped HSYNC. UVSP 5 User defined input VSYNC Polarity, active when IVSJ =1. 0: Active low. 1: Active high. IVSJ 4 Input VSYNC polarity judgment. 0: Use result of internal circuit detection. 1: Defined by user (UVSP). UHSP 3 User defined input HSYNC Polarity, active when IVSJ =1. 0: Active low. 1: Active high. IHSJ 2 Input HSYNC polarity judgment. 0: Use result of internal circuit detection. 1: Defined by user (UHSP). UINT 1 User defined non-interlace/interlace, active when INTJ = 1. 0: Non-interlace. 1: Interlace. INTJ 0 Interlace judgment. 0: Use result of internal circuit detection. 1: Defined by user (UINT). MDCTRL 7:0 Default : 0x00 Access : R/W RCFCPB 7 Resolution conversion filter Compatible select. 0: Compatible with old filter. 1: Use new filter. VERR 6 Video CCIR656 Error correct. 0: Disable. 1: Enable. 5:4 Software Compatibility Select. SCSEL[1:0] Version 0.3 7:0 VFIV 3 Video Field Inversion. 0: Normal. 1: Invert. VEXF 2 Video External Field. 0: Use result of internal circuit detection. - 52 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 1: Use external field. EAh INTF 1 Interlace Field detect method select. 0: Use the HSYNC numbers of a field to judge. 1: Use the relationship of VSYNC and HSYNC to judge. IFI 0 Interlace Field Invert. 0: Normal. 1: Invert. DVICKD 7:0 Default : - Access : RO Note: When bank 0 reg 02h[1:0] = 2’b10 (DVI feature only) OF EBh 7 DVI clock detection overflow (DVI feature only). 0: Not overflow. 1: Overflow. DVICKD[6:0] 6:0 DVI clock detection report, based on oscillator clock (DVI feature only). Freq(DVI) = Freq(xtal) * DVICKD[6:0] * 2/128, if OF = 0. Freq(DVI) > Freq(xtal) * 2, if OF = 1. DVICKTH 7:0 Default : 0x1E Access : R/W Note: When bank 0 reg 02h[1:0] = 2’b10 (DVI feature only) ECh DVICKTH[7:0] 7:0 DVI clock detection threshold, see CAh for usage (default 0x1E). CAh[6] = 0: DVI clock is OK, Freq(DVI) > Freq(xtal) * EBh/128. CAh[6] = 1: DVI clock is missing, Freq(DVI) < Freq(xtal) * EBh/128. Where EBh default to 0x1E(30). MINVTT 7:0 Default : 0x00 VFRM EDh Version 0.3 7 Access : R/W Video in free run mode (read only) MINVTT[6:0] 6:0 Min Vtt, when detected vtt<min vtt, set video free run. COCTRL1 7:0 Default : 0x00 - 7:6 Reserved. Access : R/W AVIS 5 Analog Video Input Select. 0: PC. 1: Component analog video. DLYV 4 Analog Delay Line for component analog Video input. 0: Delay 1 line. 1: Do not delay. CSCM 3 Composite SYNC cut mode. 0: Disable. 1: Enable. EXVS 2 External VSYNC polarity (only used when COVS is 1). - 53 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Normal. 1: Invert. EEh EFh F0h COVS 1 Coast VSYNC Select. 0: Internal VSEP. 1: External VSYNC. CTA 0 Coast to ADC. 0: Disable. 1: Enable. COCTRL2 7:0 Default : 0x00 COST[7:0] 7:0 Front tuning. 00: Coast start from 1 HSYNC leading edge. 01: Coast start from 2 HSYNC leading edge, default value. … 254: Coast start from 255 HSYNC leading edge. 255: Coast start from 256 HSYNC leading edge. COCTRL3 7:0 Default : 0x00 COEND[7:0] 7:0 End tuning. 00: Coast end at 1 HSYNC leading edge. 01: Coast end at 2 HSYNC leading edge, default value. … 254: Coast end at 255 HSYNC leading edge. 255: Coast end at 256 HSYNC leading edge. PDMD 7:0 Default : 0x13 APDLD 7 Automatically Power Down when Low power using Digital pin. 0: Disable. 1: Enable. APDLA 6 Automatically Power Down when Low power using Analog pin. 0: Disable. 1: Enable. PHSRM 5 PD HDCP SRAM. PDDS 4 Power Down DDC SRAM. 0: Normal. 1: Power down while not used. GCLK[1:0] PDMD Version 0.3 3:2 0 Access : R/W Access : R/W Access : R/W Gated Clock for SRAM (excluding DDC SRAM). 00: Normal. 01: V Blank. 10: H Blank and V Blank. 11: Reserved. Power Down Mode. 00: Normal. - 54 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 01: Output (OSD) only (used when no input signal). 10: BIU, mode detection, GOUT are functional. 11: All chip power down. F1h F2h SWRST 7:0 Default : 0x00 - 7:6 Reserved. ADCR 5 ADC Reset. 0: Normal operation. 1: Reset ADC. GPR 4 Graphic Port Reset. 0: Normal operation. 1: Reset. DPR 3 Display Port Reset. 0: Normal operation. 1: Reset. BIUR 2 BIU Reset. 0: Normal operation. 1: Reset BIU. OSDR 1 Internal OSD Reset. 0: Normal operation. 1: Reset internal OSD. SWR 0 Software Reset (reset GP, DP, BIU, OSD and ADC). 0: Normal operation. 1: Reset. OSCTRL 7:0 Default : 0x00 OCLKDLY[3:0] / 7:4 OCKDLY[3:0]: OCLK Delay adjustment (TCON feature only). 0: 16 step to adjust. 1: Typical 0.8ns delay/step. 7 RSDS clock inverted. 0: Normal clock out. 1: RSDS clock output inverted. RSDS clock skew adjust. 000: Max setup time / min hold time to RSDS data output. 001: … 011: … 111: Min setup time / max hold time to RSDS data output. RSCK_SKE[3] RSCK_SKE[2:0] Version 0.3 Access : R/W 6:4 OCLK 3 Output CLK control. 0: Normal. 1: Invert. ODE 2 Output DE control. 0: Active high. Access : R/W - 55 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 1: Active low. F3h OVS 1 Output VSYNC control. 0: Active high. 1: Active low. OHS 0 Output HSYNC control. 0: Active high. 1: Active low. ISCTRL DEGE DEGR[2:0] F4h Version 0.3 7:0 7 6:4 Default : 0x10 Access : R/W DE or HSYNC post Glitch removal function Enable. 0: Disable. 1: Enable. DE or HSYNC post Glitch removal Range. HSFL 3 Input HSYNC Filter. When input source is analog: 0: Filter off. 1: Filter on. When input source is DVI: 0: Normal. 1: More tolerance for unstable DE. ISSM 2 Input sync sample mode. 0: Normal. 1: Glitch-removal. - 1 Reserved. SCKI 0 Input Sample CLK Invert. 0: Normal. 1: Invert. TRISTATE 7:0 Default : 0x7F Access : R/W - 7 Reserved. TCS 6 HSYNC/VSYNC Control Signal pin tri-state control (TCON feature only). 0: Normal. 1: Tri-state. OEDB 5 Output Even Data Bus pin control. 0: Normal. 1: Tri-state. OODB 4 Output Odd Data Bus pin control. 0: Normal. 1: Tri-state. OVS 3 OVSYNC pin control. - 56 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) 0: Normal. 1: Tri-state. F5h F6h F7h Version 0.3 OHS 2 OHSYNC pin control. 0: Normal. 1: Tri-state. ODE 1 ODE pin control. 0: Normal. 1: Tri-state. OCLK 0 OCLK pin control. 0: Normal. 1: Tri-state. ODRV 7:0 Default : 0x55 DEDRV[1:0] 7:6 Output DE Driving current select. 00: 4mA; 01: 6mA; 10: 8mA; 11: 12mA. CLKDRV[1:0] 5:4 Output Clock Driving current select. 00: 4mA; 01: 6mA; 10: 8mA; 11: 12mA. ODDDRV[1:0] 3:2 Output data Odd channel Driving current select. 00: 4mA; 01: 6mA; 10: 8mA; 11: 12mA. EVENDRV[1:0] 1:0 Output data Even channel Driving current select. 00: 4mA; 01: 6mA; 10: 8mA; 11: 12mA. ECLKDLY 7:0 Default : 0x00 - 7:6 Reserved. SKEW[1:0] 5:4 Output data Skew. ECLKDLY[3:0] / 3:0 ECLK Delay adjustment (TCON feature only). 0: 16 steps to adjust. 1: typical 0.8ns delay/step. - 7:0 Default : - - 7:0 Reserved. Access : R/W Access : R/W Access : - - 57 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 Digital Image Processor Register (Bank=00) F8h TEST F9h FAh FBh FFh 7:0 Default : 0x05 Access : R/W - 7 Reserved. - 6 Reserved. - 5:4 Reserved. TESTMD[3:0] 3:0 Test Mode. 0110: VS/HS/DE output while LVDS output Other: Reserved. - 7:0 Default : - - 7:0 Reserved. - 7:0 Default : 0x00 - 7:5 Reserved. Access : Access : R/W VDOE 4 Video reference Edge.(for non-standard signal) IPAVG 3 Interlace Period Average ACLKSW 2 Auto clock switch 0: auto clock switch when detected clock great than expect value 1: Disable auto clock switch - 1:0 Reserved. ~ - 7:0 Default : - - 7:0 Reserved. Access : - OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) Index Mnemonic Bits Description 01h OSDDBC 7:0 Default : 0x00 - 7:3 Reserved. DBL[1:0] 2:1 Double Buffer load. 00: Keep old register value. 01: Load new data (auto reset to 00 when load finish). 10: Automatically load data at VSYNC blanking. 11: Reserved. DBE 02h 03h Version 0.3 0 Access : R/W Double Buffer Enable. 0: Disable. 1: Enable. OHSTA-L 7:0 Default : 0x00 Access : R/W DB OHSTA[7:0] 7:0 OSD window Horizontal Start position. OHSTA-H 7:0 Default : 0x00 Access : R/W DB - 58 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 04h 05h 07h 08h 09h 0Ah 0Bh 0Ch Version 0.3 Reserved. OHSTA[8] 0 OVSTA-L 7:0 Default : 0x00 OVSTA[7:0] 7:0 OSD window Vertical Start position. OVSTA-H 7:0 Default : 0x00 - 7:1 Reserved. OVSTA[8] 06h 7:1 0 See description for OHSTA[7:0]. Access : R/W DB Access : R/W DB See description for OVSTA[7:0]. OSDW 7:0 Default : 0x00 Access : R/W DB - 7:6 Reserved. OSDW[5:0] 5:0 OSD window Width = OSDW + 1 (column), maximum 64 columns. OSDH 7:0 Default : 0x00 - 7:5 Reserved. OSDH[4:0] 4:0 OSD window Vertical Height = OSDH + 1 (row), maximum 32 rows. OHSPA 7:0 Default : 0x00 - 7:6 Reserved. OHSPA[5:0] 5:0 OSD window Horizontal Space Start position = OHSPA + 1 (row). OVSPA 7:0 Default : 0x00 - 7:5 Reserved. OVSPA[4:0] 4:0 OSD window Vertical Space Start position = OVSPA + 1 (column). OSPW 7:0 Default : 0x00 OSPW[7:0] 7:0 OSD Space Width = 8 * OSPW (pixel). OSPH 7:0 Default : 0x00 OSPH[7:0] 7:0 OSD Space Height = 8 * OSPH (pixel). IOSDC1 7:0 Default : 0x00 OVS[1:0] 7:6 OSD Vertical Scaling. 00: Vertical normal size. 01: Vertical enlarged x2 by repeated pixels. 10: Vertical enlarged x3 by repeated pixels. 11: Vertical enlarged by x4 by repeated pixels. OHS[1:0] 5:4 OSD Horizontal Scaling. 00: Horizontal normal size. 01: Horizontal enlarged x2 by repeated pixels. 10: Horizontal enlarged x3 by repeated pixels. 11: Horizontal enlarged by x4 by repeated pixels. Access : R/W DB Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W, DB - 59 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) C1C ROT[1:0] MWIN 0Dh IOSDC2 CF8E BCLR[2:0] 0Eh 3 2:1 0 7:0 7 6:4 Character 1 line Color. 0: Disable. 1: Enable. Rotate. 00: Not rotate. 01: Rotate 90°. 10: Rotate 270°. 11: Reserved. OSD Main Window display. 0: Main window off. 1: Main window on. Default : 0x00 Access : R/W 8 Color Font Enable. 0: Disable. 1: Enable. OSD Border Color index; BCLR[3] is located at REG 0E[5]. 0000: Color index 0. 0001: Color index 1. … 1111: Color index 15. BDC 3 OSD Character Border Type Select. 0: All direction font boundary (border). 1: Bottom-right direction font boundary (shadow). BDW 2 OSD Character Border Width control. 0: One pixel width for all scale. 1: Scale with OVS[1:0] and OHS[1:0]. C16_PAL 1 Color Palette Select. 0: 8 color palette. 1: 16 color palette. CF4E 0 4 Color Font Enable. 0: Disable. 1: Enable. IOSDC3 7:0 Default : 0x00 Access : R/W, DB C4TE 7 OSD 4-color Transparency Enable. 0: Disable. 1: Enable. CKIND[3] 6 Color Index Bit 3 of Color Key. Note: When OSD register 0x10[7]=0, OSD is backward compatible. Reserved. Note: When OSD register 0x10[7]=1, OSD is not backward compatible. Version 0.3 - 60 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 0Fh 10h 11h 12h Version 0.3 BCLR[3] 5 Border Color Bit 3. This bit should work with OSD 0Dh[6:4]. SDC 4 OSD window Shadow Control. 0: Off. 1: On. SCLR[3:0] 3:0 OSD window Shadow Color index. 0000: Color index 0. 0001: Color index 1. … 1111: Color index 15. OSHC 7:0 Default : 0x00 OSDSH[3:0] 7:4 OSD Shadow Height. OSDSW[3:0] 3:0 OSD Shadow Width. OCFF 7:0 Default : 0x00 OCFF 7 OSD backward compatibility. 0: Backward compatible. 1: Not backward compatible. MFCS 6 OSD 256 color palette Mono Font Color Select. 0: Use 256 color palette select method. 1: Use 16 color palette select method. - 5 Reserved. - 4 Reserved. CFCTOSD 3 Color Font Code Address Type. 0: RAM base. 1: Code base. C256P_SEL 2 OSD 256 Palette Select. 0: Select 8 or 16 color palette. 1: Select 256 color palette. PAL_EXT 1 OSD 16/256 Palette Extended method. 0: Extended LSB. 1: Extended 0. - 0 Reserved. Access : R/W Access : R/W OSDCFA 7:0 Default : 0x00 OSDCFA[7:0] 7:0 OSD 4 Color RAM Font Starting Address. OCBUFO 7:0 Default : 0x00 COS 7 OSD Code buffer Offset Select. 0: Use OSDW[5:0] as offset. 1: Use OOFFSET[5:0] as offset. - 6 Reserved. Access : R/W Access : R/W - 61 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 13h 14h 15h OOFFSET 5:0 OSD code buffer Offset value. OSDBA-L 7:0 Default : 0x00 OSDBA[7:0] 7:0 OSD code Base Address. OSDBA-H 7:0 Default : 0x00 - 7:2 Reserved. OSDBA[9:8] 1:0 See description for OSDBA[7:0]. GCCTRL 7:0 Default : 0x00 GVS[1:0] 7:6 Gradually color Vertical Scaling. 00: Vertical normal size. 01: Vertical enlarged x2 by repeated pixels. 10: Vertical enlarged x3 by repeated pixels. 11: Vertical enlarged x4 by repeated pixels. GHS[1:0] 5:4 Gradually color Horizontal Scaling. 00: Horizontal normal size. 01: Horizontal enlarged x2 by repeated pixels. 10: Horizontal enlarged x3 by repeated pixels. 11: Horizontal enlarged x4 by repeated pixels. 16h Version 0.3 6 Access : R/W, DB Access : R/W, DB Access : R/W Reserved. OOFFSET 5:0 OSD code buffer Offset value. GRADCLR 7:0 Default : 0x00 Access : R/W NCLREN 7 New ini Color Enable. 0: Original function. 1: Frame color at bank 0 reg 0x33, 0x34 and 0x35. F/B 6 Gradually applied color. 0: Background color. 1: Foreground color. RCLR[1:0] 5:4 Red starting gradually Color. 00: Red color is 00h. 01: Red color is 55h. 10: Red color is AAh. 11: Red color is FFh. GCLR[1:0] 5:4 Green starting gradually Color. 00: Green color is 00h. 01: Green color is 55h. 10: Green color is AAh. 11: Green color is FFh. BCLR[1:0] 5:4 Blue starting gradually Color. 00: Blue color is 00h. 01: Blue color is 55h. - 62 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 10: Blue color is AAh. 11: Blue color is FFh. 17h 18h 19h 1Ah 1Bh 1Ch HGRADCR 7:0 Default : 0x00 SR 7 Sign bit of Red color. 0: Increase. 1: Decrease. IRH 6 Inverse bit of Red color. 0: Normal. 1: Invert. Access : R/W R_GRADH[5:0] 5:0 Increase/Decrease value of Red color. HGRADCG 7:0 Default : 0x00 SG 7 Sign bit of Green color. 0: Increase. 1: Decrease. IGH 6 Inverse bit of Green color. 0: Normal. 1: Invert. Access : R/W G_GRADH[5:0] 5:0 Increase/Decrease value of Green color. HGRADCB 7:0 Default : 0x00 SB 7 Sign bit of Blue color. 0: Increase. 1: Decrease. IBH 6 Inverse bit of Blue color. 0: Normal. 1: Invert. Access : R/W B_GRADH[5:0] 5:0 Increase/Decrease value of Blue color. HGRADSR 7:0 Default : 0x00 HGRADSR[7:0] 7:0 Horizontal Gradually Step of Red color. HGRADSG 7:0 Default : 0x00 HGRADSG[7:0] 7:0 Horizontal Gradually Step of Green color. HGRADSB 7:0 Default : 0x00 HGRADSB[7:0] 7:0 Horizontal Gradually Step of Blue color. Access : R/W Access : R/W Access : R/W For example, of RCLR=0, R_GRADH=16h, and HGRADSR=20h, then Pixel 0 ~ 19 = 0; Pixel 20 ~ 39 = 16; Pixel 40 ~ 59 = 32; … etc. 1Dh VGRADCR SR Version 0.3 7:0 7 Default : 0x00 Access : R/W Sign bit of Red color. - 63 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 0: Increase. 1: Decrease. IRV 1Eh 1Fh 20h 21h 22h 23h Version 0.3 6 Inverse bit of Red color. 0: Normal. 1: Invert. R_GRADV[5:0] 5:0 Increase/Decrease value of Red color. VGRADCG 7:0 Default : 0x00 SG 7 Sign bit of Green color. 0: Increase. 1: Decrease. IGV 6 Inverse bit of Green color. 0: Normal. 1: Invert. Access : R/W G_GRADV[5:0] 5:0 Increase/Decrease value of Green color. VGRADCB 7:0 Default : 0x00 SB 7 Sign bit of Blue color. 0: Increase. 1: Decrease. IBV 6 Inverse bit of Blue color. 0: Normal. 1: Invert. Access : R/W B_GRADV[5:0] 5:0 Increase/Decrease value of Blue color. VGRADSR 7:0 Default : 0x00 VGRADSR[7:0] 7:0 Vertical Gradually Step of Red color. VGRADSG 7:0 Default : 0x00 VGRADSG[7:0] 7:0 Vertical Gradually Step of Green color. VGRADSB 7:0 Default : 0x00 VGRADSB[7:0] 7:0 Vertical Gradually Step of Blue color. SUBW0C 7:0 Default : 0x00 - 7:4 Reserved. Access : R/W Access : R/W Access : R/W Access : R/W, DB BTN0 3 Enable Button function for sub window 0. 0: Off. 1: On. BD0 2 Enable OSD sub window 0 Border. 0: Disable. 1: Enable. S0C 1 Sub window 0 Color select. If button function is disabled: - 64 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 0: From sub window 0 attribute. 1: From attribute RAM. If button function is enable: 0: Set this bit with 0. Use sub window 0 attribute to select FG/BG color and use attribute RAM to select button type. S0E 24h 25h 26h 27h 28h 0 Enable OSD sub window 0. 0: Disable. 1: Enable. SW0HST 7:0 Default : 0x00 Access : R/W, DB - 7:6 Reserved. SW0HST[5:0] 5:0 Sub Window 0 Horizontal Start Position. SW0HEND 7:0 Default : 0x00 - 7:6 Reserved. SW0HEND[5:0] 5:0 Sub Window 0 Horizontal End Position. SW0VST 7:0 Default : 0x00 - 7:5 Reserved. SW0VST[4:0] 4:0 Sub Window 0 Vertical Start Position. SW0VEND 7:0 Default : 0x00 - 7:5 Reserved. SW0VEND[4:0] 4:0 Sub Window 0 Vertical End Position. SUBW0A2 7:0 Default : 0x00 Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W Note: When button function is enabled, the FG/BG color is defined by window attribute, character attribute is used to define button function border type and S0C (sub window color select) is disabled. BLNK FGCLR[2:0] TRAN BGCLR[2:0] Version 0.3 7 6:4 5 2:0 OSD sub window 0 Blink control. 0: Disable. 1: Enable. When 16 color palette is selected, BLNK will be FGCLR[3]. OSD sub window 0 Foreground Color select. 000: Color index 0. 001: Color index 1. … 111: Color index 7. OSD sub window 0 Transparency control. 0: Disable. 1: Enable. When 16 color palette is selected, TRAN will be BGCLR[3]. OSD sub window 0 Background Color select. 000: Color index 0. 001: Color index 1. - 65 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) … 111: Color index 7. 28h SUBW0A2 BTNCSEL[2:0] Default : 0x00 7:5 When OSD register 0x10[7]=0, OSD is backward compatible. Reserved. BTNCSEL[2] BTNCSEL[1] BTNCSEL[0] 7 6 5 BTNU 4 BTNTYPE[3:0] 1 ┌┐ └┘ 7:0 2 ┌ └ 3 ┐ ┘ 4 ┌┐ 3:0 5 6 ┌ └┘ Access : R/W, DB When OSD register 0x10[7]=1, OSD is not backward compatible. Button red color is selected. Button green color is selected. Button blue color is selected. Button up Control. 0: Button up. 1: Button down. Button border Type. 0: No button. 1: 7 ┐ 8 9 a b └ ┘ | | c - d - e || f - Note: The register of sub window 1, 2, and 3 are very similar with sub window 0 29h 2Ah 2Bh 2Ch 2Dh Version 0.3 SUBW1C 7:0 Default : 0x00 - 7:4 Reserved. Access : R/W, DB BTN1 3 Enable Button function for sub window 1. BD1 2 Enable OSD sub window 1 Border. S1C 1 Sub window 1 Color select. S1E 0 Enable OSD sub window 1. SW1HST 7:0 Default : 0x00 Access : R/W, DB - 7:6 Reserved. SW1HST[5:0] 5:0 Sub Window 1 Horizontal Start Position. SW1HEND 7:0 Default : 0x00 - 7:6 Reserved. SW1HEND[5:0] 5:0 Sub Window 1 Horizontal End Position. SW1VST 7:0 Default : 0x00 - 7:5 Reserved. SW1VST[4:0] 4:0 Sub Window 1 Vertical Start Position. SW1VEND 7:0 Default : 0x00 - 7:5 Reserved. Access : R/W, DB Access : R/W, DB Access : R/W, DB - 66 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 2Eh SW1VEND[4:0] 4:0 Sub Window 1 Vertical End Position. SUBW1A 7:0 Default : 0x00 BLNK FGCLR[2:0] TRAN 2Fh 30h 31h 32h 33h 34h 5 OSD sub window 1 Foreground Color select. OSD sub window 1 Transparency control. 2:0 OSD sub window 1 Background Color select. SUBW2C 7:0 Default : 0x00 - 7:4 Reserved. Access : R/W, DB BTN2 3 Enable Button function for sub window 2. BD2 2 Enable OSD sub window 2 Border. S2C 1 Sub window 2 Color select. S2E 0 Enable OSD sub window 2. SW2HST 7:0 Default : 0x00 - 7:6 Reserved. SW2HST[5:0] 5:0 Sub Window 2 Horizontal Start Position. SW2HEND 7:0 Default : 0x00 - 7:6 Reserved. SW2HEND[5:0] 5:0 Sub Window 2 Horizontal End Position. SW2VST 7:0 Default : 0x00 - 7:5 Reserved. SW2VST[4:0] 4:0 Sub Window 2 Vertical Start Position. SW2VEND 7:0 Default : 0x00 - 7:5 Reserved. SW2VEND[4:0] 4:0 Sub Window 2 Vertical End Position. SUBW2A 7:0 Default : 0x00 FGCLR[2:0] TRAN Version 0.3 6:4 OSD sub window 1 Blink control. BGCLR[2:0] BLNK 35h 7 Access : R/W 7 6:4 5 Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W OSD sub window 2 Blink control. OSD sub window 2 Foreground Color select. OSD sub window 2 Transparency control. BGCLR[2:0] 2:0 OSD sub window 2 Background Color select. SUBW3C 7:0 Default : 0x00 - 7:4 Reserved. Access : R/W, DB BTN3 3 Enable Button function for sub window 3. BD3 2 Enable OSD sub window 3 Border. S3C 1 Sub window 3 Color select. S3E 0 Enable OSD sub window 3. - 67 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 36h 37h 38h 39h 3Ah SW3HST 7:0 Default : 0x00 - 7:6 Reserved. SW3HST[5:0] 5:0 Sub Window 3 Horizontal Start Position. SW3HEND 7:0 Default : 0x00 - 7:6 Reserved. SW3HEND[5:0] 5:0 Sub Window 3 Horizontal End Position. SW2VST 7:0 Default : 0x00 - 7:5 Reserved. SW3VST[4:0] 4:0 Sub Window 3 Vertical Start Position. SW2VEND 7:0 Default : 0x00 - 7:5 Reserved. SW3VEND[4:0] 4:0 Sub Window 3 Vertical End Position. SUBW3A 7:0 Default : 0x00 BLNK FGCLR[2:0] TRAN 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 7 6:4 5 Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W OSD sub window 3 Blink control. OSD sub window 3 Foreground Color select. OSD sub window 3 Transparency control. BGCLR[2:0] 2:0 OSD sub window 3 Background Color select. OSD8CFFA 7:0 Default : 0x00 OSD8CFFA[7:0] 7:0 OSD 8 Color Font RAM start Address. OSD8CFCA 7:0 Default : 0x00 OSD8CFCA[7:0] 7:0 OSD 8 Color Font Code start Address. 256CPKEY0 7:0 Default : 0x00 256CPKEY0[7:0] 7:0 256 Color Palette Key 0. 256CPKEY1 7:0 Default : 0x00 256CPKEY1[7:0] 7:0 256 Color Palette Key 1. 256CPKEY2 7:0 Default : 0x00 256CPKEY2[7:0] 7:0 256 Color Palette Key 2. 256CPCLCI 7:0 Default : 0x00 256CPCLCI[7:0] 7:0 256 Color Palette Character 1 Line Color Index. OSDCFHA 7:0 Default : 0x00 OSD8CFFA[8] 7 OSD8CFCA[8] OSD4CFA[8] Version 0.3 Access : R/W, DB Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W See description for OSD8CFFA[7:0]. See description for OSD8CFCA[7:0]. 5:4 3 2:0 Reserved. See description for OSD4CFA[7:0]. Reserved. - 68 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 42h 57h ~ - 7:0 Default : - - 7:0 Reserved. Access : - OSD 8-Color Palette (when C16_PAL=0), 8-bit resolution 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h Version 0.3 CLR0R 7:0 Default : 0x00 CLR0R[7:0] 7:0 R component of index 0. CLR0G 7:0 Default : 0x00 CLR0G[7:0] 7:0 G component of index 0. CLR0B 7:0 Default : 0x00 CLR0B[7:0] 7:0 B component of index 0. CLR1R 7:0 Default : 0x00 CLR1R[7:0] 7:0 R component of index 1. CLR1G 7:0 Default : 0x00 CLR1G[7:0] 7:0 G component of index 1. CLR1B 7:0 Default : 0x00 CLR1B[7:0] 7:0 B component of index 1. CLR2R 7:0 Default : 0x00 CLR2R[7:0] 7:0 R component of index 2. CLR2G 7:0 Default : 0x00 CLR2G[7:0] 7:0 G component of index 2. CLR2B 7:0 Default : 0x00 CLR2B[7:0] 7:0 B component of index 2. CLR3R 7:0 Default : 0x00 CLR3R[7:0] 7:0 R component of index 3. CLR3G 7:0 Default : 0x00 CLR3G[7:0] 7:0 G component of index 3. CLR3B 7:0 Default : 0x00 CLR3B[7:0] 7:0 B component of index 3. CLR4R 7:0 Default : 0x00 CLR4R[7:0] 7:0 R component of index 4. CLR4G 7:0 Default : 0x00 CLR4G[7:0] 7:0 G component of index 4. CLR4B 7:0 Default : 0x00 CLR4B[7:0] 7:0 B component of index 4. CLR5R 7:0 Default : 0x00 CLR5R[7:0] 7:0 R component of index 5. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 69 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh CLR5G 7:0 Default : 0x00 CLR5G[7:0] 7:0 G component of index 5. CLR5B 7:0 Default : 0x00 CLR5B[7:0] 7:0 B component of index 5. CLR6R 7:0 Default : 0x00 CLR6R[7:0] 7:0 R component of index 6. CLR6G 7:0 Default : 0x00 CLR6G[7:0] 7:0 G component of index 6. CLR6B 7:0 Default : 0x00 CLR6B[7:0] 7:0 B component of index 6. CLR7R 7:0 Default : 0x00 CLR7R[7:0] 7:0 R component of index 7. CLR7G 7:0 Default : 0x00 CLR7G[7:0] 7:0 G component of index 7. CLR7B 7:0 Default : 0x00 CLR7B[7:0] 7:0 B component of index 7. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W OSD 16-Color Palette (when C16_PAL=1), 4-bit resolution 16 color format: col[7:4], 4’h0 58h 59h 5Ah 5Bh 5Ch 5Dh Version 0.3 CLR0R 7:0 Default : 0x00 CLR0R[7:4] 7:4 R component of index 0. CLR8R[7:4] 3:0 R component of index 8. CLR0G 7:0 Default : 0x00 CLR0G[7:4] 7:4 G component of index 0. CLR8G[7:4] 3:0 G component of index 8. CLR0B 7:0 Default : 0x00 CLR0B[7:4] 7:4 B component of index 0. CLR8B[7:4] 3:0 B component of index 8. CLR1R 7:0 Default : 0x00 CLR1R[7:4] 7:4 R component of index 1. CLR9R[7:4] 3:0 R component of index 9. CLR1G 7:0 Default : 0x00 CLR1G[7:4] 7:4 G component of index 1. CLR9G[7:4] 3:0 G component of index 9. CLR1B 7:0 Default : 0x00 CLR1B[7:4] 7:4 B component of index 1. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 70 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h Version 0.3 CLR9B[7:4] 3:0 B component of index 9. CLR2R 7:0 Default : 0x00 CLR2R[7:4] 7:4 R component of index 2. CLR10R[7:4] 3:0 R component of index 10. CLR2G 7:0 Default : 0x00 CLR2G[7:4] 7:4 G component of index 2. CLR10G[7:4] 3:0 G component of index 10. CLR2B 7:0 Default : 0x00 CLR2B[7:4] 7:4 B component of index 2. CLR10B[7:4] 3:0 B component of index 10. CLR3R 7:0 Default : 0x00 CLR3R[7:4] 7:4 R component of index 3. CLR11R[7:4] 3:0 R component of index 11. CLR3G 7:0 Default : 0x00 CLR3G[7:4] 7:4 G component of index 3. CLR11G[7:4] 3:0 G component of index 11. CLR4B 7:0 Default : 0x00 CLR4B[7:4] 7:4 B component of index 3. CLR11B[7:4] 3:0 B component of index 11. CLR4R 7:0 Default : 0x00 CLR4R[7:4] 7:4 R component of index 4. CLR12R[7:4] 3:0 R component of index 12. CLR4G 7:0 Default : 0x00 CLR4G[7:4] 7:4 G component of index 4. CLR12G[7:4] 3:0 G component of index 12. CLR4B 7:0 Default : 0x00 CLR4B[7:4] 7:4 B component of index 4. CLR12B[7:4] 3:0 B component of index 12. CLR5R 7:0 Default : 0x00 CLR5R[7:4] 7:4 R component of index 5. CLR13R[7:4] 3:0 R component of index 13. CLR5G 7:0 Default : 0x00 CLR5G[7:4] 7:4 G component of index 5. CLR13G[7:4] 3:0 G component of index 13. CLR5B 7:0 Default : 0x00 Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 71 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 OSD Register (Indirect mapping, using Bank 0 register A1h/A2h) 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h CLR5B[7:4] 7:4 B component of index 5. CLR13B[7:4] 3:0 B component of index 13. CLR6R 7:0 Default : 0x00 CLR6R[7:4] 7:4 R component of index 6. CLR14R[7:4] 3:0 R component of index 14. CLR6G 7:0 Default : 0x00 CLR6G[7:4] 7:4 G component of index 6. CLR14G[7:4] 3:0 G component of index 14. CLR6B 7:0 Default : 0x00 CLR6B[7:4] 7:4 B component of index 6. CLR14B[7:4] 3:0 B component of index 14. CLR7R 7:0 Default : 0x00 CLR7R[7:4] 7:4 R component of index 7. CLR15R[7:4] 3:0 R component of index 15. CLR7G 7:0 Default : 0x00 CLR7G[7:4] 7:4 G component of index 7. CLR15G[7:4] 3:0 G component of index 15. CLR7B 7:0 Default : 0x00 CLR7B[7:4] 7:4 B component of index 7. CLR15B[7:4] 3:0 B component of index 15. - 7:0 Default : 0x00 - 7:0 Reserved. OSDRTP 7:0 Default : 0x00 - 7:3 Reserved. RTPT Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : Access : R/W OSD Random Test Pattern Type. 0: RGB is same. 1: RGB is different. OSDRTP 1:0 OSD Random Test Pattern. 00: Disable. 01: 1 random bit. 10: 2 random bit. 11: Reserved. ATR0DATA 7:0 Default : 0x00 ATR0kDATA[7:0] 7:0 ATR SRAM Address0 Data read back. ~ - 7:0 Default : 0x00 - 7:0 Reserved. 72h 72h FFh 2 Access : R/W Version 0.3 Access : R/W Access : - - 72 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) TCON Register (Bank = 02) Index Mnemonic Bits Description 01h - 7:0 Default : - - 7:- Reserved. OFC1 7:0 Default : 0x02 02h 03h Version 0.3 Access : Access : R/W IFC 7 Inversion Function Combined. 0: Odd data inversion determined by OINV, even data inversion determined by EINV. 1: Odd/Even data inversion both determined by OINV. IFS 6 Inversion Function Swap. 0: OINV/EINV = 0 when data is inverted. 1: OINV/EINV = 1 when data is inverted. IFE 5 Inversion Function Enable. 0: Disable. 1: Enable. When enabled, an indication is output for each data bus. If the number of transitions from pixel to pixel exceed 24 bits from 48 bits (or 18 bits from 36 bits for 6-bit panels), the data is inverted and an indication corresponding to that bus is set active. DPFS 4 Data Polarity Function Swap (useful when DPFE = 1). 0: Odd data inversion determined by OPOL, even data inversion determined by EPOL. 1: Odd data inversion determined by OPOL, even data opposite of odd data. DPFC 3 Data Polarity Function Control. 0: Data inversion when OPOL/EPOL is 0. 1: Data inversion when OPOL/EPOL is 1. DPFE 2 Data Polarity Function Enable. 0: Disable. 1: Enable (line inversion, use OPOL/EPOL to determine that polarity of the output data). EEF 1 Early End Function. 0: Disable. 1: Enable. TCEN 0 Timing Controller Enable. 0: Disable. 1: Enable. OFC2 7:0 ESPP 7 Default : 0x00 Access : R/W Even Start Pulse Position. - 73 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index Mnemonic Bits Description 0: Start pulse before data. 1: Start pulse after data. ESPO[2:0] OSPP OSPO[2:0] 04h 05h Version 0.3 6:4 3 2:0 Even Start Pulse Offset. 000: Start pulse 0 clocks 001: Start pulse 1 clocks 010: Start pulse 2 clocks … 111: Start pulse 7 clocks before/after data. before/after data. before/after data. before/after data. Odd Start Pulse Position. 0: Start pulse before data. 1: Start pulse after data. Odd Start Pulse Offset. 000: Start pulse 0 clocks 001: Start pulse 1 clocks 010: Start pulse 2 clocks … 111: Start pulse 7 clocks before/after data. before/after data. before/after data. before/after data. ODPC 7:0 Default : 0x00 OESPDC[1:0] 7:6 OSP/ESP Drive Control. 00: 4mA. 01: 6mA. 10: 8mA. 11: 12mA. GODC[1:0] 5:4 OPOL/EPOL/GPO Drive Control. 00: 4mA. 01: 6mA. 10: 8mA. 11: 12mA. ECP 3 ECLK Polarity. 0: Normal. 1: Inverted. - 2 Reserved. OCP 1 OCLK Polarity. 0: Normal. 1: Inverted. - 0 Reserved. ODC 7:0 Default : 0x00 EDDC[1:0] 7:6 EINV Driver Control. Access : R/W Access : R/W - 74 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index Mnemonic Bits Description 00: 01: 10: 11: OIDC 06h 07h Version 0.3 5:4 4mA. 6mA. 8mA. 12mA. OINV Drive Control. - 3 Reserved. OFTG 2 One Frame Toggle mode. RSBMLSW 1 RSDS B-port MSB/LSB Swap. Bank 0 reg 0x42[5] = 0 and 0x42[2] = 1: 0: Default. 1: B-port MSB/LSB swap for 8-bit RSDS output. Bank 0 reg 0x42[5] = 0 and 0x42[2] = 1: 0: Default. 1: B-port MSB/LSB swap for 6-bit RSDS output. RSAMLSW 0 RSDS A-port MSB/LSB Swap. Bank 0 reg 0x42[5] = 0 and 0x42[3] = 1: 0: Default. 1: A-port MSB/LSB swap for 8-bit RSDS output. Bank 0 reg 0x42[5] = 0 and 0x42[3] = 1: 0: Default. 1: A-port MSB/LSB swap for 6-bit RSDS output. GPO4ADF 7:0 Default : 0x00 - 7:3 Reserved. GPO4ADF[2:0] 2:0 GPO4 (OE) Active Delay time. 000: No delay. 001: Delay 1 frame. … 111: Delay 7 frames. IFCTRL 7:0 Default : 0x00 Access : R/W Access : R/W WDG 7 White Data Generation (TCON feature only). 0: Black data generation during vertical blanking (GPOA). 1: Enable white data generation during vertical blanking (GPOA). PUA 6 Power-up Active (TCON feature only). 0: Outputs inactive. 1: Outputs active. G0AT 5 GPO0 Auto Toggle (TCON feature only). 0: Disable. 1: Enable. GDEEN 4 Gate DE Enable. - 75 - Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h Version 0.3 Mnemonic Bits Description DATI 3 Data Invert (TCON feature only). 0: Off. 1: On. POLB 2 Polarity Blanked Enable (TCON feature only). 0: Disable. 1: Enable (EPOL/OPOL will be forced to blanked when GPOA is low). SPB 1 Start Pulse Blanked enable (TCON feature only). 0: Disable. 1: Enable (EPOL/OPOL will be forced to blanked when GPOA is low). CLKB 0 Clock Blanked Enable. 0: Disable. 1: Enable (ECLK/OCLK will be forced to blanked when GPOA is low). G0VST-L 7:0 Default : 0x00 Access : R/W G0VST[7:0] 7:0 Line number that GPO0 start. G0VST -H 7:0 Default : 0x00 - 7:3 Reserved. G0VST[10:8] 2:0 See description for G0VST[7:0]. G0VEND-L 7:0 Default : 0x00 G0VEND[7:0] 7:0 Line number that GPO0 ends. G0VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G0VEND[10:8] 2:0 See description for G0VEND[7:0]. G0HST-L 7:0 Default : 0x00 G0HST[7:0] 7:0 Pixel number that GPO0 start. G0HST -H 7:0 Default : 0x00 - 7:3 Reserved. G0VHT[10:8] 2:0 Pixel description for G0HST[7:0]. G0HEND-L 7:0 Default : 0x00 G0HEND[7:0] 7:0 Pixel number that GPO0 ends. G0HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G0HEND[10:8] 2:0 See description for G0HEND[7:0]. C0CTRL 7:0 Default : 0x00 Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 76 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index 11h 12h 13h Version 0.3 Mnemonic Bits Description C0CS[2:0] 7:5 GPO0 Combination select. 000: No combination. 001: And. 010: Or. 011: Select GPO# and GPO#-1 on alternating frames. 1xx: Auto select 1 or 2 line toggle according to ATP value. G0TS[1:0] 4:3 GPO0 Type Select. When toggle mode=0: 00: Normal. 01: Duration is greater than a line time. 10: Every two lines have one GPO0 pulse. 11: Every three lines have one GPO0 pulse. When toggle mode=1: 00: One line toggle. 01: Reserved. 10: Two lines toggle. 11: Three lines toggle. G0ES 2 GPO0 Early Start function. 0: Normal. 1: Early start capability. The value in the Vertical Start Register (G0VST) is subtracted from the total number of lines/frames to determine the Vertical Start position. G0TC 1 GPO0 Toggle Circuit enable. 0: Normal. 1: Toggle. Toggle mode is useful in POL generation when alternating polarity is required from line to line. Frame to frame polarity changes are made by programming an odd # in the vertical duration when in toggle mode. G0OP 0 GPO0 Output Polarity. 0: Active high. 1: Active low. G1VST-L 7:0 Default : 0x00 G1VST[7:0] 7:0 Line number that GPO1 start. G1VST -H 7:0 Default : 0x00 - 7:3 Reserved. G1VST[10:8] 2:0 See description for G1VST[7:0]. G1VEND-L 7:0 Default : 0x00 Access : R/W Access : R/W Access : R/W - 77 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Version 0.3 Mnemonic Bits Description G1VEND[7:0] 7:0 Line number that GPO1 ends. G1VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G1VEND[10:8] 2:0 See description for G1VEND[7:0]. G1HST-L 7:0 Default : 0x00 G1HST[7:0] 7:0 Pixel number that GPO1 start. G1HST -H 7:0 Default : 0x00 - 7:3 Reserved. G1VHT[10:8] 2:0 Pixel description for G1HST[7:0]. G1HEND-L 7:0 Default : 0x00 G1HEND[7:0] 7:0 Pixel number that GPO1 ends. G1HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G1HEND[10:8] 2:0 See description for G1HEND[7:0]. C1CTRL 7:0 Default : 0x00 C1CS[2:0] 7:5 GPO1 Combination select. G1TS[1:0] 4:3 GPO1 Type Select. G1ES 2 GPO1 Early Start function. G1TC 1 GPO1 Toggle Circuit enable. G1OP 0 GPO1 Output Polarity. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W G2VST-L 7:0 Default : 0x00 Access : R/W G2VST[7:0] 7:0 Line number that GPO2 start. G2VST -H 7:0 Default : 0x00 - 7:3 Reserved. G2VST[10:8] 2:0 See description for G2VST[7:0]. G2VEND-L 7:0 Default : 0x00 G2VEND[7:0] 7:0 Line number that GPO2 ends. G2VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G2VEND[10:8] 2:0 See description for G2VEND[7:0]. G2HST-L 7:0 Default : 0x00 G2HST[7:0] 7:0 Pixel number that GPO2 start. G2HST -H 7:0 Default : 0x00 - 7:3 Reserved. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 78 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh Version 0.3 Mnemonic Bits Description G2VHT[10:8] 2:0 Pixel description for G2HST[7:0]. G2HEND-L 7:0 Default : 0x00 G2HEND[7:0] 7:0 Pixel number that GPO2 ends. G2HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G2HEND[10:8] 2:0 See description for G2HEND[7:0]. C2CTRL 7:0 Default : 0x00 C2CS[2:0] 7:5 GPO2 Combination select. G2TS[1:0] 4:3 GPO2 Type Select. G2ES 2 GPO2 Early Start function. G2TC 1 GPO2 Toggle Circuit enable. G2OP 0 GPO2 Output Polarity. Access : R/W Access : R/W Access : R/W G3VST-L 7:0 Default : 0x00 Access : R/W G3VST[7:0] 7:0 Line number that GPO3 start. G3VST -H 7:0 Default : 0x00 - 7:3 Reserved. G3VST[10:8] 2:0 See description for G3VST[7:0]. G3VEND-L 7:0 Default : 0x00 G3VEND[7:0] 7:0 Line number that GPO3 ends. G3VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G3VEND[10:8] 2:0 See description for G3VEND[7:0]. G3HST-L 7:0 Default : 0x00 G3HST[7:0] 7:0 Pixel number that GPO3 start. G3HST -H 7:0 Default : 0x00 - 7:3 Reserved. G3VHT[10:8] 2:0 Pixel description for 3HST[7:0]. G3HEND-L 7:0 Default : 0x00 G3HEND[7:0] 7:0 Pixel number that GPO3 ends. G3HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G3HEND[10:8] 2:0 See description for G3HEND[7:0]. C3CTRL 7:0 Default : 0x00 C3CS[2:0] 7:5 GPO3 Combination select. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 79 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h Version 0.3 Mnemonic Bits Description G3TS[1:0] 4:3 GPO3 Type Select. G3ES 2 GPO3 Early Start function. G3TC 1 GPO3 Toggle Circuit enable. G3OP 0 GPO3 Output Polarity. G4VST-L 7:0 Default : 0x00 G4VST[7:0] 7:0 Line number that GPO4 start. G4VST -H 7:0 Default : 0x00 - 7:3 Reserved. G4VST[10:8] 2:0 See description for G4VST[7:0]. G4VEND-L 7:0 Default : 0x00 G4VEND[7:0] 7:0 Line number that GPO4 ends. G4VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G4VEND[10:8] 2:0 See description for G4VEND[7:0]. G4HST-L 7:0 Default : 0x00 G4HST[7:0] 7:0 Pixel number that GPO4 start. G4HST -H 7:0 Default : 0x00 - 7:3 Reserved. G4VHT[10:8] 2:0 Pixel description for G4HST[7:0]. G4HEND-L 7:0 Default : 0x00 G4HEND[7:0] 7:0 Pixel number that GPO4 ends. G4HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G4HEND[10:8] 2:0 See description for G4HEND[7:0]. C4CTRL 7:0 Default : 0x00 C4CS[2:0] 7:5 GPO4 Combination select. G4TS[1:0] 4:3 GPO4 Type Select. G4ES 2 GPO4 Early Start function. G4TC 1 GPO4 Toggle Circuit enable. G4OP 0 GPO4 Output Polarity. G5VST-L 7:0 Default : 0x00 G5VST[7:0] 7:0 Line number that GPO5 start. G5VST -H 7:0 Default : 0x00 - 7:3 Reserved. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 80 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h Version 0.3 Mnemonic Bits Description G5VST[10:8] 2:0 See description for G5VST[7:0]. G5VEND-L 7:0 Default : 0x00 G5VEND[7:0] 7:0 Line number that GPO5 ends. G5VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G5VEND[10:8] 2:0 See description for G5VEND[7:0]. G5HST-L 7:0 Default : 0x00 G5HST[7:0] 7:0 Pixel number that GPO5 start. G5HST -H 7:0 Default : 0x00 - 7:3 Reserved. G5VHT[10:8] 2:0 Pixel description for G5HST[7:0]. G5HEND-L 7:0 Default : 0x00 G5HEND[7:0] 7:0 Pixel number that GPO5 ends. G5HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G5HEND[10:8] 2:0 See description for G5HEND[7:0]. C5CTRL 7:0 Default : 0x00 C5CS[2:0] 7:5 GPO5 Combination select. G5TS[1:0] 4:3 GPO5 Type Select. G5ES 2 GPO5 Early Start function. G5TC 1 GPO5 Toggle Circuit enable. G5OP 0 GPO5 Output Polarity. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W G6VST-L 7:0 Default : 0x00 Access : R/W G6VST[7:0] 7:0 Line number that GPO6 start. G6VST -H 7:0 Default : 0x00 - 7:3 Reserved. G6VST[10:8] 2:0 See description for G6VST[7:0]. G6VEND-L 7:0 Default : 0x00 G6VEND[7:0] 7:0 Line number that GPO6 ends. G6VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G6VEND[10:8] 2:0 See description for G6VEND[7:0]. G6HST-L 7:0 Default : 0x00 G6HST[7:0] 7:0 Pixel number that GPO6 start. Access : R/W Access : R/W Access : R/W Access : R/W - 81 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index Mnemonic Bits Description 43h G6HST -H 7:0 Default : 0x00 - 7:3 Reserved. G6VHT[10:8] 2:0 Pixel description for G6HST[7:0]. G6HEND-L 7:0 Default : 0x00 G6HEND[7:0] 7:0 Pixel number that GPO6 ends. G6HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G6HEND[10:8] 2:0 See description for G6HEND[7:0]. C6CTRL 7:0 Default : 0x00 C6CS[2:0] 7:5 GPO6 Combination select. G6TS[1:0] 4:3 GPO6 Type Select. 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh Version 0.3 G6ES 2 GPO6 Early Start function. G6TC 1 GPO6 Toggle Circuit enable. G6OP 0 GPO6 Output Polarity. Access : R/W Access : R/W Access : R/W Access : R/W G7VST-L 7:0 Default : 0x00 Access : R/W G7VST[7:0] 7:0 Line number that GPO7 start. G7VST -H 7:0 Default : 0x00 - 7:3 Reserved. G7VST[10:8] 2:0 See description for G7VST[7:0]. G7VEND-L 7:0 Default : 0x00 G7VEND[7:0] 7:0 Line number that GPO7 ends. G7VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G7VEND[10:8] 2:0 See description for G7VEND[7:0]. G7HST-L 7:0 Default : 0x00 G7HST[7:0] 7:0 Pixel number that GPO7 start. G7HST -H 7:0 Default : 0x00 - 7:3 Reserved. G7VHT[10:8] 2:0 Pixel description for G7HST[7:0]. G7HEND-L 7:0 Default : 0x00 G7HEND[7:0] 7:0 Pixel number that GPO7 ends. G7HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G7HEND[10:8] 2:0 See description for G7HEND[7:0]. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 82 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index Mnemonic Bits Description 4Fh C7CTRL 7:0 Default : C7CS[2:0] 7:5 GPO7 Combination select. G7TS[1:0] 4:3 GPO7 Type Select. 50h 51h 52h 53h 54h 55h 56h 57h 58h Version 0.3 Access : R/W G7ES 2 GPO7 Early Start function. G7TC 1 GPO7 Toggle Circuit enable. G7OP 0 GPO7 Output Polarity. G8VST-L 7:0 Default : 0x00 G8VST[7:0] 7:0 When Bank 0 register ABh[7] = 0: G8VST[10:0]: Line number that GPO8 start. When Bank 0 register ABh[7] = 1: G8VST-L[7:0]: GPO[7:0] gating control. G8VST-H[1:0]: O(E)SP / O(E)INV gating control. G8VST -H 7:0 Default : 0x00 - 7:3 Reserved. G8VST[10:8] 2:0 See description for G8VST[7:0]. G8VEND-L 7:0 Default : 0x00 G8VEND[7:0] 7:0 Line number that GPO8 ends. G8VEND -H 7:0 Default : 0x00 - 7:3 Reserved. G8VEND[10:8] 2:0 See description for G8VEND[7:0]. G8HST-L 7:0 Default : 0x00 G8HST[7:0] 7:0 Pixel number that GPO8 start. G8HST -H 7:0 Default : 0x00 - 7:3 Reserved. G8VHT[10:8] 2:0 Pixel description for G8HST[7:0]. G8HEND-L 7:0 Default : 0x00 G8HEND[7:0] 7:0 Pixel number that GPO8 ends. G8HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G8HEND[10:8] 2:0 See description for G8HEND[7:0]. C6CTRL 7:0 Default : 0x00 C8CS[2:0] 7:5 GPO8 Combination select. G8TS[1:0] 4:3 GPO8 Type Select. G8ES 2 GPO8 Early Start function. G8TC 1 GPO8 Toggle Circuit enable. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 83 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index Mnemonic G8OP 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h Version 0.3 Bits 0 Description GPO8 Output Polarity. G9VST-L 7:0 Default : 0x07 G9VST[7:0] 7:0 Line number that GPO9 start. G9VST -H 7:0 Default : 0x00 - 7:3 Reserved. G9VST[10:8] 2:0 See description for G9VST[7:0]. G9VEND-L 7:0 Default : 0x05 G9VEND[7:0] 7:0 Line number that GPO9 ends. G9VEND -H 7:0 Default : 0x07 - 7:3 Reserved. G9VEND[10:8] 2:0 See description for G9VEND[7:0]. G9HST-L 7:0 Default : 0x00 G9HST[7:0] 7:0 Pixel number that GPO9 start. G9HST -H 7:0 Default : 0x00 - 7:3 Reserved. G9VHT[10:8] 2:0 Pixel description for G9HST[7:0]. G9HEND-L 7:0 Default : 0x00 G9HEND[7:0] 7:0 Pixel number that GPO9 ends. G9HEND -H 7:0 Default : 0x00 - 7:3 Reserved. G9HEND[10:8] 2:0 See description for G9HEND[7:0]. C9CTRL 7:0 Default : 0x04 C9CS[2:0] 7:5 GPO9 Combination select. G9TS[1:0] 4:3 GPO9 Type Select. G9ES 2 GPO9 Early Start function. G9TC 1 GPO9 Toggle Circuit enable. G9OP 0 GPO9 Output Polarity. GAVST-L 7:0 Default : 0x00 G7VST[7:0] 7:0 Line number that GPOA start. GAVST -H 7:0 Default : 0x00 - 7:3 Reserved. GAVST[10:8] 2:0 See description for GAVST[7:0]. GAVEND-Lhjh 7:0 Default : 0x00 GAVEND[7:0] 7:0 Line number that GPOA ends. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W - 84 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 TCON Register (Bank = 02) Index Mnemonic Bits Description 65h GAVEND -H 7:0 Default : 0x00 - 7:3 Reserved. GAVEND[10:8] 2:0 See description for GAVEND[7:0]. GAHST-L 7:0 Default : 0x00 GAHST[7:0] 7:0 Pixel number that GPOA start. GAHST -H 7:0 Default : 0x00 - 7:3 Reserved. GAVHT[10:8] 2:0 Pixel description for GAHST[7:0]. GAHEND-L 7:0 Default : 0x00 GAHEND[7:0] 7:0 Pixel number that GPOA ends. GAHEND -H 7:0 Default : 0x00 - 7:3 Reserved. GAHEND[10:8] 2:0 See description for GAHEND[7:0]. CACTRL 7:0 Default : 0x00 CACS[2:0] 7:5 GPOA Combination select. GATS[1:0] 4:3 GPOA Type Select. 66h 67h 68h 69h 6Ah GAES 2 GPOA Early Start function. GATC 1 GPOA Toggle Circuit enable. GAOP 0 GPOA Output Polarity. 6Bhh ~ FFh - 7:0 Default : - 7:0 Reserved. Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : R/W Access : - MWE Register (Bank = 03) MWE Register (Bank = 03) Index 01h 16h Mnemonic Bits Description ~ - 7:0 Default : - - 7:0 Reserved. SW2CTL 7:0 Default : 0x00 17h Version 0.3 - 7 Reserved. MWEW3EN 6 MWE window 3 Enable MWEW2EN 5 MWE window 2 Enable MWEW1EN 4 MWE Window 1Enable. - 3:2 Reserved. MWE_WSEL[1:0] 1:0 MWE window Select. Access : Access : R/W, DB - 85 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 MWE Register (Bank = 03) 00: 01: 10: 11: 18h window window window window 0. 1. 2. 3. MWEHST-L 7:0 Default : 0x00 MWEHST[7:0] 7:0 MWE window Horizontal Start. MWEHST-H 7:0 Default : 0x00 - 7:3 Reserved. MWEHST[10:8] 2:0 See description for MWEHST[7:0]. MWEVEND-L 7:0 Default : 0x06 MWEVEND[7:0] 7:0 MWE window Vertical END. MWEVEND-H 7:0 Default : 0x00 - 7:3 Reserved. MWEVEND[10:8] 2:0 See description for MWEVEND[7:0]. MWEHEND-L 7:0 Default : 0x00 MWEHEND[7:0] 7:0 MWE window Horizontal END. MWEHEND-H 7:0 Default : 0x00 - 7:3 Reserved. MWEHEND[10:8] 2:0 See description for MWEHEND[7:0]. MWEVST-L 7:0 Default : 0x00 MWEVST[7:0] 7:0 MWE of Sub window Vertical Start. MWEVST-H 7:0 Default : 0x00 - 7:3 Reserved. MWEVST [10:8] 2:0 See description for MWEVST [7:0]. ~ - 7:0 Default : - - 7:0 Reserved. SPPCTRL 7:0 Default : 0x01 - 7:3 Reserved. 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 3Ah MWE MWE MWE MWE 3Bh 3Ch 3Dh Version 0.3 Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : R/W, DB Access : Access : R/W MWECEN 2 MWE window C Peaking Enable. MWEYEN 1 MWE window Y Peaking Enable. MWEPEN 0 MWE window Peaking Function Enable. SCORING 7:0 Default : 0x00 Access : R/W SCTH_2[3:0] 7:4 MWE window Coring Threshold. SCTH_1[3:0] 3:0 MWE window Coring Threshold. MWECPK 7:0 Default : 0x08 Access : R/W - 86 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 MWE Register (Bank = 03) CPK_STP[1:0] 7:6 3Eh 3Fh 5 4:0 MWE window C Peaking Coefficient. - 7:0 Default : - - 7:0 Reserved. MWEYPK 7:0 Default : 0x08 YPK_STP[1:0] 7:6 MWE window Y Peaking Step. 5 Access : Access : R/W Reserved. YPK_COEF[4:0] 4:0 MWE window Y Peaking Coefficient. SGAMMAC 7:0 Default : 0x00 - 7:5 Reserved. SGCR - 4 3:1 SGCB 42h FFh Reserved. CPK_COEF[4:0] 40h MWE window C Peaking Step. 0 Access : R/W MWE window Gamma Correction Rounding function. 0: Disable. 1: Enable. Reserved. MWE window Gamma Correction function control. 0: Bypass gamma correction function. 1: Enable gamma correction function. ~ - 7:0 Default : - - 7:0 Reserved. Access : - REGISTER TABLE REVISION HISTORY Date 07/12/04 07/30/04 08/04/04 09/01/04 09/29/04 10/01/04 Version 0.3 Bank 01 00 01 01 00 03 Register Ÿ Created first version. Ÿ 0x0A, 0x0B, 0x17 Ÿ 0xF8 Ÿ 0x15 Ÿ 0x15 Ÿ 0x32 Ÿ 0x10-0x13, 0x47 - 87 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004 TSU16AK SXGA LCD Controller with Analog Interface and Dual LVDS Transmitter Preliminary Data Sheet Version 0.3 This page is intended to leave blank. Version 0.3 - 88 Copyright © 2004 MStar Semiconductor, Inc. All rights reserved. 10/1/2004