AU OPTOELECTRONICS CORPORATION Spec. No. Version ：0 Total pages ：18 Date ：2003/07/08 TFT-LCD CONTROLLER LSI (UPS161) PRELIMINARY SPECIFICATION (TENTATIVE) MODEL NAME: UPS161 The content of this technical information is subject to change without notice. Please contact AUO or its agent for further information. Approved by Checked by Prepared by AUO copyright 2003 All rights reserved, copying forbidden. PDF created with FinePrint pdfFactory trial version www.pdffactory.com SPEC NO.: PAGE : 1/18 Contents A. General description:................................ ................................ ................................ ........................... 2 B. Feature:................................ ................................ ................................ ................................ .............. 2 C. Pin description:................................ ................................ ................................ ................................ .. 3 D. AC characteristics ................................ ................................ ................................ .............................. 6 a. Input signal characteristics ................................ ................................ ................................ .......... 6 b. Output signal characteristics ................................ ................................ ................................ ....... 7 E. DC characteristics................................ ................................ ................................ .............................. 8 a. Absolute maximum ratings................................ ................................ ................................ .......... 8 b. Recommended operating conditions................................ ................................ ............................ 8 c. General DC characteristics................................ ................................ ................................ .......... 8 d. Current consumption for different resolution modes................................ ................................ .... 9 e. DC electrical characteristics for 3.3V operation................................ ................................ ........... 9 F. Reliability test item: ................................ ................................ ................................ ......................... 10 G. Package information ................................ ................................ ................................ ........................ 11 Appendix Appendix 1. Input timing diagram ................................ ................................ ................................ 13 Appendix 2. Output timing diagram................................ ................................ .............................. 14 Appendix 3. EDGSL function................................ ................................ ................................ ....... 18 Figures Fig1.Outline drawing ................................ ................................ ................................ ............ 11 Fig2. Marking spec. ................................ ................................ ................................ .............. 12 Fig3. Input timing ................................ ................................ ................................ ................. 13 Fig4.Output timing (WVGA) 1-4................................ ................................ .......................... 14 Fig5. Timing after setting EDGSL................................ ................................ ......................... 18 PDF created with FinePrint pdfFactory trial version www.pdffactory.com SPEC NO.: PAGE : 2/18 A. General description: This timing controller is a synchronizing signal controlling CMOS LSI for AUO COG type LCD module. It accepts 6 bits RGB digital signal and provides all the necessary control signals to the LCD source and gate drivers. This controller supports 1 channel TTL signal input for the resolution is 800x480 (WVGA) display for AUO TFT-LCD panel. B. Feature: *Single power supply: +3.3 Volts *Low power consumption (CMOS) *EMI reducing *Flicker Auto-detecting *DE/HV mode auto detection *Normal /self-test mode selecting *Built-In polarity inverted circuit *Providing timing scan signals for Left / Right and Up / Down shift control *With EDGSL pin to choose data latching mode (one/dual edge of clock) *TQFP80 package ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM UNIPAC OPTOELECTRONICS CORP. PDF created with FinePrint pdfFactory trial version www.pdffactory.com SPEC NO.: PAGE : 3/18 C. Pin description: I/ O I Power Description Remark Pin-no Symbol 1 VDD 2 DE_OUT O Test pin 3 REDUCE I To reduce EMI 4 GS1 I CKV width control setting bit (MSB) 5 GS0 I CKV width control setting bit (LSB) 6 CR1 I Reset pin 7 KYESY1 I Test pin 8 KTEST2 9 MODE 10 GND I Test pin Use pin “mode” to set normal (WVGA) or self-test mode. When MODE is “L”: using the CLKIN to generate the running Note3. I pattern (6 patterns). When MODE is “H”: Normal condition (WVGA 800 x 480 / 60Hz). - Power ground 11 GND - Power ground 12 DCLK 13 LRC 14 RI0 I Dot clock signal Normal scan set to Low I Reverse scan: set to High I Red data input (LSB) 15 RI1 I Red data input 16 RI2 I Red data input 17 RI3 I Red data input 18 RI4 I Red data input 19 RI5 I Red data input (MSB) 20 GI0 I Green data input (LSB) 21 VDD I Power 22 GI1 I Green data input 23 GI2 I Green data input 24 GI3 I Green data input 25 GI4 I Green data input 26 GI5 I Green data input (MSB) 27 BI0 I Blue data input (LSB) 28 BI1 I Blue data input 29 BI2 I Blue data input 30 BI3 I Blue data input 31 GND - Power ground PDF created with FinePrint pdfFactory trial version www.pdffactory.com Note1 Note2 SPEC NO.: PAGE Pin-no Symbol 32 BI4 I/ O I Blue data input 33 BI5 I Blue data input (MSB) 34 UDC 35 HS 36 ENAB 37 VS 38 STV1 39 STV2 40 VDD UDC=’H’, STV1 is output pin of start pulse UDC=’L’, STV1 is high impedance state. UDC=’H’, STV2 is high impedance state O UDC=’L’, STV2 is output pin of start pulse. I Power 41 VDD I Power 42 CKV O Gate-open start pulse 43 UDO O 44 OEV O 45 STHR O 46 FIELD O 47 EDGSL I 48 FY O 49 LRO O 50 GND That is if LRC is high à LRO is low And if LRC is low à LRO is high - Power ground 51 GND - Power ground 52 PCTR Flicker Detect” Setting “H” à Normal Display (Dot inversion) I “L” à Auto Detect Mode Detect “Flicker Pattern” à 2 dot inversion Detect “Non- Flicker Pattern” à Dot inversion 53 RO0 O Red data output (LSB) 54 RO1 O Red data output 55 RO2 O Red data output 56 RO3 O Red data output 57 VDD I Power I Description : 4/18 Remark Normal scan: set to Low Reverse scan: set to High I Horizontal synchronizing signal I To select DE or HV mode I Vertical synchronizing signal O That is if UDC is high à UDO is low And if UDC is low à UDO is high Vertical output enable (after power on, OEV will keep high more than 2 fields) LRC=’H’, STHR is output pin of start pulse LRC=’L’, STHR is in high impedance state. In DE MODE, controller will generator a frame signal . In HV MODE, it is VSYNC signal. “L” à Normal Operating, Data will be latched on the rising edge of FY “H” àData will be latched on the rising edge and falling edge of FY, the FY frequency is 1/2 DCLK “FY” Output Buffer Settingà 4 mA PDF created with FinePrint pdfFactory trial version www.pdffactory.com Note4 SPEC NO.: PAGE Pin-no Symbol 58 RO4 I/ O O Red data output 59 RO5 O Red data output (MSB) 60 GO0 O Green data output (LSB) 61 GO1 O Green data output 62 GND - Power ground 63 GO2 O Green data output 64 GO3 O Green data output 65 GO4 O Green data output 66 GO5 O Green data output (MSB) 67 VDD I Power 68 BO0 O Blue data output (LSB) 69 BO1 O Blue data output 70 BO2 O Blue data output 71 BO3 O Blue data output 72 BO4 O Blue data output 73 BO5 O Blue data output (MSB) 74 GND - Power ground 75 LD O Operating enable per line 76 INV O Test pin 77 POL O Polarity inversion signal 78 IPOL O Opposed to POL signal 79 STHL O 80 Note1: VDD Description LRC=’H’, STHL is in high impedance state. LRC=’L’, STHL is output pin of start pulse. I Power Use pin “Reduce” to select INV function enable or not. àWhen “Reduce” is high: INV function enable. àWhen “Reduce” is low: INV function disable. INV function: Compare nth data and n+1th data 18 bit: If data change more than 10 bit, than INV n+1 = /INV n, data n+1 = /(data n+1 XOR INV n) Otherwise INV n+1 = INV n, data n+1 = data n+1 XOR INV n. Note2. CKV pulse width setting range GS0 0 0 1 1 GS1 0 1 0 1 Tgs 30DLCK 40DLCK 50DLCK 60DLCK PDF created with FinePrint pdfFactory trial version www.pdffactory.com : 5/18 Remark SPEC NO.: PAGE : 6/18 Note3. Test Pattern Generator Generate test mode pattern and DE signal by clk (Test data and Test DE) for burn in test. This block only enables in MODE is “L”. Timing: (800 x 480) WVGA (2) Patterns Change : 1. White grayscale – 64 gray 2. 2.Red grayscale -- 64 gray 3. 3.Green grayscale – 64 gray 4.Blue grayscale -- 64 gray 5.White Screen 6.Black Screen 7.White Screen 8.Black Screen Ex) 1. White gray scale 12pixel: R(5:0)=”000000”, G(5:0)=”000000”, B(5:0)=”000000” 13-24pixel: R(5:0)=”000001”, G(5:0)=”000001”, B(5:0)=”000001” 745-756pixel: R(5:0)=”111110”, G(5:0)=” 111110”, B(5:0)=” 111110” 757-768pixel : R(5:0)=”111111”, G(5:0)=” 111111”, B(5:0)=” 111111” 769-800pixel : R(5:0)=”000000”, G(5:0)=”000000”, B(5:0)=”000000” PS1: Test Pattern Resolution: 800x480 Horizontal blanking: 128 DCLK Horizontal period : 928 DCLK Vertical blanking : 45 TH Vertical period : 525 TH Note4. If ENAB signal has high/low change, ASIC will be DE mode, All of the signals will follow DE signal operating. Otherwise, ASIC will be HV mode, output signal will follow HV_ENAB signal made by HSYNC and VSYNC. D. AC characteristics a. Input signal characteristics WVGA timing (a). DE mode Item Clock frequency Clock High time Clock Low time Clock rising time Clock falling time Horizontal blanking Vertical blanking Symbol Fck Twcl Twch Trclk Tack Thbl Tvbl Min 20 8 8 － － 95 32 Typ 33.3 － － － － 128 45 PDF created with FinePrint pdfFactory trial version www.pdffactory.com Max 40 － － 1 1 280 184 Unit MHz ns ns ns ns Clk Th Remark SPEC NO.: PAGE (b). HV mode Item Clock frequency Clock High time Clock Low time Clock rising time Clock falling time Hsync period Hsync pulse width Hsync front porch Hsync back porch Symbol Fck Twcl Twch Trclk Tack Th Thw Thf Thb Thw +Thb Thbl Tsh Thh Tv Tvw Tvf Tvbl Tvpd Tsv Thv Tds Tdh Hsync width + back porch Hsync blanking Hsync setup time Hsync hold time Vsync period Vsync pulse width Vsync front porch Vsync blanking Hsync/Vsync phase shift Vsync setup time Vsync hold time Data setup time Data hold time Item Min 20 8 8 － － 895 4 7 7 Typ 33.3 － － － － 1056 40 60 Max 40 － － 1 1 1088 81 － 84 Unit MHZ ns ns ns ns Clk Clk Clk Clk － 88 － Clk 95 5 10 512 1 － 32 2 0 2 5 10 128 280 Clk 525 3 13 45 320 610 － － 184 － Th Th Th Th Clk Symbol Value Unit The 88 Clk Vertical display start Tve 32 Th Description After falling edge of Hsync, counting 88 clk, then getting valid data from 89 th clk’s data. After falling edge of Vsync, counting 32 Th, then getting 33 th Th’s data. b. Output signal characteristics DCLK frequency DCLK cycle time CLK pulse duty Time that the POL transition to LD LD width Time that the CKV rising to LD Time that the STV1/2 rising to LD STV1/2 width Remark ns ns Horizontal display start Parameter : 7/18 Symb ol Fclk Tcph Tcw Min. Typ. Max. Unit 40 33.3 30 50 60 Mhz ns % Tpl - 1 - DCLK Tldw - 3 - DCLK Tgs 30 - 60 DCLK Tgs - 500 - DCLK Tstvw - 800 - DCLK Conditions Vcc=2.5 ~3.6V Tcph PDF created with FinePrint pdfFactory trial version www.pdffactory.com SPEC NO.: PAGE Time that the POL rising to Field Time that the DE rising to V_END Tpf - 1.5 - Th Tvend - 2484 - DCLK : 8/18 E. DC characteristics a. Absolute maximum ratings Symbol VDD VIN VIL VIH VOH VOL VOUT DCLK TSTG Parameter Power supply Input voltage Low level input voltage High level input voltage High level output voltage Low level output voltage Output voltage Operating frequency Storage temperature Rating 2.5 to 3.6 -0.3 to VDD + 0.3 GND to 0.3xVDD 0.7xVDD to VDD VDD-0.4(minimum) GND to GND+0.4 -0.3 to VDD + 0.3 20~40 -40 to 85 Units V V V V V V V MHz ℃ Remark Remark b. Recommended operating conditions Symbol VDD TOPR Parameter Power supply Min 2.7 Typ 3.3 Max 3.6 Units V Operating temperature -20 25 65 ℃ c. General DC characteristics Symbol IIL IOZ CIN COUT CBID Parameter Input leakage current Conditions no pull-up or pull-down Min -1 Typ - Max 1 Units μA -10 - 10 μA Input capacitance - 3 - pF Output capacitance 3 - 6 pF Bi-directional buffer capacitance 3 - 6 pF Tri-state leakage current PDF created with FinePrint pdfFactory trial version www.pdffactory.com SPEC NO.: PAGE : 9/18 d. Current consumption for different resolution modes Parameter Current for V CC Symbol ICC Conditions VCC1=+5V Min - Typ 5.5 Max - Units mA Remark e. DC electrical characteristics for 3.3V operation Tj= 0℃ to +65℃) Symbol Parameter VIL Input Low voltage VIH Input High voltage VOL Output low voltage VOH Output high voltage RI Input pull up/down resistance Conditions CMOS Min - Typ - CMOS IOL=4mA 0.7 x VCC3IO - - - - 0.4 V IOH=4mA 3.5 - - V - 75 - KΩ Vil=0V or Vih=VCC PDF created with FinePrint pdfFactory trial version www.pdffactory.com Max 0.3 ×VCC3IO Units V V Remark SPEC NO.: PAGE : 10/18 F. Reliability test item: No. Test items 1 High temperature storage 2 Low temperature storage 3 High temperature operation 4 Low temperature operation 5 High temperature and high humidity 6 Heat shock 7 Electrostatic discharge Note : Ta is the Ambient temperature. Conditions Ta = 80℃ 240H Ta = -25℃ 240H Ta = 60℃ 240H Ta = 0℃ 240H Ta = 60℃•95%RH 240H -25℃〜+80℃/50 cycles 2H/cycle ±200V,200pF(0Ω),once for each terminal PDF created with FinePrint pdfFactory trial version www.pdffactory.com Remark Operation Non-operation Non-operation SPEC NO.: PAGE G. Package information Fig1.Outline drawing PDF created with FinePrint pdfFactory trial version www.pdffactory.com : 11/18 SPEC NO.: PAGE Fig2. Marking spec. PDF created with FinePrint pdfFactory trial version www.pdffactory.com : 12/18 SPEC NO.: PAGE Appendix Appendix 1. Input timing diagram In p u t T im in g (W V G A ) Tv Vs Tvw Th Hs Tvf Tve T vf RGB X ,47 9 ` X ,48 0 X ,2 X ,1 X ,3 X ,4 7 9 I n v a lid X ,4 80 Tvd DE Tvbl Thb Thw Hs Th CLK Thf RGB 8 0 0 ,Y T he I n v a li d T hf 1 ,Y 2 ,Y 3,Y 7 9 9 ,Y 8 0 0,Y I n v a lid Thd T h bl DE ( 1 p ix e l/ c lo c k ) Vs Hs V IH V IH R G B ,D E ,H s V IL V IL V IH V IH CLK V IL Tvpd V IL F ig 3 . I n p u t tim in g PDF created with FinePrint pdfFactory trial version www.pdffactory.com T d s ,T e s ,T h s T d h ,T h e ,T h h Tch T cl : 13/18 SPEC NO.: PAGE Appendix 2. Output timing diagram O u tp u t T im in g (W V G A )- 1 P o rt 1 1 2 3 4 5 6 7 79 9 1 80 0 S T H L /S T H R D C LK P o rt 79 7 798 799 800 D C LK LD Tpl POL /P O L PDF created with FinePrint pdfFactory trial version www.pdffactory.com T ld w 2 3 : 14/18 SPEC NO.: PAGE O u tp u t T im in g (W V G A )-2 LD Tgs CKV I/P D E I/P D ata V ertical B lanking period 477 478 479 480 476 477 478 479 1 2 3 4 1 2 3 DE O /P D ata 480 STV 1/STV 2 LD CKV * D u rin g v ertical b lan k in g p erio d ,s till h a v e L D & C K V & P O L & /P O L p u lse . PDF created with FinePrint pdfFactory trial version www.pdffactory.com : 15/18 SPEC NO.: PAGE Output Timing (WVGA)-3 STV1/STV2 Tstv LD Tsl Vcc DE OEV *After power on, OEV will keep high more than 2 field. 1H Vertical Blanking ENAB POL /POL Tpf Field *POL polarity shoudle be different in different field. */POL=POL inverting PDF created with FinePrint pdfFactory trial version www.pdffactory.com : 16/18 SPEC NO.: PAGE Output Timing (WVGA) - 4 DE V_END Tvend If DE_Sel didn`t High/Low change then “Frame End” Fig4. Output timing (WVGA) 1~4 PDF created with FinePrint pdfFactory trial version www.pdffactory.com : 17/18 SPEC NO.: PAGE Appendix 3. EDGSL function A.EDGSL = “L” Data 1 2 3 4 FY(1 DCLK) STHL/R B.EDGSL= “H” FY(1/2 DCLK) Data 1 2 3 4 5 STHL/R Fig5. Timing after setting EDGSL PDF created with FinePrint pdfFactory trial version www.pdffactory.com 6 7 5 : 18/18