ETC MAXQ613

19-5320; Rev 2; 8/10
具有红外模块的16位微控制器
♦♦3个独立的数据指针具有自动递增 / 递减特性，
加速数据转移
用于通用遥控器、消费类电子和白色家电等低功耗产品。器
件结合了强大的16 位 RISC 微控制器和集成外设，包括一个
通用同步/异步接收-发送器 (USART) 和一个SPI™ 主 /从通
信接口，以及能够产生载波频率的IR 模块和灵活的复用键
盘控制I/O。
♦♦专用指针用于直接读取程序空间
♦♦16位指令字，16位数据总线
♦♦16 x 16 位通用工作寄存器
♦♦安全 MMU用于分区和 IP保护
器件包含 48KB 程序闪存和1.5KB 数据 SRAM。通过安全
MMU 提供知识产权(IP) 保护，该安全 MMU 可支持多种授权
等级配置，保护代码不被复制和进行逆向工程。授权等级使
厂商可以提供器件运行的库文件和应用程序，并通过授权
限制对数据和代码的访问。
为实现低功耗电池供电设计，器件包括一个超低功耗停止模
式 (0.2 µA，典型值 )。该模式下，只有少数电路保持供电。
唤醒源包括外部中断、电源失效中断以及定时器中断。微控
制器工作在1.70V 至 3.6V 较宽的电压范围内。
应用
远端控制
家用产品
电池供电的便携式设备
白色家电
消费类电子
特性
♦♦高性能、低功耗、16位RISC内核
♦♦在整个工作电压范围内具有直流至12MHz 工作频率
♦♦1.70V至3.6V工作电压
♦♦存储器特性
48KB 程序闪存
512字节扇区
每个扇区所允许的擦除 / 写次数为20,000次
可屏蔽ROM
1.5KB 数据SRAM
♦♦其它外设
电源失效报警
上电复位(POR)/ 掉电复位
自动 IR 载波频率发生器和调制器
2个16位、可编程定时器/ 计数器，带预调节和捕获 /比
较功能
一个SPI和一个USART端口
可编程看门狗定时器
8kHz 超微功耗环型振荡器唤醒定时器
多达 24个通用 I/O
♦♦低功耗
停止模式下，TA = +25°C、电源失效监测器禁止时，
电流仅为 0.2µA (典型值)、2.0µA (最大值)
工作模式下，12MHz 时电流为3.25mA (典型值)
定购信息 / 选型指南
PART
TEMP RANGE
OPERATING
VOLTAGE (V)
PROGRAM
MEMORY (KB)
DATA
MEMORY (KB)
GPIO
MAXQ613A-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
20
32 TQFN-EP*
MAXQ613E-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
20
32 LQFP
MAXQ613J-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
24
44 TQFN-EP*
MAXQ613K-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
24
44 TQFP
MAXQ613X-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
24
Bare die
PIN-PACKAGE
+表示无铅(Pb)/ 符合 RoHS 标准的封装。
*EP= 裸焊盘。
MAXQ 是 MaximIntegratedProducts,Inc. 的注册商标。
SPI是 Motorola,Inc. 的商标。
注意：该器件某些版本的规格可能与发布的规格不同，会以勘误表的形式给出。通过不同销售渠道可能同时获得器件的多个版本。欲了解器件勘误
表信息，请点击：china.maxim-ic.com/errata。
________________________________________________________________ Maxim Integrated Products 1
本文是英文数据资料的译文，文中可能存在翻译上的不准确或错误。如需进一步确认，请在您的设计中参考英文资料。
有关价格、供货及订购信息，请联络Maxim亚洲销售中心：10800 852 1249 (北中国区)，10800 152 1249 (南中国区)，
或访问Maxim的中文网站：china.maxim-ic.com。
MAXQ613
♦♦总共 33条指令简化了编程
概述
®
MAXQ613 是一款低功耗、16 位 MAXQ 微控制器，设计
MAXQ613
具有红外模块的16位微控制器
目录
AbsoluteMaximumRatings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
RecommendedOperatingConditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SPIElectricalCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
引脚配置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
引脚说明 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
方框图 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
详细说明 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
微处理器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
存储器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
存储器保护. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
堆栈存储器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
固定用途 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
看门狗定时器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IR载波发生器和调制定时器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
载波发生模块 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IR 发送 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IR 发送—独立的外部载波和调制器输出. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IR 接收 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
载波突发计数模式.......................................................... 18
16位定时器 /计数器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
串行外设接口(SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
通用I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
片内振荡器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ROM加载器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
装入闪存 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
在应用闪存编程 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
在电路调试和 JTAG 接口 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
工作模式 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
电源失效检测 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
应用信息 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
接地和旁路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
其它文档 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MAXQ613与 MAXQ610用户指南的不同之处 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
开发和技术支持 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
封装信息 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
修订历史 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 _______________________________________________________________________________________
具有红外模块的16位微控制器
图1.IR 发送频偏示例 (IRCFME=0) .
.............
...........
图3.IR 发送波形 (IRCFME=0) . . . . . . . . . . . . . . . . .
图 4. 外部IRTXM(调制器) 输出. . . . . . . . . . . . . . . . .
图 5.IR 采集 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
图 6. 接收突发计数示例. . . . . . . . . . . . . . . . . . . . . .
图 7.SPI主机通信时序 . . . . . . . . . . . . . . . . . . . . . . .
图 8.SPI从机通信时序 . . . . . . . . . . . . . . . . . . . . . . .
图 9. 片内振荡器 . . . . . . . . . . . . . . . . . . . . . . . . . .
图10. 在电路调试器 . . . . . . . . . . . . . . . . . . . . . . . .
图11. 标准工作模式下的电源失效检测 . . . . . . . . . . . . .
图12. 停止模式下电源失效检测状态，使能电源失效监测器 .
图13. 停止模式下电源失效检测状态，禁用电源失效监测器 .
图2.IR 发送载波发生器和载波调制器控制
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13
14
19
24
25
26
表目录
表1. 存储区和对应的最高优先级
................
表 2. 看门狗中断超时 (Sysclk=12MHz，CD[1:0]=00) .
表3.USART模式列表 . . . . . . . . . . . . . . . . . . . . . .
表4. 标准工作模式下的电源失效检测状态. . . . . . . . . .
表5. 停止模式下电源失效检测状态，使能电源失效监测器 .
表 6. 停止模式下电源失效检测状态，禁用电源失效监测器.
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_______________________________________________________________________________________ 3
MAXQ613
图目录
MAXQ613
具有红外模块的16位微控制器
Absolute Maximum Ratings
44-Pin TQFN (single-layer board)
(derate 27mW/NC above +70NC).............................2162.2mW
44-Pin TQFN (multilayer board)
(derate 37mW/NC above +70NC)................................2963mW
44-Pin TQFP (multilayer board)
(derate 19mW/NC above +70NC)................................1504mW
Operating Temperature Range.............................. 0NC to +70NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (excluding dice; soldering, 10s).......+300NC
Soldering Temperature (reflow).......................................+260NC
Voltage Range on VDD with Respect to GND......-0.3V to +3.6V
Voltage Range on Any Lead with
Respect to GND Except VDD................ -0.3V to (VDD + 0.5V)
Continuous Power Dissipation (TA = +70NC)
32-Pin TQFN (single-layer board)
(derate 21.3mW/NC above +70NC)..........................1702.1mW
32-Pin TQFN (multilayer board)
(derate 34.5mW/NC above +70NC)..........................2758.6mW
32-Pin LQFP (multilayer board)
(derate 20.7mW/NC above +70NC)..........................1652.9mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
1.8V Internal Regulator
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
VRST
3.6
V
VREG18
1.62
1.8
1.98
V
Power-Fail Warning Voltage for
Supply
VPFW
Monitors VDD (Note 2)
1.75
1.8
1.85
V
Power-Fail Reset Voltage
VRST
Monitors VDD (Note 3)
1.64
1.67
1.70
V
POR Voltage
VPOR
Monitors VDD
RAM Data-Retention Voltage
VDRV
(Note 4)
Active Current
IDD_1
Sysclk = 12MHz (Note 5)
IS1
Power-Fail Off
Stop-Mode Current
1
1.42
1.0
V
V
3.25
4
TA = +25NC
0.2
2.0
TA = 0°C to +70NC
TA = +25NC
0.2
8
22
29.5
TA = 0°C to +70NC
27.6
42
mA
FA
IS2
Power-Fail On
Current Consumption During
Power-Fail
IPFR
(Note 6)
[(3 x IS2) +
((PCI - 3) x (IS1 +
INANO))]/PCI
FA
Power Consumption During
POR
IPOR
(Note 7)
100
nA
Stop-Mode Resume Time
tON
375 + (8192 x
tHFXIN)
Fs
Power-Fail Monitor Startup
Time
tPFM_ON
(Note 4)
Power-Fail Warning Detection
Time
tPFW
(Note 8)
Input Low Voltage for IRTX,
IRRX, RESET, and All Port Pins
VIL
VGND
0.3 x VDD
V
Input High Voltage for IRTX,
IRRX, RESET, and All Port Pins
VIH
0.7 x VDD
VDD
V
150
10
Fs
Fs
4 _______________________________________________________________________________________
具有红外模块的16位微控制器
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
PARAMETER
Input Hysteresis (Schmitt)
SYMBOL
VIHYS
CONDITIONS
MIN
TYP
MAX
300
VDD = 3.3V, TA = +25NC
UNITS
mV
Input Low Voltage for HFXIN
VIL_HFXIN
VGND
0.3 x VDD
V
Input High Voltage for HFXIN
VIH_HFXIN
0.7 x VDD
VDD
V
IRRX Input Filter Pulse-Width
Reject
tIRRX_R
50
ns
IRRX Input Filter Pulse-Width
Accept
tIRRX_A
Output Low Voltage for IRTX
VOL_IRTX
300
VDD = 3.6V, IOL = 25mA (Note 3)
VDD = 2.35V, IOL = 10mA (Note 3)
1.0
VDD = 1.85V, IOL = 4.5mA
1.0
0.4
0.5
VDD = 2.35V, IOL = 8mA (Note 3)
VDD = 1.85V, IOL = 4.5mA
0.4
0.5
0.4
0.5
VOL
Output High Voltage for IRTX
and All Port Pins
VOH
IOH = -2mA
Input/Output Pin Capacitance
for All Port Pins
CIO
(Note 4)
Input Pullup Resistor for
RESET, IRTX, IRRX, P0, P1, P2
IL
RPU
1.0
VDD = 3.6V, IOL = 11mA (Note 3)
Output Low Voltage for RESET
and All Port Pins (Note 9)
Input Leakage Current
ns
Internal pullup disabled
VDD - 0.5
-100
V
V
VDD
V
15
pF
+100
nA
VDD = 3.0V, VOL = 0.4V (Note 4)
16
28
39
VDD = 2.0V, VOL = 0.4V
17
30
41
kW
EXTERNAL CRYSTAL/RESONATOR
Crystal/Resonator
fHFXIN
Crystal/Resonator Period
tHFXIN
Crystal/Resonator Warmup
Time
Oscillator Feedback Resistor
tXTAL_RDY
ROSCF
1
From initial oscillation
(Note 4)
0.5
12
MHz
1/fHFXIN
ns
8192 x
tHFXIN
ms
1.0
1.5
MW
12
MHz
EXTERNAL CLOCK INPUT
External Clock Frequency
fXCLK
External Clock Period
tXCLK
External Clock Duty Cycle
DC
1/fXCLK
tXCLK_DUTY (Note 4)
System Clock Frequency
fCK
System Clock Period
tCK
45
ns
55
fHFXIN
HFXOUT = GND
%
MHz
fXCLK
1/fCK
ns
NANOPOWER RING
TA = +25NC
3.0
8.0
Nanopower Ring Frequency
fNANO
TA = +25NC, VDD = POR voltage
(Note 4)
1.7
2.4
Nanopower Ring Duty Cycle
tNANO
(Note 4)
40
Nanopower Ring Current
INANO
Typical at VDD = 1.64V,
TA = +25°C (Note 4)
40
20.0
kHz
60
%
400
nA
_______________________________________________________________________________________ 5
MAXQ613
RECOMMENDED OPERATING CONDITIONS (continued)
MAXQ613
具有红外模块的16位微控制器
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
65,535/
fNANO
s
WAKE-UP TIMER
Wake-Up Timer Interval
tWAKEUP
1/fNANO
fFPSYSCLK
6
FLASH MEMORY
System Clock During Flash
Programming/Erase
Flash Erase Time
Flash Programming Time per
Word
MHz
tME
Mass erase
20
40
tERASE
Page erase
20
40
tPROG
(Note 10)
20
100
Write/Erase Cycles
Data Retention
TA = +25NC
ms
Fs
20,000
Cycles
100
Years
IR
Carrier Frequency
fIR
(Note 4)
fCK/2
Hz
MAX
UNITS
SPI Electrical Characteristics
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 11)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
SPI Master Operating
Frequency
1/tMCK
fCK/2
MHz
SPI Slave Operating
Frequency
1/tSCK
fCK/4
MHz
SPI I/O Rise/Fall Time
tSPI_RF
23.6
ns
SCLK Output Pulse-Width
High/Low
CL = 15pF, pullup = 560W
8.3
tMCH, tMCL
tMCK/2 tSPI_RF
ns
MOSI Output Hold Time After
SCLK Sample Edge
tMOH
tMCK/2 tSPI_RF
ns
MOSI Output Valid to Sample
Edge
tMOV
tMCK/2 tSPI_RF
ns
MISO Input Valid to SCLK
Sample Edge Rise/Fall Setup
tMIS
25
ns
MISO Input to SCLK Sample
Edge Rise/Fall Hold
tMIH
0
ns
SCLK Inactive to MOSI
Inactive
tMLH
tMCK/2 tSPI_RF
ns
SCLK Input Pulse-Width High/
Low
tSCH, tSCL
tSCK/2
ns
SSEL Active to First Shift
Edge
tSSE
tSPI_RF
ns
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
tSIS
tSPI_RF
ns
6 _______________________________________________________________________________________
具有红外模块的16位微控制器
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 11)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MOSI Input from SCLK
Sample Edge Transition Hold
tSIH
MISO Output Valid After SCLK
Shift Edge Transition
tSOV
SSEL Inactive
tSSH
tCK +
tSPI_RF
ns
SCLK Inactive to SSEL Rising
tSD
tSPI_RF
ns
MISO Output Disabled After
SSEL Edge Rise
tSLH
tSPI_RF
ns
2tSPI_RF
2tCK +
2tSPI_RF
ns
ns
Note 1: Specifications to 0NC are guaranteed by design and are not production tested. Typical = +25NC, VDD = +3.3V, unless
otherwise noted.
Note 2: VPFW can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V ±3%. The values
listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal.
Note 3: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals
is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is
achieved.
Note 4: Guaranteed by design and not production tested.
Note 5: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or VDD. Outputs do not source/
sink any current. The device is executing code from flash memory.
Note 6: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles.
Note 7: Current consumption during POR when powering up while VDD is less than the POR release voltage.
Note 8: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected; refer to the MAXQ610
User’s Guide for details.
Note 9: The maximum total current, IOH(MAX) and IOL(MAX), for all listed outputs combined should not exceed 32mA to satisfy the
maximum specified voltage drop. This does not include the IRTX output.
Note 10:Programming time does not include overhead associated with utility ROM interface.
Note 11:AC electrical specifications are guaranteed by design and are not production tested.
_______________________________________________________________________________________ 7
MAXQ613
SPI Electrical Characteristics (continued)
引脚配置
P2.5/TDI 25
16
P1.4/INT4
P2.6/TMS 26
15
VDD
P2.7/TDO 27
14
REGOUT
13
GND
12
P1.3/INT3
11
P1.2/INT2
10
P1.1/INT1
9
P1.0/INT0
GND 30
IRTX 31
EP
+
P0.2/TX/INT10
P0.3/INT11
5
6
7
8
P0.7/TBB1/INT15
4
P0.6/TBB0/INT14
3
P0.4/INT12
2
P0.5/TBA0/TBA1/INT13
1
P0.1/RX/INT9
IRRX 32
P1.6/INT6
HFXOUT
HFXIN
P1.5/INT5
17
P2.5/TDI 25
16
P1.4/INT4
P2.6/TMS 26
15
VDD
P2.7/TDO 27
14
REGOUT
13
GND
VDD 29
12
P1.3/INT3
GND 30
11
P1.2/INT2
IRTX 31
10
P1.1/INT1
9
P1.0/INT0
RESET 28
MAXQ613
IRRX 32
+
TQFN
(5mm × 5mm)
1
2
3
4
5
6
7
8
P2.3/SSEL
P2.2/SCLK
N.C.
N.C.
P2.1/MISO
GND
P2.0/MOSI
P1.7/INT7
P1.6/INT6
HFXOUT
HFXIN
32
31
30
29
28
27
26
25
24
23
LQFP
(7mm × 7mm)
33
TOP VIEW
18
P0.7/TBB1/INT15
VDD 29
19
P0.6/TBB0/INT14
MAXQ613
20
P0.5/TBA0/TBA1/INT13
RESET 28
21
P0.4/INT12
17
P1.7/INT7
18
22
P0.3/INT11
P1.5/INT5
19
GND
HFXIN
20
23
P0.2/TX/INT10
HFXOUT
21
N.C.
P1.6/INT6
22
24
P0.1/RX/INT9
P1.7/INT7
23
P2.4/TCK
GND
24
TOP VIEW
P0.0/IRTXM/INT8
N.C.
TOP VIEW
P2.4/TCK
P0.0/IRTXM/INT8
P2.4/TCK
34
22
P1.5/INT5
P2.5/TDI
35
21
P1.4/INT4
N.C.
36
20
GND
N.C.
37
19
VDD
P2.6/TMS
38
18
REGOUT
P2.7/TDO
39
17
GND
RESET
40
16
N.C.
VDD
41
15
N.C.
GND
42
14
P1.3/INT3
IRTX
43
13
P1.2/INT2
IRRX
44
12
P1.1/INT1
MAXQ613
EP
5
6
7
8
9
10
11
P0.2/TX/INT10
P0.3/INT11
P0.4/INT12
P0.5/TBA0/TBA1/INT13
P0.6/TBB0/INT14
P0.7/TBB1/INT15
P1.0/INT0
3
P0.1/RX/INT9
4
2
N.C.
1
N.C.
+
P0.0/IRTXM/INT8
MAXQ613
具有红外模块的16位微控制器
TQFN
(7mm × 7mm)
8 _______________________________________________________________________________________
具有红外模块的16位微控制器
P2.3/SSEL
P2.2/SCLK
N.C.
N.C.
P2.1/MISO
GND
P2.0/MOSI
P1.7/INT7
P1.6/INT6
HFXOUT
HFXIN
TOP VIEW
33
32
31
30
29
28
27
26
25
24
23
P2.4/TCK 34
22
P1.5/INT5
P2.5/TDI 35
21
P1.4/INT4
N.C. 36
20
GND
N.C. 37
19
VDD
P2.6/TMS 38
18
REGOUT
17
GND
RESET 40
16
N.C.
MAXQ613
P2.7/TDO 39
VDD 41
15
N.C.
GND 42
14
P1.3/INT3
IRTX 43
13
P1.2/INT2
12
P1.1/INT1
1
2
3
4
5
6
7
8
9
10
11
N.C.
P0.1/RX/INT9
N.C.
P0.2/TX/INT10
P0.3/INT11
P0.4/INT12
P0.5/TBA0/TBA1/INT13
P0.6/TBB0/INT14
P0.7/TBB1/INT15
P1.0/INT0
+
P0.0/IRTXM/INT8
IRRX 44
TQFP
(10mm × 10mm)
NOTE: CONTACT FACTORY FOR BARE DIE PAD CONFIGURATION.
引脚说明
引脚
裸片
32 TQFNEP/LQFP
44 TQFNEP/TQFP
名称
功能
15, 36
15, 29
19, 41
VDD
电源引脚
电源电压。
13, 16, 25,
37
13, 22, 30
17, 20, 28,
42
GND
地，直接连接至地平面。
14
14
18
REGOUT
—
—
—
EP
1.8V 稳压器输出。该引脚必须通过一个1.0 μF(ESR：2Ω至10 Ω)陶瓷电容连接
至地。电容应尽可能靠近该引脚放置。除电容外，该引脚不应连接其它元件。
裸焊盘 (TQFN 封装 )。将 EP直接连接至地平面。
_______________________________________________________________________________________ 9
MAXQ613
引脚配置(续)
MAXQ613
具有红外模块的16位微控制器
引脚说明(续)
引脚
裸片
32 TQFNEP/LQFP
44 TQFNEP/TQFP
名称
功能
复位引脚
35
28
40
低电平有效的数字复位输入 / 输出。该引脚为低电平时，器件保持为复位状
态；该引脚返回至高电平时，从固定用途 ROM 的地址 8000h 开始执行指令。
该引脚具有上拉电流源，由外部器件驱动时，应由能够吸收大于4mA 的漏
极开路信号源驱动。如果无需通过外部信号将器件置于复位状态，可以不连
接该引脚。出现内部复位条件时，该引脚作为输出拉低。
RESET
时钟引脚
20
18
23
HFXIN
21
19
24
HFXOUT
高频晶体输入。在 HFXIN 和 HFXOUT之间连接外部晶体或谐振器作为高频系
统时钟。或者，当 HFXOUT 不连接时，HFXIN 作为外部高频时钟源输入。
IR 功能引脚
38
31
43
IRTX
39
32
44
IRRX
IR 发送输出。IR 发送引脚能够吸收 25mA电流。以任何形式复位时，该引脚
默认为高阻输入，禁止弱上拉。解除复位状态后，软件必须配置该引脚，
以脱离高阻输入状态。
IR 接收输入。以任何形式复位时，该引脚默认为高阻输入，禁止弱上拉。
解除复位状态后，软件必须配置该引脚，以脱离高阻输入状态。
通用 I/O 和特殊功能引脚
端口 0 通用数字I/O引脚。这些端口引脚用作通用I/O引脚时，其输入和输出状
态由 PD0、PO0 和 PI0 寄存器控制。复位后，所有端口引脚默认为高阻模式。
解除复位状态后，软件必须配置这些引脚，以脱离高阻状态。使用这些端口
引脚的特殊功能之前，必须通过软件使能这些功能。
GPIO 端口引脚
特殊功能
P0.0
IR 调制器输出 /INT8
1
1
1
P0.0/IRTXM/
INT8
2
2
3
P0.1/RX/
INT9
P0.1
USART 接收 /INT9
3
3
5
P0.2/TX/
INT10
P0.2
USART发送 /INT10
4
4
6
P0.3/INT11
P0.3
INT11
5
5
7
P0.4/INT12
P0.4
6
6
8
P0.5/TBA0/
TBA1/INT13
P0.5
INT12
B 类定时器 0引脚A 或 B 类定时器
1引脚A/INT13
10 ��
具有红外模块的16位微控制器
引脚
名称
功能
裸片
32 TQFNEP/LQFP
44 TQFNEP/TQFP
7
7
9
P0.6/TBB0/
INT14
P0.6
B 类定时器 0引脚 B/INT14
8
8
10
P0.7/TBB1/
INT15
P0.7
B 类定时器1引脚 B/INT15
端口1通用数字I/O引脚，带中断功能。这些端口引脚用作通用I/O引脚时，其
输入和输出状态由 PD1、PO1和 PI1寄存器控制。复位后，所有端口引脚默认
为高阻模式。解除复位状态后，软件必须配置这些引脚，以脱离高阻状态。
使用这些端口引脚的外部中断功能之前，必须通过软件使能这些外部中断。
GPIO 端口引脚
外部中断
9
9
11
P1.0/INT0
P1.0
INT0
10
10
12
P1.1/INT1
P1.1
INT1
11
11
13
P1.2/INT2
P1.2
INT2
12
12
14
P1.3/INT3
P1.3
INT3
17
16
21
P1.4/INT4
P1.4
INT4
18
17
22
P1.5/INT5
P1.5
INT5
22
20
25
P1.6/INT6
P1.6
INT6
23
21
26
P1.7/INT7
P1.7
INT7
端口2 通用数字I/O引脚。这些端口引脚用作通用I/O引脚时，其输入和输出状
态由 PD2、PO2 和 PI2寄存器控制。复位后，所有端口引脚默认为高阻模式。
解除复位状态后，软件必须配置这些引脚，以脱离高阻状态。使用这些端口
引脚的特殊功能之前，必须通过软件使能这些功能。
GPIO 端口引脚
特殊功能
24
—
27
P2.0/MOSI
P2.0
26
—
29
P2.1/MISO
P2.1
28
—
32
P2.2/SCLK
P2.2
SPI：主出从入
SPI：主入从出
SPI：从机时钟
30
—
33
P2.3/SSEL
P2.3
31
24
34
P2.4/TCK
P2.4
32
25
35
P2.5/TDI
P2.5
33
26
38
P2.6/TMS
P2.6
34
27
39
P2.7/TDO
P2.7
SPI：低电平有效的从机选择
JTAG：测试时钟
JTAG：测试数据输入
JTAG：测试模式选择
JTAG：测试数据输出
未连接的引脚
—
23
2, 4, 15, 16,
30, 31, 36,
37
N.C.
无连接。内部没有连接。
______________________________________________________________________________________ 11
MAXQ613
引脚说明(续)
MAXQ613
具有红外模块的16位微控制器
方框图
MAXQ613
REGULATOR
16-BIT MAXQ
RISC CPU
IR DRIVER
VOLTAGE
MONITOR
CLOCK
48KB FLASH
MEMORY
IR TIMER
GPIO
WATCHDOG
1.5KB
UTILITY ROM
SPI
2x
16-BIT TIMER
8kHz NANO
RING
5.5KB
DATA SRAM
USART
详细说明
MAXQ613 提供低成本集成解决方案，简化了通用远端控
制等IR 通信设备的设计。其标准功能电路包括经过高度优化
的单周期 MAXQ16 位 RISC 内核、48KB 程序闪存、1.5KB
数据 RAM、软件堆栈、16 个通用寄存器和 3 个数据指针。
MAXQ 内核提供业界最好的 MIPS/mA指标，使开发人员能
够以很低的时钟速率获得与微控制器竞争产品相同的性能。
较低的工作电流和极低的 MAXQ613 停止模式电流(0.2μA，
典型值 ) 相结合，大大延长了电池使用寿命。专用外设包括
用于产生IR 载波频率和调制的灵活定时器、适合IR 应用能
够吸收 25mA电流的大电流IR 驱动引脚和能够吸收 5mA电
流的输出引脚。此外还包括适合键盘矩阵输入的通用I/O 引
脚以及电源失效检测电路，当电源电压接近微控制器最小工
作电压时，该电路向应用程序发出报警。
83.3ns)中执行完毕，实际代码操作接近12MIPS。无需器件
工作时，软件可以启动超低功耗停止模式，其静态电流小于
0.2μA(典型值 ) 和 2.0 μA(最大值 )。与微控制器竞争产品
相比，高性能指令和极低的停止模式电流相结合，大大延长
了电池使用时间。集成 POR电路支持掉电保护复位，能够在
上电或电压跌落时将器件复位到已知状态。此外，当系统电
压降至电源失效报警门限VPFW 以下时，电源失效报警标志
被置位，产生电源失效中断。电源失效报警功能使应用程序
能够提醒用户：系统供电电压过低，应采取相应措施。
微处理器
该器件基于 Maxim 的低功耗16 位 MAXQ 系列 RISC 核，内
核支持哈佛存储器体系结构，具有单独的16 位程序和数据
地址总线。采用标准的固定16 位指令字，但数据可以排列
为 8 位或16 位。该器件的 MAXQ 内核可以作为流水线处理
器，性能接近于1MIPS/MHz。16 位数据通路围绕寄存器模
块运行，每个寄存器模块为内核提供特殊功能。累加器模
块包括十六个16 位寄存器，与算术逻辑单元 (ALU) 密切配
合。可配置软件堆栈支持程序流程。
功能寄存器模块之间或功能寄存器模块与存储器之间的数
据传输将触发执行指令。由于数据移动只涉及到源模块和目
的模块，因此，电路切换仅限于工作模块。对于节电应用，
这种方法能够有效降低功耗和开关噪声。模块化体系结构非
常灵活并可重复使用，这对于嵌入式应用中的微处理器非常
重要。
MAXQ 指令集高度正交。所有算术和逻辑运算都可以使用
任意寄存器和累加器。数据可以在任意寄存器之间传送。通
过可自动递增 / 递减的特殊数据指针寄存器访问存储器。
该器件的核心部分是 MAXQ16 位 RISC 核。工作在直流
至12MHz，几乎所有指令都在一个时钟周期 (12MHz 时为
12 ��
具有红外模块的16位微控制器
该款微控制器采用了以下几类存储器：
固定用途ROM
•48KB 程序闪存
•5.5KB 固定用途 ROM
固定用途 ROM 是一个 5.5KB 的内部 ROM 存储器块，起始于
程序空间的地址 8000h。该 ROM 包括以下程序：
•软件堆栈
•通过JTAG 接口进行在系统编程(引导加载程序)
•1.5KBSRAM 数据存储器
•通过JTAG 接口进行在电路调试程序
存储器保护
•生产测试程序(内部存储器测试、存储器加载程序等)，仅用
于内部测试，一般来说对终端应用开发人员没有作用
可选存储器保护功能将代码存储器分成三个区：系统、用户
加载程序和用户应用程序。系统区代码具有加密功能。用户
区程序不会影响读写系统代码。用户加载程序也不受用户应
用程序的影响。
•用于在应用闪存编程、缓存器复制和快速查找表的用户可调
用程序 ( 这些程序的更多信息，请参见MAXQ610 用户指南
(Englishonly))
利用代码优先级对存储器进行保护，每个区都有相关的
优先级。RAM/ROM 也分配了优先级，详细信息请参考
MAXQ610用户指南 (Englishonly)，参见表1。
堆栈存储器
器件提供软件堆栈，用于存储程序的返回地址 (子程序调用
和中断处理 ) 和其它通用数据。软件堆栈位于1.5KBSRAM
数据存储器内，这意味着软件堆栈和通用应用数据存储必
须共用 SRAM 数据存储器。软件堆栈的位置和大小由用户设
定，在为特定应用分配资源时，具有极大的灵活性。当执行
CALL、RET 和 RETI指令以及进行中断服务时，处理器自动
使用堆栈。应用程序也可以使用 PUSH、POP 和 POPI指令，
在堆栈中存储数据并取回数据。
SP 指针指示当前的栈顶，初始化时默认为 SRAM 数据存
储器的顶部。随着数据被压入堆栈，SP 指针递减，表明堆
栈向数据存储器的底部 (最低地址 ) 扩展。数据弹出堆栈将
无论以何种方式复位，都从地址 8000h 的固定用途 ROM 开
始运行程序。此时，除非调用加载模式或测试模式 (需通过
JTAG 接口进行特殊编程 )，否则器件的固定用途 ROM 总是
自动跳转至 0000h 位置，即程序闪存中用户应用程序的起
始处。
某些应用要求保护程序存储器，以防止在未经许可的情况下
查看程序。对于这类应用，除非提供密码，否则禁止进行
在系统编程、在应用编程或在电路调试。提供三个不同的密
码锁，分别用于保护不同的存储区(系统存储器、用户加载
程序和用户应用程序)。每个密码锁由闪存中的一个16 字长
区域控制，如果密码设置为 FFFFh 或 0000h，则禁用密码
功能。否则，将使能密码功能，并且只有在密码与用户通过
引导加载器或调试器提供的密码匹配时，才允许访问相应的
程序闪存区，详细信息请参见MAXQ610 用户指南 (English
only)。
表1. 存储区和对应的最高优先级
AREA
PAGE ADDRESS
MAXIMUM PRIVILEGE LEVEL
System
0 to ULDR-1
High
Medium
User Loader
ULDR to UAPP-1
User Application
UAPP to top
Low
Utility ROM
N/A
High
Other (RAM)
N/A
Low
______________________________________________________________________________________ 13
MAXQ613
使 SP 指针值增加。详细信息请参见MAXQ610 用户指南
(Englishonly)。
存储器
MAXQ613
具有红外模块的16位微控制器
表 2. 看门狗中断超时(Sysclk = 12MHz，CD[1:0] = 00)
WD[1:0]
WATCHDOG CLOCK
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (μs)
00
Sysclk/215
2.7ms
42.7
01
Sysclk/218
21.9ms
42.7
10
Sysclk/221
174.7ms
42.7
11
Sysclk/224
1.4s
42.7
看门狗定时器
内部看门狗定时器大大提高了系统可靠性。如果软件运行受
到干扰，定时器会复位器件。看门狗定时器是一个自由运行
的计数器，可以由应用软件进行周期性复位。如果软件运行
正常，那么计数器会被周期性复位，并且永远不会达到最大
计数值。然而，如果软件工作中断，定时器不再复位，从而
触发系统复位和可选的看门狗定时器中断。这样就保护系统
不受电气噪声或静电放电 (ESD) 干扰的影响，造成不可控制
的处理器操作。早期设计采用外部看门狗器件，内部看门狗
定时器是对这类设计的改进，在降低系统成本的同时提高
了系统可靠性。
看门狗定时器既可以作为看门狗定时器的超时源，也可以作
为看门狗定时器的复位源。可以在 215 至 224 个系统时钟周期
范围内设置超时周期。如果使能中断，达到超时周期时将产
生中断。所有看门狗定时器在可编程中断超时 512 个系统时
钟周期后复位。如果在此期间，看门狗定时器在另一完整的
周期间隔内没有重新启动，则复位超时后使系统复位，参考
表 2。
接收。IRTX 引脚没有指定对应的端口，因此，不存在标准
的 PD、PO 和 PI端口控制状态位。然而，当IR 定时器没有使
能时 (即IREN=0)，可以通过 PWCN.IRTXOUT 和 PWCN.
IRTXOE 位控制IRTX引脚输出高电平或低电平。
IR 定时器由载波发生器和载波调制器构成。载波发生模
块使用16 位IR 载波寄存器 (IRCA)，通过IR 载波高位字节
(IRCAH) 和IR 载波低位字节(IRCAL)定义载波的上限和下限
时间。载波调制器通过IR 数据位 (IRDATA) 和IR 调制器时间
寄存器 (IRMT)决定IRTX 上是否出现载波或空闲状态。
当IR使能位 (IREN)置1 时，使能IR 定时器。IR 数值寄存器
(IRV)定义载波调制器的起始值。发送期间，IRV 寄存器首
先装载IRMT值，开始递减至 0000h ；接收模式下，从IRV
寄存器初始值开始递增计数。接收操作期间，在所选边沿
采集数据后，可以配置IRV 寄存器重新装载 0000h，也可
以在接收期间继续自由运行。当IR 定时器值从0FFFFh 翻转
至 0000h 时，出现溢出。IR 溢出标志(IROV)置1，如果中断
使能 (IRIE=1)，将产生一次中断。
IR 载波发生器和调制定时器
专用IR 定时器 /计数器模块简化了低速红外 (IR) 通信的实现。
IR 定时器采用两个引脚 (IRTX 和IRRX) 分别支持IR 发送和
14 ��
具有红外模块的16位微控制器
IRCAH 字节针对IR 输入时钟数定义了载波上限时间，而
IRCAL字节定义了载波下限时间。
•IR 输入时钟(fIRCLK)=fSYS/2IRDIV[1:0]
•载波频率(fCARRIER)=fIRCLK/(IRCAH+IRCAL+2)
•载波上限时间=IRCAH+1
•载波下限时间=IRCAL+1
•载波占空比=(IRCAH+1)/(IRCAH+IRCAL+2)
发送期间，在每个IRV 递减计数间隔内锁存IRCA寄存器，
在每一个新的IRV 递减计数间隔开始时，IRCA寄存器与
IRTXPOL 和IRDATA位一起进行采样，因此，从一个时间
间隔到下一间隔，可以改变占空比和频率，如图1所示。
IR 发送
在IR 发送 (IRMODE=1) 期间，载波调制器进行调制时，载
波发生器产生合适的载波波形。载波调制可以作为载波周期
或者IRCLK 周期的函数来实现，具体取决于IRCFME 位的
设置。当IRCFME=0 时，IRV由载频时钟同步进行递减计
数，以载波周期为函数进行调制。当IRCFME=1时，IRV
由IRCLK 同步进行递减计数，按照IRCLK分辨率进行载波
调制。
IRCA
IRCA = 0202h
IRCA = 0002h
IRMT
IRMT = 3
IRMT = 5
IRCA, IRMT, IRDATA SAMPLED AT END OF IRV
DOWN-COUNT INTERVAL
3
2
1
0
5
4
3
2
1
0
CARRIER OUTPUT
(IRV)
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
图1.IR 发送频偏示例(IRCFME=0)
______________________________________________________________________________________ 15
MAXQ613
图 2 所示为载波发生器基本电路以及到IRTX 输出端的通路。
IR 发送极性位(IRTXPOL)定义了IR 定时器使能后IRTX引脚
的起始 / 空闲状态和载波极性。
载波发生模块
MAXQ613
具有红外模块的16位微控制器
IRTXPOL位定义了IRTX引脚的起始 / 空闲状态以及载波极
性。如果IRTXPOL=1，IR 定时器模块使能后，IRTX 引
脚置为逻辑高电平。如果IRTXPOL=0，IR 定时器使能后，
IRTX引脚置为逻辑低电平。
单独的寄存器位IR 数据 (IRDATA)用于确定载波发生器输出
是否在下一IRMT 载波周期输出至IRTX 引脚。当IRDATA=
1时，在下一IRMT周期，载波波形 (或者如果IRTXPOL=
1则为波形的反相) 是IRTX引脚的输出。当IRDATA=0 时，
在下一IRMT周期，由IRTXPOL 定义的空闲状态是IRTX 引
脚的输出。
发送模式下，IR 定时器用作递减计数器。在以下条件下开启
IR 发送：当IRMODE=1时，IREN 位置1 ；当IREN=1时，
IRMODE位置1；或在同一指令下，IREN 和IRMODE同时置1。
在发送过程开始时以及每次重新装载IR 定时器值时，采样
IRTXPOL
0
CARRIER GENERATION
IRTX PIN
IRCLK
1
CARRIER
IRCAH + 1
IRCAL + 1
IRCFME
0
1
IRDATA
IRMT
SAMPLE
IRDATA ON
IRV = 0000h
IR INTERRUPT
CARRIER MODULATION
图2.IR 发送载波发生器和载波调制器控制
IRMT = 3
CARRIER OUTPUT
(IRV)
3
2
1
0
3
2
1
0
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
图3.IR 发送波形 (IRCFME=0)
16 ��
具有红外模块的16位微控制器
IR 发送—独立的外部载波和调制器输出
标准发送模式根据IRDATA位调制载波。然而，如果需
要，用户可以选择在外部引脚输入调制信号 (包络)。如果
IRENV[1:0] 位配置为 01b 或10b，调制信号/包络输出到
IRTXM 引脚。在每一IRV 递减计数间隔边界处，IRDATA位
直接输出至IRTXM 引脚 ( 如果IRTXPOL=0)，如同内部调
制载波频率。如果IRTXPOL=1，在IRV间隔递减计数边
界处，IRDATA位取反并输出到IRTXM 引脚，如图 4 所示。
使能包络模式时，可以向IRTX引脚输出调制后的 (IRENV[1:0]
=01b)或者未经调制的 (IRENV[1:0]=10b) 载波。
IR 接收
配置在接收模式 (IRMODE=0) 时，IR 硬件支持IRRX 采集
功能。IRRXSEL[1:0] 位定义了IRRX 引脚的哪个边沿触发IR
定时器采集功能。
当IRMODE=0 和IREN=1时，IR 模块开始在接收模式下
工作。开启后，出现了符合IRRXSEL 定义的采集事件后，IR
定时器 (IRV)从0000h 开始向上计数。默认情况下，IRV 寄
存器对IRCA寄存器定义的载波周期进行计数。然而，IR 载
波频率检测位 (IRCFME)可以设置为1，使IRV 寄存器直接采
用IRCLK 时钟进行计数，进一步提高分辨率。当IRCFME=
0 时，IRCA 定义的载波由IRV 进行计数。当IRCFME=1时，
IRCLK为IRV 寄存器提供时钟。
对于下一个符合要求的事件，IR 模块进行以下操作：
1)采集IRRX引脚状态，将数值传送给IRDATA。如果是下
降沿，IRDATA=0。如果是上升沿，IRDATA=1。
2)将当前IRV值传送给IRMT。
3)将IRV内容复位至 0000h( 如果IRXRL=1)。
4)再次计数，直到出现下一个符合要求的事件。
如果在出现符合要求的事件之前，IR 定时器值从0FFFFh 翻
转到 0000h，IR 定时器溢出(IROV) 标志置1，如果中断使
IRTXM
IRTXPOL = 1
IRTXM
IRTXPOL = 0
IRDATA
1
0
1
0
1
0
1
0
IR INTERRUPT
IRV INTERVAL
IRMT
IRMT
IRMT
IRMT
图4. 外部IRTXM(调制器) 输出
______________________________________________________________________________________ 17
MAXQ613
IRMT 和IRCA寄存器以及IRDATA 和IRTXPOL位。当IRV
达到 0000h 时，下一载波时钟进行以下操作：
1) 以IRMT重新装载IRV。
2) 采样IRCA、IRDATA 和IRTXPOL。
3) 产生相应的IRTX。
4)IRIF置1。
5) 如果中断使能(IRIE=1)，向CPU 发出一次中断。
为了终止当前的发送，用户可以转换到接收模式 (IRMODE
=0)或把IREN 清零。
载波调制时间=IRMT+1个载波周期
MAXQ613
具有红外模块的16位微控制器
CARRIER GENERATION
CARRIER MODULATION
IRCLK
IRCAH + 1
IRCAL + 1
0
IR TIMER OVERFLOW
1
INTERRUPT TO CPU
0000h
IRCFME
IRV
IR INTERRUPT
COPY IRV TO IRMT
ON EDGE DETECT
IRXRL
IRRX PIN
RESET IRV TO 0000h
EDGE DETECT
IRDATA
图5.IR 采集
能，则产生一次中断。IR 模块继续工作在接收模式，直到切
换至发送模式 (IRMODE=1) 或清除IREN=0后停止接收。
载波突发计数模式
当执行IR 学习功能时，一种特殊模式可以减轻 CPU 处理负
荷。一般情况下，工作在IR 学习功能时，检查一定数量的载
波周期，以确定频率。一旦确定了频率，可以简化IR 接收
功能，对突发载波脉冲数进行计数，以及对突发中的组合
符号间隔持续时间进行计数。为简化这一过程，可以使用接
收突发计数模式 (由 RXBCNT位使能)。当 RXBCNT=0 时，
采用标准IR 接收采集功能。当 RXBCNT=1 时，禁止IRV
采集功能，与采集相关的中断标志不再表示采集。在载波
突发计数模式中，IRMT 寄存器只用于对符合要求的边沿进
行计数。如果经过两个连续IRCA 周期后没有得到符合要求
的边沿，那么IRIF中断标志(当 RXBCNT=0 时，通常用于
发出采集信号) 被置位。IRIF中断标志由此指示没有出现载
波，接收信号的起始数据为空。当 RXBCNT位由 0 变为1时，
IRMT 寄存器置为 0001h。IRCFME 位仍被用于定义IRV 寄
存器对系统IRCLK 时钟进行计数，还是对IRCA 定义的载波
周期进行计数。IRXRL位定义IRV 寄存器是否在检测到符合
要求的边沿时重新装载 0000h(每个IRXSEL[1:0] 位 )。图 6
以及图中嵌入的时序说明解释了接收突发计数模式的使用。
16 位定时器/ 计数器
该款微控制器提供支持以下功能的两类定时器 /计数器：
•16 位定时器 /计数器
•16 位上 / 下自动重载
•外部脉冲计数器功能
•支持采集功能的16 位定时器
•支持比较功能的16 位定时器
•增强了输入 / 输出功能的脉冲宽度调制
•比较器匹配的设置 / 复位 / 触发输出状态
•支持 2n 分频的预分频器 (n=0、2、4、6、8、10)
器件的一个 USART外设支持以下功能：
•2 线接口
•异步数据传输，全双工工作
•同步数据传输，半双工工作
•发送或接收数据完成时的可编程中断
•独立的可编程波特率发生器
•可选择第 9 位奇偶校验
• 支持开始 /停止位
18 ��
USART
具有红外模块的16位微控制器
IRMT = PULSE COUNTING
IRMT = PULSE COUNTING
IRV = CARRIER CYCLE COUNTING
IRRX
IRV
IRMT
1
2
3
4
6
7
8
5
1 TO 4
9
CAPTURE INTERRUPT (IRIF = 1).
IRV ≥ IRMT.
IRV = 0 (IF IRXRL = 1).
5
SOFTWARE SETS IRCA = CARRIER FREQUENCY.
SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE).
SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1.
SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT.
IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS).
6
QUALIFIED EDGE DETECTED: IRMT++
IRV RESET TO 0 IF IRXRL = 1.
7
IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE.
BURST MARK = IRMT PULSES.
SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE.
8
9
QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE).
SOFTWARE SET RXBCNT = 1 AS IN (5).
CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED.
图 6. 接收突发计数示例
表3. USART模式列表
MODE
TYPE
START BITS
DATA BITS
STOP BITS
Mode 0
Synchronous
N/A
8
N/A
Mode 1
Asynchronous
1
8
1
Mode 2
Asynchronous
1
8+1
1
Mode 3
Asynchronous
1
8+1
1
串行外设接口(SPI)
集成 SPI提供独立的串行通信通道，在多主机或多从机系统
中，与外设器件进行同步通信。接口支持 4 线全双工串行总
线的读写操作，可以工作在主机或从机模式。当两个或两个
以上主机同时发送数据时，提供冲突检测功能。
SPI主机最高数据传输速率是Sysclk/2。作为SPI从机工作时，
该器件能够支持 Sysclk/4 的 SPI传输速率。数据以8 位或16
位、MSB 在前的方式进行传输。此外，通过从机有效工作的
选择，SPI模块支持有效的 SSEL 状态 (低电平有效或高电平
有效 ) 配置。
______________________________________________________________________________________ 19
MAXQ613
CARRIER FREQUENCY
CALCULATION
MAXQ613
具有红外模块的16位微控制器
SHIFT
SAMPLE
SHIFT
SAMPLE
SSEL
tMCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tMCH
tMCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV
MSB
MOSI
tRF
LSB
MSB-1
tMIS
tMIH
MSB
MISO
tMLH
MSB-1
LSB
图7.SPI主机通信时序
SHIFT
SSEL
SAMPLE
SHIFT
SAMPLE
tSSH
tSSE
tSD
tSCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tSCH
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tSCL
tSIS
MOSI
tSIH
MSB
MSB-1
tSOV
MISO
MSB
LSB
tRF
MSB-1
tSLH
LSB
图 8.SPI从机通信时序
20 ��
具有红外模块的16位微控制器
该款微控制器提供用作通用I/O 的端口引脚，支持以下功能：
•CMOS 输出驱动电路
•施密特触发器输入
ROM加载器
ROM 加载器可以用于禁止对系统、用户加载程序和用户应
用程序存储器的访问，除非提供专区密码。ROM 版的该器
件不具备 ROM 加载器。
•工作在输入模式时，可选择弱上拉至 VDD
当微控制器处于复位状态时，所有端口引脚变为高阻态，除
非另有声明，否则禁止弱上拉和内部缓冲器。
内部引导加载程序允许通过简单的 JTAG 接口对器件重新装
载。因此，需要升级时可以在系统升级软件，而不必进行昂
贵的硬件改进。可以进行远程软件更新，从而允许对实际应
用中难以接近的设备进行频繁的更新。接口硬件可以与另一
个微控制器的 JTAG 连接，或者使用串口至 JTAG 转换器 (例
如 Maxim 提供的 MAXQJTAG-001) 与 PC串口连接。如果不
需要在系统编程功能，可以使用商用编程器进行大批量编
程。使用系统编程指令激活JTAG 接口并装载到测试访问端
口(TAP) 时，会调用引导加载程序。复位期间，通过JTAG
接口将 SPE 位置1将执行驻留在固定用途 ROM 中的引导加载
程序。编程结束时，引导加载程序将 SPE 位清零并复位器件，
从而允许器件跳过固定用途 ROM 并开始执行应用程序。
从软件的角度，可以把每个端口看作具有特定地址的一组外
设寄存器。特殊功能引脚的特殊功能被禁用后，这些引脚也
可以用作通用I/O 引脚。关于每个引脚特殊功能的详细说明，
请参考MAXQ610用户指南 (Englishonly)。
片内振荡器
如图 9 所示，HFXIN 和 HFXOUT之间连接外部石英晶体或
陶瓷谐振器。
HFXIN 和 HFXOUT上的噪声会影响片内时钟时序。将晶体
和电容靠近振荡器电路放置，通过短线直接连接 HFXIN 和
HFXOUT 至地，这些都是较好的设计方法。外部电容的典
型值随所采用的晶体类型而变化，应按照厂商建议的负载
电容选择最初的电容值。
此外，ROM 加载程序还提供存储器保护功能，访问 ROM 加
载程序接口时需要16 字长密码。
ROM 版的该器件不支持存储器装载功能。
VDD
HFXIN
CLOCK CIRCUIT
STOP
RF
C2
在应用闪存编程
从用户应用程序代码中，可以使用 C 或者汇编语言 ROM 函
数对闪存进行编程。下面的函数声明是为在应用闪存编程提
供的某些 ROM 函数的例子：
/* Write one 16-bit word to code address ‘dest’.
* Dest must be aligned to 16 bits.
* Returns 0 = failure, 1 = OK.
HFXOUT
C1
装入闪存
RF = 1MI Q50%
C1 = C2 = 12pF
*/
int flash_write (uint16_t dest, uint16_t
data);
图9. 片内振荡器
______________________________________________________________________________________ 21
MAXQ613
通用I/O
具有红外模块的16位微控制器
MAXQ613
•背景模式：
CPU 执行常规用户程序
支持主机配置并建立在电路调试器
MAXQ613
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
•调试模式：
调试器接管 CPU 控制权
内部寄存器和存储器的读 / 写操作
CPU 单步执行，进行跟踪操作
CPU
DEBUG
ENGINE
TMS
TCK
TDI
TDO
TAP
CONTROLLER
CONTROL
BREAKPOINT
ADDRESS
DATA
图10. 在电路调试器
进行擦除时，需要使用以下函数：
/* Erase the given Flash page
* addr: Flash offset (anywhere within page)
*/
int flash_erasepage(uint16_t addr);
在应用闪存编程必须调用 ROM 函数来擦除闪存和对闪存进
行编程。ROM 函数具有存储器保护功能。ROM 版的该器件
不支持在应用编程。
在电路调试和 JTAG 接口
器件具有嵌入式调试硬件和软件，能够在用户应用环境中提
供全面的在电路调试功能。这些硬件和软件功能包括：
•调试引擎
•寄存器组能够使用 ROM中存储的调试服务子程序，在寄存器、
代码或数据中设置断点。
总体上，这些硬件和软件特性支持两种模式的在电路调试
功能：
调试引擎接口是TAP 控制器。接口支持与总线主机的通信，
总线主机可以是自动测试设备或与上层系统中测试总线连
接的元件。符合JTAGIEEE1149 标准的专用 TAP 通过4 线
串行接口进行通信。TAP 提供独立串行通道，与主机系统
同步通信。
为防止在未经授权条件下通过 JTAG 接口访问受保护的存储
区，除非禁用存储器保护功能，否则调试引擎不允许对优先
级寄存器进行修改，禁止对系统存储器的所有访问。此外，
在系统区内部执行代码时，禁止所有服务 (例如，寄存器显
示或修改 )。ROM 版的该器件不具备调试器功能。
工作模式
最低功耗模式是停止模式。该模式下，将维持 CPU 状态和
存储器内容，但 CPU 并没有进入有效工作状态。唤醒源包括：
外部I/O 中断、电源失效报警中断、唤醒定时器以及电源失
效复位。任何时候，只要微控制器不需要执行代码，用户程
序即可控制该器件进入停止模式。超低功耗环行振荡器指的
是内部超低功耗 (400nA)、8kHz 环行振荡器，可用于驱动
唤醒定时器，使器件退出停止模式。软件可以对唤醒定时器
进行编程，步长125 μs，最大值约为 8s。
正常工作模式下，电源失效监测器始终保持工作。而停止模
式下，可以选择禁用该功能，以降低功耗。使用 PWCN 寄
存器中的电源失效监测禁用 (PFD) 位可以使能该功能。PFD
位的复位默认状态为1，禁止停止模式下的电源失效监测功
能。停止模式下，如果电源失效监测功能被禁止(PFD=1)，
将关断电源失效报警或复位电路，此时无法检测两种条件。
由此，VDD<VRST 不会触发复位状态。
22 ��
具有红外模块的16位微控制器
图11、图12 和图13 所示为标准工作模式和停止模式下的电
源失效检测和响应。如果由电源失效引起复位，电源失效监
测器的检测间隔可以设置为以下数值之一：
•始终有效—连续监测
VDD>VRST，则对 VDD 额外监测一个超低功耗环行振荡器
周期。如果VDD 在第三个超低功耗环形振荡器周期内仍然高
于VRST，经过晶振预热周期后，CPU 将退出复位状态，从
固定用途 ROM 的 8000h 恢复工作。
如果复位由其它事件引起，例如：RESET 引脚由外部拉至低
电平或者是看门狗定时器将其驱动为低电平，则电源失效
监测器、内部稳压器和晶体在 CPU 复位期间保持有效状态。
这些情况下，解除复位条件后，CPU 在不到 20 个晶体周期
内退出复位状态。
•211超低功耗环行振荡器时钟(约为256ms)
•212 超低功耗环行振荡器时钟(约为512ms)
•213 超低功耗环行振荡器时钟(约为1.024s)
对于周期性开启的电源失效检测，电源失效检测器在超低
功耗环行振荡器的两个周期内进行检测。检测期间，如果
VDD
t < tPFW
t ≥ tPFW
t ≥ tPFW
t ≥ tPFW
C
VPFW
G
VRST
E
F
B
VPOR
H
D
I
A
INTERNAL RESET
(ACTIVE HIGH)
图11. 标准工作模式下的电源失效检测
______________________________________________________________________________________ 23
MAXQ613
电源失效检测
MAXQ613
具有红外模块的16位微控制器
表4. 标准工作模式下的电源失效检测状态
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
On
Off
Off
—
VDD < VPOR.
B
On
On
On
—
VPOR < VDD < VRST.
Crystal warmup time, tXTAL_RDY.
CPU held in reset.
C
On
On
On
—
VDD > VRST.
CPU normal operation.
D
On
On
On
—
Power drop too short.
Power-fail not detected.
—
VRST < VDD < VPFW.
PFI is set when VRST < VDD < VPFW and
maintains this state for at least tPFW, at
which time a power-fail interrupt is generated (if enabled).
CPU continues normal operation.
E
On
On
On
F
On
(Periodically)
Off
Off
Yes
G
On
On
On
—
H
On
(Periodically)
Off
Off
Yes
I
Off
Off
Off
—
COMMENTS
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
VDD > VRST.
Crystal warmup time, tXTAL_RDY.
CPU resumes normal operation from 8000h.
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
VDD < VPOR.
Device held in reset. No operation allowed.
24 ��
具有红外模块的16位微控制器
t < tPFW
A
t ≥ tPFW
MAXQ613
VDD
t ≥ tPFW
VPFW
D
VRST
B
C
E
VPOR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
图12. 停止模式下电源失效检测状态，使能电源失效监测器
表5. 停止模式下电源失效检测状态，使能电源失效监测器
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
On
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
B
On
Off
Off
Yes
Power drop too short.
Power-fail not detected.
COMMENTS
C
On
On
On
Yes
VRST < VDD < VPFW.
Power-fail warning detected.
Turn on regulator and crystal.
Crystal warmup time, tXTAL_RDY.
Exit stop mode.
D
On
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
E
On
(Periodically)
Off
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
F
Off
Off
Off
—
VDD < VPOR.
Device held in reset. No operation allowed.
______________________________________________________________________________________ 25
MAXQ613
具有红外模块的16位微控制器
VDD
A
D
VPFW
B
VRST
C
E
VPOR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
INTERRUPT
图13. 停止模式下电源失效检测状态，禁用电源失效监测器
表6. 停止模式下电源失效检测状态，禁用电源失效监测器
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
Off
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
B
Off
Off
Off
Yes
VDD < VPFW.
Power-fail not detected because power-fail
monitor is disabled.
Yes
VRST < VDD < VPFW.
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail warning, and sets the power-fail
interrupt flag.
Turn on regulator and crystal.
Crystal warmup time, tXTAL_RDY.
On stop mode exit, CPU vectors to the
higher priority of power-fail and the interrupt that causes stop mode exit.
C
On
On
On
COMMENTS
26 ��
具有红外模块的16位微控制器
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
D
Off
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
MAXQ613
表6. 停止模式下电源失效检测状态，禁用电源失效监测器(续)
COMMENTS
E
On
(Periodically)
Off
Off
Yes
VPOR < VDD < VRST.
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail, and puts CPU in reset.
Power-fail monitor is turned on periodically.
F
Off
Off
Off
—
VDD < VPOR.
Device held in reset. No operation allowed.
应用信息
该器件的低功耗、高性能 RISC体系结构使其非常适合很多
便携式或电池供电产品。它是通用远端控制等需要高性价比
集成IR 发送 / 接收功能应用的理想选择。
接地和旁路
因为它们会直接耦合进入内部电源总线。键盘这类设备会产
生静电放电，直接进入微控制器，从而损坏器件。系统设计
人员必须保护元件不受这些会导致损坏系统存储器的瞬态
干扰的影响。
其它文档
仔细的 PCB 布板能够显著降低微控制器或者外设带来的系
统级数字噪声。需要采用多层电路板，以提供专用的电源层。
尽可能使数字元件下面的区域为连续地平面。保证旁路电容
走线尽量短，最大限度地抑制噪声，并且将电容尽可能靠近
器件放置。
为了充分发挥本器件的功能，设计人员应具备以下资料。本
数据资料包括引脚说明、特性简介和电气规范。勘误表列
出了与已公布规范的差别之处。用户指南提供了器件特性
和工作的详细信息。以下文档可以从china.maxim-ic.com/
microcontrollers下载。
所有半导体的 CMOS设计指南要求引脚上的电压不超过 VDD
或者低于 GND。违反这些指南将导致硬件失效 ( 损害器件内
部的硅片) 或者软故障 (错误地修改存储器内容)。电压尖峰
脉冲超出或低于器件的绝对最大范围时可能会导致破坏性的
IC 闭锁。
•MAXQ613 数据资料，包括电气 / 时序规范、引脚说明以及
封装信息。
•MAXQ613 相关版本的勘误表(china.maxim-ic.com/errata)。
•MAXQ610用户指南 (English only)，其中包含特性和工作的
详细信息，包括编程功能等。
微控制器通常会在其电源引脚或者通用I/O 引脚上出现负压
尖峰脉冲。电源引脚上的负压尖峰脉冲是非常严重的问题，
______________________________________________________________________________________ 27
MAXQ613
具有红外模块的16位微控制器
MAXQ613 与MAXQ610用户指南的不同之处
MAXQ610 用户指南 (Englishonly) 包含 MAXQ613 微控
制器应用程序开发所需的全部信息。虽然 MAXQ610 和
MAXQ613 的大部分代码是兼容的，但是两个器件之间仍有
一定的差异，在参考MAXQ610 用户指南 (Englishonly) 时
必须加以注意。
MAXQ613 不具备 MAXQ610 中的以下寄存器 (参见
MAXQ610 用户指南 (Englishonly))，所有与其相关的内容
应当忽略：
•端口3 输出寄存器 (PO3)
•端口3 方向寄存器 (PD3)
•端口3 输入寄存器 (PI3)
•端口4 输出寄存器 (PO4)
开发和技术支持
Maxim 以及第三方供应商为该微控制器提供了多种功能丰
富、价格适中的开发工具，主要包括：
•编译器
•在电路仿真器
•集成开发环境 (IDE)
•用于编程和调试的串口至JTAG 和 USB至JTAG 接口板( 适用
于带有可写存储器的微控制器)
部分开发工具供应商的列表可从china.maxim-ic.com/
MAXQ_tools查找。
如需技术支持，请访问https://support.maxim-ic.com/cn/
micro。
封装信息
•端口4方向寄存器 (PD4)
•端口4 输入寄存器 (PI4)
如需最近的封装外形信息和焊盘布局，请查询china.maxim-ic.com/
packages。请注意，封装编码中的“+”、
“#”或“-”仅表示 RoHS
状态。封装图中可能包含不同的尾缀字符，但封装图只与封装有关，
与 RoHS 状态无关。
封装类型
封装编码
外形编号
焊盘布局编号
32 TQFN-EP
T3255+3
21-0140
90-0001
32 LQFP
C32+2
21-0054
90-0111
44 TQFN-EP
T4477+2
21-0144
90-0127
44 TQFP
C44+2
21-0293
90-0316
28 ��
具有红外模块的16位微控制器
修订号
修订日期
0
7/10
最初版本。
说明
修改页
1
7/10
修正了引脚说明表中VDD、GND、RESET、IRTX、IRRX、P2.5/TDI、P2.6/TMS 和 P2.7/TDO 的
裸片号。
2
8/10
在特性部分中，将工作模式下的电流典型值由2.0mA修改为3.25mA。
—
9, 10, 11
1
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Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2010MaximIntegratedProducts
29
Maxim 是 MaximIntegratedProducts,Inc.的注册商标。
MAXQ613
修订历史
MAXQ613 具有红外模块的16位微控制器 - 概述
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MAXQ613
具有红外模块的16位微控制器
以更低功耗(200nA待机、12MHz下3.75mA)和更宽的工作电压范围(1.7V至3.6V)有效延长电池寿命
概述技术文档定购信息相关产品用户说明 (0) 所有内容状况
状况：生产中。
概述
数据资料
MAXQ613是一款低功耗、16位MAXQ®微控制器，设计用于通用遥控器、消费类电子和白色家电等低功耗产品。器件结合了强大的16位RISC微控制器和集成外设，包括一个通用同步/异步收发器(USART)和一个SPI™主/从通信接口，以及能够产生
载波频率的IR模块和灵活的复用键盘控制I/O。
器件包含48KB闪存和1.5KB数据SRAM。通过安全MMU提供知识产权(IP)保护，该安全MMU可支持多种授权等级配置，保护
代码不被复制和进行逆向工程。授权等级使厂商可以提供器件运行的库文件和应用程序，并通过授权限制对数据和代码的访
问。
完整的数据资料
英文
下载 Rev. 2 (PDF, 1.1MB)
中文
下载 Rev. 2 (PDF, 1.7MB)
勘误表
为实现低功耗电池供电设计，器件包括一个超低功耗停止模式(0.2µA，典型值)。该模式下，只有少数电路保持供电。唤醒源
包括外部中断、电源失效中断以及定时器中断。微控制器工作在1.70V至3.6V宽工作电压范围内。
设计人员需参考以下文档，以充分使用该器件的全部功能。数据资料包含引脚说明、特性概述和电气规格。勘误表包含了与
已发布版本的电气规格差异。用户指南提供器件特性和工作相关的详细信息。
MAXQ613 IC数据资料
MAXQ613不同版本的勘误表(点击此处获取)
MAXQ610用户指南 (English only)
关键特性
高性能、低功耗，16位RISC内核
在整个工作电压范围内具有直流至12MHz工作频率
1.70V至3.6V工作电压
总共33条指令简化了编程
3个独立的数据指针具有自动递增/递减特性，加速数据转移
专用指针用于直接读取程序空间
16位指令字，16位数据总线
16 x 16位通用工作寄存器
安全MMU用于分区和IP保护
存储器特性
48KB程序闪存
512字节扇区
每个扇区所允许的擦除/写次数为20,000次
可屏蔽ROM
1.5KB数据SRAM
http://china.maxim-ic.com/datasheet/index.mvp/id/6786[2010-12-18 9:09:39]
应用/使用
电池供电产品
消费类电子
家用产品
便携式设备
远端控制
白色家电
MAXQ613 具有红外模块的16位微控制器 - 概述
其它外设
电源失效报警
上电复位(POR)/掉电复位
自动IR载波频率发生器和调制器
2个16位、可编程定时器/计数器，带预调节和捕获/比较功能
一个SPI和一个USART端口
可编程看门狗定时器
8kHz超微功耗环型振荡器唤醒定时器
多达24个通用I/O
低功耗
停止模式下，TA = +25°C、电源失效监测器禁止时，电流仅为0.2µA (典型值)、2.0µA (最大值)
工作模式下，12MHz时电流为3.25mA (典型值)
Key Specifications: Microcontrollers
Part Number
MAXQ613 NEW!
Microcontroller
Type
Low Power
MCU
Core
MAXQ20S
Core
Clock
GPIO
Timers
Stop Price
Active
Internal Internal
Internal
Speed
16-bit
Mode
Data
SPI Pins
Timer VSUPPLY
Power
SRAM USARTs
Ring Features
PWM
(MHz) Processing Flash
Current
Bus
Features
(V)
(mA)
(KBytes) (KBytes)
Osc.
(nA)
See
max
max
max
Notes
12
16-bit
48
1.5
1
1
24
No
Internal
Voltage
Regulator
Multiple
External
Interrupts
2
查看所有Microcontrollers (33)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may
differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized
distributor.
图表
http://china.maxim-ic.com/datasheet/index.mvp/id/6786[2010-12-18 9:09:39]
2
Wake Up
Timer
Watchdog
1.7 to
3.6
3.25
(12MHz)
200
$1.32
@1k
MAXQ613 具有红外模块的16位微控制器 - 概述
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概述
关键特性
应用/ 使用
关键指标
图表
注释、注解
数据资料
勘误表
应用笔记
评估板
设计指南
可靠性报告
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参考文献： 19- 5320 Rev. 2; 2010- 09- 01
本页最后一次更新: 2010- 09- 01
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© 2010 Maxim Integrated Products版权所有
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19-5320; Rev 2; 8/10
16-Bit Microcontroller with Infrared Module
Features
S High-Performance, Low-Power, 16-Bit RISC Core
The MAXQ613 is a low-power, 16-bit MAXQ® microcon-
S DC to 12MHz Operation Across Entire Operating Range
troller designed for low-power applications including universal remote controls, consumer electronics, and white
goods. The device combines a powerful 16-bit RISC
microcontroller and integrated peripherals including a
universal synchronous/asynchronous receiver-transmitter (USART) and an SPI™ master/slave communications
port, along with an IR module with carrier frequency
generation and flexible port I/O capable of multiplexed
keypad control.
S 1.70V to 3.6V Operating Voltage
S 33 Total Instructions for Simplified Programming
S Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
S Dedicated Pointer for Direct Read from Code Space
S 16-Bit Instruction Word, 16-Bit Data Bus
S 16 x 16-Bit General-Purpose Working Registers
S Secure MMU for Application Partitioning and IP
The device includes 48KB of flash program memory and
1.5KB of data SRAM. Intellectual property (IP) protection is provided by a secure MMU that supports multiple
application privilege levels and protects code against
copying and reverse engineering. Privilege levels enable
vendors to provide libraries and applications to execute
on the device, while limiting access to only data and
code allowed by their privilege level.
Protection
S Memory Features
48KB Program Flash Memory
512-Byte Sectors
20,000 Erase/Write Cycles per Sector
Masked ROM Available
1.5KB Data SRAM
S Additional Peripherals
Power-Fail Warning
Power-On Reset (POR)/Brownout Reset
Automatic IR Carrier Frequency Generation and
For the ultimate in low-power battery-operated performance, the device includes an ultra-low-power stop
mode (0.2µA typ). In this mode, the minimum amount of
circuitry is powered. Wake-up sources include external
interrupts, the power-fail interrupt, and a timer interrupt.
The microcontroller runs from a wide 1.70V to 3.6V operating voltage.
Modulation
Prescaler and Capture/Compare
Two 16-Bit Programmable Timers/Counters with
One SPI and One USART Port
Programmable Watchdog Timer
8kHz Nanopower Ring Oscillator Wake-Up Timer
Up to 24 General-Purpose I/Os
Applications
Remote Controls
Battery-Powered
Portable Equipment
Consumer Electronics
Home Appliances
White Goods
S Low Power Consumption
0.2µA (typ), 2.0µA (max) in Stop Mode,
TA = +25NC, Power-Fail Monitor Disabled
3.25mA (typ) at 12MHz in Active Mode
Ordering Information/Selector Guide
PART
TEMP RANGE
OPERATING
VOLTAGE (V)
PROGRAM
MEMORY (KB)
DATA
MEMORY (KB)
GPIO
PIN-PACKAGE
MAXQ613A-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
20
32 TQFN-EP*
MAXQ613E-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
20
32 LQFP
MAXQ613J-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
24
44 TQFN-EP*
MAXQ613K-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
24
44 TQFP
MAXQ613X-0000+
0NC to +70NC
1.7 to 3.6
48 Flash
1.5
24
Bare die
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAXQ613
General Description
MAXQ613
16-Bit Microcontroller with Infrared Module
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IR Transmit—Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IR Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Carrier Burst-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16-Bit Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Loading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
In-Circuit Debug and JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Deviations from the MAXQ610 User’s Guide for the MAXQ613 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 _______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. IR Transmission Waveform (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. External IRTXM (Modulator) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. IR Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Receive Burst-Count Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. SPI Master Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. SPI Slave Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LIST OF TABLES
Table 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . 26
_______________________________________________________________________________________ 3
MAXQ613
LIST OF FIGURES
MAXQ613
16-Bit Microcontroller with Infrared Module
ABSOLUTE MAXIMUM RATINGS
44-Pin TQFN (single-layer board)
(derate 27mW/NC above +70NC).............................2162.2mW
44-Pin TQFN (multilayer board)
(derate 37mW/NC above +70NC)................................2963mW
44-Pin TQFP (multilayer board)
(derate 19mW/NC above +70NC)................................1504mW
Operating Temperature Range.............................. 0NC to +70NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (excluding dice; soldering, 10s).......+300NC
Soldering Temperature (reflow).......................................+260NC
Voltage Range on VDD with Respect to GND......-0.3V to +3.6V
Voltage Range on Any Lead with
Respect to GND Except VDD................ -0.3V to (VDD + 0.5V)
Continuous Power Dissipation (TA = +70NC)
32-Pin TQFN (single-layer board)
(derate 21.3mW/NC above +70NC)..........................1702.1mW
32-Pin TQFN (multilayer board)
(derate 34.5mW/NC above +70NC)..........................2758.6mW
32-Pin LQFP (multilayer board)
(derate 20.7mW/NC above +70NC)..........................1652.9mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
1.8V Internal Regulator
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
VRST
3.6
V
VREG18
1.62
1.8
1.98
V
Power-Fail Warning Voltage for
Supply
VPFW
Monitors VDD (Note 2)
1.75
1.8
1.85
V
Power-Fail Reset Voltage
VRST
Monitors VDD (Note 3)
1.64
1.67
1.70
V
POR Voltage
VPOR
Monitors VDD
RAM Data-Retention Voltage
VDRV
(Note 4)
Active Current
IDD_1
Sysclk = 12MHz (Note 5)
IS1
Power-Fail Off
Stop-Mode Current
1
1.42
1.0
V
V
3.25
4
TA = +25NC
0.2
2.0
TA = 0°C to +70NC
TA = +25NC
0.2
8
22
29.5
TA = 0°C to +70NC
27.6
42
mA
FA
IS2
Power-Fail On
Current Consumption During
Power-Fail
IPFR
(Note 6)
[(3 x IS2) +
((PCI - 3) x (IS1 +
INANO))]/PCI
FA
Power Consumption During
POR
IPOR
(Note 7)
100
nA
Stop-Mode Resume Time
tON
375 + (8192 x
tHFXIN)
Fs
Power-Fail Monitor Startup
Time
tPFM_ON
(Note 4)
Power-Fail Warning Detection
Time
tPFW
(Note 8)
Input Low Voltage for IRTX,
IRRX, RESET, and All Port Pins
VIL
VGND
0.3 x VDD
V
Input High Voltage for IRTX,
IRRX, RESET, and All Port Pins
VIH
0.7 x VDD
VDD
V
150
10
Fs
Fs
4 _______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
PARAMETER
Input Hysteresis (Schmitt)
SYMBOL
VIHYS
CONDITIONS
MIN
TYP
MAX
300
VDD = 3.3V, TA = +25NC
UNITS
mV
Input Low Voltage for HFXIN
VIL_HFXIN
VGND
0.3 x VDD
V
Input High Voltage for HFXIN
VIH_HFXIN
0.7 x VDD
VDD
V
IRRX Input Filter Pulse-Width
Reject
tIRRX_R
50
ns
IRRX Input Filter Pulse-Width
Accept
tIRRX_A
Output Low Voltage for IRTX
VOL_IRTX
300
VDD = 3.6V, IOL = 25mA (Note 3)
VDD = 2.35V, IOL = 10mA (Note 3)
1.0
VDD = 1.85V, IOL = 4.5mA
1.0
0.4
0.5
VDD = 2.35V, IOL = 8mA (Note 3)
VDD = 1.85V, IOL = 4.5mA
0.4
0.5
0.4
0.5
VOL
Output High Voltage for IRTX
and All Port Pins
VOH
IOH = -2mA
Input/Output Pin Capacitance
for All Port Pins
CIO
(Note 4)
Input Pullup Resistor for
RESET, IRTX, IRRX, P0, P1, P2
IL
RPU
1.0
VDD = 3.6V, IOL = 11mA (Note 3)
Output Low Voltage for RESET
and All Port Pins (Note 9)
Input Leakage Current
ns
Internal pullup disabled
VDD - 0.5
-100
V
V
VDD
V
15
pF
+100
nA
VDD = 3.0V, VOL = 0.4V (Note 4)
16
28
39
VDD = 2.0V, VOL = 0.4V
17
30
41
kW
EXTERNAL CRYSTAL/RESONATOR
Crystal/Resonator
fHFXIN
Crystal/Resonator Period
tHFXIN
Crystal/Resonator Warmup
Time
Oscillator Feedback Resistor
tXTAL_RDY
ROSCF
1
From initial oscillation
(Note 4)
0.5
12
MHz
1/fHFXIN
ns
8192 x
tHFXIN
ms
1.0
1.5
MW
12
MHz
EXTERNAL CLOCK INPUT
External Clock Frequency
fXCLK
External Clock Period
tXCLK
External Clock Duty Cycle
DC
1/fXCLK
tXCLK_DUTY (Note 4)
System Clock Frequency
fCK
System Clock Period
tCK
45
ns
55
fHFXIN
HFXOUT = GND
%
MHz
fXCLK
1/fCK
ns
NANOPOWER RING
TA = +25NC
3.0
8.0
Nanopower Ring Frequency
fNANO
TA = +25NC, VDD = POR voltage
(Note 4)
1.7
2.4
Nanopower Ring Duty Cycle
tNANO
(Note 4)
40
Nanopower Ring Current
INANO
Typical at VDD = 1.64V,
TA = +25°C (Note 4)
40
20.0
kHz
60
%
400
nA
_______________________________________________________________________________________ 5
MAXQ613
RECOMMENDED OPERATING CONDITIONS (continued)
MAXQ613
16-Bit Microcontroller with Infrared Module
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
65,535/
fNANO
s
WAKE-UP TIMER
Wake-Up Timer Interval
tWAKEUP
1/fNANO
fFPSYSCLK
6
FLASH MEMORY
System Clock During Flash
Programming/Erase
Flash Erase Time
Flash Programming Time per
Word
MHz
tME
Mass erase
20
40
tERASE
Page erase
20
40
tPROG
(Note 10)
20
100
Write/Erase Cycles
Data Retention
TA = +25NC
ms
Fs
20,000
Cycles
100
Years
IR
Carrier Frequency
fIR
(Note 4)
fCK/2
Hz
MAX
UNITS
SPI ELECTRICAL CHARACTERISTICS
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 11)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
SPI Master Operating
Frequency
1/tMCK
fCK/2
MHz
SPI Slave Operating
Frequency
1/tSCK
fCK/4
MHz
SPI I/O Rise/Fall Time
tSPI_RF
23.6
ns
SCLK Output Pulse-Width
High/Low
CL = 15pF, pullup = 560W
8.3
tMCH, tMCL
tMCK/2 tSPI_RF
ns
MOSI Output Hold Time After
SCLK Sample Edge
tMOH
tMCK/2 tSPI_RF
ns
MOSI Output Valid to Sample
Edge
tMOV
tMCK/2 tSPI_RF
ns
MISO Input Valid to SCLK
Sample Edge Rise/Fall Setup
tMIS
25
ns
MISO Input to SCLK Sample
Edge Rise/Fall Hold
tMIH
0
ns
SCLK Inactive to MOSI
Inactive
tMLH
tMCK/2 tSPI_RF
ns
SCLK Input Pulse-Width High/
Low
tSCH, tSCL
tSCK/2
ns
SSEL Active to First Shift
Edge
tSSE
tSPI_RF
ns
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
tSIS
tSPI_RF
ns
6 _______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
(VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 11)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MOSI Input from SCLK
Sample Edge Transition Hold
tSIH
MISO Output Valid After SCLK
Shift Edge Transition
tSOV
SSEL Inactive
tSSH
tCK +
tSPI_RF
ns
SCLK Inactive to SSEL Rising
tSD
tSPI_RF
ns
MISO Output Disabled After
SSEL Edge Rise
tSLH
tSPI_RF
ns
2tSPI_RF
2tCK +
2tSPI_RF
ns
ns
Note 1: Specifications to 0NC are guaranteed by design and are not production tested. Typical = +25NC, VDD = +3.3V, unless
otherwise noted.
Note 2: VPFW can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V ±3%. The values
listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal.
Note 3: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals
is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is
achieved.
Note 4: Guaranteed by design and not production tested.
Note 5: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or VDD. Outputs do not source/
sink any current. The device is executing code from flash memory.
Note 6: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles.
Note 7: Current consumption during POR when powering up while VDD is less than the POR release voltage.
Note 8: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected; refer to the MAXQ610
User’s Guide for details.
Note 9: The maximum total current, IOH(MAX) and IOL(MAX), for all listed outputs combined should not exceed 32mA to satisfy the
maximum specified voltage drop. This does not include the IRTX output.
Note 10:Programming time does not include overhead associated with utility ROM interface.
Note 11:AC electrical specifications are guaranteed by design and are not production tested.
_______________________________________________________________________________________ 7
MAXQ613
SPI ELECTRICAL CHARACTERISTICS (continued)
P2.5/TDI 25
16
P1.4/INT4
P2.6/TMS 26
15
VDD
P2.7/TDO 27
14
REGOUT
13
GND
12
P1.3/INT3
11
P1.2/INT2
10
P1.1/INT1
9
P1.0/INT0
GND 30
IRTX 31
EP
+
P0.2/TX/INT10
P0.3/INT11
5
6
7
8
P0.7/TBB1/INT15
4
P0.6/TBB0/INT14
3
P0.4/INT12
2
P0.5/TBA0/TBA1/INT13
1
P0.1/RX/INT9
IRRX 32
P1.6/INT6
HFXOUT
HFXIN
P1.5/INT5
17
P2.5/TDI 25
16
P1.4/INT4
P2.6/TMS 26
15
VDD
P2.7/TDO 27
14
REGOUT
13
GND
VDD 29
12
P1.3/INT3
GND 30
11
P1.2/INT2
IRTX 31
10
P1.1/INT1
9
P1.0/INT0
RESET 28
MAXQ613
IRRX 32
+
TQFN
(5mm × 5mm)
1
2
3
4
5
6
7
8
P2.3/SSEL
P2.2/SCLK
N.C.
N.C.
P2.1/MISO
GND
P2.0/MOSI
P1.7/INT7
P1.6/INT6
HFXOUT
HFXIN
32
31
30
29
28
27
26
25
24
23
LQFP
(7mm × 7mm)
33
TOP VIEW
18
P0.7/TBB1/INT15
VDD 29
19
P0.6/TBB0/INT14
MAXQ613
20
P0.5/TBA0/TBA1/INT13
RESET 28
21
P0.4/INT12
17
P1.7/INT7
18
22
P0.3/INT11
P1.5/INT5
19
GND
HFXIN
20
23
P0.2/TX/INT10
HFXOUT
21
N.C.
P1.6/INT6
22
24
P0.1/RX/INT9
P1.7/INT7
23
P2.4/TCK
GND
24
TOP VIEW
P0.0/IRTXM/INT8
N.C.
TOP VIEW
P2.4/TCK
Pin Configurations
P0.0/IRTXM/INT8
P2.4/TCK
34
22
P1.5/INT5
P2.5/TDI
35
21
P1.4/INT4
N.C.
36
20
GND
N.C.
37
19
VDD
P2.6/TMS
38
18
REGOUT
P2.7/TDO
39
17
GND
RESET
40
16
N.C.
VDD
41
15
N.C.
GND
42
14
P1.3/INT3
IRTX
43
13
P1.2/INT2
IRRX
44
12
P1.1/INT1
MAXQ613
EP
5
6
7
8
9
10
11
P0.2/TX/INT10
P0.3/INT11
P0.4/INT12
P0.5/TBA0/TBA1/INT13
P0.6/TBB0/INT14
P0.7/TBB1/INT15
P1.0/INT0
3
P0.1/RX/INT9
4
2
N.C.
1
N.C.
+
P0.0/IRTXM/INT8
MAXQ613
16-Bit Microcontroller with Infrared Module
TQFN
(7mm × 7mm)
8 _______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
P2.3/SSEL
P2.2/SCLK
N.C.
N.C.
P2.1/MISO
GND
P2.0/MOSI
P1.7/INT7
P1.6/INT6
HFXOUT
HFXIN
TOP VIEW
33
32
31
30
29
28
27
26
25
24
23
P2.4/TCK 34
22
P1.5/INT5
P2.5/TDI 35
21
P1.4/INT4
N.C. 36
20
GND
N.C. 37
19
VDD
P2.6/TMS 38
18
REGOUT
17
GND
RESET 40
16
N.C.
MAXQ613
P2.7/TDO 39
VDD 41
15
N.C.
GND 42
14
P1.3/INT3
IRTX 43
13
P1.2/INT2
12
P1.1/INT1
1
2
3
4
5
6
7
8
9
10
11
N.C.
P0.1/RX/INT9
N.C.
P0.2/TX/INT10
P0.3/INT11
P0.4/INT12
P0.5/TBA0/TBA1/INT13
P0.6/TBB0/INT14
P0.7/TBB1/INT15
P1.0/INT0
+
P0.0/IRTXM/INT8
IRRX 44
TQFP
(10mm × 10mm)
NOTE: CONTACT FACTORY FOR BARE DIE PAD CONFIGURATION.
Pin Description
PIN
BARE DIE
32 TQFNEP/LQFP
44 TQFNEP/TQFP
NAME
FUNCTION
15, 36
15, 29
19, 41
VDD
Supply Voltage
13, 16, 25,
37
13, 22, 30
17, 20, 28,
42
GND
Ground. Connect directly to the ground plane.
POWER PINS
14
14
18
REGOUT
—
—
—
EP
1.8V Regulator Output. This pin must be connected to ground through
a 1.0FF (ESR: 2W–10W) external ceramic-chip capacitor. The capacitor
must be placed as close to this pin as possible. No devices other than
the capacitor should be connected to this pin.
Exposed Pad (TQFN Only). Connect EP directly to the ground plane.
_______________________________________________________________________________________ 9
MAXQ613
Pin Configurations (continued)
MAXQ613
16-Bit Microcontroller with Infrared Module
Pin Description (continued)
PIN
BARE DIE
32 TQFNEP/LQFP
44 TQFNEP/TQFP
NAME
FUNCTION
RESET
Digital, Active-Low, Reset Input/Output. The device remains in reset
as long as this pin is low and begins executing from the utility ROM at
address 8000h when this pin returns to a high state. The pin includes
pullup current source; if this pin is driven by an external device, it should
be driven by an open-drain source capable of sinking in excess of 4mA.
This pin can be left unconnected if there is no need to place the device in
a reset state using an external signal. This pin is driven low as an output
when an internal reset condition occurs.
RESET PIN
35
28
40
CLOCK PINS
20
18
23
HFXIN
21
19
24
HFXOUT
High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT for use as the high-frequency system
clock. Alternatively, HFXIN is the input for an external, high-frequency
clock source when HFXOUT is unconnected.
IR FUNCTION PINS
38
39
31
32
43
44
IRTX
IR Transmit Output. IR transmission pin capable of sinking 25mA. This
pin defaults to a high-impedance input with the weak pullup disabled
during all forms of reset. Software must configure this pin after release
from reset to remove the high-impedance input condition.
IRRX
IR Receive Input. This pin defaults to a high-impedance input with the
weak pullup disabled during all forms of reset. Software must configure
this pin after release from reset to remove the high-impedance input
condition.
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS
Port 0 General-Purpose, Digital I/O Pins. These port pins function as
general-purpose I/O pins with their input and output states controlled by
the PD0, PO0, and PI0 registers. All port pins default to high-impedance
mode after a reset. Software must configure these pins after release
from reset to remove the high-impedance condition. All alternate functions must be enabled from software before they can be used.
GPIO PORT PIN
SPECIAL FUNCTION
1
1
1
P0.0/IRTXM/
INT8
P0.0
IR Modulator Output/INT8
2
2
3
P0.1/RX/
INT9
P0.1
USART Receive/INT9
3
3
5
P0.2/TX/
INT10
P0.2
USART Transmit/INT10
4
4
6
P0.3/INT11
P0.3
INT11
5
5
7
P0.4/INT12
P0.4
INT12
6
6
8
P0.5/TBA0/
TBA1/INT13
P0.5
Type B Timer 0 Pin A or Type B
Timer 1 Pin A/INT13
10 ��
16-Bit Microcontroller with Infrared Module
PIN
NAME
FUNCTION
BARE DIE
32 TQFNEP/LQFP
44 TQFNEP/TQFP
7
7
9
P0.6/TBB0/
INT14
P0.6
Type B Timer 0 Pin B/INT14
8
8
10
P0.7/TBB1/
INT15
P0.7
Type B Timer 1 Pin B/INT15
Port 1 General-Purpose, Digital I/O Pins with Interrupt Capability. These
port pins function as general-purpose I/O pins with their input and output states controlled by the PD1, PO1, and PI1 registers. All port pins
default to high-impedance mode after a reset. Software must configure
these pins after release from reset to remove the high-impedance condition. All external interrupts must be enabled from software before they
can be used.
GPIO PORT PIN
EXTERNAL INTERRUPT
9
9
11
P1.0/INT0
P1.0
INT0
10
10
12
P1.1/INT1
P1.1
INT1
11
11
13
P1.2/INT2
P1.2
INT2
12
12
14
P1.3/INT3
P1.3
INT3
17
16
21
P1.4/INT4
P1.4
INT4
18
17
22
P1.5/INT5
P1.5
INT5
22
20
25
P1.6/INT6
P1.6
INT6
23
21
26
P1.7/INT7
P1.7
INT7
Port 2 General-Purpose, Digital I/O Pins. These port pins function as
general-purpose I/O pins with their input and output states controlled by
the PD2, PO2, and PI2 registers. All port pins default to high-impedance
mode after a reset. Software must configure these pins after release
from reset to remove the high-impedance condition. All special functions must be enabled from software before they can be used.
GPIO PORT PIN
SPECIAL FUNCTION
24
—
27
P2.0/MOSI
P2.0
SPI: Master Out-Slave In
26
—
29
P2.1/MISO
P2.1
SPI: Master In-Slave Out
28
—
32
P2.2/SCLK
P2.2
SPI: Slave Clock
30
—
33
P2.3/SSEL
P2.3
SPI: Active-Low Slave Select
31
24
34
P2.4/TCK
P2.4
JTAG: Test Clock
32
25
35
P2.5/TDI
P2.5
JTAG: Test Data In
33
26
38
P2.6/TMS
P2.6
JTAG: Test Mode Select
34
27
39
P2.7/TDO
P2.7
JTAG: Test Data Out
NO CONNECTION PINS
—
23
2, 4, 15, 16,
30, 31, 36,
37
N.C.
No Connection. Not internally connected.
______________________________________________________________________________________ 11
MAXQ613
Pin Description (continued)
MAXQ613
16-Bit Microcontroller with Infrared Module
Block Diagram
MAXQ613
REGULATOR
16-BIT MAXQ
RISC CPU
IR DRIVER
VOLTAGE
MONITOR
CLOCK
48KB FLASH
MEMORY
IR TIMER
GPIO
WATCHDOG
1.5KB
UTILITY ROM
SPI
2x
16-BIT TIMER
8kHz NANO
RING
5.5KB
DATA SRAM
USART
Detailed Description
The MAXQ613 provides integrated, low-cost solutions
that simplify the design of IR communications equipment
such as universal remote controls. Standard features
include the highly optimized, single-cycle, MAXQ, 16-bit
RISC core; 48KB of program flash memory; 1.5KB data
RAM; soft stack; 16 general-purpose registers; and
three data pointers. The MAXQ core has the industry’s
best MIPS/mA rating, allowing developers to achieve
the same performance as competing microcontrollers
at substantially lower clock rates. Lower active-mode
current combined with the even lower MAXQ613 stopmode current (0.2FA typ) results in increased battery life.
Application-specific peripherals include flexible timers
for generating IR carrier frequencies and modulation. A
high-current IR drive pin capable of sinking up to 25mA
current and output pins capable of sinking up to 5mA
are ideal for IR applications. It also includes generalpurpose I/O pins ideal for keypad matrix input, and a
power-fail-detection circuit to notify the application when
the supply voltage is nearing the microcontroller’s minimum operating voltage.
At the heart of the device is the MAXQ 16-bit, RISC core.
Operating from DC to 12MHz, almost all instructions execute in a single clock cycle (83.3ns at 12MHz), enabling
nearly 12MIPS true-code operation. When active device
operation is not required, an ultra-low-power stop mode
can be invoked from software, resulting in quiescent
current consumption of less than 0.2FA (typ) and 2.0FA
(max). The combination of high-performance instructions
and ultra-low stop-mode current increases battery life
over competing microcontrollers. An integrated POR circuit with brownout support resets the device to a known
condition following a power-up cycle or brownout condition. Additionally, a power-fail warning flag is set, and a
power-fail interrupt can be generated when the system
voltage falls below the power-fail warning voltage, VPFW.
The power-fail warning feature allows the application to
notify the user that the system supply is low and appropriate action should be taken.
Microprocessor
The device is based on Maxim’s low-power, 16-bit MAXQ
family of RISC cores. The core supports the Harvard
memory architecture with separate 16-bit program and
data address buses. A fixed 16-bit instruction word is
standard, but data can be arranged in 8 or 16 bits. The
MAXQ core in the device is implemented as a pipelined processor with performance approaching 1MIPS
per MHz. The 16-bit data path is implemented around
register modules, and each register module contributes
specific functions to the core. The accumulator module
consists of sixteen 16-bit registers and is tightly coupled
with the arithmetic logic unit (ALU). A configurable soft
stack supports program flow.
Execution of instructions is triggered by data transfer
between functional register modules or between a functional register module and memory. Because data movement involves only source and destination modules,
circuit switching activities are limited to active modules
only. For power-conscious applications, this approach
localizes power dissipation and minimizes switching
noise. The modular architecture also provides a maximum of flexibility and reusability that are important for a
microprocessor used in embedded applications.
The MAXQ instruction set is highly orthogonal. All arithmetical and logical operations can use any register
in conjunction with the accumulator. Data movement
is supported from any register to any other register.
Memory is accessed through specific data-pointer registers with autoincrement/decrement support.
12 ��
16-Bit Microcontroller with Infrared Module
The SP pointer indicates the current top of the stack,
which initializes by default to the top of the SRAM data
memory. As values are pushed onto the stack, the SP
pointer decrements, which means that the stack grows
downward towards the bottom (lowest address) of the
data memory. Popping values off the stack causes the
SP pointer value to increase. Refer to the MAXQ610
User’s Guide for more details.
The microcontroller incorporates several memory types:
• 48KB program flash memory
• 1.5KB SRAM data memory
• 5.5KB utility ROM
• Soft stack
Memory Protection
Utility ROM
The optional memory-protection feature separates code
memory into three areas: system, user loader, and user
application. Code in the system area can be kept confidential. Code in the user areas can be prevented from
reading and writing system code. The user loader can
also be protected from user application code.
The utility ROM is a 5.5KB block of internal ROM memory
located in program space beginning at address 8000h.
This ROM includes the following routines:
• In-system programming (bootstrap loader) using
JTAG interface
• In-circuit debugging routines using JTAG interface
Memory protection is implemented using privilege levels
for code. Each area has an associated privilege level.
RAM/ROM are assigned privilege levels as well. Refer to
the MAXQ610 User’s Guide for a more thorough explanation of the topic. See Table 1.
• P
roduction test routines (internal memory tests,
memory loader, etc.), which are used for internal
testing only, and are generally of no use to the endapplication developer
• U
ser-callable routines for in-application flash programming, buffer copying, and fast table lookup (more
information on these routines can be found in the
MAXQ610 User’s Guide)
Stack Memory
The device provides a soft stack that can be used to
store program return addresses (for subroutine calls
and interrupt handling) and other general-purpose data.
This soft stack is located in the 1.5KB SRAM data
memory, which means that the SRAM data memory must
be shared between the soft stack and general-purpose
application data storage. However, the location and
size of the soft stack is determined by the user, providing maximum flexibility when allocating resources for a
particular application. The stack is used automatically
by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An
application can also store and retrieve values explicitly
using the stack by means of the PUSH, POP, and POPI
instructions.
Following any reset, execution begins in the utility ROM
at address 8000h. At this point, unless loader mode or
test mode has been invoked (which requires special programming through the JTAG interface), the utility ROM in
the device always automatically jumps to location 0000h,
which is the beginning of user application code in program flash memory.
Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, in-application programming, or in-circuit debugging functions is
prohibited until a password has been supplied. Three
Table 1. Memory Areas and Associated Maximum Privilege Levels
AREA
PAGE ADDRESS
System
0 to ULDR-1
MAXIMUM PRIVILEGE LEVEL
High
User Loader
ULDR to UAPP-1
Medium
User Application
UAPP to top
Low
Utility ROM
N/A
High
Other (RAM)
N/A
Low
______________________________________________________________________________________ 13
MAXQ613
Memory
MAXQ613
16-Bit Microcontroller with Infrared Module
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WD[1:0]
WATCHDOG CLOCK
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (μs)
00
Sysclk/215
2.7ms
42.7
01
Sysclk/218
21.9ms
42.7
10
Sysclk/221
174.7ms
42.7
11
Sysclk/224
1.4s
42.7
different password locks are provided, each of which
can be used to protect a different area of memory (system memory, user loader, and user application). Each
password lock is controlled by a 16-word area of flash
memory; if the password is set to all FFFFh values or all
0000h values, the password is disabled. Otherwise, the
password is active and must be matched by the user of
the bootloader or debugger before access is granted to
the corresponding area of flash program memory. Refer
to the MAXQ610 User’s Guide for more details.
Watchdog Timer
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum
count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
215 to 224 system clock cycles. An interrupt is generated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the programmed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires. See Table 2.
IR Carrier Generation
and Modulation Timer
The dedicated IR timer/counter module simplifies lowspeed infrared (IR) communication. The IR timer implements two pins (IRTX and IRRX) for supporting IR
transmit and receive, respectively. The IRTX pin has no
corresponding port pin designation, so the standard
PD, PO, and PI port control status bits are not present.
However, the IRTX pin output can be manipulated high
or low using the PWCN.IRTXOUT and PWCN.IRTXOE
bits when the IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of a carrier generator and a
carrier modulator. The carrier generation module uses
the 16-bit IR carrier register (IRCA) to define the high
and low time of the carrier through the IR carrier high
byte (IRCAH) and IR carrier low byte (IRCAL). The carrier
modulator uses the IR data bit (IRDATA) and IR modulator time register (IRMT) to determine whether the carrier
or the idle condition is present on IRTX.
The IR timer is enabled when the IR enable bit (IREN) is
set to 1. The IR Value register (IRV) defines the beginning value for the carrier modulator. During transmission,
the IRV register is initially loaded with the IRMT value
and begins down counting towards 0000h, whereas
in receive mode it counts upward from the initial IRV
register value. During the receive operation, the IRV
register can be configured to reload with 0000h when
capture occurs on detection of selected edges or can be
allowed to continue free-running throughout the receive
operation. An overflow occurs when the IR timer value
rolls over from 0FFFFh to 0000h. The IR overflow flag
(IROV) is set to 1 and an interrupt is generated if enabled
(IRIE = 1).
14 ��
16-Bit Microcontroller with Infrared Module
Figure 2 illustrates the basic carrier generation and its
path to the IRTX output pin. The IR transmit polarity bit
(IRTXPOL) defines the starting/idle state and the carrier
polarity of the IRTX pin when the IR timer is enabled.
• IR Input Clock (fIRCLK) = fSYS/2IRDIV[1:0]
IR Transmission
During IR transmission (IRMODE = 1), the carrier generator creates the appropriate carrier waveform, while
the carrier modulator performs the modulation. The carrier modulation can be performed as a function of carrier
cycles or IRCLK cycles dependent on the setting of the
IRCFME bit. When IRCFME = 0, the IRV down counter is
clocked by the carrier frequency and thus the modulation is a function of carrier cycles. When IRCFME = 1, the
IRV down counter is clocked by IRCLK, allowing carrier
modulation timing with IRCLK resolution.
• C
arrier Frequency (fCARRIER) = fIRCLK/(IRCAH +
IRCAL + 2)
• Carrier High Time = IRCAH + 1
• Carrier Low Time = IRCAL + 1
• Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for
each IRV down-count interval, and is sampled along with
the IRTXPOL and IRDATA bits at the beginning of each
new IRV down-count interval so that duty-cycle variation
and frequency shifting is possible from one interval to the
next, which is illustrated in Figure 1.
The IRTXPOL bit defines the starting/idle state as well as
the carrier polarity for the IRTX pin. If IRTXPOL = 1, the
IRCA
IRCA = 0202h
IRCA = 0002h
IRMT
IRMT = 3
IRMT = 5
IRCA, IRMT, IRDATA SAMPLED AT END OF IRV
DOWN-COUNT INTERVAL
3
2
1
0
5
4
3
2
1
0
CARRIER OUTPUT
(IRV)
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0)
______________________________________________________________________________________ 15
MAXQ613
Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of
the number of IR input clocks, whereas the IRCAL byte
defines the carrier low time.
MAXQ613
16-Bit Microcontroller with Infrared Module
IRTX pin is set to a logic-high when the IR timer module is
enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low
when the IR timer is enabled.
condition, as defined by IRTXPOL, is output on the IRTX
pin during the next IRMT cycles.
The IR timer acts as a down counter in transmit mode. An
IR transmission starts when the IREN bit is set to 1 when
IRMODE = 1; when the IRMODE bit is set to 1 when IREN
= 1; or when IREN and IRMODE are both set to 1 in the
same instruction. The IRMT and IRCA registers, along
with the IRDATA and IRTXPOL bits, are sampled at the
beginning of the transmit process and every time the IR
A separate register bit, IR data (IRDATA), is used to
determine whether the carrier generator output is output
to the IRTX pin for the next IRMT carrier cycles. When
IRDATA = 1, the carrier waveform (or inversion of this
waveform if IRTXPOL = 1) is output on the IRTX pin during the next IRMT cycles. When IRDATA = 0, the idle
IRTXPOL
0
CARRIER GENERATION
IRTX PIN
IRCLK
1
CARRIER
IRCAH + 1
IRCAL + 1
IRCFME
0
1
IRDATA
IRMT
SAMPLE
IRDATA ON
IRV = 0000h
IR INTERRUPT
CARRIER MODULATION
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control
IRMT = 3
CARRIER OUTPUT
(IRV)
3
2
1
0
3
2
1
0
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
Figure 3. IR Transmission Waveform (IRCFME = 0)
16 ��
16-Bit Microcontroller with Infrared Module
When configured in receive mode (IRMODE = 0), the
IR hardware supports the IRRX capture function. The
IRRXSEL[1:0] bits define which edge(s) of the IRRX pin
should trigger the IR timer capture function.
1) Reloads IRV with IRMT.
2) Samples IRCA, IRDATA, and IRTXPOL.
3) Generates IRTX accordingly.
The IR module starts operating in the receive mode when
IRMODE = 0 and IREN = 1. Once started, the IR timer
(IRV) starts up counting from 0000h when a qualified
capture event as defined by IRRXSEL happens. The IRV
register is, by default, counting carrier cycles as defined
by the IRCA register. However, the IR carrier frequency
detect (IRCFME) bit can be set to 1 to allow clocking of
the IRV register directly with the IRCLK for finer resolution. When IRCFME = 0, the IRCA defined carrier is
counted by IRV. When IRCFME = 1, the IRCLK clocks
the IRV register.
4) Sets IRIF to 1.
5) Generates an interrupt to the CPU if enabled (IRIE = 1).
To terminate the current transmission, the user can
switch to receive mode (IRMODE = 0) or clear IREN to 0.
Carrier Modulation Time = IRMT + 1 carrier cycles
IR Transmit—Independent External Carrier
and Modulator Outputs
The normal transmit mode modulates the carrier based
upon the IRDATA bit. However, the user has the option
to input the modulator (envelope) on an external pin if
desired. If the IRENV[1:0] bits are configured to 01b or
10b, the modulator/envelope is output to the IRTXM pin.
The IRDATA bit is output directly to the IRTXM pin (if
IRTXPOL = 0) on each IRV down-count interval boundary just as if it were being used to internally modulate
the carrier frequency. If IRTXPOL = 1, the inverse of
the IRDATA bit is output to the IRTXM pin on the IRV
interval down-count boundaries. See Figure 4. When
the envelope mode is enabled, it is possible to output
either the modulated (IRENV[1:0] = 01b) or unmodulated
(INENV[1:0] = 10b) carrier to the IRTX pin.
On the next qualified event, the IR module does the
following:
1) C
aptures the IRRX pin state and transfers its value
to IRDATA. If a falling edge occurs, IRDATA = 0. If a
rising edge occurs, IRDATA = 1.
2) Transfers its current IRV value to the IRMT.
3) Resets IRV content to 0000h (if IRXRL = 1).
4) Continues counting again until the next qualified event.
If the IR timer value rolls over from 0FFFFh to 0000h
before a qualified event happens, the IR timer overflow
(IROV) flag is set to 1 and an interrupt is generated, if
IRTXM
IRTXPOL = 1
IRTXM
IRTXPOL = 0
IRDATA
1
0
1
0
1
0
1
0
IR INTERRUPT
IRV INTERVAL
IRMT
IRMT
IRMT
IRMT
Figure 4. External IRTXM (Modulator) Output
______________________________________________________________________________________ 17
MAXQ613
IR Receive
timer value reloads its value. When the IRV reaches 0000h
value, on the next carrier clock, it does the following:
MAXQ613
16-Bit Microcontroller with Infrared Module
CARRIER GENERATION
CARRIER MODULATION
IRCLK
IRCAH + 1
IRCAL + 1
0
IR TIMER OVERFLOW
1
IRCFME
INTERRUPT TO CPU
0000h
IRV
IR INTERRUPT
COPY IRV TO IRMT
ON EDGE DETECT
IRXRL
IRRX PIN
RESET IRV TO 0000h
EDGE DETECT
IRDATA
Figure 5. IR Capture
enabled. The IR module continues to operate in receive
mode until it is stopped by switching into transmit mode
(IRMODE = 1) or clearing IREN = 0.
Carrier Burst-Count Mode
A special mode reduces the CPU processing burden
when performing IR learning functions. Typically, when
operating in an IR learning capacity, some number of
carrier cycles are examined for frequency determination. Once the frequency has been determined, the IR
receive function can be reduced to counting the number
of carrier pulses in the burst and the duration of the
combined mark-space time within the burst. To simplify
this process, the receive burst-count mode (as enabled
by the RXBCNT bit) can be used. When RXBCNT = 0,
the standard IR receive capture functionality is in place.
When RXBCNT = 1, the IRV capture operation is disabled and the interrupt flag associated with the capture
no longer denotes a capture. In the carrier burst-count
mode, the IRMT register only counts qualified edges.
The IRIF interrupt flag (normally used to signal a capture
when RXBCNT = 0) now becomes set if two IRCA cycles
elapse without getting a qualified edge. The IRIF interrupt flag thus denotes absence of the carrier and the
beginning of a space in the receive signal. When the
RXBCNT bit is changed from 0 to 1, the IRMT register
is set to 0001h. The IRCFME bit is still used to define
whether the IRV register is counting system IRCLK
clocks or IRCA-defined carrier cycles. The IRXRL bit
defines whether the IRV register is reloaded with 0000h
on detection of a qualified edge (per the IRXSEL[1:0]
bits). Figure 6 and the descriptive sequence embedded
in the figure illustrate the expected usage of the receive
burst-count mode.
16-Bit Timers/Counters
The microcontroller provides two timers/counters that
support the following functions:
• 16-bit timer/counter
• 16-bit up/down autoreload
• Counter function of external pulse
• 16-bit timer with capture
• 16-bit timer with compare
• Input/output enhancements for pulse-width modulation
• Set/reset/toggle output state on comparator match
• Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
USART
The device provides a USART peripheral with the following features:
• 2-wire interface
• Full-duplex operation for asynchronous data transfers
• Half-duplex operation for synchronous data transfers
• P
rogrammable interrupt when transmit or receive data
operation completes
• Independent programmable baud-rate generator
• Optional 9th bit parity support
• Start/stop bit support
18 ��
16-Bit Microcontroller with Infrared Module
IRMT = PULSE COUNTING
IRMT = PULSE COUNTING
IRV = CARRIER CYCLE COUNTING
IRRX
IRV
IRMT
1
2
3
4
6
7
8
5
1 TO 4
9
CAPTURE INTERRUPT (IRIF = 1).
IRV ≥ IRMT.
IRV = 0 (IF IRXRL = 1).
5
SOFTWARE SETS IRCA = CARRIER FREQUENCY.
SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE).
SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1.
SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT.
IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS).
6
QUALIFIED EDGE DETECTED: IRMT++
IRV RESET TO 0 IF IRXRL = 1.
7
IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE.
BURST MARK = IRMT PULSES.
SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE.
8
9
QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE).
SOFTWARE SET RXBCNT = 1 AS IN (5).
CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED.
Figure 6. Receive Burst-Count Example
Table 3. USART Mode Details
MODE
TYPE
START BITS
DATA BITS
STOP BITS
Mode 0
Synchronous
N/A
8
N/A
Mode 1
Asynchronous
1
8
1
Mode 2
Asynchronous
1
8+1
1
Mode 3
Asynchronous
1
8+1
1
Serial Peripheral Interface (SPI)
The integrated SPI provides an independent serial
communication channel that communicates synchronously with peripheral devices in a multiple master or
multiple slave system. The interface allows access to
a 4-wire, full-duplex serial bus, and can be operated in
either master mode or slave mode. Collision detection
is provided when two or more masters attempt a data
transfer at the same time.
The maximum SPI master transfer rate is Sysclk/2. When
operating as an SPI slave, the device can support up to
Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit
or 16-bit value, MSB first. In addition, the SPI module
supports configuration of an active SSEL state (active
low or active high) through the slave active select.
______________________________________________________________________________________ 19
MAXQ613
CARRIER FREQUENCY
CALCULATION
MAXQ613
16-Bit Microcontroller with Infrared Module
SHIFT
SAMPLE
SHIFT
SAMPLE
SSEL
tMCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tMCH
tMCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV
MSB
MOSI
tRF
LSB
MSB-1
tMIS
tMIH
MSB
MISO
tMLH
MSB-1
LSB
Figure 7. SPI Master Communication Timing
SHIFT
SSEL
SAMPLE
SHIFT
SAMPLE
tSSH
tSSE
tSD
tSCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tSCH
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tSCL
tSIS
MOSI
tSIH
MSB
MSB-1
tSOV
MISO
MSB
LSB
tRF
MSB-1
tSLH
LSB
Figure 8. SPI Slave Communication Timing
20 ��
16-Bit Microcontroller with Infrared Module
ROM Loader
The microcontroller provides port pins for general-purpose I/O that have the following features:
The ROM loader denies access to the system, user loader, or user-application memories unless an area-specific
password is provided. The ROM loader is not available
in ROM-only versions.
• CMOS output drivers
• Schmitt trigger inputs
• O
ptional weak pullup to VDD when operating in input
mode
While the microcontroller is in a reset state, all port pins
become high impedance with both weak pullups and
input buffers disabled, unless otherwise noted.
From a software perspective, each port appears as a
group of peripheral registers with unique addresses.
Special function pins can also be used as general-purpose I/O pins when the special functions are disabled.
For a detailed description of the special functions available for each pin, refer to the MAXQ610 User’s Guide.
On-Chip Oscillator
An external quartz crystal or a ceramic resonator can be
connected between HFXIN and HFXOUT, as illustrated
in Figure 9.
Noise at HFXIN and HFXOUT can adversely affect onchip clock timing. It is good design practice to place the
crystal and capacitors near the oscillator circuitry and
connect HFXIN and HFXOUT to ground with a direct
short trace. The typical values of external capacitors vary
with the type of crystal to be used and should be initially
selected based on load capacitance as suggested by
the manufacturer.
HFXIN
CLOCK CIRCUIT
STOP
RF
In addition, the ROM loader also enforces the memoryprotection policies. Passwords that are 16 words are
required to access the ROM loader interface.
Loading memory is not possible for ROM-only versions
of the device.
From user-application code, flash memory can be programmed using the ROM utility functions from either C
or assembly language. The function declarations below
show examples of some of the ROM utility functions
provided for in-application flash memory programming:
/* Write one 16-bit word to code address ‘dest’.
HFXOUT
RF = 1MI Q50%
C1 = C2 = 12pF
C2
An internal bootstrap loader allows reloading over a
simple JTAG interface. As a result, software can be
upgraded in-system, eliminating the need for a costly
hardware retrofit when updates are required. Remote
software uploads are possible that enable physically
inaccessible applications to be frequently updated. The
interface hardware can be a JTAG connection to another
microcontroller, or a connection to a PC serial port using
a serial-to-JTAG converter such as the MAXQJTAG-001,
available from Maxim. If in-system programmability is not
required, a commercial gang programmer can be used
for mass programming. Activating the JTAG interface
and loading the test access port (TAP) with the system
programming instruction invokes the bootstrap loader.
Setting the SPE bit to one during reset through the JTAG
interface executes the bootstrap-loader mode program
that resides in the utility ROM. When programming is
complete, the bootstrap loader can clear the SPE bit and
reset the device, allowing the device to bypass the utility
ROM and begin execution of the application software.
In-Application Flash Programming
VDD
C1
Loading Flash Memory
* Dest must be aligned to 16 bits.
* Returns 0 = failure, 1 = OK.
*/
Figure 9. On-Chip Oscillator
int flash_write (uint16_t dest, uint16_t
data);
______________________________________________________________________________________ 21
MAXQ613
General-Purpose I/O
16-Bit Microcontroller with Infrared Module
MAXQ613
• Debug mode:
Debugger takes over the control of the CPU
MAXQ613
Read/write accesses to internal registers and memory
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
Single-step of the CPU for trace operation
CPU
DEBUG
ENGINE
TMS
TCK
TDI
TDO
TAP
CONTROLLER
CONTROL
BREAKPOINT
ADDRESS
DATA
Figure 10. In-Circuit Debugger
To erase, the following function would be used:
/* Erase the given Flash page
* addr: Flash offset (anywhere within page)
*/
int flash_erasepage(uint16_t addr);
The in-application flash memory programming must call
ROM utility functions to erase and program any of the
flash memory. Memory protection is enforced by the
ROM utility functions. In-application is not available in
ROM-only versions of the device.
In-Circuit Debug and JTAG
Interface
Embedded debug hardware and software are developed and integrated to provide full in-circuit debugging
capability in a user-application environment. These hardware and software features include the following:
• Debug engine
• S
et of registers providing the ability to set breakpoints
on register, code, or data using debug service routines stored in ROM
Collectively, these hardware and software features support two modes of in-circuit debug functionality:
• Background mode:
CPU is executing the normal user program
The interface to the debug engine is the TAP controller. The interface allows for communication with a bus
master that can either be automatic test equipment or a
component that interfaces to a higher level test bus as
part of a complete system. The communication operates
across a 4-wire serial interface from a dedicated TAP
that is compatible with the JTAG IEEE Standard 1149.
The TAP provides an independent serial channel to communicate synchronously with the host system.
To prevent unauthorized access of the protected memory regions through the JTAG interface, the debug engine
prevents modification of the privilege registers and
disallows all access to system memory, unless memory
protection is disabled. In addition, all services (such as
register display or modification) are denied when code
is executing inside the system area. The debugger is not
available for ROM-only versions of the device.
Operating Modes
The lowest power mode of operation is stop mode. In this
mode, CPU state and memories are preserved, but the
CPU is not actively running. Wake-up sources include
external I/O interrupts, the power-fail warning interrupt,
wake-up timer, or a power-fail reset. Any time the microcontroller is in a state where code does not need to be
executed, the user software can put the device into stop
mode. The nanopower ring oscillator is an internal ultralow-power (400nA) 8kHz ring oscillator that can be used
to drive a wake-up timer that exits stop mode. The wakeup timer is programmable by software in steps of 125Fs
up to approximately 8s.
The power-fail monitor is always on during normal operation. However, it can be selectively disabled during stop
mode to minimize power consumption. This feature is
enabled using the power-fail monitor disable (PFD) bit
in the PWCN register. The reset default state for the PFD
bit is 1, which disables the power-fail monitor function
during stop mode. If power-fail monitoring is disabled
(PFD = 1) during stop mode, the circuitry responsible
for generating a power-fail warning or reset is shut down
and neither condition is detected. Thus, the VDD < VRST
condition does not invoke a reset state.
Allows the host to configure and set up the in-circuit
debugger
22 ��
16-Bit Microcontroller with Infrared Module
• Always on—continuous monitoring
• 211 nanopower ring oscillator clocks (~256ms)
• 212 nanopower ring oscillator clocks (~512ms)
• 213 nanopower ring oscillator clocks (~1.024s)
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
VDD
t < tPFW
t ≥ tPFW
nanopower ring-oscillator cycles. If VDD > VRST during
detection, VDD is monitored for an additional nanopower
ring-oscillator period. If VDD remains above VRST for
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the CPU
exits the reset state in less than 20 crystal cycles after
the reset source is removed.
t ≥ tPFW
t ≥ tPFW
C
VPFW
G
VRST
E
F
B
H
D
VPOR
I
A
INTERNAL RESET
(ACTIVE HIGH)
Figure 11. Power-Fail Detection During Normal Operation
______________________________________________________________________________________ 23
MAXQ613
Power-Fail Detection
Figures 11, 12, and 13 show the power-fail detection and
response during normal and stop-mode operation. If a
reset is caused by a power-fail, the power-fail monitor
can be set to one of the following intervals:
MAXQ613
16-Bit Microcontroller with Infrared Module
Table 4. Power-Fail Detection States During Normal Operation
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
On
Off
Off
—
VDD < VPOR.
B
On
On
On
—
VPOR < VDD < VRST.
Crystal warmup time, tXTAL_RDY.
CPU held in reset.
C
On
On
On
—
VDD > VRST.
CPU normal operation.
D
On
On
On
—
Power drop too short.
Power-fail not detected.
—
VRST < VDD < VPFW.
PFI is set when VRST < VDD < VPFW and
maintains this state for at least tPFW, at
which time a power-fail interrupt is generated (if enabled).
CPU continues normal operation.
E
On
On
On
F
On
(Periodically)
Off
Off
Yes
G
On
On
On
—
H
On
(Periodically)
Off
Off
Yes
I
Off
Off
Off
—
COMMENTS
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
VDD > VRST.
Crystal warmup time, tXTAL_RDY.
CPU resumes normal operation from 8000h.
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
VDD < VPOR.
Device held in reset. No operation allowed.
24 ��
16-Bit Microcontroller with Infrared Module
t < tPFW
A
t ≥ tPFW
MAXQ613
VDD
t ≥ tPFW
VPFW
D
VRST
B
C
E
VPOR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
On
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
B
On
Off
Off
Yes
Power drop too short.
Power-fail not detected.
COMMENTS
C
On
On
On
Yes
VRST < VDD < VPFW.
Power-fail warning detected.
Turn on regulator and crystal.
Crystal warmup time, tXTAL_RDY.
Exit stop mode.
D
On
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
E
On
(Periodically)
Off
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
F
Off
Off
Off
—
VDD < VPOR.
Device held in reset. No operation allowed.
______________________________________________________________________________________ 25
MAXQ613
16-Bit Microcontroller with Infrared Module
VDD
A
D
VPFW
B
VRST
C
E
VPOR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
INTERRUPT
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
Off
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
B
Off
Off
Off
Yes
VDD < VPFW.
Power-fail not detected because power-fail
monitor is disabled.
Yes
VRST < VDD < VPFW.
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail warning, and sets the power-fail
interrupt flag.
Turn on regulator and crystal.
Crystal warmup time, tXTAL_RDY.
On stop mode exit, CPU vectors to the
higher priority of power-fail and the interrupt that causes stop mode exit.
C
On
On
On
COMMENTS
26 ��
16-Bit Microcontroller with Infrared Module
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
D
Off
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
COMMENTS
E
On
(Periodically)
Off
Off
Yes
VPOR < VDD < VRST.
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail, and puts CPU in reset.
Power-fail monitor is turned on periodically.
F
Off
Off
Off
—
VDD < VPOR.
Device held in reset. No operation allowed.
Applications Information
The low-power, high-performance RISC architecture of
this device makes it an excellent fit for many portable
or battery-powered applications. It is ideally suited for
applications such as universal remote controls that
require the cost-effective integration of IR transmit/
receive capability.
Grounds and Bypassing
purpose I/O pins. Negative voltage spikes on power pins
are especially problematic as they directly couple to the
internal power buses. Devices such as keypads can
conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System
designers must protect components against these transients that can corrupt system memory.
Additional Documentation
Careful PCB layout significantly minimizes system-level
digital noise that could interact with the microcontroller
or peripheral components. The use of multilayer boards
is essential to allow the use of dedicated power planes.
The area under any digital components should be a continuous ground plane if possible. Keep bypass capacitor
leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible.
Designers must have the following documents to fully
use all the features of this device. This data sheet
contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations
from published specifications. The user’s guides offer
detailed information about device features and operation. The following documents can be downloaded from
www.maxim-ic.com/microcontrollers.
CMOS design guidelines for any semiconductor require
that no pin be taken above VDD or below GND. Violation
of this guideline can result in a hard failure (damage to
the silicon inside the device) or a soft failure (unintentional modification of memory contents). Voltage spikes
above or below the device’s absolute maximum ratings
can potentially cause a devastating IC latchup.
• T
his MAXQ613 data sheet, which contains electrical/
timing specifications, pin descriptions, and package
information.
Microcontrollers commonly experience negative voltage spikes through either their power pins or general-
• T
he MAXQ613 revision-specific
(www.maxim-ic.com/errata).
errata
sheet
• T
he MAXQ610 User’s Guide, which contains detailed
information on features and operation, including programming.
______________________________________________________________________________________ 27
MAXQ613
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
(continued)
MAXQ613
16-Bit Microcontroller with Infrared Module
Development and
Technical Support
Deviations from the MAXQ610 User’s Guide
for the MAXQ613
The MAXQ610 User’s Guide contains all the information that is needed to develop application code for the
MAXQ613 microcontroller. However, even though the
MAXQ610 and the MAXQ613 are largely code-compatible, there are certain differences between the two
devices that must be kept in mind when referring to the
MAXQ610 User’s Guide.
The following registers on the MAXQ610 (which are
described in the MAXQ610 User’s Guide) do not exist
on the MAXQ613, and all references to them should be
disregarded:
• Port 3 Output Register (PO3)
• Port 3 Direction Register (PD3)
• Port 3 Input Register (PI3)
• Port 4 Output Register (PO4)
Maxim and third-party suppliers provide a variety of
highly versatile, affordably priced development tools for
this microcontroller, including the following:
• Compilers
• In-circuit emulators
• Integrated Development Environments (IDEs)
• S
erial-to-JTAG and USB-to-JTAG interface boards for
programming and debugging (for microcontrollers
with rewritable memory)
A partial list of development tool vendors can be found
at www.maxim-ic.com/MAXQ_tools.
For technical support, go to https://support.maxim-ic.
com/micro.
Package Information
• Port 4 Direction Register (PD4)
• Port 4 Input Register (PI4)
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN
NO.
32 TQFN-EP
T3255+3
21-0140
90-0001
32 LQFP
C32+2
21-0054
90-0111
44 TQFN-EP
T4477+2
21-0144
90-0127
44 TQFP
C44+2
21-0293
90-0316
28 ��
16-Bit Microcontroller with Infrared Module
REVISION
NUMBER
REVISION
DATE
0
7/10
Initial release
1
7/10
Corrected bare die numbers in the Pin Description table for VDD, GND, RESET,
IRTX, IRRX, P2.5/TDI, P2.6/TMS, and P2.7/TDO
2
8/10
Corrected the active mode typ value from 2.0mA to 3.25mA in the Features
DESCRIPTION
PAGES
CHANGED
—
9, 10, 11
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010
Maxim Integrated Products 29
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAXQ613
Revision History

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