高精度 三 相 PWM波 形产 生器 SA鲳 28在 逆 变器 中的应 用 ^i,~ ●新 特 器 件 应 用 岛铕 煮王巾 PWM波 形 产 哇器 SA4828 在 迸 变器 中沩 宠用 空军工程大学电讯 工程 学院 张颖超 侯振义 Application of PWM Waveform Generator SA4828 Zhang Yingchao Hou Zhenyi 摘要 :SA4828是 Mitel公 司生产的三相 PWM波 形产 生器 ,它 可提供 高质量 ,全 数 字的三相脉宽调 制波形 ,而 且编程简单方便 ,修 改灵活 ,文 中介 绍了 SA48⒛ 的原理及其应 周在逆变器中的软、 硬件 设计 方法。 关键词 :脉 宽调制 (PWM);控 制 ;逆 变;SA鲳 ⒛ 分类号 :TM呢 1 1~。 52 文献标识码 :B 文章编号 :1~0O6-ˉ 6四7(⒛ 00)09-0003一 Os 对 SA娲 28的 控制是邋过微处理器接 口将数据 引言 送人芯片和两个寄存器 (初 始化寄存器和控制寄存 (PWM)控 制技术在逆变 电路 中得到 器 )来 实现的。初始化寄存器用于设定 与逆变器有 广泛 的应用 ,其 波形产生方法有两种 :一 是模拟方 关 的一些基 本参数 ,这 些参数在 PWM输 出端允许 输 出前初始化 ,逆 变器 工 作 以后不允许改变 。 脉宽调制 法 ,二 是数字方法 。模拟方法 电路结构复杂 ,有 温漂 现象 ,难 以实现精确控制 。数字方法则克服 了上述 MITEL公 司生产 的 SA系 列 PWM波 形产生 缺点 。 控制寄存器在工作过程 中控制输 出脉宽调制波 的状态 ,从 丽进 一 步控制逆变器 的运行状态 。通常 器具有精度高 、抗干扰能力强 、外 围电路简单等优 在 工 作时该寄存器 内容常被改写 以实现实时控制 。 点 ,其 中 ⅣⅥsz8是 主要用于变频调速 、 逆变 电源及 UPS等 工业领域 的高精度 PWM波 形产生器。 2 sA48zs的 主要特点及控制方法 参数是通过 8个 暂存器 R0、 R1、 R2、 R3、 R4、 R15来 传送 的 ”初始化参数先被写人 Rθ 、 ・ …。 R1。 R5,然 后通过对 R14的 写操作将参 数送人 初始化寄存器 ”最后再将控制参数写人 R0、 R1。 … R5、 R14、 2.1SA4828的 主要特点 R5,并 通过对 R15的 写操作将参数送 人 控制 寄存 和 Mitel公 司的先前产 品 SA828相 比 ,SA+828 主要具有 以下 特点 器 。各控制寄存器的地址如表 1所 列 。 : ●具有增强型微处理器 接 口 ,可 与更多的单片 机兼容 3 参数设置 3.1初 始化参数的设置 ; ●将调制波频率 的分辨率提高到 16位 ● 由于采用 了可 由用户选择 的三相幅值独立控 ; 名称 ; m 载 表 1 (弘 鲥 28的 寄存器地址 、 m一 m一 制方式 ,因 而使得 三 相逆变器可用于任意不对称负 ●有 三 种可供选择 的输 出波形 ,适 用于多种应 用场合 ; ●可提供软件复位功能 ” “ ● 内置 看 门狗 定时器 以加强 监控 ,从 雨提蠃 ; 了可靠性 。 2。 2 SA娲 28芯 片的控制方法 m 01llll 0101 暂存器 传送初始化参数 传送控制参数 2000年 第 9期 《¤舛电弓竞器件》 ˉ ˉ・ 犀- ⒛00年 9月 表 2 初始化参数 空间分配表 2 7 FRm R(l R1 R2 R3 FRS1 RFo × PDTC FIDT5 × × × × | WD15 ∶ R4 WD14 MDT R§ W“ × × σ CFS1 CF∞ Hr3 PDYs Pm PDT1 Pm PDYs PDT0 PDY0 PDYz AC 0 WD13 WDS WD12 WIy PDY1 WS1 WD9 WD1 PDYO WSO WDs WDO f。 当 AC=1时 ,三 个 幅值暂存器独立控制各 自的 幅值 ,该 方式适用于三 相不平衡负载。 看门狗定时器时间设置 (WD) 看门狗定时器的时间 辐d由 下式给出 彦 wd=10zTIM/r血 g。 c。 脲冲延迟时间 莎 pdy的 值 由下式给出 氵 pdy=(63一 k)/512五 arr 幅值控制 (AC) ,三 相 幅值均 由 R相 幅值暂存器 R3控 制 。而 B相 幅值暂存器 R4和 Y相 幅值暂存器 R5内 容无效 。 FRS值 对应 的十进制 自然数 0~6。 脉冲延 迟 时间(PDY) : : 式中 ,y∶ k是 输入的时钟频率 ,TIM是 16位 二 进制数 WD(WD15、 WD14… …WD0)对 应 的十进 式 屮 ,k的 值为与二 进制 的 PDY值 对应 的十进 制 洳然数 0~“ 。 制数 。 逋。脉 冲取 消时间(PDT) 瞧冲取消时间 莎 pd由 下式给出 如果在 矽 wd时 间内未对定时器 中的数据更新 (表 明程 序 执 行 不 正 常 ),则 定 时 器 溢 出 9系 统 关 断 : PWM输 出。 茁 泌=(127-L)/512五 arr 3.2控 制参数 的设置 表 3 波形选择表 WDCl 各控制参数在暂存器 波形 ・ R0・ …・ 表 4所 列 。其参数说 明如下 a,电 源频 率 (PFS) Sinusold纯 正 弦形 Triplen三 次谐波叠加 Deadbanded(减 少开关损耗) R5的 空间分配如 : 电源频率 几唧er的 值 由下式给出 几⒅c Ι彡ange× PFs/65535 为用户预 留 l PDT值 对 应 的十进 当 AC=0时 : 0 WlDz 输 出波形选择控制字如表 3所 列 。 : 戍arr=ytk/(512× 2n+1) 、 式 中 Ⅱ足k是 输 人的时钟频率 。n的 值为对应 于 Ι遘制 C「 S值 的十进制 自然数 0~7。 b。 电源频 率 范围(FRS) 电源频率范 围 彡angC的 值 由下式给 出 式 中 :m的 值为与 二 进 九 nge=2m五 aⅡ /s“ 0 WD10 制 自然数 0~127。 e。 波形选择 (WS) 戴波频率 五aⅡ 的值 由下式给出 0 WD11 WDs 式 中 ,L的 值 为与 二 进 制 的 表。现将各参数作一说明。 a眇 戴波频 率(CFS) 、 VS1 m × 表 2为 初 始 化参 数 在各个 寄存 器 中的空 间分 配 制的 0 : 表 4 控 制参数 空间分配表 R0 PFS7 PFSC R1 PFS15 R曰 PFS14 PFSs PFS13 PF⒊ PFS12 × × × RAMlD5 RAMP+ m R3 蛳 RAMP6 R4 BAMPT 蛳 R5 Y咖 YAMP6 BAMP5 YAMPs PFS3 PFS11 吼 P4 E√ 廴 卜明 YAMP0 RAMPs BAMP3 YAMPS PFSz PFS10 CR RAMPz BAMPz Y衄 PFS1 PFSg Ir`Ⅱ PFη PB` F用 「 I RAMP1 BAMP1 Y胛 1 RAWO 蛳 ⒕ 卜惆 高精度 三相 PWM波 形产 生器 SA4828在 逆 变器 中的应用 式 中 ,凡 nge为 电源频率范 围。PFS是 16位 与 二 进制 (PFS15、 PFS14… …PFS⑴ 对应 的十进制数 的 将4828复 位 值。 b。 电源幅值 (RAMP、 YAMP、 B/矾ⅠP) 各 项 幅值 的百分 比计 算 公 式 如下 往R0~R5中 写 初始化参数 : 写虚拟寄存器 R14 以完成数据传输 ∧哪呵 =A× 100%/255 式 中 ,A是 8位 幅 值 选 择 字 (AMP7、 …・ AMP0)对 应 的十进制 的值 。 AMP6・ ・ o。 往R0~R5中 写 控制参数 参数是否需要 相序 选择 (F/R) 三相 写虚拟寄存器R15 以完成数据传输 PWM输 出的相序受控于正 /反 转选择位 F/R,该 位为 0时 ,相 序为红→ 黄→ 蓝 ;反 之 ,相 序为 图 2 程序流程图 蓝→ 黄→ 红 。 输 出禁 止位 (INH) “ 该位有效时 (为 0” ),所 有 的 PWM输 出变为低 电平 ,但 不影响其它操作 。一旦设置无效 ,输 出立 即 离 电路 )后 输 出 ,在 控 制 电路 中 ,单 片机不但 用来 完 恢复 。 数据 复 的逻辑 检测 。 由于 51系 列单 片机都是地址 、 d。 e。 计 数 器复位 (CR) “ 当计数器复位位 (CR)为 0” 时 ,红 相相位计数 “ 器设置为 0” 。 软件 复位 (RST) “ 当该位有效时 (为 1” ),芯 片复原为初始时的默 f。 用 总线 模 式 ,故 将 MUX、 RS引 线 连 到 高 电平 。 SETTRIP用 来 快速关 断 PWM输 TRIP端 输 出高 电平 ,指 示 灯亮 。 出 ,当 其 有效 时 。 , 4.2系 统 软件设计 软件设 计 是 整个 逆 变控 制 的核 心 ,它 决 定 着逆 变 器 的输 出特 性 。 图 认状态 ,它 的效果与硬件复位脚相 同。 看 门狗定时器选择 (WTE) “ 当该位有效时 (为 1” ),看 门狗定时器被启用 SA鲳 28的 初 始化 、输 出脉 宽 和频 率 的控 制 ,还 要处 理采样 数据 以形成 闭环控 制 ,完 成对倮 护信 号 成对 2给 出 了本 系 统 的程 序 流 程 图。 g。 从 程 序 流 程 图 中可 看 出 :单 片机 先 将 SA4828 ; ,在 向其 传 送 初 始 化 参 数 和 控 制 参 数 之 后 反之 ,看 门狗定时器被禁 止 。 复位 4 工 作状 态 ,这 时单 片机应 不 断查 询输 出状 态 ,以 便 随 硬件的设计与实现 系统软、 SA4828即 可输 出 PWM波 形 ,逆 变 器 随后 将 处 于 PWM输 出特性 ,以 满 足 系统要 求 ;只 要 系统 4.1系 统硬件 连接方案 SA4828用 在逆 变器 上 的连接 电路 如 图 1所 工 作 正 常 ,看 门狗定 时器 就不 断被更新 ,以 防止其溢 示 。图中 ,AC交 流信号经整流 、逆变 、隔离 (对 于 出而 中断 UPS和 逆变器而言 ,若 用于变频调速 ,则 不需要 隔 5 时调整 PWM输 出。 结论 SA4828可 以提供高质量 、全数字化 的三 相脉 取样A/D 宽调制波形 ,并 能实现精确控制 ,以 构成性能优异 的 逆变系统 。该系统设计简单 ,控 制 电路使用器件少 , 因而可降低成本 、提高可靠性 。另外 ,芯 片提供 的 sETTRIP sA4828 M【 氵 ADo.7 ALE RD WR TR IP SETTRIP端 在异 常情 况 下 可越 过 CPU的 控 制 而 直接关断 PWM输 出 ,因 而进 一 步提高 了系统 的可 靠性 。 收稿 日期 :2000-04-05 咨询编号 :000gO1 图1 系统 原 理 框 图 This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer SA4828 SA4828 3-Phase Pulse Width Modulation Engine Replaces November 1999 version, DS4204-3.2 DS4204-4.0 January 2000 The SA4828 PWM engine has been designed to provide waveforms for the control of variable speed AC induction motors, static and uninterruptible power supplies and other forms of electronic equipment which require precise power waveform generation. AD3 1 28 AD2 AD4 2 27 AD1 AD5 3 26 AD0 AD6 4 25 VDD The six digital PWM outputs control the six power semiconductors in a three phase inverter bridge, usually via an external isolated gate driver stage. AD7 5 24 MUX WR 6 23 RS RD 7 22 ZPPR Information contained within the PWM sequences controls the wave shape, frequency, direction and amplitude of the output waveform and also the phase relationship between each of the outputs. Parameters such as the carrier (switching) frequency, pulse underlap and pulse deletion times may be defined during initialisation of the device to allow the SA4828 to be used with all power semiconductors, irrespective of switching times. The carrier frequency may be selected up to 24kHz to allow silent ultrasonic operation. ALE 8 21 WSS RESET 9 20 RPHT CLK 10 19 SET TRIP CS 11 18 YPHT TRIP 12 17 BPHT RPHB 13 16 VSS YPHB 14 15 BPHB The device operates as a stand-alone microprocessor peripheral and it may be controlled by virtually any microprocessor or microcontroller with little or no additional logic. Configuration pins are provided to allow the device to be adapted for most data bus formats, including multiplexed and non-multiplexed data busses and RD/WR or R/W control formats. Microprocessor overhead is kept to a minimum since the device requires intervention only when a change is made to the running conditions. Steady-state operation imposes no microprocessor overhead. The PWM implementation is fully digital, giving predictable accuracy and temperature stability in hostile environments which are common to motor drive applications. An internal ROM holds the power waveforms in compressed form. Fully digital operation also provides for operation at or around zero speed, enabling DC injection braking to be implemented. Rotational frequency is defined to 16 bits, giving a resolution better than 0.05 rpm for a two pole motor running at 3000rpm. SA4828 Fig.1 Pin connections (top view) FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Fully Digital Operation Configurable Microprocessor Interface Power Frequency Range up to 4kHz 16-Bit Speed Control Resolution Carrier Frequency Selectable up to 24kHz Three Selectable Power Waveforms held in Internal ROM Selectable Minimum Pulse Width and Underlap Time Separate Amplitude Registers for Unbalanced Load Compensation Deadbanding Technique to Reduce Losses in Power Semiconductors Watchdog Timer Bootstrap Driver Precharge The effective rms amplitude of each of the three phases may be controlled individually if required. This allows compensation of unbalanced loads which is particularly useful with static inverter and uninterruptible power supplies. In addition the independent amplitude control can be used to create two phase output for use in single phase induction motor controllers. APPLICATIONS Three power waveforms are provided to cover various applications: pure sinusoid, Triplen and Deadbanded Triplen for reduced switching losses. ORDERING INFORMATION The SA4828 is implemented on sub-micron CMOS technology for low power consumption. It is available with an Industrial temperature range, and in either DIL or SOIC plastic packages. ■ ■ ■ ■ Three Phase Induction Motor Speed Controllers Uninterruptible Power Supplies Static Inverter Power Supplies Power Waveform Generators SA4828/IG/DP1S 28 lead plastic dual-in-line package, industrial temp range. SA4828/IG/MP1S 28 lead plastic small-outline package, industrial temp range. Note:- For simplicity reference is made throughout to “motor” but comments can equally apply to power supply inverters. 1/18 SA4828 ABSOLUTE MAXIMUM RATINGS Supply voltage, VDD Voltage on any pin Storage temperature Operating temperature (industrial) 7V VSS –0.5V to VDD +0.5V –55°C to 150°C –40°C to 85°C The temperature ranges quoted apply to all package types. Many package types are available. Further information is available on request. Stresses above those listed in the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the devices at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS All characteristics are quoted for VDD = 5V ± 10% and Tamb = 25˚C unless otherwise stated. Characteristic Symbol Min. Typ. Max. Units Input high voltage VIH 2 - - V - Input low voltage VIL - - 0.8 V - Input low current IIL VIN = VSS, VDD = 5.5V SET TRIP inputs –1.0 - 1.0 µA RS, MUX inputs –25 - –66 µA All other inputs - - 10 µA Input high current Conditions IIH VIN = VDD= 5.5V SET TRIP inputs 22 - 66 µA RS, MUX inputs –1.0 - 1.0 µA All other inputs - - 10 µA Output high voltage VOH 4.0 4.5 - V IOH = –12mA. Phase outputs and TRIP Output low voltage VOL - 0.2 0.4 V IOH = 12mA. Phase outputs and TRIP Output high voltage VOH 4.0 4.5 - V IOH = –2mA. All other outputs Output low voltage VOL - 0.2 0.4 V IOH = 2mA. All other outputs IDD (static) - - 500 µA All outputs open circuit IDD (dynamic) - (TBD) (TBD) µA fCLK = 25MHz Supply voltage VDD 4.5 5.0 5.5 V - Clock frequency fCLK - - 25 MHz - Clock duty cycle DCLK 40 - 60 % - SET TRIP = 0 → outputs tripped tTRIP 3/fCLK - 4/fCLK µs fCLK = in MHz 3/fCLK - 4/fCLK µs fCLK = in MHz Supply current (static) Supply current (dynamic) → TRIP = 0 Note 1: For microprocessor interface timings, see figs. 4 - 7. 2/18 SA4828 PIN DESCRIPTIONS Pin No. Name Type Pin No. Name Type 1 AD3 I Address/Data 15 2 AD4 I Address/Data 16 3 AD5 I Address/Data 17 4 AD6 I Address/Data 18 5 AD7 I Address/Data (MSB) 19 6 WR (R/W) I Write Strobe (Read/Write) 7 RD (DS) I Read Stobe (Data Strobe) 20 RHPT O Red Phase (Top Switch) 8 ALE (AS) I Address Latch Enable (Address Strobe) 21 WSS O Waveform Sampling Sync. 9 RESET I Hardware Reset; active low 22 ZPPR O Zero Phase Pulse (Red Phase) 10 CLK I Clock Input 23 RS I Register Select; internal pull up 11 CS I Chip Select; active low 24 MUX I Bus Select; internal pull up 12 TRIP O Trip Status; low = tripped 25 VDD P Positive Power Supply 13 RPHB O Red Phase (Bottom Switch) 26 AD0 I Address/Data (LSB) 14 YPHB O Yellow Phase (Bottom Switch) 27 AD1 I Address/Data 28 AD2 I Address/Data Function Function O Blue Phase (Bottom Switch) VSS P 0V Power Supply BPHT O Blue Phase (Top Switch) YPHT O Yellow Phase (Top Switch) SET TRIP I Set Output Trip; BPHB active high; internal pull down ZPPR WSS RESET SYSTEM BUS AD0-AD7 8 BUS DEMULTIPLEXER INITIALISATION REGISTER PHASING AND CONTROL LOGIC REGISTER BANK CONTROL REGISTER CS WR RD PULSE WIDTH DELETION PULSE DELAY CIRCUIT PULSE WIDTH DELETION PULSE DELAY CIRCUIT PULSE WIDTH DELETION PULSE DELAY CIRCUIT UPPER SWITCHING OUTPUT RED PHASE LOWER SWITCHING OUTPUT UPPER SWITCHING OUTPUT YELLOW PHASE LOWER SWITCHING OUTPUT BUS CONTROL ALE MUX UPPER SWITCHING OUTPUT BLUE PHASE LOWER SWITCHING OUTPUT RS CLOCK CLOCK DIVIDER TRIP LATCH ADDRESS GENERATOR WATCHDOG TIMER TRIP SET TRIP WAVEFORM SELECT WAVEFORM ROMS RESET WATCHDOG Fig. 2 SA4828 internal block diagram 3/18 SA4828 PWM SWITCHING INSTANTS TRIANGLE WAVE AT CARRIER FREQUENCY, SAMPLING ON +VE AND –VE PEAKS +1 0 –1 +1 POWER WAVEFORM AS READ FROM INTERNAL ROM EQUIVALENT CONTINUOUS POWER WAVEFORM RESULTING PWM WAVEFORM 0 –1 Fig.3 Asynchronous PWM generation with uniform or ‘double-edged’ regular sampling as used on the SA4828 FUNCTIONAL DESCRIPTION An asynchronous method of PWM generation is used with uniform or ‘double-edged’ regular sampling of the stored power waveform, as illustrated in Fig. 3. Three standard waveforms exist so that the device may be adapted to particular applications. In general, a pulse width modulation signal is derived by comparing a signal waveform (in this case the power waveform) with a saw-tooth or triangular carrier waveform of significantly higher frequency. The intersections between the two waveforms in the time domain define the location of transitions in the digital output train and hence the width of the output pulses. The width of the pulses are directly proportional to the magnitude of the power waveform, thus the larger the magnitude, the longer the ‘ON’ pulse. The SA4828 uses a digital implementation of this technique which avoids drift problems associated with the use of analog circuitry. A triangular waveform is synthesised using an up/down counter and a digital comparator used to compare this with the power waveform. The power waveform is sampled regularly at every peak and every trough of the carrier waveform allowing both edges of the PWM output pulse to move in time, hence the term ‘double-edged regular sampling.’ (A saw-tooth carrier waveform would result in one fixed edge and one moving edge for each PWM pulse). The power waveform is stored digitally in on-chip ROM (1536 samples per 360˚). The power frequency is controlled by the rate at which the ROM is addressed - a rate which is not related to the carrier frequency on the SA4828, hence the term ‘asynchronous method of PWM generation’. The waveform values obtained from the ROM may also be scaled to produce variable voltage amplitude. Fig. 3 shows the triangular carrier waveform together with the stepped waveform which results from sampling the output of the ROM at the peaks and troughs of the carrier. (A continuous power waveform is also shown for reference). It can be seen that the PWM edges of the waveform (Fig. 3) are obtained at the points where the carrier and the sampled power waveform intersect. The carrier (switching) frequency is selectable up to 24kHz (assuming a 24.576MHz clock input) enabling ultrasonic switch4/18 ing in noise critical applications. Power frequency ranges of up to 4kHz are possible with the actual output frequency resolved to 16-bits within the chosen range. This allows for precise motor speed control and smooth frequency changing. Because the SA4828 implementation is entirely digital, operation at (or around) 0Hz is possible without stability or temperature problems. The output phase sequence may be changed to allow both forward and reverse motor operation. PWM output pulses can be tailored to the inverter characteristics by defining minimum allowable pulse width and the pulse delay (underlap) time without the need for external circuitry. This gives cost savings in terms of the power semiconductor ratings and the size of heatsink required. Power amplitude control is also provided via three 8-bit registers. By default one register is used to define the amplitude of all three phases. However, by setting the Amplitude Control (AC) bit in the Initialisation Register, the amplitude of each phase may be controlled individually. This allows unbalanced load compensation which is of particular use in static inverter and uninterruptible power supplies and the generation of 2 phase supplies for two winding single phase motors. To ensure a robust solution, a trip input allows the PWM outputs to be shut down immediately, overriding microprocessor control in the event of an emergency. This circumvents the delay which a microprocessor interrupt service cycle would inevitably introduce. A Watchdog Timer function is included. This is intended as a safeguard to trip the device outputs in the event that communications with a controlling processor are lost. MICROPROCESSOR INTERFACE The SA4828 has a parallel write-only interface which is connected to the microprocessor/microcontroller by means of a configurable data bus. This ensures compatibility with virtually all microprocessors/ microcontrollers irrespective of bus width and format and with little or no additional logic. Most data bus formats may be categorised as either having a multiplexed address/ data bus or separate address and data buses. Similarly, most microprocessors have either a WR/RD or a R/W structure. The SA4828 has been designed to operate SA4828 t4 ALE RD Minimum bus timings: t1 t2 t3 t4 t5 t6 t7 t8 WR CS AD0-7 t2 CS setup time Address hold time Address setup time ALE pulse width WR pulse width Data setup time Data hold time CS hold time 10ns 10ns 10ns 30ns 60ns 20ns 10ns 0ns t5 t1 t8 t3 t6 t7 WR mode Fig.4 Bus timing diagram - multiplexed RD RD/WR t4 AS Minimum bus timings: DS R/W CS AD0-7 t2 t7 t8 t1 t9 t3 t5 t6 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 CS setup time Address hold time Address setup time AS pulse width DS pulse width R/W pulse width R/W setup time CS hold time Data setup time Data hold time R/W hold time 10ns 10ns 10ns 30ns 60ns 60ns 20ns 0ns 20ns 10ns 10ns t10 t11 W mode Fig.5 Bus timing diagram - multiplexed R/W 5/18 SA4828 Add RS CS D0-7 RD WR Minimum bus timings: RS/CS setup time Data setup time RS/CS hold time Data hold time WR pulse width t1 t2 t3 t4 t5 10ns 30ns 0ns 10ns 30ns t1 t4 t2 t3 t5 Address write cycle Data write cycle N.B. Timings for both cycles are the same WR mode Fig.6 Bus timing diagram - non-multiplexed RD RD/WR Add RS CS D0-7 DS R/W Minimum bus timings: t1 t2 t3 t4 t5 RS/CS/R/W setup time DS pulse width Data setup time RS/CS/R/W hold time Data hold time 30ns 30ns 30ns 0ns 10ns t2 t1 t3 t5 t4 Address write cycle N.B. Timings for both cycles are the same W mode Fig.7 Bus timing diagram - non-multiplexed R/W 6/18 Data write cycle SA4828 with any combination of these four categories. A configuration pin, MUX, is used to differentiate between multiplexed and non-multiplexed buses. This pin is held at a low logic level for non-multiplexed operation and is either pulled to a high logic level or left floating for multiplexed operation (by virtue of an internal pull-up resistor). A further signal, named Register Select (RS) is used while in non-multiplexed bus mode to define whether the incoming byte is address (0) or data (1). It is pulled high via an internal resistor so that it need not be connected in multiplexed mode. It is ordinarily connected to an address line in non-multiplexed mode. In addition to these signals, the SA4828 automatically adjusts itself to the format of the bus control signals. During each write cycle, an internal detection circuit determines whether the RD/WR or R/W format is being used and automatically adapts the SA4828 to suit. A chip select (CS) pin is also provided to allow the device to share the same bus as other peripherals. The interface operates as follows: (i) Multiplexed mode Connect MUX to VDD or leave open-circuit. RS is don’t care so leave open-circuit or connect to either rail. The Initialisation Register sets up the basic operating parameters associated with the motor and inverter. This would normally be loaded prior to motor operation (i.e. before the PWM outputs are activated) and is not normally updated during motor operation. The Control Register is used to control the PWM outputs (and hence the motor) during operation. For example, speed, forward/reverse, start and stop. Typically, this register will be written to many times during motor operation in order to achieve motor acceleration etc. The addressing of the SA4828 registers is shown in table 1. Comment AD3 AD2 AD1 AD0 Register Temporary register R0 0 0 0 0 Temporary register R1 1 0 0 0 Temporary register R2 0 0 0 1 Temporary register R3 1 0 0 1 Temporary register R4 0 0 1 0 Temporary register R5 1 0 1 0 Transfers initialisation data R14 0 1 1 1 Transfers control data R15 1 1 1 1 Table 1 SA4828 register addressing The incoming address is latched into the address register during each write cycle on the falling edge of ALE (provided CS set-up and hold times are adhered to). Within the same cycle, the data is latched into the temporary registers on the rising edge of WR (RD/WR format) or the falling edge of DS (R/W format). This is shown diagramatically in Figs. 4 and 5. (ii) Non-Multiplexed mode Connect MUX to VSS. Connect RS to any suitable address bit (usually A0). Connect ALE to VSS. This means that any write operation which clears A0 will write the address into the SA4828 and any which sets it will write the corresponding data. To write to the device in this mode, first perform a write operation to the device such that RS=0 and the data is equal to the required address. As WR returns high (RD/WR format) or DS returns low (R/W format) the information is written into the SA4828 address register. Next write the data itself with RS=1. As WR returns high (or DS returns low) the data is written into the temporary register dictated by the SA4828 address register. When RS is connected to the least significant address line, this gives an equivalent memory map of just two locations, the upper one being ‘Data’ and the lower being ‘Address’. Operation in this mode is shown diagramatically in Figs. 6 and 7. Industry standard microprocessors such as the 8051, 6805, 68000 and TMS320 may be used with little or no additional circuitry. Since the microprocessor interface is fully static, bus operation may be emulated using port pins- allowing operation with microcontrollers which have no data bus such as the PIC, ST6 and Z86C series. CONTROLLING THE SA4828 The SA4828 is controlled by loading data into two 48-bit registers via the microprocessor interface. These are the Initialisation Register and the Control Register. Data is initially loaded into a series of Temporary Registers which are then transferred simultaneously to either of the two registers by means of a dummy write operation. Since the width of the microprocessor interface is restricted to 8 bits, data is initially loaded into a series of six Temporary Registers, named R0, R1....R5. This data is then transferred simultaneously to either the Initialisation or Control Register. New data is only acted upon once it has been transferred. Transfer of data takes place by performing a write operation to a ‘dummy’ register. Writing to Temporary Register 14 transfers the data to the Initialisation Register. Similarly, writing to Temporary Register 15 transfers the data to the Control Register. The data written to Registers 14 and 15 is irrelevant since these are not physically implemented registers, but the write cycle must be completed in order to transfer the data. INITIALISATION REGISTER FUNCTIONS 3 4 5 6 7 2 1 X CFS2 CFS1 R0 FRS2 FRS1 FRS0 X X PDT6 PDT5 PDT4 PDT3 PDT2 PDT1 R1 X PDY5 PDY4 PDY3 PDY2 PDY1 X R2 O O AC X X X WS1 R3 R4 WD15 WD14 WD13 WD12 WD11 WD10 WD9 R5 WD7 WD6 WD5 WD4 WD3 WD2 WD1 Table 2 Initialisation register allocation 0 CFS0 PDT0 PDY0 WS0 WD8 WD0 The Initialisation Register data is loaded in 8-bit bytes into Temporary Registers R0-R5. It may be transferred to the Initialisation Register by writing ‘dummy’ data to Temporary Register R14. Note that don’t care (X) bits should always be written to ensure code compatibility in the event of future augmentations. Under normal operation, the contents of this register will be defined during the power up sequence. These parameters are particular to the inverter circuitry used and therefore changing these parameters during motor operation is not recommended. Modifications should be made by first inhibiting the PWM outputs using the INH bit in the Control Register, or by asserting the hardware reset. 7/18 SA4828 Carrier Frequency (CFS) R0 FRS2 FRS1 FRS0 The power frequency range, fRANGE, is then given by: X X CFS2 CFS1 CFS0 CARRIER FREQUENCY WORD (3-BIT) CFS2 = MSB CFS0 = LSB 111 7 110 6 101 100 5 4 011 3 010 2 384 where fCARR = carrier frequency Pulse Delay Time (Underlap) (PDY) Defines the frequency of the triangular waveform to which the power waveform is compared - see Fig. 3. Choice of carrier frequency is largely dependent upon the power semiconductors used in the inverter. Slower devices such as bipolar transistors require a lower carrier frequency whilst fast devices such as MOSFETs and IGBTs may be used at much higher carrier frequencies. High carrier frequencies are advantageous since they increase waveform resolution, but with increased switching losses in the power semiconductors. Carrier frequencies in excess of about 18kHz are beyond the range of human hearing which helps to eliminate audible noise. The carrier frequency is a function of the externally applied clock frequency and a division ratio n, determined by the 3-bit CFS word set during initialisation. The values of n are selected as shown in table 3. CFS word Value of n fCARR x 2m fRANGE = 001 000 1 0 Table 3 Values of clock division ratio n R2 X X PDY5 PDY4 PDY3 PDY2 PDY1 PDY0 PULSE DELAY WORD (6-BIT) PDY5 = MSB PDY0 = LSB For each output phase there are two PWM control signalscontrolling the upper and lower switches in the inverter. In theory, these two control signals are always complementary. However, due to the finite and non-equal turn-on and turn-off times of power semiconductors, it is necessary to provide a short time during which both outputs are off in order to avoid a transient short circuit through the two devices. The length of this ‘underlap’ period is dependent upon the technology of the power semiconductors. Again, slow devices such as bipolar transistors require a longer underlap time whilst faster devices require a shorter time. The pulse delay time affects all six PWM outputs by delaying the rising edges of each of the outputs by an amount. The pulse delay time is a function of the carrier waveform frequency and PDY, defined by the 6-bit pulse delay time select word. The value of pdy is selected as shown in table 5. The carrier frequency, fCARR, is then given by: fCARR = PDY word Value of PDY fCLK 512 x 2 n+1 Power Frequency Range (FRS) FRS2 FRS1 FRS0 X X 101 5 100 4 011 3 010 2 001 1 Table 4 Values of clock division ratio m 8/18 tpdy = CFS2 CFS1 CFS0 000000 0 63 - PDY fCARR x 512 where fCARR = carrier frequency. In order to optimise the frequency resolution of the SA4828, the required range of power frequencies may be selected using this parameter. Within the selected range, the frequency may be set with 16-bit resolution. It is recommended that the next higher power frequency range than the maximum required motor frequency is used. The power frequency range defines the maximum limit of the power frequency. The actual operating power frequency is controlled by the 16-bit Power Frequency Select (PFS) word in the Control Register but it may not exceed the value set here. The power frequency range is a function of the carrier waveform frequency (fCARR) and a multiplication factor m, determined by the 3-bit FRS word. The value of m is determined as shown in Table 4. 110 6 ...etc... ...etc... The pulse delay time, tpdy, is then given by: FREQUENCY RANGE WORD (3-BIT) FRS2 = MSB FRS0 = LSB FRS word Value of m 111110 62 Table 5 Values of PDY where fCLK = clock input frequency. R0 111111 63 000 0 Fig.8 shows the effect of pulse delay on a pure PWM waveform. It should be noted that as the pulse delay circuit follows the pulse deletion circuit (see Fig.2), the minimum pulse width seen at the PWM outputs will be shorter than the pulse deletion time set in the initialisation register. The actual shortest pulse generated is given by tpd – tpdy. Pulse Deletion Time (PDT) R1 X PDT6 PDT5 PDT4 PDT3 PDT2 PDT1 PDT0 PULSE DELETION WORD (7-BIT) PDT6 = MSB PDT0 = LSB Pure PWM pulse trains contain pulses which vary in duty cycle from 0% to 100%. Therefore pulse widths may become very small indeed. In practice short pulses have no useful purpose since the power semiconductors cannot fully turn on/off within the active period of the pulse. Such pulses only increase the power dissipation in the power devices. SA4828 induction motors. For three phase induction motor control a Triplen waveform is included which provides maximum utilisation of the inverter DC link voltage using a harmonic injection technique. Also for motor control, a Deadbanded Triplen waveform may be selected which in addition to providing DC link voltage boost, acts to reduce the number of switching events in the power semiconductors in order to reduce the switching losses. A symmetrical technique is used to ensure that each power semiconductor benefits to the same degree. PWM SIGNAL REQUIRED AT INVERTER OUTPUT tpdy tpdy OUTPUT SIGNAL TO DRIVE TOP SWITCH INVERTER ARM tpdy tpdy R3 OUTPUT SIGNAL TO DRIVE BOTTOM SWITCH INVERTER ARM X X AC 0 0 X WS1 WS0 WAVEFORM SELECTION BITS tpdy = PULSE DELAY TIME Two bits, WS0 and WS1, in Temporary Register 3 are used to define the power waveform, according to Table 7: Fig.8 Effect of pulse delay on PWM pulse train Therefore, a minimum pulse width may be defined. All pulses shorter in duration than this are eliminated from the PWM train, whether they are low-going or high-going. To eliminate short pulses the true PWM train is passed through a pulse deletion circuit. The pulse deletion circuit compares pulse widths with the pulse deletion time set in the Initialisation Register. If a pulse (either positive or negative) is greater in duration than the pulse deletion time, it is passed through unaltered, otherwise the pulse is deleted. The pulse deletion time, tpd , is a function of the carrier wave frequency and PDT, defined by the 7-bit pulse deletion time word. The value of PDT is selected as shown in Table 6. PDT word Value of PDT 1111111 127 1111110 126 ...etc... ...etc... 0000000 0 Table 6 Values of PDT WS1 WS0 Waveform 0 0 Sinusoid (default) 0 1 Triplen (harmonic injection) 1 0 Deadbanded Triplen (switching loss reduction) 1 1 Reserved Table 7 Waveform selection The waveforms may be described by the following mathematical relationships and are shown graphically in Fig. 10: Sinusoid: f(t) = A sin (ωt) where A = amplitude, ω = angular displacement Triplen: f(t) f(t) = A(2. sin (ωt + 30˚) –1 f(t) = A f(t) = A(2. sin (ωt – 30˚) –1 f(t) = A(2. sin (ωt + 30˚) +1 f(t) = –A f(t) = A(2. sin (ωt –30˚) +1 The pulse deletion time, tpd, is then given by: tpd = 127 - PDT fCARR x 512 where fCARR = carrier frequency. Valid 0˚ ≤ ωt < 60˚ 60˚ ≤ ωt ≤ 120˚ 120˚ ≤ ωt < 180˚ 180˚ ≤ ωt < 240˚ 240˚ ≤ ωt ≤ 300˚ 300˚ ≤ ωt < 360˚ Fig. 9 shows the effect of pulse deletion on a pure PWM waveform. Waveform Selection Three waveforms are included as standard with the SA4828. A pure sine wave is available for applications where waveform purity is important such as static inverter power supplies, uninterruptible power supplies and for driving single or two phase PWM SIGNAL BEFORE PULSE DELETION >tpd tpd >tpd >tpd >tpd >tpd >tpd <tpd >tpd tpd >tpd <tpd PWM SIGNAL AFTER PULSE DELETION PULSE DELETED PULSE DELETED Fig.9 The effect of the pulse delay deletion circuit 9/18 SA4828 f(t) Line output voltages appearing across the load are: Vfg = f(t) – g(t) Vgh = g(t) – h(t) Vhf = h(t) – f(t) SINUSOID A The line voltage waveforms are sinusoidal. 0° 180° 360° Amplitude Control (AC) R3 X AC 0 0 X WS1 WS0 AMPLITUDE CONTROL BIT f(t) TRIPLEN A 0° 60° 120° 180° 240° 300° 360° This is a single bit, AC in Temporary register 3, which controls the amplitude control mode for each of the three phases. When the AC bit is cleared the red Amplitude byte in the Control Register is used to define the amplitude of all three phases. When the AC bit is set, the individual Amplitude bytes, Red, Yellow and Blue in the Control Register are used to define the amplitudes of the respective phases. Watchdog Timer (WD) f(t) DEADBANDED TRIPLEN Example with A = 0.75 0° 60° 120° 180° 240° 300° 360° Fig.10 Waveforms implemented in SA4828 Deadbanding: Below are the modulating functions for the Deadbanded Triplen waveform. These have been normalised and scaled to give a peak line (phase to phase) voltage of 2A. All the 3 phases are shown for clarity, f(t), g(t) and h(t). Function f(t) = 2A. sin(ωt + 30˚) –1 g(t) = –1 h(t) = 2A. sin(ωt + 90˚) –1 Valid 0˚ < ωt ≤ 60˚ f(t) = 1 g(t) = 1 + 2A. sin (ωt – 150˚) h(t) = 1 + 2A. sin(ωt + 150˚) 0˚ < ωt ≤ 120˚ f(t) = 2A. sin(ωt – 30˚) –1 g(t) = 2A. sin(ωt – 90˚) –1 h(t) = –1 120˚ < ωt ≤ 180˚ f(t) = 1 + 2A. sin(ωt + 30˚) g(t) = 1 h(t) = 1 + 2A. sin(ωt + 90˚) 180˚ < ωt ≤ 240˚ f(t) = –1 g(t) = 2A. sin(ωt – 150˚) –1 h(t) = 2A. sin(ωt + 150˚) –1 240˚ < ωt ≤ 300˚ f(t) = 1 + 2A. sin(ωt – 30˚) –1 g(t) = 1 + 2A. sin(ωt – 90˚) –1 h(t) = 1 300˚ < ωt ≤ 360˚ 10/18 X R4 WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 R5 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 WATCHDOG COUNTER WORD (16-BIT) WD15 = MSB WD0 = LSB The Watchdog Timer consists of a 16-bit programmable counter, which is decremented at a sub-multiple of the fCLK frequency. If the counter is allowed to reach its terminal condition (time-out), then the PWM outputs are set to the off (low) state and the TRIP output asserted low. Initialisation temporary registers R4 and R5 are used to transfer the initial data for the 16-bit Watchdog programmable counter. Register R4 is the most significant byte (MSB). The programmable counter is reset to its initial value every time a write is made to the Control register. The time-out period twd, is given by the formula: twd = TIM x 1024 fCLK Where TIM is the equivalent decimal value of the 16-bit binary number loaded to registers R4 and R5, 0 < TIM < 65535. This gives a time-out range of 41µs < twd < 2.68s at 25MHz master clock. When the Watchdog times out a TRIP condition is activated, (see SET TRIP). This state can only be cleared by application of a Reset signal, (either hardware or software). The Watchdog Timer function is always disabled following a hardware or software reset. It is enabled by setting the WTE bit in the Control Register to an active logic 1 level. If the Watchdog function is not required the WTE bit should be set to logic 0. SA4828 CONTROL REGISTER FUNCTIONS R0 R1 R2 R3 R4 R5 7 6 5 4 3 2 1 0 PFS7 PFS6 PFS5 PFS4 PFS3 PFS2 PFS1 PFS0 PFS15 PFS14 PFS13 PFS12 PFS11 PFS10 PFS9 PFS8 RST X X X WTE CR INH F/R RAMP7 RAMP6 RAMP5 RAMP4 RAMP3 RAMP2 RAMP1 RAMP0 BAMP7 BAMP6 BAMP5 BAMP4 BAMP3 BAMP2 BAMP1 BAMP0 YAMP7 YAMP6 YAMP5 YAMP4 YAMP3 YAMP2 YAMP1 YAMP0 where A = integer value of 8-bit amplitude select word. Note that the Amplitude Control (AC) bit in the Initialisation Register determines whether the Red Amplitude register value is used for all three phases, or if they are controlled independently. R2 RST X X X WTE CR INH F/R FORWARD/REVERSE BIT Table 8 Control register allocation The Control Register data is loaded in 8-bit bytes into Temporary Registers R0-R5. It may be transferred to the Control Register by writing ‘dummy’ data to Temporary Register R15. Note that don’t care (X) bits should always be written to logic 0 to ensure code compatibility in the event of future product augmentations. Power Frequency (PFS) R0 PFS7 PFS6 PFS5 PFS4 PFS3 PFS2 PFS1 PFS0 R1 PFS15 PFS14 PFS13 PFS12 PFS11 PFS10 PFS9 PFS8 POWER FREQUENCY WORD (16-BIT) PFS15 = MSB PFS0 = LSB The power frequency is selected as a proportion of the power frequency range (defined in the Initialisation Register) by the 16-bit power frequency select word, PFS, allowing the power frequency to be defined in 65536 equal steps. As the PFS word spans the two temporary registers R0 and R1 it is essential, when changing the power frequency, that both these registers are updated before writing to R15. The power frequency (fPOWER) is given by: fRANGE fPOWER = x PFS 65536 F/R) Forward/Reverse (F The phase sequence of the three-phase PWM output waveforms is controlled by the Forward/Reverse bit F/R. The actual effect of changing this bit from 0 (forward) to 1 (reverse) is to reverse the power frequency phase counter from incrementing the phase angle to decrementing it. The required output waveforms are all continuous with time during a forward/ reverse change. In the forward mode the output phase sequence is red-yellow-blue and in the reverse mode the sequence is blue-yellowred. R2 RST X X X WTE CR INH F/R OUTPUT INHIBIT BIT INH Output Inhibit (INH INH) When active (i.e., low) the output inhibit bit INH sets all the PWM outputs to the off (low) state. No other internal operation of the device is affected. When the inhibit is released, the phase bottom outputs are driven high for a whole carrier cycle before the phase top outputs are enabled. This allows time for the capacitors in bootstrap drive circuits to be charged. R2 RST X X X WTE CR INH F/R COUNTER RESET BIT where PFS = decimal value of the 16-bit PFS word and fRANGE = power frequency range set in the Initialisation Register. CR Counter Reset (CR CR) R3 RAMP7 RAMP6 RAMP5 RAMP4 RAMP3 RAMP2 RAMP1 RAMP0 R4 BAMP7 BAMP6 BAMP5 BAMP4 BAMP3 BAMP2 BAMP1 BAMP0 R5 YAMP7 YAMP6 YAMP5 YAMP4 YAMP3 YAMP2 YAMP1 YAMP0 AMPLITUDE WORDS (3x 8-BIT) RAMP7, BAMP7, YAMP7 = MSB RAMP0, BAMP0, YAMP0 = LSB This facility allows the internal power frequency phase counter to be set to 0˚ (red phase) while Counter Reset (CR) is low. Normal frequency control is suspended; the red phase outputs have 50% duty cycle and yellow and blue phases have duty cycles corresponding to +120˚ and –120˚ respectively. R2 RST X X X WTE CR INH F/R WATCHDOG ENABLE BIT Power Frequency Amplitude (RAMP, YAMP, BAMP) This defines the effective rms amplitude of the output PWM signals. In a motor application this allows the voltage/frequency (flux) relationship to be defined. The power waveform amplitude is determined by scaling the amplitude of the waveform samples stored in the internal ROM by the value of the 8-bit amplitude select words (RAMP, YAMP and BAMP). The percentage amplitude control for each A phase is given by: 255 x 100 Power Amplitude (%), APOWER = Watchdog Timer Enable (WTE) The Watchdog Timer Enable bit WTE enables the watchdog function when set to an active high level. When WTE is set to 11/18 SA4828 a low level the Watchdog function is disabled. The 16-bit Watch- R2 RST X X X WTE CR INH F/R SOFTWARE RESET BIT dog counter forms part of the Initialisation Register. isters remain unchanged. Notes: 1. After a reset operation, in order to enable the PWM outputs, the INH bit-1 and the CR bit-2 in Temporary Register R2 must be set to a logic “1” state, and a Write operation to register address R15 performed. Software Reset The software reset bit RST provides a facility to reset the device from the microprocessor interface instead of using the RESET pin. When active (high), the chip is put into the same state as that when RESET is asserted except that the RST bit is not itself forced low. The reset condition may be cleared by writing ‘0’ to the RST bit using the microprocessor interface, or by toggling the RESET pin. HARDWARD INPUT/OUTPUT INSTRUCTIONS Set Output Trip (SET TRIP input) The SET TRIP input is provided separately from the microprocessor interface in order to allow an external source to override the microprocessor and provide a rapid shutdown facility. For example, logic signals from overcurrent sensing circuitry might be used to activate this input. When the SET TRIP input is taken to a logic high, the output trip latch is activated. This results in the TRIP output and the six PWM outputs being latched low immediately. This condition can only be cleared by applying a reset cycle to the RESET input or by toggling the RST control bit. It is essential that when not in use SET TRIP is tied low and isolated from potential sources of noise; on no account should it be left floating. SET TRIP is latched internally at the master clock rate in order to reduce noise sensitivity. 2. Following a reset sequence after power up, in order to prevent spurious operation, it is essential to write known values to the Initialisation and Control Registers before the INH bit is set to a logic “1” state. (See Fig.12 Programming example.) 3. Following any other reset sequence it should be noted that PFS and the AMP registers are not cleared and it may be desirable to write to these registers before INH and CR bits are set to logic 1. Zero Phase Pulse (ZPPR output) The zero phase pulse output provides a signal at the same frequency as the power frequency with a 1 : 1 mark-space ratio. When in the forward mode of operation the falling edge of ZPPR corresponds to 0° for the red phase. In the reverse mode, the rising edge of ZPPR corresponds to 0° for the red phase. Waveform Sampling Synchronisation (WSS output) The WSS output is derived from the LSB of the waveform ROM address generator and toggles once every ROM address. There are a total of 768 rising and 768 falling edges output over a complete power frequency cycle. Note that because the ROM is addressed at a rate controlled by a digital rate generator, the edges are not equispaced. TRIP output) Output Trip Status (TRIP Clock (CLK input) The TRIP output indicates the status of the output trip latch and is active low. The CLK input provides a timing reference used by the SA4828 for all timings related to the PWM outputs. The microprocessor interface, however, derives all its timings from the microprocessor and therefore the microprocessor and the SA4828 may be run either from the same or from different clocks. RESET input) Reset Operation (RESET Operation of the Hardware Reset, RESET (active low); or Software Reset, RST (active high); performs the following functions: 1. All PWM outputs are forced low (if not already low) thereby turning off the drive switches. 2. All internal counters, (including the Watchdog Timer), are reset. (This corresponds to zero degrees for the red phase output.) 3. The trailing edge of reset sets the TRIP output high - assuming that the SET TRIP input is inactive (i.e. low). Default/Reset Conditions The following default conditions are imposed after a reset: 1. INH = 0. PWM outputs disabled. 2. CR = 0. Internal Counter Reset held active low. 3. WTE = 0. Watchdog Timer is disabled. 4. RST = 0. Software reset is deasserted (assertion of RESET only). The status of all other bits in the Initialisation and Control Reg12/18 SA4828 PROGAMMING EXAMPLE The following example assumes that a master clock of 24.576 MHz is used. This clock frequency will allow a maximum carrier frequency of 24 kHz and a maximum power frequency of 4 kHz. Initialisation Register Programming Example A power waveform range of up to 250Hz is required with a carrier frequency of 6kHz, a pulse deletion time of 10µs and an underlap of 5µs. The Triplen waveform is required and common amplitude control should be used across all three phases. 1. Setting the carrier frequency The carrier frequency should be set first as the power frequency, pulse deletion time and pulse delay time are all defined relative to the carrier frequency. Calculate the valuef of n that will give the required carrier freCLK quency: 512 x 2n + 1 fCARR = ⇒ 2n+1 = fCLK 24.576 x 106 512 x fCARR 512 x 6 x 103 = =8 SA4828 ⇒n=2 From Table 3, n = 2 corresponds to a 3-bit CFS word of 010 in temporary register R0. 2. Setting the power frequency range Calculate the value ofmm that will give the required power fCARR x 2 frequency: 384 fRANGE = ⇒ 2m = 6 x 10 = The Triplen waveform is selected by setting WS0 = 1 and WS1 = 0. Common amplitude control is required across the three phases. This is selected by setting AC = 0. Hence Temporary Register R3 should be set to 00000001. This function is disabled so temporary registers R4 and R5 can be set to all zero. 3 fCARR 5. Setting waveform select, amplitude control etc. 6. Setting Watchdog Timer Counter. 250 x 384 fRANGE x 384 From Table 6, PDT = 80 corresponds to a value of PDT, the 7-bit word in temporary register R1 of 1010000. = 16 ⇒m=4 From Table 4, m = 4 corresponds to a 3-bit FRS word of 100 in temporary register R0. 3. Setting the pulse delay time Calculate the of PDY that will give the required pulse (63value - PDY) delay time: fCARR x 512 Control Register Programming Example The control register would normally be updated many times while the motor is running, but just one example is given here. It is assumed that the Initialisation Register has already been programmed with the parameters given in the previous example. A power waveform of 100Hz is required with a PWM waveform amplitude of 80% of that stored in the ROM across all three phases. The phase sequence should be set to give forward motor rotation. The outputs should be enabled. tpdy = 1. Setting the power frequency ⇒ PDY = 63 – (tpdy x fCARR x 512) The power frequency, fPOWER, can be selected to 16-bit accuracy (i.e 65536 equal steps) from 0Hz to fRANGE as defined in the Initialisation Register. In this case, with fRANGE = 250Hz, the power fRANGE frequency can be adjusted in increments of 0·0038Hz. 65536 ⇒ 63 – ((5 x 10–6) x (6 x 103) x 512) = 47.64 fPOWER = However, the value of PDY must be an integer. As the purpose of the pulse delay is to prevent ‘shoot-through’ (where both top and bottom arms of the inverter are on simultaneously), it is sensible to round the pulse delay time up to a higher, rather than a lower figure. Thus, assigning the value 47 to PDY gives a delay time of 5·2µs. From Table 5, PDY = 47 corresponds to a 6-bit PDY word of 101111 in temporary register R2. 4. Setting the pulse deletion time In setting pulse deletion time (i.e., the minimum pulse width) account must be taken of the pulse delay time, as the actual minimum pulse width seen at the PWM outputs is equal to tpd –tpdy. Therefore, the value of the pulse deletion time must, in this instance, be set 5.2µs longer than the minimum pulse length required. Minimum pulse length required = 10µs ... tpd 127 to be- PDT set to 10µs + 5.2µs = 15.2µs Now, fCARR x 512 tpd = ⇒ PDT = 127 – (tpd x fCARR x 512) ⇒ PFS = PFS fPOWER xx65536 100 x 65536 fRANGE 250 = = 26214.4 PFS must be an integer, so assigning a value of 26214 gives fPOWER = 99.998 Hz.The 16-bit binary equivalent of this value 8051 SA4828 AD0-7 AD0-7 VDD RS MUX CS DECODE CS ALE ALE RD WR RD WR 6805 SA4828 AD0-7 AD0-7 VDD RS MUX ⇒ 127 – ((15.2 x 10–6) x (6 x 103) x 512) = 80.30 Again, PDT must be an integer and so must be either rounded up or down – the choice of which will depend on the application. Choosing in this case the value 80 for PDT, gives a value of tpd of 15.3µs. CS DECODE CS AS ALE DS RD R/W WR Fig.11 Connection details for industry standard multiplexed architecture 13/18 SA4828 gives a PFS word of 0110011001100110 in temporary registers R0 and R1. 2. Setting the powerA waveform amplitude RESET (SOFTWARE OR HARDWARE) 255 APOWER (%) = x 255x 10080 x 255 APOWER 100 ⇒A= 100 = SET UP TEMP REGS 0-5 WITH INIT DATA = 204 The 8-bit binary equivalent of this value gives a RAMP word of 11001100 in temporary register R3. YAMP and BAMP contents are don’t care. WRITE TO TEMP REG R14 TO TRANSFER 3. Setting forward/reverse, output inhibit etc. Forward motor control is required (i.e., the phase sequence of the PWM outputs should be red-yellow-blue) therefore forward/reverse bit, F/R = 0. Output inhibit should be disabled (i e., the outputs should be active), therefore output inhibit bit, INH = 1. Watchdog Timer is disabled so WTE = 0, RST bit = 0 and CR bit = 1. Hence Temporary Register R2 should be set to 00000110. SET UP TEMP REGS 0-5 WITH CNTRL DATA WRITE TO TEMP REG R15 TO TRANSFER APPLICATIONS INFORMATION Microprocessor Interfacing (i) Multiplexed data buses SET UP TEMP REGS 0-5 WITH CONTRL DATA CR = 1,INH = 1 Fig. 11 shows the connection details when interfacing industry standard microprocessors to the SA4828. The 8051 and 6805 series are given as examples. Since the address is written into the SA4828 during each write cycle, this mode of operation is the simplest in terms of the required software. Fig. 12 shows a typical programming example when using multiplexed data buses. WRITE TO TEMP REG R15 TO TRANSFER (ii) Non-multiplexed data buses Fig. 13 shows the connection scheme for some industry standard microprocessors with non-multiplexed data busses. The 6802, 68000 and TMS320 series are given as examples. Before each successive write operation with non-multiplexed data busses, it is essential that the address is specified using an extra write operation. Therefore, a write to a specific Temporary Register actually consists of two write cycles - the first defines the address and the second defines the data. To differentiate between them, the Register Select (RS) pin is used. This should be low for the first (address) cycle and high for the second (data) cycle. As shown in Fig. 13, this pin is usually tied to the least significant microprocessor address line. Fig. 14 shows the flow diagram for each successive write operation to a Temporary Register. (iii) Using microcontroller port pins to emulate a data bus Since the SA4828 is implemented in static logic, the bus timings have no maximum values. This allows the use of microcontrollers where port pins are used to emulate the function of a databus. In order to minimise the number of port pins used, it is clearly better to emulate a multiplexed data bus. The control lines may be minimised as follows: If there are no other peripherals connected to the ‘bus’ then CS may be tied to VSS. Emulating the RD/WR control structure 14/18 N Y UPDATE Fig.12 SA4828 programming example means that the RD pin would be permanently high. It may therefore be tied to VDD. RS is not relevant to multiplexed mode, so this pin may be tied to VDD. MUX should also be tied to VDD. Therefore, the necessary control may be achieved using just two signals - WR and ALE, giving ten port pins in total i.e. 8 address/data and 2 control. Fig. 15 shows this for a generic microcontroller and Fig. 16 shows a flow diagram for a single write cycle. Circuit and Layout Considerations The SET TRIP input forms a fast means of shutting down the inverter bridge by circumventing the latency associated with a microprocessor interrupt. It is recommended that the TRIP output is also linked to a microprocessor interrupt pin in order that the microprocessor is made aware of an incoming trip. It may then perform the necessary housekeeping following the inverter shut down. Although the SET TRIP input has a debounce circuit built in, SA4828 6802 SA4828 VDD PORT 9 = LOW PORT 10 = HIGH AD0-7 D0-7 ALE CS DECODE A0 CS E RS RD R/W WR OUTPUT ADDRESS ON PORTS 1-8 MUX VSS TOGGLE PORT 9 HIGH FOR ≥ 1µs 68000 SA4828 VDD OUTPUT DATA ON PORTS 1-8 AD0-7 D0-7 ALE CS DECODE CS A0 RS LDS RD WR R/W TMS320 MUX TOGGLE PORT 10 LOW FOR ≥ 1µs VSS SA4828 VDD AD0-7 D0-7 RD ALE CS DECODE CS A0 RS WE WR MUX VSS Fig.13 Connection details for industry-standard non-multiplexed architectures WRITE ADDRESS WITH RS=0 Fig.16 Flow diagram - interfacing SA4828 to microcontroller compromised. It is therefore important to eliminate any possible sources of noise from the SET TRIP input. It may be advantageous to place decoupling capacitors close to the SET TRIP pin if nuisance trips are of concern. The clock input (CLK) has a high impedance CMOS input and therefore presents very little load. However, when driving this pin from an unbuffered microprocessor crystal, the tracking capacitance may cause the oscillator to stop. It is therefore recommended that a CMOS Schmitt buffer is placed between the crystal and the CLK input of the SA4828 which is physically located as close to the crystal as possible. The six PWM outputs each have a ±12mA drive capability, enabling them to directly drive optocouplers for isolation purposes. Small pulse transformers may also be driven directly, provided that due consideration is given to back emf generated at turn-off. In addition, the TRIP pin has a ±12mA drive capability to enable it to drive a status LED directly. Fig. 17 shows a typical application of the SA4828 to a three phase variable speed motor drive. QUICK REFERENCE GUIDE TO ENHANCEMENTS The following list gives a brief outline of the differences between the SA4828 and the SA828 series:- WRITE DATA WITH RS=1 Fig.14 Flow diagram for non-multiplexed write operation MICROCONTROLLER SA4828 VDD PORTS 1-8 AD0-7 RS RD PORT 9 PORT 10 ALE WR MUX CS VSS Fig.15 Connection details for microcontroller interface to SA4828 ● Microprocessor interface re-designed for compatibility with more micros. ● Register memory map changed to accommodate more registers. ● Frequency resolution extended to 16-bits. ● Optional independent control of amplitude for each phase. ● Software reset provision. ● Device powers up with the inhibit bit (INH) active to force PWM outputs off. ● ZPPY and ZPPB outputs deleted. ● WSS output re-defined. ● Watchdog Timer added. ● Triplen and Deadbanded Triplen waveforms added. ● All waveform options are user selectable. ● All phase bottom outputs pulse high on deassertion of INH to charge boot-strap drive capacitors. 15/18 SA4828 INVERTER – RECTIFIER AND SMOOTHING R Y 3-PHASE AC INDUCTION MOTOR DC LINK B SINGLE OR 3-PHASE POWER SUPPLY 3-PHASE VARIABLE VOLTAGE, VARIABLE FREQUENCY WAVEFORM + 6 ISOLATOR TTL LEVEL PWM WAVEFORMS 6 FAST SHUTDOWN SA4828 DATA/ADDRESS BUS (AD0-AD7) 8 MICROPROCESSOR OR MICROCONTROLLER WITH ON-CHIP ROM AND RAM Fig.17 A typical SA4828 application 16/18 OPTIONAL EXTERNAL RAM OPTIONAL EXTERNAL ROM SA4828 Package Details Dimensions are shown in : mm (in). For further package information, please contact your local representative or nearest Customer Service Centre. 0-8° 28 10·00/10·64 7·40/7·60 (0·291/0·299) (0·394/0·419) SPOT REF. CHAMFER REF. 0·25/0·71 (0·010/0·028) ¥45° 0·41/1·27 (0·016/0·050) 1 0·36/0·48 (0·014/0·019) 0·23/0·33 (0·009/0·013) 2·36/2·64 (0·093/0·104) 0·74 (0·029) MAX. 28 LEADS AT 1·27 (0·050) NOM. SPACING NOTES 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your Customer Service Centre for further information. 0·10/0·30 (0·004/0·012) 17·70/18·10 (0·697/0·713) 28-LEAD MINIATURE PLASTIC DIL - MP28 1 PIN 1 REF NOTCH 14·73 (0·58) MAX 15.24 (0·6) NOM CTRS 28 1·14/1·65 (0·045/0·065) 0·23/0·41 (0·009/0·016) 38·10 (1·5) MAX 3·05 (0·120) MIN 0·51 (0·02) MIN 5·08/(0·200) MAX SEATING PLANE 0·38/0·61 (0·015/0·024) NOTES 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your Customer Service Centre for further information. 28 LEADS AT 2·54 (0·10) NOM. SPACING 28-LEAD PLASTIC DIL – DP28 17/18 SA4828 http://www.dynexsemi.com e-mail: [email protected] HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: 00-44-(0)1522-500500 Fax: 00-44-(0)1522-500550 DYNEX POWER INC. Unit 7 - 58 Antares Drive, Nepean, Ontario, Canada K2E 7W6. Tel: 613.723.7035 Fax: 613.723.1518 Toll Free: 1.888.33.DYNEX (39639) CUSTOMER SERVICE CENTRES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 North America Tel: 011-800-5554-5554. Fax: 011-800-5444-5444 UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 SALES OFFICES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 Germany Tel: 07351 827723 North America Tel: (613) 723-7035. Fax: (613) 723-1518. Toll Free: 1.888.33.DYNEX (39639) / Tel: (831) 440-1988. Fax: (831) 440-1989 / Tel: (949) 733-3005. Fax: (949) 733-2986. UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. © Dynex Semiconductor 2000 Publication No. DS4204-4 Issue No. 4.0 January 2000 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand. No Annotation: The product parameters are fixed and the product is available to datasheet specification. This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. 18/18