ETC VS1011B

VS1011 B
VS1011b
VS1011b - MP3 AUDIO CODEC
Features
Description
• Decodes MPEG 1 & 2 audio layer 3 (ISO
11172-3), WAV and PCM files
• Supports VBR (variable bitrate) for MP3
• Stream support
• Can be used as a slave co-processor
• Operates with single clock 12.288..14 MHz
or 24.576..28 MHz.
• Low-power operation
• High-quality stereo DAC with no phase error between channels
• Stereo earphone driver capable of driving a
30Ω load
• Separate 2.5 .. 3.6V operating voltages for
analog and digital
• 5.5 KiB On-chip RAM for user code / data
• Serial control and data interfaces
• New functions may be added with software
and 4 GPIO pins
GPIO
VS1011
GPIO
VS1011b is a single-chip MP3 audio decoder. The
chip contains a high-performance, low-power DSP
processor core VS DSP4 , working memory, 5 KiB
instruction RAM and 0.5 KiB data RAM for user
applications, serial control and input data interfaces, 4 general purpose I/O pins, as well as a
high-quality variable-sample-rate stereo DAC, followed by an earphone amplifier and a ground buffer.
VS1011b receives its input bitstream through a
serial input bus, which it listens to as a system
slave. The input stream is decoded and passed
through a digital volume control to an 18-bit oversampling, multi-bit, sigma-delta DAC. The decoding is controlled via a serial control bus. In addition to the basic decoding, it is possible to add
application specific features, like DSP effects, to
the user RAM memory.
Stereo
DAC
4
Stereo Ear−
phone Driver
audio
L
R
output
X ROM
DREQ
SO
SI
SCLK
XCS
4
Serial
Data/
Control
Interface
X RAM
VSDSP
Y ROM
XDCS
Y RAM
Instruction
RAM
Version 1.01,
2004-11-19
Instruction
ROM
1
VLSI
VS1011b
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Solution
VS1011 B
CONTENTS
Contents
1
License
8
2
Disclaimer
8
3
Definitions
8
4
Characteristics & Specifications
9
4.1
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4.2
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
4.3
DAC Interpolation Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
10
4.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
4.5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
4.6
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
4.7
Switching Characteristics - Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
4.8
Switching Characteristics - DREQ Signal . . . . . . . . . . . . . . . . . . . . . . . . .
12
4.9
Switching Characteristics - SPI Interface Output . . . . . . . . . . . . . . . . . . . . . .
12
4.10 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . .
12
Packages and Pin Descriptions
13
5.1
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
5.1.1
LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
5.1.2
BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
5.1.3
SOIC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
5.2.1
15
5
5.2
Version 1.01,
LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . .
2004-11-19
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VS1011b
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Solution
5.2.2
VS1011 B
CONTENTS
SOIC-28 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
6
Connection Diagram, LQFP-48
17
7
SPI Buses
18
7.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
7.2
SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
7.2.1
VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . . . . .
18
7.2.2
VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . .
19
7.3.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7.3.2
SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . .
19
7.3.3
SDI in VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . .
19
7.3.4
SDI and DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . .
20
7.4.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
7.4.2
SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
7.4.3
SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
7.5
SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
7.6
SPI Examples with SM SDINEW and SM SDISHARED set . . . . . . . . . . . . . . .
23
7.6.1
Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
7.6.2
Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
7.6.3
SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . . . . . .
23
7.3
7.4
8
Functional Description
24
8.1
24
Version 1.01,
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2004-11-19
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VS1011b
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Solution
8.2
CONTENTS
Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
8.2.1
Supported MP3 (MPEG layer 3) Formats . . . . . . . . . . . . . . . . . . . . .
24
8.2.2
Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
8.3
Data Flow of VS1011b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
8.4
Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
8.5
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
8.6
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
8.6.1
SCI MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
8.6.2
SCI STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
8.6.3
SCI BASS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
8.6.4
SCI CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
8.6.5
SCI DECODE TIME (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
8.6.6
SCI AUDATA (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
8.6.7
SCI WRAM (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
8.6.8
SCI WRAMADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
8.6.9
SCI HDAT0 and SCI HDAT1 (R) . . . . . . . . . . . . . . . . . . . . . . . . .
31
8.6.10 SCI AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
8.6.11 SCI VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
8.6.12 SCI AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
Stereo Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
8.7
9
VS1011 B
Operation
34
9.1
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
9.2
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
9.3
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
Version 1.01,
2004-11-19
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VLSI
Solution
VS1011b
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VS1011 B
CONTENTS
9.4
Play/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
9.5
Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
9.6
SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
9.6.1
Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
9.6.2
Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
9.6.3
Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
9.6.4
Erk Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
9.6.5
SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
10 VS1011b Registers
37
10.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
10.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
10.3 VS1011b Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
10.4 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
10.5 Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
10.6 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
10.7 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
10.8 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
10.9 System Vector Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
10.9.1 AudioInt, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
10.9.2 SciInt, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
10.9.3 DataInt, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
10.9.4 UserCodec, 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
10.10System Vector Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
10.10.1 WriteIRam(), 0x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Version 1.01,
2004-11-19
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Solution
VS1011b
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VS1011 B
CONTENTS
10.10.2 ReadIRam(), 0x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
10.10.3 DataBytes(), 0x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
10.10.4 GetDataByte(), 0x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
10.10.5 GetDataWords(), 0xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
11 Document Version Changes
44
11.1 Version 1.01 for VS1011b, 2004-11-19 . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
11.2 Version 1.00 for VS1011b, 2004-10-22 . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
11.3 Version 0.71 for VS1011, 2004-07-20 . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
11.4 Version 0.70 for VS1011, 2004-05-13 . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
11.5 Version 0.62 for VS1011, 2004-03-24 . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
11.6 Version 0.61 for VS1011, 2004-03-11 . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
11.7 Version 0.6 for VS1011, 2004-02-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
12 Contact Information
Version 1.01,
2004-11-19
45
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VLSI
Solution
VS1011b
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VS1011 B
LIST OF FIGURES
List of Figures
1
Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2
Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
3
Pin Configuration, SOIC-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
4
Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . . . .
17
5
BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
6
BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7
SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
8
SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
9
SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
10
Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
11
Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
12
Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . . . .
23
13
Data Flow of VS1011b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
14
User’s Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Version 1.01,
2004-11-19
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VLSI
VS1011b
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Solution
1
VS1011 B
1. LICENSE
License
MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson.
2
Disclaimer
All properties and figures are subject to change.
3
Definitions
ASIC Application Specific Integrated Circuit.
B Byte, 8 bits.
b Bit.
IC Integrated Circuit.
Ki “Kibi” = 210 = 1024 (IEC 60027-2).
Mi “Mebi” = 220 = 1048576 (IEC 60027-2).
VS DSP VLSI Solution’s DSP core.
W Word. In VS DSP, instruction words are 32-bit and data words are 16-bit wide.
Version 1.01,
2004-11-19
8
VLSI
VS1011 B
VS1011b4. CHARACTERISTICS & SPECIFICATIONS
y
Solution
4
Characteristics & Specifications
Unless otherwise noted: AVDD=2.7..3.6V, DVDD=2.3..3.6V, TA=-30..+85◦ C, XTALI=26.000MHz, FullScale Output Sinewave at 1.526 kHz, measurement bandwidth 20..20000 Hz, analog output load 30Ω
with ground buffer, bitstream 128 kbit/s, local components as shown in Figure 4.
Note, that some analog values are in practice better than in these tables if chips are used within a limited
temperature range and not too close to lower voltage limits.
4.1 Analog Characteristics
Parameter
DAC Resolution
Total Harmonic Distortion
Dynamic Range (DAC unmuted, A-weighted)
S/N Ratio (full scale signal)
Interchannel Isolation (Crosstalk)1
Interchannel Isolation (Crosstalk)2
Interchannel Isolation (Crosstalk)3
Interchannel Gain Mismatch
Frequency Response, 20..15000 Hz
Full Scale Output Voltage (Peak-to-peak)
Deviation from Linear Phase
Out of Band Energy
Analog Output Load Resistance
Analog Output Load Capacitance6
Symbol
THD
IDR
SNR
Min
70
-0.5
-0.2
1.4
AOLR
Typ
16
0.1
88
81
41
90
70
1.64
Max
0.2
0.5
0.2
2.1
5
-90
305
10
Unit
bits
%
dB
dB
dB
dB
dB
dB
dB
Vpp
◦
dB
Ω
pF
1
Ground buffer, 30Ω load
Ground buffer, no load
3 AC coupled towards ground, 30Ω load
4 Double voltage can be achieved with +-to-+ wiring for mono difference sound.
5 AOLR may be much lower, but below Typical distortion performance may be compromised.
6 Use small series resistor if load is capacitive.
2
Version 1.01,
2004-11-19
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VS1011 B
VS1011b4. CHARACTERISTICS & SPECIFICATIONS
y
Solution
4.2
Power Consumption
Following table measured with XTALI=12.288MHz, clock doubler on.
Parameter
Power Supply Rejection
Power Supply Consumption AVDD, Reset
Power Supply Consumption AVDD, no load, no signal
Power Supply Consumption AVDD, o. @ 30Ω.
Power Supply Consumption DVDD, Reset
Power Supply Consumption DVDD
4.3
Symbol
Min
Typ
40
1.4
6.2
6.5
6.5
16.0
Max
30.0
8.0
40.0
30.0
Unit
dB
µA
mA
mA
µA
mA
DAC Interpolation Filter Characteristics
Parameter
Passband (to -3dB corner)
Passband (Ripple Spec)
Passband Ripple
Stop Band
Stop Band Rejection
Group Delay
Symbol
Min
0
0
Typ
Max
0.453
0.340
±0.2
0.560Fs
85
15/Fs
Unit
Fs
Fs
dB
Hz
dB
s
Fs is conversion frequency
4.4
Absolute Maximum Ratings
Parameter
Analog Positive Supply
Digital Positive Supply
Current at Any Digital Output
Voltage at Any Digital Input
Operating Temperature
Functional Operating Temperature
Storage Temperature
Version 1.01,
2004-11-19
Symbol
AVDD
DVDD
Min
-0.3
-0.3
DGND-1.0
-30
-40
-65
Max
3.6
3.6
±50
DVDD+1.0
+85
+95
+150
Unit
V
V
mA
V
◦C
◦C
◦C
10
VLSI
VS1011 B
VS1011b4. CHARACTERISTICS & SPECIFICATIONS
y
Solution
4.5
Recommended Operating Conditions
Parameter
Analog and Digital Ground
Positive Analog
Positive Digital
Ambient Operating Temperature
Symbol
AGND DGND
AVDD
DVDD
Min
2.5
2.3
-30
Typ
0.0
2.7
2.5
Max
3.6
3.6
+85
Unit
V
V
V
◦C
The following values are to be used when the clock doubler is active:
Parameter
Input Clock Frequency
Internal Clock Frequency1
1
Symbol
XTALI
CLKI
Min
Typ
12.288
24.576
Max
15
30
Unit
MHz
MHz
The maximum sample rate that may be played with correct speed is CLKI/512.
The following values are to be used when the clock doubler is not active:
Parameter
Input Clock Frequency
Internal Clock Frequency1
1
Symbol
XTALI
CLKI
Min
Typ
24.576
24.576
Max
30
30
Unit
MHz
MHz
The maximum sample rate that may be decoded with correct speed is CLKI/512.
Note: See Application notes for what clock speeds are required to play specific bit rates and sample rates.
4.6
Digital Characteristics
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at IO = -1.0 mA
Low-Level Output Voltage at IO = 1.0 mA
Input Leakage Current
Version 1.01,
2004-11-19
Symbol
Min
0.7DVDD
Typ
Max
0.3DVDD
0.7DVDD
-1.0
0.3DVDD
1.0
Unit
V
V
V
V
µA
11
VLSI
VS1011 B
VS1011b4. CHARACTERISTICS & SPECIFICATIONS
y
Solution
4.7
Switching Characteristics - Clocks
Parameter
Master Clock Frequency 1
Master Clock Frequency 2
Master Clock Duty Cycle
Clock Output 3
Symbol
XTALI
XTALI
Min
40
XTALO
Typ
12.288
24.576
50
XTALI
Max
60
Unit
MHz
MHz
%
MHz
1
Clock doubler active.
Clock doubler not active.
3 Do not load XTALO by connecting other devices to it.
2
4.8
Switching Characteristics - DREQ Signal
Parameter
Data Request Signal
4.9
Symbol
DREQ
Min
Typ
Max
200
Unit
ns
Switching Characteristics - SPI Interface Output
Parameter
SPI Input Clock Frequency
Rise time for SO
Symbol
Min
Typ
Max
CLKI
6
25
Unit
MHz
ns
Note: Maximum load for SO is 100 pF.
4.10
Switching Characteristics - Boot Initialization
Parameter
RESET active time
Power-up to software ready
RESET inactive to software ready
Version 1.01,
2004-11-19
Symbol
Min
2
Max
2 ms + 30000 XTALI
30000
Unit
XTALI
XTALI
12
VLSI
VS1011b
y
Solution
5
VS1011 B
5. PACKAGES AND PIN DESCRIPTIONS
Packages and Pin Descriptions
5.1
5.1.1
Packages
LQFP-48
48
1
Figure 1: Pin Configuration, LQFP-48.
LQFP-48 package dimensions are at http://www.vlsi.fi/vs1001/lqfp48.pdf .
5.1.2
BGA-49
A1 BALL PAD CORNER
1
2
4
3
5
6
7
A
D
7.00
0.80 TYP
C
4.80
B
E
F
G
0.80 TYP
4.80
1.10 REF
1.10 REF
7.00
TOP VIEW
Figure 2: Pin Configuration, BGA-49.
BGA-49 package dimensions are at http://www.vlsi.fi/vs1001/bga49.pdf
Version 1.01,
2004-11-19
13
VLSI
Solution
VS1011b
y
5.1.3
VS1011 B
5. PACKAGES AND PIN DESCRIPTIONS
SOIC-28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
9
10
11
12
13
14
SOIC − 28
1
2
3
4
5
6
7
8
Figure 3: Pin Configuration, SOIC-28.
SOIC-28 package dimensions are at http://www.vlsi.fi/vs1001/soic28.pdf .
Version 1.01,
2004-11-19
14
VLSI
VS1011b
y
Solution
5.2
5.2.1
5. PACKAGES AND PIN DESCRIPTIONS
Pin Descriptions
LQFP-48 and BGA-49 Pin Descriptions
Pin Name
XRESET
DGND0
DVDD0
DREQ
GPIO22 / DCLK1
GPIO32 / SDATA1
XDCS / BSYNC1
DVDD1
DGND1
XTALO
XTALI
DVDD2
DGND2
DGND3
DGND4
XCS
SCLK
SI
SO
TEST
GPIO02
GPIO12
AGND0
AVDD0
RIGHT
AGND1
AGND2
GBUF
AVDD1
RCAP
AVDD2
LEFT
AGND3
1
2
VS1011 B
LQFP48 Pin
3
4
6
8
9
10
13
14
16
17
18
19
20
21
22
23
28
29
30
32
33
34
37
38
39
40
41
42
43
44
45
46
47
BGA49
Ball
B1
D2
D3
E2
E1
F2
E3
F3
F4
G3
E4
G4
F5
G5
F6
G6
D6
E7
D5
C6
C7
B6
C5
B5
A6
B4
A5
C4
A4
B3
A3
B2
A2
Pin
Type
DI
PWR
PWR
DO
DI
DI
DI
PWR
PWR
AO
AI
PWR
PWR
PWR
PWR
DI
DI
DI
DO3
DI
DIO
DIO
PWR
PWR
AO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
Function
active low asynchronous reset
digital ground
digital power supply
data request, input bus
general purpose IO 2 / serial input data bus clock
general purpose IO 3 / serial data input
data chip select / byte sync, connect to DVDD if not used
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground (in BGA-49, DGND2, 3, 4 conn. together)
digital ground
digital ground
chip select input (active low)
clock for serial bus
serial input
serial output
reserved for test, connect to DVDD
general purpose IO 0, use 100 kΩ pull-down resistor
general purpose IO 1
analog ground, low-noise reference
analog power supply
right channel output
analog ground
analog ground
ground buffer
analog power supply
filtering capacitance for reference
analog power supply
left channel output
analog ground
First pin function is active in New Mode, latter in Compatibility Mode.
If not used, use 100 kΩ pull-down resistor.
Pin types:
Type
DI
DO
DIO
DO3
Description
Digital input, CMOS Input Pad
Digital output, CMOS Input Pad
Digital input/output
Digital output, CMOS Tri-stated Output Pad
Type
AI
AO
AIO
PWR
Description
Analog input
Analog output
Analog input/output
Power supply pin
In BGA-49, no-connect balls are A1, A7, B7, C1, C2, C3, D1, D4, D7, E5, E6, F1, F7, G1, G2, G7.
In LQFP-48, no-connect pins are 1, 2, 5, 7, 11, 12, 15, 24, 25, 26, 27, 31, 35, 36, 48.
Version 1.01,
2004-11-19
15
VLSI
VS1011b
y
Solution
5.2.2
1
2
VS1011 B
5. PACKAGES AND PIN DESCRIPTIONS
SOIC-28 Pin Descriptions
Pin Name
Pin
DREQ
GPIO22 / DCLK1
GPIO32 / SDATA1
XDCS / BSYNC1
DVDD1
DGND1
XTALO
XTALI
DVDD2
DGND2
XCS
SCLK
SI
SO
TEST
GPIO02
GPIO12
AGND0
AVDD0
RIGHT
AGND2
RCAP
AVDD2
LEFT
AGND3
XRESET
DGND0
DVDD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin
Type
DO
DIO
DI
DI
PWR
PWR
CLK
CLK
PWR
PWR
DI
DI
DI
DO3
DI
DIO
DIO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
DI
PWR
PWR
Function
data request, input bus
serial input data bus clock
serial data input
byte synchronization signal
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground
chip select input (active low)
clock for serial bus
serial input
serial output
reserved for test, connect to DVDD
reserved for test, do not connect!
reserved for test, do not connect!
analog ground
analog power supply
right channel output
analog ground
filtering capacitance for reference
analog power supply
left channel output
analog ground
active low asynchronous reset
digital ground
digital power supply
First pin function is active in New Mode, latter in Compatibility Mode.
If not used, use 100 kΩ pull-down resistor.
Pin types:
Type
DI
DO
DIO
DO3
Version 1.01,
Description
Digital input, CMOS Input Pad
Digital output, CMOS Input Pad
Digital input/output
Digital output, CMOS Tri-stated Output Pad
2004-11-19
Type
AI
AO
AIO
PWR
Description
Analog input
Analog output
Analog input/output
Power supply pin
16
VLSI
VS1011b
y
Solution
6
VS1011 B
6. CONNECTION DIAGRAM, LQFP-48
Connection Diagram, LQFP-48
Figure 4: Typical Connection Diagram Using LQFP-48.
The ground buffer GBUF can be used for common voltage (1.25 V) for earphones. This will eliminate
the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1011b may
be connected directly to the earphone connector.
If GBUF is not used, LEFT and RIGHT must be provided with 100 µF capacitors.
Note: This connection assumes SM SDINEW is active (see Chapter 8.6.1). If also SM SDISHARE is
used, xDCS doesn’t need to be connected (see Chapter 7.2.1).
Version 1.01,
2004-11-19
17
VLSI
VS1011b
y
Solution
7
VS1011 B
7. SPI BUSES
SPI Buses
7.1
General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1011b’s
Serial Data Interface SDI (Chapters 7.3 and 8.4) and Serial Control Interface SCI (Chapters 7.4 and 8.5).
7.2
SPI Bus Pin Descriptions
7.2.1
VS1002 Native Modes (New Mode)
These modes are active on VS1011b when SM SDINEW is set to 1. DCLK, SDATA and BSYNC are
replaced with GPIO2, GPIO3 and XDCS, respectively.
SDI Pin
XDCS
SCI Pin
XCS
SCK
SI
-
7.2.2
SO
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. If SM SDISHARE is 1, pin
XDCS is not used, but the signal is generated internally by inverting
XCS.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. If a chip select is active, SI is sampled on the rising CLK edge.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
VS1001 Compatibility Mode
This mode is active when SM SDINEW is 0 (default). In this mode, DCLK, SDATA and BSYNC are
active.
SDI Pin
-
SCI Pin
XCS
DCLK
SCK
SDATA
-
SI
SO
Version 1.01,
2004-11-19
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. There is no chip select for SDI, which
is always active.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
18
VLSI
VS1011b
y
Solution
7.3
7.3.1
VS1011 B
7. SPI BUSES
Serial Protocol for Serial Data Interface (SDI)
General
The serial data interface operates in slave mode so the DCLK signal must be generated by an external
circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.6).
VS1011b assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or
LSb first, depending of contents of SCI MODE (Chapter 8.6).
7.3.2
SDI in VS1002 Native Modes (New Mode)
In VS1002 native modes (which are available also in VS1011b), byte synchronization is achieved by
XDCS (or XCS if SM SDISHARE is 1). The state of XDCS (or XCS) may not change while a data
byte transfer is in progress. To always maintain data synchronization even if there may be glitches in
the boards using VS1011b, it is recommended to turn XDCS (or XCS) every now and then, for instance
once after every flash data block or a few kilobytes, just to keep sure the host and VS1011b are in sync.
For new designs, using VS1002 native modes are recommended, as they are easier to implement than
BSYNC generation.
7.3.3
SDI in VS1001 Compatibility Mode
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 5: BSYNC Signal - one byte transfer.
When VS1011b is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure
correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending
on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first
order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiver
stays active and next 8 bits are also received.
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 6: BSYNC Signal - two byte transfer.
Version 1.01,
2004-11-19
19
VLSI
VS1011b
y
Solution
VS1011 B
7. SPI BUSES
Using VS1001 compatibility mode in new designs is strongly discouraged.
7.3.4
SDI and DREQ
The DREQ signal of the data interface is used in slave mode to signal if VS1011b’s FIFO is capable of
receiving more input data. If DREQ is high, VS1011b can take at least 32 bytes of data. When there is
less than 32 bytes of free space, DREQ is turned low, and the sender should stop transferring new data.
Because of the 32-byte safety area, the sender may send upto 32 bytes of data at a time without checking
the status of DREQ, making controlling VS1011b easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It should not abort a byte transmission that has
already started.
7.4
7.4.1
Serial Protocol for Serial Command Interface (SCI)
General
The serial bus protocol for the Serial Command Interface SCI (Chapter 8.5) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes are
always send MSb firrst.
The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.
See table below.
Name
READ
WRITE
Instruction
Opcode
Operation
0000 0011 Read data
0000 0010 Write data
Note: After sending an SCI command, it is not allowed to send SCI or SDI data for 5 microseconds.
Version 1.01,
2004-11-19
20
VLSI
Solution
VS1011b
y
7.4.2
VS1011 B
7. SPI BUSES
SCI Read
VS1011b registers are read by the following sequence, as shown in Figure 7. First, XCS line is pulled
SI line followed by an 8-bit word address. After the address has been read in, any further data on SI is
ignored. The 16-bit data corresponding to the received address will be shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
0
0
0
0
0
0
1
1
0
0
0
30 31
SCK
3
SI
instruction (read)
2
1
0
don’t care
0
data out
address
15 14
SO
0
0
0
0
0
0
0
0
0
0
0
0
0
don’t care
0
0
1
0
0
X
Figure 7: SCI Word Read
7.4.3
SCI Write
VS1011b registers are written to using the following sequence, as shown in Figure 8. First, XCS line is
pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed by
an 8-bit word address.
After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the
WRITE sequence.
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
0
0
0
0
0
0
1
0
0
0
0
30 31
SCK
3
SI
instruction (write)
SO
0
0
0
0
0
0
2
1
0
15 14
0
0
0
0
0
0
X
data out
address
0
1
0
0
0
0
0
0
0
0
0 X
Figure 8: SCI Word Write
Version 1.01,
2004-11-19
21
VLSI
VS1011b
y
Solution
7.5
VS1011 B
7. SPI BUSES
SPI Timing Diagram
tWL
tXCSS
tWH
tXCSH
XCS
0
1
14
15
30
16
31
tXCS
SCK
SI
tH
tSU
SO
tZ
tV
tDIS
Figure 9: SPI Timing Diagram.
Symbol
tXCSS
tSU
tH
tZ
tWL
tWH
tV
tXCSH
tXCS
tDIS
1
Min
5
-26
2
0
2
2
Max
2 (+ 25ns1 )
-26
2
10
Unit
ns
ns
XTALI cycles
ns
XTALI cycles
XTALI cycles
XTALI cycles
ns
XTALI cycles
ns
25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can easily be used is 1/6 of VS1011b’s external clock speed XTALI. Slightly higher speed can
be achieved with very careful timing tuning. For details, see Application Notes for VS10XX.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
Version 1.01,
2004-11-19
22
VLSI
VS1011b
y
Solution
7.6
7.6.1
VS1011 B
7. SPI BUSES
SPI Examples with SM SDINEW and SM SDISHARED set
Two SCI Writes
SCI Write 1
SCI Write 2
XCS
0
1
2
3
30
31
1
0
32
33
61
62
63
2
1
0
SCK
SI
0
0
0
0
0
X
0
X
Figure 10: Two SCI Operations.
Figure 10 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between
the writes.
7.6.2
Two SDI Bytes
SDI Byte 1
SDI Byte 2
XCS
0
1
2
3
7
6
5
4
6
7
8
9
1
0
7
6
13
14
15
2
1
0
SCK
3
5
SI
X
Figure 11: Two SDI Bytes.
SDI data is synchronized with a raising edge of xCS as shown in Figure 11. However, every byte doesn’t
need separate synchronization.
7.6.3
SCI Operation in Middle of Two SDI Bytes
SDI Byte
SDI Byte
SCI Operation
XCS
0
1
7
6
6
7
8
9
38
39
40
41
1
0
7
6
46
47
1
0
SCK
SI
5
1
0
0
0
5
X
Figure 12: Two SDI Bytes Separated By an SCI Operation.
Figure 12 shows how an SCI operation is embedded in between SDI operations. The changes in xCS are
used to synchronize both SDI and SCI.
Version 1.01,
2004-11-19
23
VLSI
VS1011b
y
Solution
8
VS1011 B
8. FUNCTIONAL DESCRIPTION
Functional Description
8.1
Main Features
VS1011b is based on a proprietary digital signal processor, VS DSP. It contains all the code and data
memory needed for MPEG and WAV PCM audio decoding, together with serial interfaces, a multirate
stereo audio DAC and analog output amplifiers and filters.
VS1011b can play all MPEG 1 and 2 layer III files, with all sample rates and bitrates, including variable
bitrate (VBR).
8.2 Supported Audio Codecs
Mark
+
-
8.2.1
Conventions
Description
Format is supported
Format exists but is not supported
Format doesn’t exist
Supported MP3 (MPEG layer 3) Formats
MPEG 1.01 :
Samplerate / Hz
48000
44100
32000
32
+
+
+
40
+
+
+
48
+
+
+
56
+
+
+
64
+
+
+
80
+
+
+
Bitrate / kbit/s
96
112 128
+
+
+
+
+
+
+
+
+
160
+
+
+
192
+
+
+
224
+
+
+
256
+3
+
+
320
+3
+3
+
8
+
+
+
16
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
48
+
+
+
Bitrate / kbit/s
56
64
80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
8
+
+
+
16
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
48
+
+
+
Bitrate / kbit/s
56
64
80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
MPEG 2.01 :
Samplerate / Hz
24000
22050
16000
MPEG 2.51 2 :
Samplerate / Hz
12000
11025
8000
1
Also all variable bitrate (VBR) formats are supported.
Incompatibilities may occur because MPEG 2.5 is not a standard format.
3 Nominal CLKI=24.576 MHz may be too little for glitchless playback.
2
Version 1.01,
2004-11-19
24
VLSI
VS1011b
y
Solution
8.2.2
VS1011 B
8. FUNCTIONAL DESCRIPTION
Supported RIFF WAV Formats
The most common RIFF WAV subformats are supported.
Format
0x01
0x02
0x03
0x06
0x07
0x10
0x11
0x15
0x16
0x30
0x31
0x3b
0x3c
0x40
0x41
0x50
0x55
0x64
0x65
8.3
Name
PCM
ADPCM
IEEE FLOAT
ALAW
MULAW
OKI ADPCM
IMA ADPCM
DIGISTD
DIGIFIX
DOLBY AC2
GSM610
ROCKWELL ADPCM
ROCKWELL DIGITALK
G721 ADPCM
G728 CELP
MPEG
MPEGLAYER3
G726 ADPCM
G722 ADPCM
Supported
+
+
-
Comments
16 and 8 bits, any sample rate ≤ 48kHz
For supported MP3 modes, see Chapter 8.2.1
Data Flow of VS1011b
SCI_BASS = 0
SDI
Bitstream
FIFO
16384 bits
MP3/WAV
decoding
Bass
enhancer
SCI_BASS != 0
A1ADDR = 0
User
application
A1ADDR != 0
Volume
control
SCI_VOL
Audio
FIFO
L
S.rate.conv.
and DAC R
512 stereo
samples
Figure 13: Data Flow of VS1011b.
First, depending on the audio data, MP3 or PCM WAV data is received and decoded from the SDI bus.
After decoding, data may be sent to the Bass Enhancer depending on SCI BASS.
Then, if SCI AIADDR is non-zero, application code is executed from the address pointed to by that
register. For more details, see Application Notes for VS10XX.
After the optional user application, the signal is fed to the volume control unit, which also copies the
data to the Audio FIFO.
The Audio FIFO holds the data, which is read by the Audio interrupt (Chapter 10.9.1) and fed to the
sample rate converter and DACs. The size of the audio FIFO is 512 stereo (2×16-bit) samples.
The sample rate converter converts all different sample rates to CLKI/512 and feeds the data to the DAC,
which in order creates a stereo in-phase analog signal. This signal is then forwarded to the earphone
amplifier.
Version 1.01,
2004-11-19
25
VLSI
VS1011b
y
Solution
8.4
VS1011 B
8. FUNCTIONAL DESCRIPTION
Serial Data Interface (SDI)
The serial data interface is meant for transferring compressed MP3 audio data as well as WAV PCM data.
Also several different tests may be activated through SDI as described in Chapter 9.
8.5
Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are always 16
bits. VS1011b is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
•
•
•
•
•
8.6
Reg
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
1
control of the operation mode
uploading user programs
access to header data
status information
feeding input data
SCI Registers
Type
rw
rw
rw
rw
r
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
Reset
0
0x1C1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCI registers, prefix SCI , offset 0xC000
Abbrev[bits]
Description
MODE
Mode control.
STATUS
Status of VS1011b.
BASS
Built-in bass enhancer.
CLOCKF
Clock freq + doubler.
DECODE TIME
Decode time in seconds.
AUDATA
Misc. audio data.
WRAM
RAM write.
WRAMADDR
Base address for RAM write.
HDAT0
Stream header data 0.
HDAT1
Stream header data 1.
AIADDR
Start address of application.
VOL
Volume control.
AICTRL0
Application control register 0.
AICTRL1
Application control register 1.
AICTRL2
Application control register 2.
AICTRL3
Application control register 3.
Firmware changes the value of this register immediately to 0x18, and in less than 100 ms to 0x10.
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8.6.1
VS1011 B
8. FUNCTIONAL DESCRIPTION
SCI MODE (RW)
SCI MODE is used to control operation of VS1011b.
Bit
0
Name
SM DIFF
Function
Differential
1
SM SETTOZERO1
Set to zero
2
SM RESET
Soft reset
3
SM OUTOFWAV
Jump out of WAV decoding
4
SM SETTOZERO2
set to zero
5
SM TESTS
Allow SDI tests
6
SM STREAM
Stream mode
7
SM SETTOZERO3
set to zero
8
SM DACT
DCLK active edge
9
SM SDIORD
SDI bit order
10
SM SDISHARE
Share SPI chip select
11
SM SDINEW
VS1002 native SPI modes
12
SM SETTOZERO4
set to zero
13
SM SETTOZERO5
set to zero
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
normal in-phase audio
left channel inverted
right
wrong
no reset
reset
no
yes
right
wrong
not allowed
allowed
no
yes
right
wrong
rising
falling
MSb first
MSb last
no
yes
no
yes
right
wrong
right
wrong
When SM DIFF is set, the player inverts the left channel output. For a stereo input this creates a virtual
surround, and for a mono input this effectively creates a differential left/right signal.
By setting SM RESET to 1, the player is software reset. This bit clears automatically.
When the user decoding a WAV file wants to get out of the file without playing it to the end, set
SM OUTOFWAV, and send zeros to VS1002c until SM OUTOFWAV is again zero. If the user doesn’t
want to check SM OUTOFWAV, send 128 zeros.
If SM TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 9.6.
SM STREAM activates VS1011b’s stream mode. In this mode, data should be sent with as even intervals
as possible (and preferable with data blocks of less than 512 bytes), and VS1011b makes every attempt
to keep its input buffer half full by changing its playback speed upto 5%. For best quality sound, the
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VS1011 B
8. FUNCTIONAL DESCRIPTION
average speed error should be within 0.5%, the bitrate should not exceed 160 kbit/s and VBR should not
be used. For details, see Application Notes for VS10XX.
SM DACT defines the active edge of data clock for SDI. If clear data is read at the rising edge, and if set
data is read at the falling edge.
When SM SDIORD is clear, bytes on SDI are sent as a default MSb first. By setting SM SDIORD, the
user may reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however, still
sent in the default order. This register bit has no effect on the SCI bus.
Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 7.2, if
also SM SDINEW is set.
Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 7.2.1 and 7.3.2.
8.6.2
SCI STATUS (RW)
SCI STATUS contains information on the current status of VS1011b and lets the user shutdown the chip
without audio glitches.
Name
SS VER
SS APDOWN2
SS APDOWN1
SS AVOL
Bits
6..4
3
2
1..0
Description
Version
Analog driver powerdown
Analog internal powerdown
Analog volume control
SS VER is 0 for VS1001, 1 for VS1011, 2 for VS1002 and 3 for vs1003.
SS APDOWN2 controls analog driver powerdown. Normally this bit is controlled by the system firmware.
However, if the user wants to powerdown VS1011b with a minimum power-off transient, turn this bit
to 1, then wait for at least a few milliseconds before activating reset. For more details, see Application
Notes for VS10XX.
SS APDOWN1 controls internal analog powerdown. This bit is meant to be used by the system firmware
only.
SS AVOL is the analog volume control: 0 = -0 dB, 1 = -6 dB, 3 = -12 dB. This register is meant to be
used automatically by the system firmware only.
8.6.3
SCI BASS (RW)
Name
SB AMPLITUDE
SB FREQLIMIT
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Bits
7..4
3..0
Description
Enhancement in 1 dB steps (0..15)
Lower limit frequency in 10 Hz steps (2..15)
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8. FUNCTIONAL DESCRIPTION
The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most out
of the users earphones without causing clipping.
VSBE is activated when SB AMPLITUDE is set to non-zero. SB AMPLITUDE should be set to the
user’s preferences, and SB FREQLIMIT to roughly 1.5 times the lowest frequency the user’s audio
system can reproduce.
Note: Because VSBE tries to avoid clipping, it gives the best bass boost with dynamical music material,
or when the playback volume is not set to maximum.
8.6.4
SCI CLOCKF (RW)
SCI CLOCKF is used to tell if the input clock XTALI is running at something else than 24.576 MHz.
ALI
XTALI is set in 2 kHz steps. Thus, the formula for calculating the correct value for this register is XT
2000
(XTALI is in Hz). Values may be between 0..32767, although hardware limits the highest allowed speed.
Also, with speeds lower than 24.576 MHz all sample rates and bitstream widths are no longer available.
Setting the MSB of SCI CLOCKF to 1 activates internal clock-doubling. A clock of upto 15 MHz may
be doubled depending on the voltage provided to the chip.
Note: SCI CLOCKF must be set before beginning decoding audio data; otherwise the sample rate will
not be set correctly.
Note: SCI CLOCKF needs to be rewritten after each software reset. This is different from how VS1002
operates.
Example 1: For a 26 MHz clock the value would be
26000000
2000
= 13000.
Example 2: For a 13 MHz external clock and using internal clock-doubling for a 26 MHz internal
frequency, the value would be 0x8000 + 13000000
= 39268.
2000
Example 3: For a 24.576 MHz clock the value would be either 24576000
= 12288, or just the default
2000
value 0. For this clock frequency, SCI CLOCKF doesn’t need to be set.
8.6.5
SCI DECODE TIME (RW)
When decoding correct data, current decoded time is shown in this register in full seconds.
The user may change the value of this register. However, in that case the new value should be written
twice.
SCI DECODE TIME is reset at every software reset.
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8.6.6
VS1011 B
8. FUNCTIONAL DESCRIPTION
SCI AUDATA (RW)
When decoding correct data, the current sample rate and number of channels can be found in bits 15..1
and 0 of SCI AUDATA, respectively. Bits 15..1 contain the sample rate divided by two, and bit 0 is 0 for
mono data and 1 for stereo. Writing to this register will change the sample rate on the run to the number
given.
Example: 44100 Hz stereo data reads as 0xAC45 (44101).
8.6.7
SCI WRAM (RW)
SCI WRAM is used to upload application programs and data to instruction and data RAMs. The start
address must be initialized by writing to SCI WRAMADDR prior to the first call of SCI WRAM. As 16
bits of data can be transferred with one SCI WRAM write, and the instruction word is 32 bits long, two
consecutive writes are needed for each instruction word. The byte order is big-endian (i.e. MSBs first).
After each full-word write, the internal pointer is autoincremented.
SM WRAMADDR
Start. . . End
0x1380. . . 0x13FF
0x4780. . . 0x47FF
0x8030. . . 0x84FF
8.6.8
Dest. addr.
Start. . . End
0x1380. . . 0x13FF
0x0780. . . 0x07FF
0x0030. . . 0x04FF
Bits/
Word
16
16
32
Description
X data RAM
Y data RAM
Instruction RAM
SCI WRAMADDR (RW)
SCI WRAMADDR is used to set the program address for following SCI WRAM writes.
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8.6.9
VS1011 B
8. FUNCTIONAL DESCRIPTION
SCI HDAT0 and SCI HDAT1 (R)
Bit
HDAT1[15:5]
HDAT1[4:3]
Function
syncword
ID
HDAT1[2:1]
layer
HDAT1[0]
protect bit
HDAT0[15:12]
HDAT0[11:10]
bitrate
sample rate
HDAT0[9]
pad bit
HDAT0[8]
HDAT0[7:6]
private bit
mode
HDAT0[5:4]
HDAT0[3]
extension
copyright
HDAT0[2]
original
HDAT0[1:0]
emphasis
Value
2047
3
2
1
0
3
2
1
0
1
0
3
2
1
0
1
0
3
2
1
0
1
0
1
0
3
2
1
0
Explanation
stream valid
ISO 11172-3 1.0
MPG 2.0 (1/2-rate)
MPG 2.5 (1/4-rate)
MPG 2.5 (1/4-rate)
I
II
III
reserved
No CRC
CRC protected
ISO 11172-3
reserved
32/16/8 kHz
48/24/12 kHz
44/22/11 kHz
additional slot
normal frame
not defined
mono
dual channel
joint stereo
stereo
ISO 11172-3
copyrighted
free
original
copy
CCITT J.17
reserved
50/15 microsec
none
When read, SCI HDAT0 and SCI HDAT1 contain header information that is extracted from MPEG
stream being currently being decoded. Right after resetting VS1011b, 0 is automatically written to both
registers, indicating no data has been found yet.
The “sample rate” field in SCI HDAT0 is interpreted according to the following table:
“sample rate”
3
2
1
0
ID=3 / Hz
32000
48000
44100
ID=2 / Hz
16000
24000
22050
ID=0,1 / Hz
8000
12000
11025
The “bitrate” field in HDAT0 is read according to the following table:
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“bitrate”
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID=3 / kbit/s
forbidden
320
256
224
192
160
128
112
96
80
64
56
48
40
32
-
VS1011 B
8. FUNCTIONAL DESCRIPTION
ID=0,1,2 / kbit/s
forbidden
160
144
128
112
96
80
64
56
48
40
32
24
16
8
-
When decoding a WAV file, SPI HDAT0 and SPI HDAT1 read as 0x7761, and 0x7665, respectively.
8.6.10
SCI AIADDR (RW)
SCI AIADDR indicates the start address of the application code written earlier with SCI WRAMADDR
and SCI WRAM registers. If no application code is used, this register should not be initialized, or it
should be initialized to zero. For more details, see Application Notes for VS10XX.
8.6.11
SCI VOL (RW)
SCI VOL is a volume control for the player hardware. For each channel, a value in the range of 0..191
or 255 may be defined to set its attenuation from the maximum volume level (in 0.5 dB steps). The
left channel value is then multiplied by 256 and the values are added. Thus, maximum volume is 0 and
total silence if 0xFFFF. Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right
channel: (4*256) + 7 = 0x407. Note, that at startup volume is set to full volume. Resetting the software
does not reset the volume setting.
Note: Setting the volume to total silence (255 for both left and right channels) will turn analog power
off.
8.6.12
SCI AICTRL[x] (RW)
SCI AICTRL[x] registers ( x=[0 .. 3] ) can be used to access the user’s application program.
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8.7
VS1011 B
8. FUNCTIONAL DESCRIPTION
Stereo Audio DAC
Decoded digital data is transformed into analog format by an 18/20-bit oversampling multi-bit sigmadelta D/A converter. The oversampled output is low-pass filtered by an on-chip analog filter. The output
rate of the D/A converter is always 1/4 of the clock rate, or 128 times the highest usable sample rate. For
instance for a 24.576 MHz clock, the D/A converter operates at 128x48 kHz, which is 6.144 MHz. If the
input sample rate is other than 48 kHz, it is internally converted to 48 kHz by the DAC. This removes the
need for complex PLL-based clocking schemes and allows almost unlimited sample rate accuracy with
one fixed master clock frequency.
If the input ot the decoder is invalid or it is not received fast enough, analog outputs are automatically
muted.
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9
VS1011 B
9. OPERATION
Operation
9.1
Clocking
VS1011b operates on a single, nominally 24.576 MHz fundamental frequency master clock. This clock
can be generated by external circuitry (connected to pin XTALI) or by the internal clock chrystal interface
(pins XTALI and XTALO). This clock is sufficient to support a high quality audio output for almost all
standard sample rates and bit-rates (see Application Notes for VS10XX).
9.2
Hardware Reset
When the XRESET -signal is driven low, VS1011b is reset and all the control registers and internal
states are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1011b are in minimum
power consumption stage, and where clocks are stopped. Also XTALO and XTALI are grounded.
After a hardware reset (or at power-up), the user should set such basic software registers as SCI VOL
for volume (and SCI CLOCKF if the input clock is anything else than 24.576 MHz) before starting
decoding.
9.3 Software Reset
In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register
(Chapter 8.6.1). Then wait for at least 2 µs, then look at DREQ. DREQ will stay down for at least 6000
clock cycles, which means an approximate 250 µs delay if VS1011b is run at 24.576 MHz. After DREQ
is up, you may continue playback as usual.
If you want to make sure VS1011b doesn’t cut the ending of low-bitrate data streams and you want to do
a software reset, it is recommended to feed 2048 zeros to the SDI bus after the file and before the reset.
9.4 Play/Decode
This is the normal operation mode of VS1011b. SDI data is decoded. Decoded samples are converted to
analog domain by the internal DAC. If there are bad problems in the decoding process, the error flags of
SCI HDAT0 and SCI HDAT1 are set to 0 and analog outputs are muted.
When there is no input for decoding, VS1011b goes into idle mode (lower power consumption than
during decoding) and actively monitors the serial data input for valid data.
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9.5
VS1011 B
9. OPERATION
Feeding PCM data
VS1011b can be used as a PCM decoder by sending to it a WAV file header. If the length sent in the
WAV file is 0 or 0xFFFFFFF, VS1011b will stay in PCM mode indefinitely. 8-bit linear and 16-bit linear
audio is supported in mono or stereo.
9.6
SDI Tests
There are several test modes in VS1011b, which allow the user to perform memory tests, SCI bus tests,
and several different sine wave tests.
All tests are started in a similar way: VS1011b is hardware reset, SM TESTS is set, and then a test
command is sent to the SDI bus. Each test is started by sending a 4-byte special command sequence,
followed by 4 zeros. The sequences are described below.
9.6.1
Sine Test
Sine test is initialized with the 8-byte sequence 0x53 0xEF 0x6E n 0 0 0 0, where n defines the sine test
to use. n is defined as follows:
Name
F s Idx
S
Bits
7:5
4:0
n bits
Description
Sample rate index
Sine skip speed
F s Idx
0
1
2
3
4
5
6
7
Fs
44100 Hz
48000 Hz
32000 Hz
22050 Hz
24000 Hz
16000 Hz
11025 Hz
12000 Hz
The frequency of the sine to be output can now be calculated from F = F s ×
S
128 .
Example: Sine test is activated with value 126, which is 0b01111110. Breaking n to its components,
F s Idx = 0b011 = 1 and thus F s = 22050Hz. S = 0b11110 = 30, and thus the final sine frequency
30
F = 22050Hz × 128
≈ 5168Hz.
To exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0.
Note: Sine test signals go through the digital volume control, so it is possible to test channels separately.
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9.6.2
VS1011 B
9. OPERATION
Pin Test
Pin test is activated with the 8-byte sequence 0x50 0xED 0x6E 0x54 0 0 0 0. This test is meant for chip
production testing only.
9.6.3
Memory Test
Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this
sequence, wait for 200000 clock cycles. The result can be read from the SCI register SCI HDAT0, and
’one’ bits are interpreted as follows:
Bit(s)
15
14..7
6
5
4
3
2
1
0
Meaning
Test finished
Unused
Mux test succeeded
Good I RAM
Good Y RAM
Good X RAM
Good I ROM
Good Y ROM
Good X ROM
Memory tests overwrite the current contents of the RAM memories.
9.6.4
Erk Test
Erk test is activated with the 8-byte sequence 0xCB 0x72 0x6B 0x54 0 0 0 0. This test is meant for chip
production testing only.
9.6.5
SCI Test
Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n − 48 is the register
number to test. The content of the given register is read and copied to SCI HDAT0. If the register to be
tested is HDAT0, the result is copied to SCI HDAT1.
Example: if n is 48, contents of SCI register 0 (SCI MODE) is copied to SCI HDAT0.
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10
10.1
VS1011 B
10. VS1011B REGISTERS
VS1011b Registers
Who Needs to Read This Chapter
User software is required when a user wishes to add some own functionality like DSP effects or tone
controls to VS1011b.
However, most users of VS1011b don’t need to worry about writing their own code, or about this chapter,
including those who only download software plug-ins from VLSI Solution’s Web site.
10.2
The Processor Core
VS DSP is a 16/32-bit DSP processor core that also had extensive all-purpose processor features. VLSI
Solution’s free VSKIT Software Package contains all the tools and documentation needed to write, simulate and debug Assembly Language or Extended ANSI C programs for the VS DSP processor core.
VLSI Solution also offers a full Integrated Development Environment VSIDE for full debug capabilities.
10.3 VS1011b Memory Map
VS1011b’s Memory Map is shown in Figure 14.
10.4 SCI Registers
SCI registers described in Chapter 8.6 can be found here between 0xC000..0xC00F. In addition to these
registers, there is one in address 0xC010, called SPI CHANGE.
Reg
0xC010
Type
r
Name
SPI CH WRITE
SPI CH ADDR
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0
SPI registers, prefix SPI
Abbrev[bits]
Description
CHANGE[5:0]
Last SCI access address.
SPI CHANGE bits
Bits Description
4 1 if last access was a write cycle.
3:0 SPI address of last access.
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VS1011b
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10. VS1011B REGISTERS
Instruction (32−bit)
X (16−bit)
Y (16−bit)
System Vectors
User
Instruction
RAM
Stack
Stack
0000
0030
0098
X DATA
RAM
Y DATA
RAM
0500
0000
0030
0098
0500
0780
0780
User
Space
0800
0C00
0800
0C00
1380
1380
User
Space
1400
1400
1800
1800
4000
4000
Instruction
ROM
X DATA
ROM
Y DATA
ROM
6000
6000
7000
7000
C000
C000
Hardware
Register
Space
C100
C100
Figure 14: User’s Memory Map.
10.5 Serial Data Registers
Reg
0xC011
0xC012
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w
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Reset
0
0
SDI registers, prefix SER
Abbrev[bits]
Description
DATA
Last received 2 bytes, big-endian.
DREQ[0]
DREQ pin control.
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10.6
VS1011 B
10. VS1011B REGISTERS
DAC Registers
Reg
0xC013
0xC014
0xC015
0xC016
Type
rw
rw
rw
rw
Reset
0
0
0
0
DAC registers, prefix DAC
Abbrev[bits]
Description
FCTLL
DAC frequency control, 16 LSbs.
FCTLH[4:0]
Clock doubler + DAC frequency control MSbs.
LEFT
DAC left channel PCM value.
RIGHT
DAC right channel PCM value.
Every fourth clock cycle, an internal 26-bit counter is added to by DAC FCTLH[3:0] × 65536 + DAC FCTLL.
Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and a DAC interrupt is generated.
If DAC FCTL[4] is 1, the internal clock doubler is activated.
10.7
GPIO Registers
Reg
0xC017
0xC018
0xC019
Type
rw
r
rw
Reset
0
0
0
GPIO registers, prefix GPIO
Abbrev[bits]
Description
DDR[3:0]
Direction.
IDATA[3:0]
Values read from the pins.
ODATA[3:0]
Values set to the pins.
GPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers its
values even if a GPIO DIR bit is set to input.
GPIO registers don’t generate interrupts.
Note: Bits 2 and 3 of GPIO DDR and GPIO ODATA are switched in some pre-production VS1011’s
dated 2003. Thus, for example, writing 8 to both registers in such a chip will set pin GPIO2 to 1 instead
of GPIO3.
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10.8
VS1011 B
10. VS1011B REGISTERS
Interrupt Registers
Reg
0xC01a
0xC01b
0xC01c
0xC01d
Type
rw
w
w
rw
Reset
0
0
0
0
Interrupt registers, prefix INT
Abbrev[bits]
Description
ENABLE[2:0]
Interrupt enable.
GLOB DIS[-]
Write to add to interrupt counter.
GLOB ENA[-]
Write to subtract from interript counter.
COUNTER[4:0]
Interrupt counter.
INT ENABLE controls the interrupts. The control bits are as follows:
Name
INT EN SDI
INT EN SCI
INT EN DAC
Bits
2
1
0
INT ENABLE bits
Description
Enable Data interrupt.
Enable SCI interrupt.
Enable DAC interrupt.
Note: It may take upto 6 clock cycles before changing INT ENABLE has any effect.
Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectively
disables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect.
Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTER
already was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are restored. An interrupt routine should always write to this register as the last thing it does, because interrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the
responsibility of the user. It may take upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the register
is not 0, interrupts are disabled.
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10.9
VS1011 B
10. VS1011B REGISTERS
System Vector Tags
The System Vector Tags are tags that may be replaced by the user to take control over several decoder
functions.
10.9.1
AudioInt, 0x20
Normally contains the following VS DSP assembly code:
jmpi DAC_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a jmpi command to gain control over the audio
interrupt.
10.9.2
SciInt, 0x21
Normally contains the following VS DSP assembly code:
jmpi SCI_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a jmpi command to gain control over the SCI interrupt.
10.9.3
DataInt, 0x22
Normally contains the following VS DSP assembly code:
jmpi SDI_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a jmpi command to gain control over the SDI interrupt.
10.9.4
UserCodec, 0x0
Normally contains the following VS DSP assembly code:
jr
nop
If the user wants to take control away from the standard decoder, the first instruction should be replaced
with an appropriate j command to user’s own code.
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VS1011 B
10. VS1011B REGISTERS
Unless the user is feeding MP3 data at the same time, the system activates the user program in less than
1 ms. After this, the user should steal interrupt vectors from the system, and insert user programs.
10.10
System Vector Functions
The System Vector Functions are pointers to some functions that the user may call to help implementing
his own applications.
10.10.1 WriteIRam(), 0x2
VS DSP C prototype:
void WriteIRam(register i0 u int16 *addr, register a1 u int16 msW, register a0 u int16 lsW);
This is the only supported way to write to the User Instruction RAM. This is because Instruction RAM
cannot be written when program control is in RAM. Thus, the actual implementation of this function is
in ROM, and here is simply a tag to that routine.
10.10.2
ReadIRam(), 0x4
VS DSP C prototype:
u int32 ReadIRam(register i0 u int16 *addr);
This is the only supported way to read from the User Instruction RAM. This is because Instruction RAM
cannot be read when program control is in RAM. Thus, the actual implementation of this function is in
ROM, and here is simply a tag to that routine.
A1 contains the MSBs and a0 the LSBs of the result.
10.10.3
DataBytes(), 0x6
VS DSP C prototype:
u int16 DataBytes(void);
If the user has taken over the normal operation of the system by switching the pointer in UserCodec
to point to his own code, he may read data from the Data Interface through this and the following two
functions.
This function returns the number of data bytes that can be read.
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VS1011 B
10. VS1011B REGISTERS
10.10.4 GetDataByte(), 0x8
VS DSP C prototype:
u int16 GetDataByte(void);
Reads and returns one data byte from the Data Interface. This function will wait until there is enough
data in the input buffer.
10.10.5 GetDataWords(), 0xa
VS DSP C prototype:
void GetDataWords(register i0 y u int16 *d, register a0 u int16 n);
Read n data byte pairs and copy them in big-endian format (first byte to MSBs) to d. This function will
wait until there is enough data in the input buffer.
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VS1011 B
11. DOCUMENT VERSION CHANGES
Document Version Changes
This chapter describes the most important changes to this document.
11.1
Version 1.01 for VS1011b, 2004-11-19
• Removed non-existing SCIMB POWERDOWN bit.
• Added SOIC-28 package to Chapters 5.1.3 and 5.2.2.
11.2
Version 1.00 for VS1011b, 2004-10-22
• Fully qualified values to tables in Chapter 4.
• Reassigned BGA-49 balls for pins DVDD2, DGND2 and DGND3 in Chapter 5.2.
11.3
Version 0.71 for VS1011, 2004-07-20
• Added instructions to add 100 kΩ pull-down resistor to unused GPIOs to Chapter 5.2.
11.4 Version 0.70 for VS1011, 2004-05-13
• Removed SM JUMP.
11.5 Version 0.62 for VS1011, 2004-03-24
• Rewrote and clarified Chapter 8.2, Supported Audio Codecs.
11.6
Version 0.61 for VS1011, 2004-03-11
• Added samplerate and bitrate tables to Chapter 8.6.9.
11.7
Version 0.6 for VS1011, 2004-02-13
• Added BGA-49 to Packages and Pin Descriptions (Chapter 5).
• Added new Chapter 8.2, Supported Audio Codecs.
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VS1011 B
12. CONTACT INFORMATION
Contact Information
VLSI Solution Oy
Hermiankatu 6-8 C
FIN-33720 Tampere
FINLAND
联系人：王立青
手机：１３２６７２３１７２５
Phone:0755-82565571
ＱＱ：２３５５３５５２５４
Email:[email protected]
URL: http://www.vlsi.fi/
Note: If you have questions, first see http://www.vlsi.fi/vs1011/faq/ .
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