ISP Interface Module ISP Interface Module for Atmel Microcontrollers User Guide (Version 1.01) Contents Copyright Information ...........................................................................................................................iii Equinox Warranty Information.............................................................................................................iv Electromagnetic Compatibility (EMC) Compliance ...........................................................................v Technical Support .................................................................................................................................vi 1.0 ISP Interface Module .......................................................................................................................1 1.1 Overview .......................................................................................................................................1 1.2 Features ........................................................................................................................................1 1.3 Packing List ..................................................................................................................................2 1.4 Different version of the PIM Module .........................................................................................2 2.0 Layout, Dimensions & Mounting Guidelines ...............................................................................3 2.1 Layout Overview ..........................................................................................................................3 2.2 ISP Interface Module Dimensions .............................................................................................4 2.3 Mounting Guidelines ...................................................................................................................4 3.0 P IM Jumper Descriptions ...............................................................................................................5 3.1 Overview .......................................................................................................................................5 3.2 Jumper Link – Detailed Descriptions ........................................................................................6 3.2.1 VPP Supply option link (LK1) .............................................................................................6 3.2.2 RESET select options link (LK2)........................................................................................6 3.2.3 Target Clock source option (LK3) ......................................................................................7 3.2.4 Target supply option link (LK4) ..........................................................................................7 3.2.5 Remote Target VCC sense option (LK5)..........................................................................8 3.2.6 VPP RESET options link (LK6) ..........................................................................................8 3.2.7 VPP RESET options link (LK7) – PIM V2 Iss 2 only.......................................................8 4.0 ISP Header Connections ................................................................................................................9 4.1 Selecting ISP Connection Method ............................................................................................9 4.2 Equinox 10 way IDC ISP header (J1).................................................................................... 10 4.3 Atmel 10 way IDC ISP header (J2) ........................................................................................ 11 4.4 FS2000/Micro-ISP/Epsilon5 input (J3).................................................................................. 12 4.5 10-way IDC Connector Considerations ................................................................................. 14 4.6 Wire wrapping to ISP Header Connectors J1/J2 ................................................................. 14 4.7 Fast connect target connector (J4) ........................................................................................ 15 4.8 Fast connect target connector (J5) ........................................................................................ 16 4.9 J7 PPM ISP Connector ............................................................................................................ 17 5.0 LED Status Indicators .................................................................................................................. 18 5.1 Programmer Status LED’s ...................................................................................................... 18 5.2 Target Vcc Presence LED....................................................................................................... 18 6.0 Configuring the SCK2 Oscillator Output ................................................................................... 19 6.1 Overview .................................................................................................................................... 19 6.2 Microcontrollers requiri ng the SCK2 signal .......................................................................... 20 6.3 Configuring the PIM SCK2 Output Frequency..................................................................... 21 6.4 Enabling the PIM SCK2 Output Signal with a PPM ............................................................ 22 6.5 Using the FS2000A SCK2 Frequency................................................................................... 23 6.6 ATmega163 + SCK2 ................................................................................................................ 24 6.7 ATtiny12 + SCK2 ...................................................................................................................... 25 ISP Interface Module Version 1.00 27/06/01 i 7.0 Signal Test Points .........................................................................................................................26 7.1 Overview .....................................................................................................................................26 8.0 PPM/Target System Power Supply Configuration...................................................................27 8.1 Overview .....................................................................................................................................27 8.2 Selecting the Target Power Supply Configuration...............................................................27 8.2.1 PPM Powers the Target System .....................................................................................28 8.2.2 Target System is independently powered ......................................................................29 8.3 Protecting the PPM from over-voltage ...................................................................................30 9.0 Target System Detection Methods .............................................................................................31 9.1 Standard Target Load Detection.............................................................................................32 9.1.1 Overview..............................................................................................................................32 9.1.2 Circuit Implementation.......................................................................................................32 9.1.3 EQTools Project / Script Implementation.......................................................................32 9.1.4 Running the Script/Project Files ......................................................................................33 9.2 Push Button (SI) Start ...............................................................................................................34 9.2.1 Overview..............................................................................................................................34 9.2.2 Circuit Implementation.......................................................................................................34 9.2.3 EQTools Project / Script Implementation.......................................................................34 9.2.4 Running the Script / Project Files ....................................................................................35 9.3 Bed-of-Nails shorting pins detection.......................................................................................36 9.3.1 Overview..............................................................................................................................36 9.3.2 Circuit Implementation.......................................................................................................36 9.3.3 EQTools Project / Script Implementation.......................................................................36 9.3.4 Running the Script / Project Files ....................................................................................37 9.4 Presence of Independent Target Power Supply ..................................................................38 9.4.1 Overview..............................................................................................................................38 9.4.2 Circuit Implementation.......................................................................................................38 9.4.3 EQTools Project / Script Implementation.......................................................................39 9.4.4 Running the Script/Project Files ......................................................................................39 9.5 Opto-Isolated input start...........................................................................................................40 9.5.1 Overview..............................................................................................................................40 9.5.2 Circuit Implementation.......................................................................................................40 9.5.3 EQTools Project/Script Implementation .........................................................................41 ii ISP Interface Module Version 1.00 27/06/01 Copyright Information Information in this document is subject to change without notice and does not represent a commitment on the part of the manufacturer. The software described in this document is furnished under license agreement or nondisclosure agreement and may be used or copied only in accordance with the terms of the agreement. It is against the law to copy the software on any medium except as specifically allowed in the license or nondisclosure agreement. The purchaser may make one copy of the software for backup purposes. No part of this manual may be reproduced or transmitted in any form or by any means, electronic, mechanical, including photocopying, recording, or information retrieval systems, for any purpose other than for the purchaser’s personal use, without written permission. © 2001 Copyright Equinox Technologies UK Limited. All rights reserved. AtmelTM and AVR TM are trademarks of the Atmel Corporation Microsoft, MS-DOS, WindowsTM and Windows 95TM are registered trademarks of the Microsoft Corporation IBM, PC and PS/2 are registered trademarks of International Business Machines Corporation Intel, MCS 51, ASM-51 and PL/M-51 are registered trademarks of the Intel Corporation Every effort was made to ensure accuracy in this manual and to give appropriate credit to persons, companies and trademarks referenced herein. Equinox guarantees that its products will be free from defects of material and workmanship under normal use and service, and these products will perform to current specifications in accordance with, and subject to, the Company’s standard warranty which is detailed in Equinox’s Purchase Order Acknowledgment. ISP Interface Module Version 1.00 27/06/01 iii Equinox Warranty Information This product is guaranteed by Equinox Technologies UK Limited for a period of 12 months (1 year) after the date of purchase against defects due to faulty workmanship or materials. The guarantee covers both parts and labour. Service under the guarantee is only provided upon presentation of reasonable evidence that the date of the claim is within the guarantee period (e.g. completed registration/guarantee card or a purchase receipt). The guarantee is not valid if the defect is due to accidental damage, misuse or neglect and in the case of alterations or repair carried out by unauthorised persons. A number of exceptions to the warranty are listed in the ‘Exceptions to warranty’ section below. Service (during and after guarantee period) is available in all countries where the product is distributed by Equinox Technologies UK Limited. Exceptions to warranty i. Over-voltage damage This warranty does not cover damage to the ISP Interface Module due to voltages beyond the specified voltage limits being applied to the ‘DC Power Input’ or the ‘Target Connector’. The user must ensure that sufficient care is taken to avoid over-voltage and static conditions on any of the ‘Target Connector’ I/O pins. ii. Short-circuit damage This warranty does not cover damage to the ISP Interface Module due to short-circuit loads being placed across programmer I/O lines. Disclaimer Equinox Technologies UK Ltd. can not be held responsible for any third party claims which arise out of the use of this ISP Interface Module including ‘consequential loss’ and ‘loss of profit’. Equinox Technologies UK Ltd. cannot be held responsible for any programming problems which are ‘out of our control’. This type of problem is usually listed in the ‘Errata Sheet’ for the particular device being programmed and is available from the silicon vendor. Information contained in this manual is for guidance purposes only and is subject to change. E&OE. iv ISP Interface Module Version 1.00 27/06/01 Electromagnetic Compatibility (EMC) Compliance The ‘ISP Interface Module’ is a CE Approved Product. It is designed for use in an ESD controlled environment i.e. development or production. This means, therefore, that the user must ensure that there is no possibility of damage from electrostatic discharge (ESD). Since the devices and equipment to which this product is likely to be connected may well themselves be susceptible to ESD, this should not pose any difficulty. For example, if you are handling microcontrollers and EEPROMS etc. then you will already be used to appropriate precautions, such as the use of anti-static mats, wrist straps and so on. You should treat your ‘ISP Interface Module’ with the same care as you would these other types of devices. Always ensure that you are not yourself carrying a static charge before handling the product. Wearing an earthed anti-static wrist strap is recommended. Equinox have taken great care in designing this product to be compliant with the European EMC directive. When using the equipment be sure to follow the instructions provided. Although RF emissions are within prescribed limits, care should be taken if you are using the product near to sensitive apparatus. If you experience any difficulty please refer to Equinox technical support. ESD Points to remember • Work in a static-free environment. • Wear an earthed wrist strap when handling this product and/or any programmable device. ISP Interface Module Version 1.00 27/06/01 v Technical Support It is often the case that users experience problems when installing or using a product for the first time. Equinox are unable to answer technical support questions about this product or its use by telephone. If you have a technical support problem, please consult the following list for help: i. Manual ii. Internet Web Site Equinox have set up an In-System Programming (ISP) support page on our web site. This page is designed to provide up-to date information on all issues associated with ISP. The ISP support page can be found at: www.equinox-tech.com/isp.htm iii. E-mail Please e-mail any technical support questions about this product to: [email protected] Equinox will try our best to answer your questions about this product as quickly as possible. However, we cannot promise an immediate reply. Please consult our web site for new software updates as the problem that you are enquiring about may have already been fixed in a new version. iv. Fax Please fax any technical support questions about this product to: +44 (0) 1204 535555 Equinox will try our best to answer your questions about this product as quickly as possible. However, we cannot promise an immediate reply. Please consult our web site for new software updates as the problem that you are enquiring about may have already been fixed in a new version. vi ISP Interface Module Version 1.00 27/06/01 1.0 ISP Interface Module 1.1 Overview The ISP Interface Module (PIM) is a versatile PCB assembly designed to interconnect a Production Programming Module (PPM), an FS2000 or the Epsilon programmer to a user Target System. The module can connect to the PPM using the ‘PPM ISP Cable’ supplied or to the FS2000/Epsilon via the 10-way FS2000 header. Connections to the Target System are provided in the form of wired connections and also the Atmel and Equinox 10-way IDC headers. The module is designed to be easily mounted within a Target System using the four mounting holes provided. The PIM has an on-board clock generator which is capable of supplying a programmable clock signal on the SCK2 pin. 1.2 Features • Interfaces the Production Programming Module (PPM) to the Target System • Interfaces FS2000/Epsilon programmer to the target system • On board SCK2 Clock Generator with frequency range 62.5 KHz to 8.0MHz • Suitable for incorporating into the product ‘test fixture’ (includes four fixing holes) • Features ‘Fast-connect’ clip-in wire connectors suitable for wiring to bed-of-nails test points • Equinox 10-way ISP header (suitable for plug or wire wrap) • Atmel 10-way ISP header (suitable for plug or wire wrap) • Clip-in ‘Fast Connect’ Target ISP Connector • Manual auto-program <START> switch (S1) • Independent Target Vcc Detection Circuit • Opto-isolated input for auto-program START (J6) • On board +12v VPP generator Figure1 – Typical connection of PPM to Target System using PIM ISP Interface Module Version 1.00 27/06/01 1 Figure 2 - showing FS2000 connected to PIM 1.3 Packing List The PPM Interface Module package is supplied with the following: • 1 x ISP Interface Module • 1 x PPM ISP Cable (25-way to 25-way ribbon cable for connection from PPM to PIM) • 1 x 10-way IDC ISP Cable (for connection to target) 1.4 Different versions of the PIM Module This manual covers the two different revisions of this module as follows: • PP-MODV2 Issue 1 • PP-MODV2 Issue 2 PPM-MODV2 Issue 2 has the following enhancements from Issue 1: • Jumper LK7 added to allow +5V to be connected to PPM Buffer Supply • Zener Diode added across TARGET_VCC and GROUND • Extra ground point added next to J7 for test purposes 2 ISP Interface Module Version 1.00 27/06/01 2.0 Layout, Dimensions & Mounting Guidelines 2.1 Layout Overview Figure 3 – Layout overview of PIM Key ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description Target Vcc - POWER ON LED Indicator (RED) Equinox 10-way IDC ISP Header Atmel 10-way IDC ISP Header BUSY LED Indicator (YELLOW) OK LED Indicator (GREEN) FS2000/Epsilon programmers - 10-way IDC Header PPM ISP Connector (25-way D male connector) Signal Test Points Manual Programming <Start> Switch FAIL LED Indicator (RED) DIP Switch (SCK2 frequency + Vpp Enable) Opto-isolated signal input connector Target System ISP Connector (Fast connect) Target System ISP Connector (Fast connect) Circuit Descriptor LD4 J1 J2 LD1 LD3 J3 J7 TP1..TP25 S1 LD2 SW1 J6 J5 J4 See Section 5 4 4 5 5 4 4 7 8 5 6 8 4 4 Figure 4 – Component ID’s for PIM ISP Interface Module Version 1.00 27/06/01 3 2.2 ISP Interface Module Dimensions The PIM is designed to be mounted into a suitable test fixture using the four mounting holes provided. PPM Interface Module Dimensions Figure 5 Dimension Value Units PCB Length PCB Width PCB max. height Fixing hole diameter 96.0 69.0 29.0 3.0 mm mm mm mm Figure 6 2.3 Mounting Guidelines • Keep the PPM ISP Cable as short as possible by mounting the PPM as close as possible to the PIM. • Minimise the length of all ISP cables between the PIM and the Target System • Carefully route all ISP cables between the PIM and the Target System so as to avoid pick up of noise, glitches etc. • Extreme care must be taken to ensure that no dust or metal debris falls onto the PIM as this could cause a catastrophic failure of the board. 4 ISP Interface Module Version 1.00 27/06/01 3.0 PIM Jumper Descriptions 3.1 Overview The PIM features a number of user-selectable ‘jumpers’ which allow different circuit configurations to be implemented. Please refer to figure 7 for the position of these jumpers. The functionality of each jumper is listed in figure 8. A full description can be found in the following section. Figure 7 - Layout of PPM Interface Module Links Key ID Description Link Positions Default Position LK1 LK2 LK3 LK4 LK5 LK6 Vpp Supply – Option Link RESET select – Options Link Target Clock Source (SCK2) – Option Link Target Supply – Option Link Remote Target Vcc Sense – Option Link Vpp RESET – Option Link 3-way 3-way 3-way 2-way 2-way 2-way Not Fitted 1-2 Fitted Not Fitted 1-2 Fitted Not Fitted Not Fitted Figure 8 ISP Interface Module Version 1.00 27/06/01 5 3.2 Jumper Link – Detailed Descriptions 3.2.1 VPP Supply option link (LK1) This link controls the source voltage for the on-board Vpp Generator IC. This IC requires +5V to operate. LK 1 – Pin Descriptions Key ID Pin Description/Functions LK1 pin 1 LK1 pin 2 LK1 pin 3 +5V continuous supply from PRO101/4/8 programmer VCC actual supply to VPP Generator IC (U2) VCC voltage supplied by the user Target System Figure 9 LK 1 – Function Selection Position Selected Function LK1 1-2 The Vpp (+12V) Generator IC is supplied from the +5V output from the PPM programmer. The Vpp Generator IC is supplied from the Target system Vcc. If the Target Vcc is <+5V and you wish to use the on-board Vpp Generator, it is necessary to supply the IC from the PPM +5V line by connecting LK1 1-2. The Vpp (+12V) Generator IC is not powered at all. This setting is the default setting. Power is only required to this IC if you are using the Vpp(+12V). LK1 2-3 Not Fitted Figure 10 3.2.2 RESET select options link (LK2) This link selects whether the RESET signal connected to the Target System is +12V or the normal (3.0 - 5.0V) RESET voltage. The +12V option is only required when programming ATtiny11/12/15/22 devices in ‘High Voltage Serial Programming Mode’. These algorithms are not currently implemented on the PRO101/4/8 programmers and so this jumper should always be fitted in the LK2 1 -2 position. LK 2 – Pin Descriptions Key ID Pin Description/Functions LK2 pin 1 LK2 pin 2 Programmer RESET signal (P-RESET) from PRO101/4/8 programmer. Target RESET signal (T-RESET) which connects to the RESET pin of the Target System +12V Vpp Output (VPP-RESET) from on-board VPP Generator IC LK2 pin 3 Figure 11 6 ISP Interface Module Version 1.00 27/06/01 LK 2 – Function Selection Position Selected Function LK2 1-2 Programmer RESET signal (P-RESET) from PRO101/4/8 programmer is connected to the reset pin on the target micro-controller +12V Vpp Output (VPP-RESET) from on-board VPP Generator IC is connected to the reset pin on the target micro-controller. This link should be used in conjunction with link 6. LK2 2-3 Figure 12 3.2.3 Target Clock source option (LK3) This link selects the source of the oscillator signal SCK. This signal is only required when the target microcontroller either does not have a clock signal during the programming cycle or a faster clock signal is required to speed up programming. LK 3 – Pin Descriptions Key ID Pin Description/Functions LK3 pin 1 FS-SCK2 SCK2 clock signal available from FS2000/Epsilon programmers if connected to ISP Header J3. The SCK2 clock signal (T-SCK2) which is connected to the XTAL1 pin of the target microcontroller SCK2 Clock signal available from on-board Clock Generator IC (U3) LK3 pin 2 LK3 pin 3 Figure 13 LK 3 – Function Selector Position Selected Function LK3 1-2 The SCK2 clock signal is routed from the FS2000/Epsilon programmers if connected to ISP Header J3. It is then connected to the XTAL1 pin on the target micro-controller. The SCK2 Clock signal available from on-board Clock Generator IC (U3) is connected to the XTAL1 pin on the micro-controller If SCK2 clock is not required do not put any jumper on LK3 LK3 2-3 Not Fitted Figure 14 3.2.4 Target supply option link (LK4) This link configures whether the Target System sources its power from the programmer or from an external power supply as follows: LK 4 – Pin Descriptions Key ID Pin Description/Functions LK4 pin 1 Programmer Programmable Output Voltage (PPM-VOUT) from PRO101/4/8 programmers Target Voltage Vcc (T-VCC) – connected directly to Target System supply voltage LK4 pin 2 Figure 15 ISP Interface Module Version 1.00 27/06/01 7 LK 4 – Function Selector Position Selected Function LK4 1-2 Not fitted The programmer supplies power to the Target System. The Target System is powered by an external power supply. Figure 16 3.2.5 Remote Target VCC sense option (LK5) This link configures the PIM to use an on-board ‘Target Vcc Detection Circuit’. This allows the PIM to sense whether the Target Voltage is present. It is necessary to set this up in your ‘programming project’ within EQTools. LK 5 – Function Selection Position Selected Function LK5 1-2 Not fitted If auto-programming is to be initiated on detection of target VCC If auto-programming is to be initiated by some other method e.g. manual switch Figure 17 3.2.6 VPP RESET options link (LK6) This link enables the +12V Vpp to be available at link 2 pin 3. If you do not require the +12V Vpp and wish to avoid possible damage to your damage to your Target System, do NOT fit this link. LK 6 –Function Selection Position Selected Function LK6 1-2 Enables +12V Vpp to be applied to the Target RESET pin. This link must be set in conjunction with link 2. +12V Vpp is NOT available at link 2. Default setting. Not fitted Figure 18 3.2.7 VPP RESET options link (LK7) – PIM V2 Iss 2 only This link is only present on PIM V2 Iss2. It allows +5V internally generated by the PPM (PRO101) to be connected to the V_TARGET_IN pin (pin 25) of the PPM. This can be used to power the PPM Line Driver IC’s at +5V if the PPM Jumper J8 is set to the ‘TGT’ position (default). LK 7 –Function Selection Position Selected Function LK7 1-2 PPM Buffer IC Supply is derived from PPM +5V internal supply This setting can only be used if your Target Vcc is always +5V. PPM Buffer IC Supply is derived from Target Vcc Not fitted (default) 8 ISP Interface Module Version 1.00 27/06/01 4.0 ISP Header Connections 4.1 Selecting ISP Connection Method There are three possible ways to connect the PIM to the Target System as detailed in the table below: Physical Connection Method Explanation 1 Wired connections using Quick Connector Block (J4 & J5) This connection method allows connection wires to be clipped into the connector block (J4 & J5). The other end of each wire can be soldered to a suitable bed-of-nails connector test point as illustrated below. 2 Equinox 10-way IDC Header (J1) Section 4.2 3 Atmel 10-way IDC Header (J2) Section 4.3 This connection method allows the PIM to connect to a Target System which features the Equinox 10-way IDC Header. To implement this connection, simply plug the 10-way ISP cable into PIM J1 and plug the other end of the cable into the matching header on the Target System. This connection method allows the PIM to connect to a Target System which features the Atmel 10-way IDC Header. To implement this connection, simply plug the 10-way ISP cable into PIM J2 and plug the other end of the cable into the matching header on the Target System. Figure 19 ISP Interface Module Version 1.00 27/06/01 9 4.2 Equinox 10 way IDC ISP header (J1) This connection method allows the PIM to connect to a Target System which features the Equinox 10-way IDC Header. To implement this connection, simply plug the 10-way ISP cable into PIM J3 and plug the other end of the cable into the matching header on the Target System. Figure 20 – Equinox 10-way IDC Header (J1) viewed from above Warning! Connecting to the wrong ISP Header may cause catastrophic damage to the PIM, Programmer & Target System Key to figure 21: O = Output, I = Input, P = Passive Pin No Pin name Input / Output Description 1 2 Target Vcc PPM-OP2 (Slave Select) P O 3 T-SCK2 O 4 MOSI O 5 6 Not Connected MISO O I 7 GND P 8 SCK1 O 9 GND P 10 RESET O Target Vcc PPM Output 2 (OP2 pin 2) This output signal can be used to control logic on the Target System. e.g. the pin can be used to select a particular device on the SPI bus. SCK2 Clock output This output signal can be used to supply an external clock signal (SCK2) to the target microcontroller. Master Out Slave In (PPM pin 5) This is the SPI data output pin from the programmer. This pin should be connected to the MOSI pin on the Target Microcontroller. Not connected Master In Slave Out (PPM pin 11) This is the SPI data input pin to the programmer. This pin should be connected to the MISO pin on the Target Microcontroller. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. SPI Serial Clock Output (PPM pin 6) This is the SPI clock output signal. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. RESET control signal (PPM OP4 – pin 4) This is the default positive RESET control signal and should be connected to the Target Microcontroller RESET pin. Figure 21 10 ISP Interface Module Version 1.00 27/06/01 4.3 Atmel 10 way IDC ISP header (J2) This connection method allows the PIM to connect to a Target System which features the Atmel 10-way IDC Header. To implement this connection, simply plug the 10-way ISP cable into PIM J4 and plug the other end of the cable into the matching header on the Target System. Figure 22- Atmel 10-way IDC Header (J2) viewed from above Warning! Connecting to the wrong ISP Header may cause catastrophic damage to the PIM, Programmer & Target System Key to figure 23: O = Output, I = Input, P = Passive Pin No Pin name Input / Output Description 1 MOSI O 2 3 4 Target Vcc Not Connected GND P O P 5 RESET O 6 GND P 7 SCK1 O 8 GND P 9 MISO I 10 GND P Master Out Slave In (PPM pin 5) This is the SPI data output pin from the programmer. This pin should be connected to the MOSI pin on the Target Microcontroller. Target Vcc Not connected Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. RESET control signal (PPM OP4 – pin 4) This is the default positive RESET control signal and should be connected to the Target Microcontroller RESET pin. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. SPI Serial Clock Output (PPM pin 6) This is the SPI clock output signal. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. Master In Slave Out (PPM pin 11) This is the SPI data input pin to the programmer. This pin should be connected to the MISO pin on the Target Microcontroller. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. Figure 23 ISP Interface Module Version 1.00 27/06/01 11 4.4 FS2000/Micro-ISP/Epsilon5 input (J3) This connection method allows the signals from an FS2000A/Micro-ISP/ Epsilon5 ISP programmer to be routed to the Target System through the PIM as shown in figure 23. This can be useful when debugging Target System problems as each signal is brought out to a Test Point on the PIM. Figure 24 Figure 25 – FS2000/EPSILON5 ISP Header (J3) viewed from above. Warning! Connecting to the wrong ISP Header may cause catastrophic damage to the PIM, Programmer & Target System If a programmer is plugged into J3, the signals from the programmer will be routed to J1, J2, J4 and J5. The routing of these signals is detailed in figure 26. 12 ISP Interface Module Version 1.00 27/06/01 Pin no. J3 Pin name 1 2 Target Vcc PPM-OP2 (Slave Select) 3 FS-SCK2 4 MOSI 5 6 Not Connected MISO 7 GND 8 SCK1 9 GND 10 RESET Description/Function J4 & J5 J1 Equinox ISP Header Target Vcc PPM Output 2 (OP2 pin 2) This output signal can be used to control logic on the Target System. eg. the pin can be used to select a particular device on the SPI bus. SCK2 Clock output This output signal can be used to supply an external clock signal (SCK2) to the target microcontroller. Master Out Slave In (PPM pin 5) This is the SPI data output pin from the programmer. This pin should be connected to the MOSI pin on the Target Microcontroller. Not connected J4 – T-Vcc J5 – OP2 1 2 2 No connection. J5 – SCK2 3 via LK3 1-2 No connection J4 – MOSI 4 1 5 Master In Slave Out (PPM pin 11) This is the SPI data input pin to the programmer. This pin should be connected to the MISO pin on the Target Microcontroller. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. SPI Serial Clock Output (PPM pin 6) This is the SPI clock output signal. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. RESET control signal (PPM OP4 – pin 4) This the RESET control signal and should be connected to the Target Microcontroller RESET pin. J4 – MISO 6 No connection 9 J4 – GND 7 4,6,8,10 J4 – SCK1 8 7 J4 – GND 9 4,6,8,10 J4 - RESET 10 J2 Atmel ISP Header 5 Figure 26 – Routing of programmer signals from J3 to J1, J2, J4 & J5 ISP Interface Module Version 1.00 27/06/01 13 4.5 10-way IDC Connector Considerations The ISP Headers used on the PIM (J1, J2, J3) are standard 10-way IDC box headers which are designed to mate with a suitable IDC plug on the end of an IDC cable. The pin spacing is 0.1" with pin 1 being denoted with a square solder pad on the PCB. These headers feature a location notch which prevents the ISP cable from being plugged in the wring way around. All diagrams shown in this manual for headers J1, J2, J3 refer to the header when viewing the PCB from above see figure 27 Figure 27 4.6 Wire wrapping to ISP Header Connectors J1/J2 If you wish to use wire wrapped cables to the test fixture, the black header on J1 or J2 can be removed by carefully inserting a screwdriver under the header and the exposed pins can be used for wire wrapping. 14 ISP Interface Module Version 1.00 27/06/01 4.7 Fast connect target connector (J4) This connection method allows connection wires to be clipped into the connector block. The other end of each wire can be connected to a suitable bed-of-nails connector test point as illustrated figure 28. Figure 28 – ISP Interface Module connected to a Bed-of-Nails Test Fixture via connector J4 Label Pin description/function T-VCC MISO SCK1 MOSI RESET GND Target System Vcc Connection SPI signal – Master In Slave Out SPI signal – Serial Clock (connects to SCK on target microcontroller) SPI signal – Master Out Slave In RESET signal (connect to target microcontroller RESET pin) Target System Ground Figure 29 Figure 30 Pin No Pin name Input / Output Description 1 2 Target Vcc MISO P I 3 SCK1 O 4 MOSI O 5 RESET O 6 GND P Target Vcc Master In Slave Out (PPM pin 11) This is the SPI data input pin to the programmer. This pin should be connected to the MISO pin on the Target Microcontroller. SPI Serial Clock Output (PPM pin 6) This is the SPI clock output signal. Master Out Slave In (PPM pin 5) This is the SPI data output pin from the programmer. This pin should be connected to the MOSI pin on the Target Microcontroller. RESET control signal (PPM OP4 – pin 4) This is the default positive RESET control signal and should be connected to the Target Microcontroller RESET pin. Ground Connection (PPM pin 23) Common ground connection between PPM and Target System. Key: O = Output, I = Input, P = Passive ISP Interface Module Version 1.00 27/06/01 15 4.8 Fast connect target connector (J5) This connection method allows connection wires to be clipped into the connector block. The other end of each wire can be connected to a suitable bed-of-nails connector test point as illustrated figure 31. Figure 31 – ISP Interface Module connected to a Bed-of-Nails Test Fixture via connector J5 Label Pin description/function OP2 PPM Output 2 Used by PIM to control RESET line during programming. Do NOT connect to target system. SCK2 Output Connect to XTAL1 pin of target microcontroller (if required). PPM Input signal 1 PPM Input signal 2 PPM Input signal 3 Programmable voltage from PPM (PPM-VOUT) SCK2 IP1 IP2 IP3 VOUT Figure 32 Figure 33 Pin Number Pin name Input / Output Description 1 OP2 O 2 SCK2 O 3 IP1 I 4 IP2 I 5 IP3 I 6 VOUT P PPM Output 2 (OP2 pin 2) This output signal can be used to control logic on the Target System. e.g. the pin can be used to select a particular device on the SPI bus. SCK2 Clock output This output signal can be used to supply an external clock signal (SCK2) to the target microcontroller. PPM input 1 (IP2 pin 7) Input control signal to PPM PPM input 2 (IP3 pin 8) Input control signal to PPM PPM input 3 (IP3 pin 9) Input control signal to PPM PPM-VOUT VCC for target. Programmable voltage level Key: O = Output, I = Input, P = Passive 16 ISP Interface Module Version 1.00 27/06/01 4.9 J7 PPM ISP Connector This connector provides the I/O interface between the PPM and the PIM. The following groups of signals are provided: • General purpose outputs • The SPI bus (MOSI, MISO, SCK) • Connections for three PPM “Status” LED’s • Target power supply +5V and a special negative voltage output signal • General purpose Inputs (reserved for future use) Figure 34 – Target Programming Connector (25-way Male D Connector) J1 Target Programming Connector - Pin out Pin No Title Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 OP1_C OP2_C OP3_C OP4_C (RESET) MOSI_C SCK_C IP1_C IP2_C IP3_C IP4_C MISO_C LED1A LED1K LED2A LED2K LED3A LED3K OP5 Vcc_OUT Vcc_OUT GND SP1_IP GND Vcc Vcc_TARGET_IN Output 1. Used to enable SCK2 generator U3 Output 2. Used to control VPP generator (Controls +12V RESET line) Output 3. Used to control VPP generator (Vpp Output enable) Output 4. Default RESET control signal MOSI SPI signal. Master Out Slave In SCK SPI signal. (Serial clock) Input 1. Do not connect. Reserved for future use N/C Input 2. Do not connect. Reserved for future use N/C Input 3. Do not connect. Reserved for future use N/C Input 4. Used with opto-isolator start MISO SPI signal. Master In Slave Out Anode of Busy LED (usually yellow) Cathode of Busy LED (usually yellow) Anode of Fault LED (usually red) Cathode of Fault LED (usually red) Anode of OK LED (usually green) Cathode of OK LED (usually green) Output 5. Negative voltage output signal. (-4.5V) Vcc for target. Programmable voltage level Vcc for target. Programmable voltage level 0V for target Reserved for future use 0V for target +5V Target Vcc Voltage Input (Connects to J8 TV pin on PPM) Figure 35 Please refer to the ‘PPM Programmer Module’ manual for further details ISP Interface Module Version 1.00 27/06/01 17 5.0 LED Status Indicators 5.1 Programmer Status LED’s The PIM features a traffic light 3-way LED Status Indicator. These LED’s are controlled from a PPM programmer (PRO101) and will mimic the LED’s on the programmer exactly. The possible status conditions are described in the table below. Please consult the PPM Manual for a full description. Figure 36 LED Condition Status Description Flashing Green Target System Powered Off (Programmer Inactive) Flashing Red Programming Operation Failed or Programmer has Rebooted Flashing Yellow Programmer in ‘Wait Disconnect’ state. Target is powered OFF, but ‘Target Sense’ circuit is active. Constant Yellow Programmer is BUSY. Programmer is either executing a ‘script command’ or running an autoprogram project. Figure 37 5.2 Target Vcc Presence LED The PIM features an LED (LD4) which illuminates when a Target Vcc voltage is sensed. The threshold voltage for illuminating the LED is approx 2.5V. This LED is powered from the PIM +5V supply which is derived from the programmer and so does not load the Target Vcc supply. The LED will illuminate whether the programmer is powering the Target System or not (see Link LK4). 18 ISP Interface Module Version 1.00 27/06/01 6.0 Configuring the SCK2 Oscillator Output 6.1 Overview The PIM features an on-board Clock Generator IC which is capable of generating a programmable frequency square wave signal. This clock signal can be used as a clock source for a target microcontroller which either does not have an external clock source or requires a faster clock to speed up the programming cycle. e.g. Atmel ATmega163, ATtiny12. The SCK2 signal, once enabled, is output from the PIM on the SCK2 pin of the ISP headers J1 and J5. If you are using the Equinox FS2000A programmer, it is possible to route the SCK2 signal generated by the FS2000A from the FS2000 J3 header to SCK2 pin of the ISP headers J1 and J5. Figure 38 ISP Interface Module Version 1.00 27/06/01 19 6.2 Microcontrollers requiring the SCK2 signal The SCK2 signal may be required during programming for the microcontrollers listed in figure 37 below. 1 2 Microcontroller Description ATmega163(L) • The SCK2 signal is only required if the target device is running on ‘Internal RC Oscillator’ and there is no external oscillator on the Target System. • Applying the SCK2 signal to the microcontroller XTAL1 pin allows the device to be programmed at a much higher SPI frequency (e.g. 700 KHz) than would be possible when running of the Internal Oscillator (150 kHz). This makes the overall programming cycle much faster. • The Programming Project must swap from Internal Oscillator to External Oscillator, program the device and then swap back to Internal Oscillator. • The SCK2 signal may be required if the CKSEL bits have been incorrectly programmed on this device. • The SCK2 signal may be required if the CKSEL bits have been incorrectly programmed on this device. ATtiny12 Figure 39 20 ISP Interface Module Version 1.00 27/06/01 6.3 Configuring the PIM SCK2 Output Frequency The SCK2 output frequency is configurable from 62.5 KHz to 8 MHz using the DIP Switch SW1. The range of available frequencies and corresponding DIP switch settings are shown in the table below. The relative ON/OFF positions of SW1 are shown in figure 41. SW1 – SCK2 Clock Frequency DIP Switch settings SW1-1 SW1-2 SW1-3 Frequency ON OFF ON OFF ON OFF ON OFF ON ON OFF OFF ON ON OFF OFF ON ON ON ON OFF OFF OFF OFF 8.0 MHz 4.0 MHz 2.0 MHz 1.0 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz Figure 40 Warning ! DIP Switch SW1 is used to enable the +12V Vpp generator. If you are not using this function, please make sure that DIP Switch SW1 - 4 is in the OFF position. Figure 41 ISP Interface Module Version 1.00 27/06/01 21 6.4 Enabling the PIM SCK2 Output Signal with a PPM The following section details how to use the SCK2 signal generator on the PIM with a PPM (PRO101/104/108) programmer. Fig 42 – PPM connected to Target System via PIM producing SCK2 signal To enable the PIM SCK2 signal: • Set the PIM jumper LK3 to position 2-3. • Connect the SCK2 signal from the PIM to the XTAL1 pin of your target microcontroller. • In your EQTools project, select the <Pre-Program State Machine> tab and select the <AVR + PPM Int Module Rev2 + SCK Osc> state machine and then re-compile your project. • If you now run the programming project, the desired frequency should now be output on the PIM SCK2 pin of J1 and J5 during the programming operation. • The SCK2 signal is gated by the PPM Output 1 signal (OP1) and so will only be present during a programming cycle and will be OFF at all other times. • If you wish to manually ENABLE/DISABLE the SCK2 output for test purposes, this can be achieved by asserting pin 3 of IC U3 HIGH. 22 ISP Interface Module Version 1.00 27/06/01 6.5 Using the FS2000A SCK2 Frequency If you are using the PIM with the FS2000A programmer and you wish to route the SCK2 signal which can be output from this programmer to your Target System, please follow the instructions detailed below. Figure 43 – FS2000A connected to Target System via PIM (FS2000A producing SCK2 signal) To use this configuration: • Set link 3 to position 1-2 on the PIM • Enable the FS2000A SCK2 oscillator by setting the frequency using the DIP Switch SW6 inside the programmer. • Connect the ISP programmer from the FS2000A to the PIM J3 connector. • Connect the SCK2 signal from the PIM to the XTAL1 pin of the Target Microcontroller. • If you now run the programming project, the desired frequency should now be output on the PIM SCK2 pin of J1 and J5 during the programming operation. Please note: The FS2000A will only output the SCK2 signal during an actual programming cycle. The SCK2 pin will be driven HIGH at all other times. ISP Interface Module Version 1.00 27/06/01 23 6.6 ATmega163 + SCK2 The diagram below shows the connections required to In-system Program (ISP) an ATmega163 microcontroller. Figure 44 Please note: The SCK2 signal is only required if the device if there is no external oscillator on your Target System and you wish to program with an SPI frequency > 150 kHz. 24 ISP Interface Module Version 1.00 27/06/01 6.7 ATtiny12 + SCK2 The diagram below shows the connections required to In-system Program (ISP) an ATtiny12/15 microcontroller using the ‘Low Voltage Serial Programming Algorithm’. This is does NOT suitable for programming the ATtiny11/12/15 devices using the ‘High Voltage +12V Vpp - Serial Programming Algorithm’. Figure 45 Please note: The SCK2 signal is only required if the device if there is no external oscillator on your Target System and you wish to program with an SPI frequency > 150 kHz. ISP Interface Module Version 1.00 27/06/01 25 7.0 Signal Test Points 7.1 Overview Please Note: On PP-MODIV2 issue 2 a scope GND point has been added next to J7. Figure 46 Pin No Title Description TP1 SCK-CTL Output signal from PPM used to enable SCK2 on interface module TP2 PPM-OPT Output signal from PPM used to control 12V VPP reset signal TP3 VPP-CTL Output signal from PPM used to control 12V VPP reset signal TP4 P-RESET Output RESET signal from PPM TP5 MOSI Master Out Slave In SPI signal from PPM TP6 SCK1 Serial clock SPI signal from PPM TP7 PPM-IP1 Input Signal 1 to PPM TP8 PPM-IP2 Input Signal 2 to PPM TP9 PPM-IP3 Input Signal 3 to PPM TP10 PPM-IP4 Input Signal 4 to PPM - used to detect auto-start Opto-isolator signal TP11 MISO Master In Slave Out SPI signal to PPM TP18 -PPM-OP5 Negative Output Signal from PPM TP19 PPM-VOUT Programmable output voltage from PPM TP22 SPI_IP Input signal to PPM TP23 GND Ground reference test point TP24 +5V Continuous 5v output from programme TP25 TVCC Target Voltage from target system also used as Input voltage to PPM input/output buffers GND Scope ground point Figure 47 26 ISP Interface Module Version 1.00 27/06/01 8.0 PPM/Target System Power Supply Configuration 8.1 Overview The PPM (PRO101/104/108) is capable of supplying ‘controlled’ power to the Target System during a programming operation. It is also possible to use an external power supply to power the Target System, but this cannot be controlled (i.e. switched on and off) by the PPM. However, the presence of the external Target Vcc can be detected by a circuit on the PIM and can trigger an auto-programming sequence. 8.2 Selecting the Target Power Supply Configuration The following Programmer (PPM) / Target System power supply configurations are possible: Option Link LK4 Figure number Configuration Description 1 CLOSED (Default) Figure 49 2 OPEN Figure 50 PPM powers the Target System The PPM supplies power to the Target System. The Target Vcc is connected to the PPM Vout voltage (PPM J1 pin 20). Target System is independently powered Target System is powered from an external supply. Target Vcc is not connected to PPM Vout. Figure 48 – PPM / Target System Power Supply Configurations To select the required configuration, simply jumper LK4 as detailed in the table above. ISP Interface Module Version 1.00 27/06/01 27 8.2.1 PPM Powers the Target System The diagram below shows LK4 CLOSED allowing the PPM to supply power to the Target System. The Target System must NOT be powered by any other source at the same time as catastrophic damage to the PPM could occur. Figure 49 – Power supplied by PPM. * The switch S1 is shown for reference purposes only. 28 ISP Interface Module Version 1.00 27/06/01 8.2.2 Target System is independently powered The diagram below shows LK4 OPEN so the PPM does NOT supply power to the Target System. The Target System must be powered from an independent source e.g. bench power supply. Figure 50 - Power supplied by an external power supply, auto programming initiated by detection of Target Vcc. Designator Value R17 R7 R8 D2 TR1 22k 47K 220R IN4148 BC337 Figure 51 – Component values for figure 50 Please note: • ZD1 should be a 6.2 Zener diode to protect the PPM Line Driver pins (now fitted as standard on PIM Iss2 V2) • LK4 must be OPEN • LK5 must be CLOSED to allow the PPM to detect the presence of the independent Target power. ISP Interface Module Version 1.00 27/06/01 29 8.3 Protecting the PPM from over-voltage The PPM Line Driver IC’s within the PPM (PRO101) may be damaged if excessive voltages are applied to the Target I/O pins or the TARGET_VCC pin. To help prevent over-voltage damage it is recommended that a 6.2V Zener diode with the highest power rating possible (eg. 650 mW) is placed across the Target Vcc supply. The ‘PIM rev 2 Iss2’ now features this diode on the PCB so you no longer need to add it to your test fixture. Please note: The Zener diode is still required even if the Target System is not powered by the PPM as the TARGET_VCC pin is connected to the PPM Line Driver Vcc pin. 30 ISP Interface Module Version 1.00 27/06/01 9.0 Target System Detection Methods The PPM supports automatic detection of the presence of the Target System by sensing a suitable load across the PPM_ V_OUT pin and ground. This can be used to automatically initiate an auto-program operation. The PPM Interface Module supports the following methods of Target System detection as detailed in the table below. Please refer to the relevant section for further details of each detection method. Section Description 9.1 9.2 9.3 9.4 9.5 Standard Target Load Detection (PPM powers Target System) Push-button Start Bed-of-nails shorting pins detection Presence of Independent Target Power Supply Opto-isolated input start Figure 52 – Target System detection methods ISP Interface Module Version 1.00 27/06/01 31 9.1 Standard Target Load Detection 9.1.1 Overview This configuration allows the PPM to automatically detect the presence of a Target System when connected to the programmer. It is possible to set up a Programming Project using EQTools so that the PPM can detect both the connection and disconnection of the Target System. This configuration requires the minimum of operator intervention as the programmer detects the Target System being connected and then automatically applies power, programs the target device and then removes power at the end of the programming sequence. This scenario can only be used when the PPM is powering the Target System. 9.1.2 Circuit Implementation To use this configuration LNK 4 must be inserted on the PIM. This allows the Target System to be powered by the PPM. The Target Vcc should be connected to the T_VCC connection on J4 or to ‘Target Vcc’ on J1 or J2. Figure 53 - Power supplied by PPM. Programming initiated by auto detection of target load. 9.1.3 EQTools Project / Script Implementation In order for the PPM to automatically detect the connection/disconnection of the Target System, it is necessary to set up a Programming Project and Script within EQTools as follows: 32 ISP Interface Module Version 1.00 27/06/01 9.1.3.1 EQTools – Programming Project Setup The EQTools project must be set up as follows: i. Set up so that the PPM Powers the Target System/Interface Module ii. Set up the required voltage and current for your Target System iii. Measure and set up the ‘Target Connect’ and ‘Target Disconnect’ voltages for your Target System iv. Enable ‘Detect Target Connect’ and ‘Detect Target Disconnect’ on the <Entry/Exit> tab of your Programming Project. 9.1.3.2 EQTools – Script File Setup The EQTools Script File must be set up as follows: i. ii. In the <Base Project> and <Target Autoprogram1> tabs, select the required Programming Project which you have just created In the <Target Connection and Disconnection> tab, select ‘PPM Auto-connect -> PPM Auto-disconnect’ 9.1.4 Running the Script/Project Files Once you have created the require Programming Project and Script File, these can then be tested with EQTools or ISP-PRO as follows: i. Make sure the Target System is NOT connected to the programmer ii. Run the Script File à The Connect Icon should appear iii. Connect the Target System to the PIM à The PPM should detect the presence of the Target System and the icon should change to the ‘Auto-Program’ icon. iv. When the programming sequence is complete (PASS or FAIL), either the PASS or FAIL DISCONNECT icons will be displayed. v. Remove the Target System à The PPM should detect the removal of the Target System and the ‘Connect’ icon should reappear. ISP Interface Module Version 1.00 27/06/01 33 9.2 Push Button (SI) Start 9.2.1 Overview This configuration allows a PPM programming project to be initiated by the operator pressing the push-button switch <S1> on the PIM. 9.2.2 Circuit Implementation To use this configuration LNK 4 must be inserted on the PIM. This allows the Target System to be powered by the PPM. The Target Vcc should be connected to the T_VCC connection on J4 or to ‘Target Vcc’ on J1 or J2. Figure 54 - Power supplied by PPM. Programming initiated by a manual switch. 9.2.3 EQTools Project / Script Implementation In order for the PPM to detect pressing of the switch (S1) and disconnection of the Target System, it is necessary to set up a Programming Project and Script within EQTools as follows: 9.2.3.1 EQTools – Programming Project Setup The EQTools project must be set up as follows: i. Set up so that the PPM Powers the Target System/Interface Module ii. Set up the required voltage and current for your Target System iii. Measure and set up the ‘Target Connect’ and ‘Target Disconnect’ voltages for your Target System iv. Enable ‘Detect Target Connect’ and ‘Detect Target Disconnect’ on the <Entry/Exit> tab of your Programming Project. 34 ISP Interface Module Version 1.00 27/06/01 9.2.3.2 EQTools – Script File Setup The EQTools Script File must be set up as follows: i. ii. In the <Base Project> and <Target Autoprogram1> tabs, select the required Programming Project which you have just created In the <Target Connection and Disconnection> tab, select ‘PPM Auto-connect -> PPM Auto-disconnect’ 9.2.4 Running the Script / Project Files Once you have created the require Programming Project and Script File, these can then be tested with EQTools or ISP-PRO as follows: i. Make sure the Target System is NOT connected to the programmer ii. Run the Script File à The Connect Icon should appear iii. Connect the Target System to the PIM à The PPM should remain in the <Connect> state. iv. Press the switch S1 and release when the Autoprogram icon appears. v. When the programming sequence is complete (PASS or FAIL), either the PASS or FAIL DISCONNECT icons will be displayed. vi. Remove the Target System à The PPM should detect the removal of the Target System and the ‘Connect’ icon should reappear. ISP Interface Module Version 1.00 27/06/01 35 9.3 Bed-of-Nails shorting pins detection 9.3.1 Overview This configuration allows a PPM programming project to be initiated by the contact of the Target System on a bed of nails test fixture. 9.3.2 Circuit Implementation To use this configuration LNK 4 must NOT be inserted on the PIM. The Target System is powered by an external power supply. R1 should be connected to VOUT on J5 on the PIM. The Target Vcc should be connected to the T_VCC connection on J4 or to ‘Target Vcc’ on J1 or J2. Figure 55 - Power supplied by an external power supply, auto detection of target using a ‘bed of nails’ test fixture. Please note: • ZD1 should be a 6.2V Zener diode to protect the PPM Line Driver pins (now fitted as standard on PIM Iss2 V2) • R1 should be 220 ohms 9.3.3 EQTools Project / Script Implementation In order for the PPM to automatically detect the connection/disconnection of the Target System, it is necessary to set up a Programming Project and Script within EQTools as follows: 36 ISP Interface Module Version 1.00 27/06/01 9.3.3.1 EQTools – Programming Project Setup The EQTools project must be set up as follows: i. Set up so that the PPM Powers the Target System/Interface Module ii. Set up the target power supply voltage to +5V and set the current to eg. 100mA iii. Measure and set up the ‘Target Connect’ and ‘Target Disconnect’ voltages for your Target System iv. Enable ‘Detect Target Connect’ and ‘Detect Target Disconnect’ on the <Entry/Exit> tab of your Programming Project. 9.3.3.2 EQTools – Script File Setup The EQTools Script File must be set up as follows: i. ii. In the <Base Project> and <Target Autoprogram1> tabs, select the required Programming Project which you have just created In the <Target Connection and Disconnection> tab, select ‘PPM Auto-connect -> PPM Auto-disconnect’ 9.3.4 Running the Script / Project Files Once you have created the require Programming Project and Script File, these can then be tested with EQTools or ISP-PRO as follows: i. ii. Make sure the Target System is NOT connected to the programmer Run the Script File à The Connect Icon should appear iii. Place your Target system onto the bed of nails à The PPM should detect the presence of the Target System and the icon should change to the ‘Auto-Program’ icon. iv. When the programming sequence is complete (PASS or FAIL), either the PASS or FAIL DISCONNECT icons will be displayed. v. Remove the Target System from the Bed-of-nails à The PPM should detect the removal of the Target System and the ‘Connect’ icon should reappear. ISP Interface Module Version 1.00 27/06/01 37 9.4 Presence of Independent Target Power Supply 9.4.1 Overview This configuration allows a PPM programming project to be initiated by the programmer sensing the presence of the Target Supply Voltage. 9.4.2 Circuit Implementation To use this configuration LNK4 must NOT be inserted on the PIM and a LNK5 must be inserted. The circuit comprising of R7/R8/R17, D2 & TR1 asserts the PPM_V_OUT pin LOW when a suitable Target Voltage is applied to the PIM. This detection method allows an Autoprogram sequence to be triggered when the Target Vcc is applied. Once the programming sequence has finished and the Target Vcc is manually removed, the PIM will allow the PPM_V_OUT pin to go HIGH, thus ending the programming sequence. The Target Vcc should be connected to the T_VCC connection on J4 or to ‘Target Vcc’ on J1 or J2. Figure 56 - Power supplied by an external power supply when target draws insufficient current to initiate direct sensing of target. Designator Value R17 R7 R8 D2 TR1 22k 47K 220R IN4148 BC337 Figure 57 – Component values for figure 56 Please note: • 38 ZD1 should be a 6.2V Zener diode to protect the PPM Line Driver pins (now fitted as standard on PIM Iss2 V2) ISP Interface Module Version 1.00 27/06/01 9.4.3 EQTools Project / Script Implementation In order for the PPM to automatically detect the Target System Vcc Voltage, it is necessary to set up a Programming Project and Script within EQTools as follows: 9.4.3.1 EQTools – Programming Project Setup The EQTools project must be set up as follows: i. Set up so that the PPM Powers the Target System/Interface Module ii. Set up the target power supply voltage to +5V and set the current to eg. 100mA iii. Measure and set up the ‘Target Connect’ and ‘Target Disconnect’ voltages for your Target System iv. Enable ‘Detect Target Connect’ and ‘Detect Target Disconnect’ on the <Entry/Exit> tab of your Programming Project. 9.4.3.2 EQTools – Script File Setup The EQTools Script File must be set up as follows: i. ii. In the <Base Project> and <Target Autoprogram1> tabs, select the required Programming Project which you have just created In the <Target Connection and Disconnection> tab, select ‘PPM Auto-connect -> PPM Auto-disconnect’ 9.4.4 Running the Script/Project Files Once you have created the require Programming Project and Script File, these can then be tested with EQTools or ISP-PRO as follows: i. ii. iii. iv. v. vi. vii. Make sure the Target System is NOT connected to the programmer Run the Script File à The Connect Icon should appear. Connect the Target System to the PIM Switch on the external Target Power Supply à The PPM should detect the presence of the Target Vcc Voltage and the icon should change to the ‘Auto-Program’ icon. When the programming sequence is complete (PASS or FAIL), either the PASS or FAIL DISCONNECT icons will be displayed. Switch off the external Target Power Supply à The PPM should detect the absence of the Target Vcc and the <Connect> icon should reappear. Remove the Target System ISP Interface Module Version 1.00 27/06/01 39 9.5 Opto-Isolated input start 9.5.1 Overview This configuration allows a PPM programming project to be initiated by an external voltage being applied to J6. e.g. a voltage derived from the test fixture. 9.5.2 Circuit Implementation To use this configuration LNK 4 must be inserted on the PIM. This allows the Target System to be powered by the PPM. The Target Vcc should be connected to the T_VCC connection on J4 or to ‘Target Vcc’ on J1 or J2. The circuit comprising of R1, R2, R3, U1 & D1 senses the presence of an isolated voltage applied to connector J6. This voltage can be used to trigger the start and end of an auto-programming sequence. To use this method requires a DC voltage in the range of +15 to +30V applied to connector J6. If you require an input voltage outside of this range then R1 can be changed accordingly. Figure 58 - Opto-Isolated Auto-Program Start Designator Value D1 R1 R2 R3 U1 1N4148 1K5 1K5 4K7 6N136 Figure 59 – Component values for figure 60 Please note: • 40 ZD1 should be a 6.2V Zener diode to protect the PPM Line Driver pins (now fitted as standard on PIM Iss2 V2) ISP Interface Module Version 1.00 27/06/01 9.5.3 EQTools Project/Script Implementation In order for the PPM to automatically detect the connection/disconnection of the Target System, it is necessary to set up a Programming Project and Script within EQTools as follows: 9.5.3.1 EQTools – Programming Project Setup We regret that this feature is not yet implemented within EQTools. Please contact Equinox for further information. ISP Interface Module Version 1.00 27/06/01 41