IS61LV6416 IS61LV6416L ISSI 64K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES ® OCTOBER 2003 DESCRIPTION The ISSI IS61LV6416/IS61LV6416L is a high-speed, • High-speed access time: 8, 10, 12 ns • CMOS low power operation — 61LV6416: 75 mW (typical) operating current 0.5 mW (typical) standby current — 61LV6416L: 65 mW (typical) operating current 50 µW (typical) standby current • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available 1,048,576-bit static RAM organized as 65,536 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV6416/IS61LV6416L is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER 64K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE UB LB CONTROL CIRCUIT Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. Rev. C 10/14/03 1 ISSI IS61LV6416 IS61LV6416L ® PIN CONFIGURATIONS 44-Pin TSOP-II (T) 44-Pin SOJ (K) A15 1 44 A0 A14 2 43 A1 A13 3 42 A2 A12 4 41 OE A11 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 VDD 11 34 GND GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A10 18 27 A3 A9 19 26 A4 A8 20 25 A5 A7 21 24 A6 NC 22 23 NC A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 48-Pin mini BGA (6mm x 8mm) (B) 1 2 2 3 4 5 6 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS A0-A15 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 UB Upper-byte Control (I/O8-I/O15) D GND I/O11 NC A7 I/O3 VDD NC No Connection E VDD I/O12 NC NC I/O4 GND VDD Power F I/O14 I/O13 A14 A15 I/O5 I/O6 GND Ground G I/O15 NC A12 A13 WE I/O7 H NC A9 A10 A11 NC A8 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC Integrated Silicon Solution, Inc. Rev. C 10/14/03 ISSI IS61LV6416 IS61LV6416L ® TRUTH TABLE Mode Not Selected Output Disabled Read Write WE CE OE LB UB X H X H H H L L L H L L L L L L L L X H X L L L X X X X X H L H L L H L X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN 1 VDD Current ISB1, ISB2 ICC 2 ICC 3 ICC 4 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to VDD+0.5 –65 to +150 1.5 20 Unit V °C W mA 5 6 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD (8,10 ns) 3.3V+10%,-5% 3.3V+10%,-5% 8 VDD (12 ns) 3.3V ± 10% 3.3V ± 10% 9 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage(1) ILI Input Leakage ILO Output Leakage 10 Min. Max. Unit VDD = Min., IOH = –4.0 mA 2.4 — V VDD = Min., IOL = 8.0 mA — 0.4 V 2 VDD + 0.3 V –0.3 0.8 V GND ≤ VIN ≤ VDD –2 2 µA GND ≤ VOUT ≤ VDD, Outputs Disabled –2 2 µA 11 12 Notes: 1. VIL (min.) = –2.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. Rev. C 10/14/03 3 ISSI IS61LV6416 IS61LV6416L ® IS61LV6416 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. Symbol Parameter Test Conditions Unit ICC VDD Dynamic Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. typ.(2) — — — 140 150 105 — — — 120 130 95 — — — 100 110 75 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 Com. Ind. — — 15 20 — — 15 20 — — 15 20 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) — — — 5 10 0.5 — — — 5 10 0.5 — — — 5 10 0.5 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested. IS61LV6416L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns Min. Max. -10 ns Min. Max. Symbol Parameter Test Conditions Unit ICC VDD Dynamic Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. typ.(2) — — — 100 110 75 — — — 95 105 70 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 Com. Ind. — — 15 20 — — 15 20 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) — — — 1 1.5 0.05 — — — 1 1.5 0.05 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested. CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. 4 Integrated Silicon Solution, Inc. Rev. C 10/14/03 ISSI IS61LV6416 IS61LV6416L ® AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V 1 2 See Figures 1a and 1b AC TEST LOADS 3 319 Ω 319 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF Including jig and scope 353 Ω 4 5 pF Including jig and scope Figure 1a. 5 353 Ω 6 Figure 1b. 7 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -8 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. Unit tRC Read Cycle Time 8 — 10 — 12 — ns tAA Address Access Time — 8 — 10 — 12 ns tOHA Output Hold Time 3 — 3 — 3 — ns tACE CE Access Time — 8 — 10 — 12 ns OE Access Time — 5 — 5 — 6 ns (2) tHZOE OE to High-Z Output — 5 — 5 — 6 ns tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — ns tHZCE(2 CE to High-Z Output 0 4 0 5 0 6 ns tLZCE CE to Low-Z Output 3 — 3 — 3 — ns tBA LB, UB Access Time — 6 — 6 — 6 ns tHZB LB, UB to High-Z Output 0 4 0 5 0 6 ns tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns tDOE (2) 8 9 10 11 12 Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. Rev. C 10/14/03 5 ISSI IS61LV6416 IS61LV6416L ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tHZOE tDOE CE tLZOE tACE tHZCE tBA tHZB tLZCE LB, UB DOUT HIGH-Z tLZB DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 6 Integrated Silicon Solution, Inc. Rev. C 10/14/03 ISSI IS61LV6416 IS61LV6416L ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -8 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. tWC Write Cycle Time 8 — 10 — 12 — ns tSCE CE to Write End 6 — 8 — 9 — ns tAW Address Setup Time to Write End 8 — 8 — 9 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPBW LB, UB Valid to End of Write 7 — 8 — 9 — ns tPWE1/tPWE2 WE Pulse Width (OE = HIGH/LOW) 6 — 8 — 9 — ns tSD Data Setup to Write End 6 — 6 — 6 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output — 4 — 5 — 6 ns tLZWE WE HIGH to Low-Z Output 3 — 3 — 3 — ns (2) 1 Unit 2 3 4 5 Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. Rev. C 10/14/03 7 ISSI IS61LV6416 IS61LV6416L ® WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR1.eps 8 Integrated Silicon Solution, Inc. Rev. C 10/14/03 ISSI IS61LV6416 IS61LV6416L ® WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS 1 VALID ADDRESS t HA OE CE 2 LOW 3 t AW t PWE1 WE t SA t PBW 4 UB, LB t HZWE DOUT t LZWE 5 HIGH-Z DATA UNDEFINED t SD t HD 6 DATAIN VALID DIN UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) 7 t WC ADDRESS 8 VALID ADDRESS OE LOW CE LOW t HA 9 t AW t PWE2 10 WE t SA t PBW 11 UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN 12 t HD DATAIN VALID UB_CEWR3.eps Integrated Silicon Solution, Inc. Rev. C 10/14/03 9 ISSI IS61LV6416 IS61LV6416L ® WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)(1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 10 Integrated Silicon Solution, Inc. Rev. C 10/14/03 ISSI IS61LV6416 IS61LV6416L ® DATA RETENTION SWITCHING CHARACTERISTICS Min. Typ.(1) Max. Unit 2.0 — 3.6 V — — 0.5 0.05 10 1.5 mA See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time IS61LV6416 IS61LV6416L 1 2 Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. O 3 4 DATA RETENTION WAVEFORM (CE Controlled) 5 tSDR Data Retention Mode tRDR 6 VDD 7 VDR CE GND CE ≥ VDD - 0.2V 8 9 10 11 12 Integrated Silicon Solution, Inc. Rev. C 10/14/03 11 ISSI IS61LV6416 IS61LV6416L ® IS61LV6416 ORDERING INFORMATION Speed (ns) Order Part No. Package Temperature Range 8 8 8 IS61LV6416-8T IS61LV6416-8BI IS61LV6416-8TI Plastic TSOP mini BGA (6mm x 8mm) Plastic TSOP Commercial (0°C to +70°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) 10 10 10 10 10 10 IS61LV6416-10T IS61LV6416-10B IS61LV6416-10K IS61LV6416-10BI IS61LV6416-10TI IS61LV6416-10KI Plastic TSOP mini BGA (6mm x 8mm) 400-mil Plastic SOJ mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ Commercial (0°C to +70°C ) Commercial (0°C to +70°C ) Commercial (0°C to +70°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) 12 12 12 12 12 12 IS61LV6416-12B IS61LV6416-12T IS61LV6416-12K IS61LV6416-12BI IS61LV6416-12TI IS61LV6416-12KI mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ Commercial (0°C to +70°C ) Commercial (0°C to +70°C ) Commercial (0°C to +70°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) Order Part No. Package Temperature Range 8 8 8 8 IS61LV6416L-8T IS61LV6416L-8BI IS61LV6416L-8TI IS61LV6416L-8KI Plastic TSOP mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ Commercial (0°C to +70°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) 10 10 10 10 IS61LV6416L-10T IS61LV6416L-10BI IS61LV6416L-10TI IS61LV6416L-10KI Plastic TSOP mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ Commercial (0°C to +70°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) Industrial (-40°C to +85°C ) IS61LV6416L ORDERING INFORMATION Speed (ns) 12 Integrated Silicon Solution, Inc. Rev. C 10/14/03 ISSI ® PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View Bottom View φ b (48x) 1 2 3 4 5 6 6 A 4 3 2 1 A e B B C C D D D 5 D1 E E F F G G H H e E E1 A2 Notes: 1. Controlling dimensions are in millimeters. A A1 SEATING PLANE mBGA - 6mm x 8mm mBGA - 8mm x 10mm MILLIMETERS INCHES MILLIMETER Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 Sym. Min. Typ. Max. N0. Leads 48 INCHES Min. Typ. Max. A — — 1.20 — — 0.047 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — A2 0.60 — — 0.024 — — D 7.90 — 8.10 0.311 — 0.319 D 9.90 — 10.10 0.390 — 0.398 D1 E 5.25 BSC 5.90 — 6.10 0.207 BSC 0.232 — 0.240 D1 E 5.25 BSC 7.90 — 0.207 BSC 8.10 0.311 — 0.319 E1 3.75 BSC 0.148 BSC E1 3.75 BSC 0.148 BSC e 0.75 BSC 0.030 BSC e 0.75 BSC 0.030 BSC 0.012 0.014 0.016 b b 0.30 0.35 0.40 0.30 0.35 0.40 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 ISSI PACKAGING INFORMATION ® K-400 mil SOJ PACKAGE OUTLINE N Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027. N/2+1 E1 1 E N/2 SEATING PLANE D b A C A2 e B A1 E2 400-mil Plastic SOIC (J-bend) (K) Ref. Std. 28 No. Leads (N) inch mm Symbol Min Max Min Max A 0.128 0.148 3.250 3.750 MS-027 32 36 inch Min Max 0.128 1.048 mm Min Max 3.250 3.750 inch Min Max 0.128 1.048 mm Min Max 3.250 3.750 A1 0.025 — 0.635 — 0.025 — 0.635 — 0.025 — 0.635 — A2 0.082 — 2.080 — 0.082 — 2.080 — 0.082 — 2.080 — B 0.015 0.020 0.380 0.510 0.015 0.020 0.380 0.510 0.015 0.020 0.380 0.510 b 0.026 0.032 0.660 0.810 0.026 0.032 0.660 0.810 0.026 0.032 0.660 0.810 C 0.007 0.013 0.180 0.330 0.007 0.013 0.180 0.330 0.007 0.013 0.180 0.330 D 0.720 0.730 18.29 18.54 0.820 0.830 20.82 21.08 0.920 0.930 23.37 23.62 E 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 E1 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 E2 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC e 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 10/03/02 ISSI PACKAGING INFORMATION ® 400-mil Plastic SOIC (J-bend) (K) Ref. Std. 40 No. Leads (N) inch mm Sym bol Min M ax Min Max A 0.128 0.148 3.250 3.750 MS-027 42 44 inch M in Max 0.128 1.048 mm Min Max 3.250 3.750 inch M in Max 0.128 1.048 mm Min Max 3.250 3.750 A1 0.025 — 0.635 — 0.025 — 0.635 — 0.025 — 0.635 — A2 0.082 — 2.080 — 0.082 — 2.080 — 0.082 — 2.080 — B 0.015 0.020 0.380 0.510 0.015 0.020 0.380 0.510 0.015 0.020 0.380 0.510 b 0.026 0.032 0.660 0.810 0.026 0.032 0.660 0.810 0.026 0.032 0.660 0.810 C 0.007 0.013 0.180 0.330 0.007 0.013 0.180 0.330 0.007 0.013 0.180 0.330 D 1.020 1.030 25.91 26.16 1.070 1.080 27.18 27.43 1.120 1.130 28.45 28.70 E 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 E1 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 E2 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC e 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 10/03/02 ISSI ® PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) N N/2+1 E1 1 Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. E N/2 D SEATING PLANE A ZD . b e Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° L α A1 Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° Millimeters Min Max C Inches Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03