MDTIC MDT10P55

深圳市美芯微电子有限公司 麦肯单片机授权一级代理商
电话:0755-36857609/27945551/29491882
地址;深圳市宝安区宝源路名优产品采购中心B1区721室
MDT10P55B
u
Power-on Reset
u
Power edge-detector Reset
This EPROM-Based 8-bit micro-controller uses a fully
u
Sleep Mode for power saving
static CMOS technology process to achieve higher
u
5 types of oscillator can be selected by
1. General Description
speed
and
smaller
size
with
the
low
power
programming option:
consump-tion and high noise immunity. On chip
INTRC-Internal 4 MHz RC oscillator
memory inclu-des 1K words of ROM, and 72 bytes of
RC-Low cost RC oscillator
static RAM.
LFXT-Low frequency crystal oscillator
XTAL-Standard crystal oscillator
2. Features
HFXT-High frequency crystal oscillator
u
The followings are some of the features on the
3 oscillator start-up time can be selected by
hardware and software :
programming option:
u
Fully CMOS static design
20 ms, 40 ms, 80 ms
u
8-bit data bus
u
On chip EPROM size : 1K words
u
Internal RAM size : 72 bytes
u
36 single word instructions
u
14-bit instructions
u
2-level stacks
u
Operating voltage : 2.5 V ~ 5.5 V
u
Operating frequency : 0 ~ 20 MHz
u
The most fast execution time is 200 ns under
The application areas of this MDT10P55B range
20 MHz in all single cycle instructions except
from appliance motor control and high speed
the branch instruction
automotive to low power remote
Addressing modes include direct, indirect and
transmitters/receivers, small instruments, chargers,
relative addressing modes
toy, automobile and PC pe-ripheral … etc.
u
u
8-bit real time clock/counter(RTCC) with 8-bit
programmable prescaler
u
On-chip RC oscillator based Watchdog
Timer(WDT)
u
Wake-up from sleep on pin change
3. Applications
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P. 1
2005/6 Ver. 1.2
MDT10P55B
4. Pin Assignment
MDT10P55B3P/MDT10P55B3S
MDT10P55B1P/MDT10P55B1S
VDD
PB5
PB4
PB3
PC5/RTCC
PC4
PC3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
PB5
PB4
/MCLR
PC5/RTCC
PC4
PC3
VSS
PB0
PB1
PB2
PC0
PC1
PC2
1
2
3
4
5
6
7
14
12
12
11
10
9
8
14
13
12
11
10
9
8
VSS
PB0
PB1
PB2
PC0
PC1
PC2
MDT10P55B4P/MDT10P55B4S
MDT10P55B2P/MDT10P55B2S
VDD
OSC1
OSC2/PB4
PB3
PC5/RTCC
PC4
PC3
1
2
3
4
5
6
7
VDD
OSC1
OSC2/PB4
/MCLR
PC5/RTCC
PC4
PC3
VSS
PB0
PB1
PB2
PC0
PC1
PC2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VSS
PB0
PB1
PB2
PC0
PC1
PC2
5. Pin Function Description
Pin Name
I/O
Function Description
PB5~0
I/O
Port B, TTL input level,PB3 input only.
PC4~0
I/O
Port C, TTL input level
PC5/RTCC
I/O
Real Time Clock/Counter, Schmitt Trigger input levels
/MCLR
I
Master Clear, Schmitt Trigger input levels
OSC1
I
Oscillator Input
OSC2
O
Oscillator Output
Vdd
Power supply
Vss
Ground
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P. 2
2005/6 Ver. 1.2
MDT10P55B
6. Memory Map
(A) Register Map
Address
Description
00
Indirect Addressing Register
01
RTCC
02
PC
03
STATUS
04
MSR
06
Port B
07
Port C
08~1F
30~3F
General purpose registers
50~5F
70~7F
(1)IAR ( Indirect Address Register) : R0
(2) RTCC (Real Time Counter/Counter Register) : R1
(3) PC (Program Counter) : R2
Write PC, CALL --- always 0
JUMP --- from instruction word
RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5
RTWI, RET --- from STACK
Write PC --- from ALU
JUMP, CALL --- from instruction word
RTWI, RET --- from STACK
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P. 3
2005/6 Ver. 1.2
MDT10P55B
(4) STATUS (Status register) : R3
Bit
Symbol
Function
0
C
Carry bit
1
HC
Half Carry bit
2
Z
Zero bit
3
PF
Power down bit
4
TF
WDT Timer overflow Flag bit
5
PAGE
ROM page select bit
6
——
Unimplemented
7
PCWUF
Pin change wake up from sleep
(5) MSR (Memory Bank Select Register) : R4
b7
b6
Read only “1”
b5
b4
b3
b2
b1
BANK Select
Indirect Addressing Mode
(6) PORT B : R6
PB5~PB0, I/O Register ,PB3 input only.
(7) PORT C: R7
PC5~PC0, I/O Register
(8) TMR (Time Mode Register)
Bit
Symbol
Function
Prescaler Value
2—0
3
PS2—0
PSC
RTCC rate
WDT rate
0 0 0
1:2
1:1
0 0 1
1:4
1:2
0
1:8
1:4
0 1 1
1 : 16
1:8
1 0 0
1 : 32
1 : 16
1 0 1
1 : 64
1 : 32
1 1 0
1 : 128
1 : 64
1 : 256
1 : 128
1 0
1 1 1
Prescaler assignment bit :
0 — RTCC
1 — Watchdog Timer
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P. 4
2005/6 Ver. 1.2
b0
MDT10P55B
Bit
Symbol
4
TCE
5
TCS
6
PBPHB
7
PBWUB
Function
RTCC signal Edge :
0 — Increment on low-to-high transition on RTCC pin
1 — Increment on high-to-low transition on RTCC pin
RTCC signal set :
0 — Internal instruction cycle clock
1 — Transition on RTCC pin
PortB pull-high :(RB0,RB1,RB3,RB4)
0 — Enable
1 — Disable
PortB wake-up : (RB0,RB1,RB3,RB4)
0 — Enable
1 — Disable
(9) CPIO B ,CPIO C (Control Port I/O Mode Register)
The CPIO register is “write-only”
=“0”, I/O pin in output mode;
=“1”, I/O pin in input mode.
(10) Configurable options for EPROM (Set by writer) :
Oscillator Type
Oscillator Start-up Time
INTRC Oscillator
RC
20ms,40ms,80ms
Oscillator
20ms,40ms,80ms
HFXT Oscillator
20 ms,40ms,80ms
XTAL Oscillator
20ms,40 ms,80ms
LFXT Oscillator
20ms,40 ms,80 ms
Watchdog Timer control
Watchdog timer disable all the time
Watchdog timer enable all the time
Security state
Security Disable
Security Enable
The default security state of EPROM is weak disable. Once the IC was set to
enable or disable, it’s forbidden to change.
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P. 5
2005/6 Ver. 1.2
MDT10P55B
(B) Program Memory
Address
Description
000-3FF
Program memory
000
The starting address of power on, external reset or WDT time-out reset.
8. Reset Condition for all Registers
Register
Address
Power-On Reset
/MCLR Reset
WDT Reset
CPIO B
--
--11 1111
--111 1111
--11 1111
CPIO C
--
--11 1111
--11 1111
--11 1111
TMR
--
1111 1111
1111 1111
--11 1111
IAR
00h
xxxx xxxx
uuuu uuuu
uuuu uuuu
RTCC
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PC
02h
0000 0000
0000 0000
0000 0000
STATUS
03h
0001 1xxx
#00# #uuu
#00# #uuu
MSR
04h
110x xxxx
11uu uuuu
11uu uuuu
PORT B
06h
--xx xxxx
--uu uuuu
--uu uuuu
PORT C
07h
--xx xxxx
--uu uuuu
--uu uuuu
Note : u=unchanged, x=unknown, - =unimplemented, read as “0”
#=value depends on the condition of the following table
Condition
Status: bit 7
Status: bit 4
Status: bit 3
/MCLR reset (not during SLEEP)
0
u
u
/MCLR reset during SLEEP
0
1
0
WDT reset (not during SLEEP)
0
0
1
WDT reset during SLEEP
0
0
0
Wake-up from SLEEP on pin change
1
1
0
9. Instruction Set :
Mnemonic
Operands
Instruction Code
Function
Operating
Status
010000 00000000
NOP
No operation
None
010000 00000001
CLRWT
Clear Watchdog timer
0→WT
TF, PF
010000 00000010
SLEEP
Sleep mode
0→WT, stop OSC
TF, PF
010000 00000011
TMODE
Load W to TMODE register
W→TMODE
None
010000 00000100
RET
Return
Stack→PC
None
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P. 6
2005/6 Ver. 1.2
MDT10P55B
Mnemonic
Operands
Instruction Code
Function
Operating
Status
010000 00000rrr
CPIO R
Control I/O port register
W→CPIO r
None
010001 1rrrrrrr
STWR R
Store W to register
W→R
None
011000 trrrrrrr
LDR R, t
Load register
R→t
Z
111010 iiiiiiii
LDWI I
Load immediate to W
I→W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3) ↔R(4~7)]
→t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1→t
Z
011010 trrrrrrr
INCRSZ R, t
Increment register, skip if zero
R + 1→t
None
011011 trrrrrrr
ADDWR R, t
Add W and register
W + R→t
C, HC, Z
011100 trrrrrrr
SUBWR R, t
Subtract W from register
R ﹣W→t or
(R+/W+1→t)
C, HC, Z
011101 trrrrrrr
DECR R, t
Decrement register
R ﹣1→t
Z
011110 trrrrrrr
DECRSZ R, t
Decrement register, skip if zero
R ﹣1→t
None
010010 trrrrrrr
ANDWR R, t
AND W and register
R ∩ W→t
Z
110100 iiiiiiii
ANDWI i
AND W and immediate
i ∩ W→W
Z
010011 trrrrrrr
IORWR R, t
Inclu. OR W and register
R ∪ W→t
Z
110101 iiiiiiii
IORWI i
Inclu. OR W and immediate
i ∪ W→W
Z
010100 trrrrrrr
XORWR R, t
Exclu. OR W and register
R ♁ W→t
Z
110110 iiiiiiii
XORWI i
Exclu. OR W and immediate
i ♁ W→W
Z
011111 trrrrrrr
COMR R, t
Complement register
/R→t
Z
010110 trrrrrrr
RRR
Rotate right register
R(n) →R(n-1),
C
R, t
C→R(7), R(0)→C
010101 trrrrrrr
RLR
R, t
Rotate left register
R(n)→r(n+1),
C
C→R(0), R(7)→C
010000 1xxxxxxx
CLRW
Clear working register
0→W
Z
010001 0rrrrrrr
CLRR
Clear register
0→R
Z
0000bb brrrrrrr
BCR
R, b
Bit clear
0→R(b)
None
0010bb brrrrrrr
BSR
R, b
Bit set
1→R(b)
None
0001bb brrrrrrr
BTSC R, b
Bit Test, skip if clear
Skip if R(b)=0
None
0011bb brrrrrrr
BTSS R, b
Bit Test, skip if set
Skip if R(b)=1
None
1000nn nnnnnnnn
LCALL n
Long CALL subroutine
n→PC,
None
R
PC+1→Stack
1010nn nnnnnnnn
LJUMP n
Long JUMP to address
n→PC
None
110000 nnnnnnnn
CALL
Call subroutine
n→PC,
None
n
PC+1→Stack
110001 iiiiiiii
RTWI
11001n nnnnnnnn
JUMP
i
n
Return, place immediate to W
Stack→PC,i→W
None
JUMP to address
n→PC
None
Note :
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P. 7
2005/6 Ver. 1.2
MDT10P55B
W
WT
TMODE
CPIO
TF
PF
PC
OSC
Inclu.
Exclu.
AND
:
:
:
:
:
:
:
:
:
:
:
Working register
Watchdog timer
TMODE mode register
Control I/O port register
Timer overflow flag
Power loss flag
Program Counter
Oscillator
Inclusive ‘∪’
Exclusive ‘♁’
Logic AND ‘∩’
b
t
R
C
HC
Z
/
x
i
n
:
:
0
1
:
:
:
:
:
:
:
:
Bit position
Target
:
Working register
:
General register
General register address
Carry flag
Half carry
Zero flag
Complement
Don’t care
Immediate data ( 8 bits )
Immediate address
10. Oscillator start up timer condition :
Oscillator Type
INTRC,RC
HF,XT,LF
Porwer-on reset
Subsequest resets
20ms,40ms,80ms
300us
20ms,40ms,80ms
20ms,40ms,80ms
11. Electrical Characteristics
*Note: Temperature=25°C
1.Operation Current :
(1) HF (C=10p) , WDT - enable
4M
10M
20M
Sleep
2.5V
250uA
600uA
1.2mA
3.0uA
3.0V
325uA
740uA
1.4mA
8uA
4.0V
400uA
820uA
1.8mA
16uA
5.0V
622uA
1mA
2mA
30uA
6.4V
1mA
1.6mA
2.9mA
42.5uA
These parameters are for reference only.
(2) XT (C=10p) , WDT - enable
1M
4M
10M
Sleep
500uA
1.0uA
2.5V
100uA
280uA
3.0V
185uA
250uA
460uA
10uA
4.0V
280uA
340uA
700uA
15uA
5.0V
400uA
600uA
1mA
30uA
6.4V
900uA
980uA
1.6mA
60uA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview
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P. 8
2005/6 Ver. 1.2
MDT10P55B
(3) RC , WDT – Enable , @Vdd = 5.0V
C
3p
20p
100p
300p
R
Freq.
Current
4.7k
8.2M
1mA
10k
4.2M
630uA
47k
968K
180uA
100k
464K
130uA
300k
156K
114uA
470k
100K
110uA
4.7k
4.9M
630uA
10k
2.5M
360uA
47k
540K
156uA
100k
260K
128uA
300k
84K
112uA
470k
56K
100uA
4.7k
1.76M
300uA
10k
860K
200uA
47k
190K
120uA
100k
90.8K
113uA
300k
30K
97uA
470k
18.8K
97uA
4.7k
776K
170uA
10k
376K
133uA
47k
82K
106uA
100k
39.2K
102uA
300k
12.8K
91uA
470k
8K
85uA
These parameters are for reference only.
(4) LF (C=10p) , WDT - disable
32K
455K
1M
Sleep
2.5V
30uA
X
X
1.0uA
3.0V
60uA
@3.2V,300uA
@3.2V,300uA
1.0uA
4.0V
150uA
450uA
450uA
1.0uA
5.0V
300uA
750uA
750uA
1.0uA
6.4V
750uA
1.2mA
1.2mA
1.0uA
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview
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P. 9
2005/6 Ver. 1.2
MDT10P55B
2. Input Voltage (Vdd = 5V) :
Port
Min
Max
TTL
Vss
1.5V
Schmitt trigger
Vss
1.25V
TTL
2V
Vdd
Schmitt trigger
3V
Vdd
Vil
Vih
These parameters are for reference only.
3. Output Voltage (Vdd = 5V) :
PA,PB
Condition
Voh
3.8V
Ioh =-20mA
Vol
0.8V
Iol =+20mA
Voh
4.3V
Ioh = -5mA
Vol
0.6V
Iol = +5mA
These parameters are for reference only.
4. Output Current (Max.) (Vdd = 5V) :
Port B:
Current
Source current
25mA
Sink current
25mA
These parameters are for reference only.
Port C:
Current
Source current
25mA
sink current
25mA
These parameters are for reference only.
5. The basic WDT time-out cycle time :
Time
2.5V
25ms
3.0V
23ms
4.0V
20ms
5.0V
19ms
6.3V
18ms
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview
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P. 10
2005/6 Ver. 1.2
MDT10P55B
6.
(1)INT_RC,WDT – disable
IC1:
4M
Sleep
3.0V
500uA
1.0uA
4.0V
800A
1.0uA
5.0V
1mA
These parameters are for reference only.
1.0uA
(2)INT_RC,WDT – enable
IC1:
4M
Sleep
3.0V
600uA
5uA
4.0V
1mA
15uA
5.0V
1.2mA
These parameters are for reference only.
30uA
7. Min Operation Voltage :
C =>
10p
20p
30p
XT, 20M
2.5V
2.7V
3V
2.7V
3V
10p
20p
3.2V
3.4V
HF, 20M
2.5V
These parameters are for reference only.
RC, 1k, no cap.
2.2V
These parameters are for reference only.
C =>
0p
LF, 1M
2.8V
These parameters are for reference only.
8. MCLR filter time :
Vdd=5V
time
1000ns
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview
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P. 11
2005/6 Ver. 1.2