MDT2030(CF) 8-bit real time clock/counter(RTCC) with 1. General Description This ROM-Based 8-bit micro-controller uses a 8-bit programmable prescaler fully static CMOS technology process to On-chip RC oscillator based Watchdog achieve high speed, small size, the low power Timer(WDT) and high noise immunity. 12 I/O pins with their own independent On chip memory includes 2K words EPROM, direction control 3. Applications and 80 bytes static RAM. The application areas of this MDT2030 range 2. Features The followings are some of the features on the from appliance motor control and high speed hardware and software : automotive to low power remote transmitters Fully CMOS static design /receivers, pointing devices, and 8-bit data bus telecommunications processors, such as On chip EPROM size : 2.0 K words Remote controller, small instruments, Internal RAM size : 80 bytes chargers, toy, automobile and PC (73 general purpose registers, 7 special peripheral … etc. registers) 4. Pin Assignment DIP / SOP PA2 1 18 PA1 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3 V ~ 6.0 V Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes Power-on Reset (POR),only available while PED is Disable PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 10 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 SSOP PA2 1 20 PA1 Power edge-detector Reset Sleep Mode for power saving 4 types of oscillator can be selected by programming option: RC－Low cost RC oscillator LFXT－Low frequency crystal oscillator XTAL－Standard crystal oscillator HFXT－High frequency crystal oscillator 4 oscillator start-up time can be selected by programming option: 150 μs, 20 ms, 40 ms, 80 ms PA3 RTCC /MCLR VSS VSS PB0 2 3 4 5 6 7 PB1 8 PB2 9 PB3 10 19 18 17 16 15 14 PA0 OSC1 OSC2 VDD VDD PB7 13 PB6 12 PB5 11 PB4 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2007/8 Ver. 1.6 MDT2030(CF) 5. Block Diagram EP RO M S ta ck Two Le ve ls P ort P A0~P A3 4 bits RAM 73X8 2048X14 P ort A 11 bits 14 bits 11 bits P rogra m Counte rs Ins truction Re gis te r S pe cia l Re gis te r OS C2 MCLR OS C1 P ort P B0~P B7 8 bits D0~D7 P ort B Os cilla tor Circuit Ins truction De code r Control Circuit Da ta 8-bit P owe r on Re s e t P owe r Down Re s e t Working Re gis te r S ta tus Re gis te r ALU 8-bit Tim e r/Counte r WDT/OS T Tim e r P re s ca le RTCC This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2007/8 Ver. 1.6 MDT2030(CF) 6. Pin Function Description Pin Name I/O Function Description PA0~PA3 I/O Port A, TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output Vdd Power supply Vss Ground 7. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2007/8 Ver. 1.6 MDT2030(CF) (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 JUMP --- from instruction word RTWI, RET --- from STACK A10 A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b6 b5 RTWI, RET --- from STACK Write PC --- from ALU JUMP, CALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF WDT Timer overflow Flag bit page ROM page select bit : 6—5 00 : Page 0, 000H --- 1FFH 01 : Page 1, 200H --- 3FFH 10 : Page 2, 400H --- 5FFH 11 : Page 3, 600H --- 7FFH 7 —— General purpose bit This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2007/8 Ver. 1.6 MDT2030(CF) (5) MSR (Memory Bank Select Register) : R4 Memory Bank Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only “1” Indirect Addressing Mode (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) TMR (Time Mode Register) Bit Symbol Function Prescaler Value 2—0 PS2—0 3 PSC 4 TCE 5 TCS RTCC rate WDT rate 1:1 1:2 0 0 0 1:2 1:4 0 0 1 1:4 1:8 0 1 0 1:8 1 : 16 0 1 1 1 : 16 1 : 32 1 0 0 1 : 32 1 : 64 1 0 1 1 : 64 1 : 128 1 1 0 1 : 128 1 : 256 1 1 1 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin (9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2007/8 Ver. 1.6 MDT2030(CF) (10) Configurable options for EPROM (Set by writer) : Oscillator Type RC Oscillator Start-up Time 150 μs,20ms,40ms,80ms Oscillator HFXT Oscillator 20 ms,40ms,80ms XTAL Oscillator 20ms,40 ms,80ms LFXT Oscillator 40 ms,80 ms Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power Edge Detect Security state PED Disable Security weak Disable PED Enable Security Disable Security Enable The default security state of EPROM is weak disable. Once the IC was set to enable or disable, it’s forbidden to change. (B) Program Memory Address Description 000-7FF Program memory 7FF The starting address of power on, external reset or WDT time-out reset. 8. Reset Condition for all Registers Register Address Power-On Reset /MCLR or WDT Reset CPIO A －－ 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 TMR －－ --11 1111 --11 1111 IAR 00h － － RTCC 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu MSR 04h 100x xxxx 100u uuuu This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2007/8 Ver. 1.6 MDT2030(CF) Register Address Power-On Reset /MCLR or WDT Reset PORT A 05h - - - - xxxx - - - - uuuu PORT B 06h xxxx xxxx uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) u u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 9. Instruction Set : Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT, stop OSC TF, PF 010000 00000011 TMODE Load W to TMODE register W→TMODE None 010000 00000100 RET Return Stack→PC None 010000 00000rrr CPIO R Control I/O port register W→CPIO r None 010001 1rrrrrrr STWR R Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) ↔R(4~7)] →t None 011001 trrrrrrr INCR R, t Increment register R + 1→t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t or (R+/W+1→t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t Z 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t None 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2007/8 Ver. 1.6 MDT2030(CF) Instruction Code Mnemonic Operands Function Operating Status 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR R, t Rotate right register R(n) →R(n-1), C→R(7), R(0)→C C 010101 trrrrrrr RLR R, t Rotate left register R(n)→r(n+1), C→R(0), R(7)→C C 010000 1xxxxxxx CLRW Clear working register 0→W Z 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1000nn nnnnnnnn LCALL n Long CALL subroutine n→PC, PC+1→Stack None 1010nn nnnnnnnn LJUMP n Long JUMP to address n→PC None 110000 nnnnnnnn CALL n Call subroutine n→PC, PC+1→Stack None 110001 iiiiiiii RTWI i Return, place immediate to W Stack→PC,i→W None 11001n nnnnnnnn JUMP n JUMP to address n→PC None R Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2007/8 Ver. 1.6 MDT2030(CF) 10. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Vdd Operating voltage Min Typ Max Uni t 2.3 6.0 V VIL Input Low Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V -0.6 -0.6 1.0 1.0 V V VIH Input high Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V 2.0 3.3 Vdd Vdd V V IIL Vdd=5V +/-1 µA Input leakage current VOL Output Low Voltage PA, PB VOH Output High Voltage PA, PB Islp Sleep current (WDT disable) Islp Sleep current (WDT enable) Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA 0.5 0.1 V V Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vdd＝2.3 ~ 6.0 V 3.8 4.5 V V Vdd＝2.3 V Vdd＝3.0 V Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 1 3 6 11 17 Vpr Power Edge-detector Reset Voltage 0.1 1.0 μA μA μA μA μA μA 1.1 1.3 V Twdt The basic WDT time-out cycle Vdd＝2.3 V Vdd＝3.0 V time Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 25.2 22.4 20.4 18.8 18.0 mS mS mS mS mS TFLT /MCLR filter Vdd＝5.0 V 600 nS Icc Comparator Supply current (one comparator) Vdd=5.0v 15 μA Vref Input reference voltage Vdd=2.5v ~6.0 V Vdd-0.8 V v This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2007/8 Ver. 1.6 MDT2030(CF) Sym --- Description Condition Comparator Response time V-=Vdd/4, V+=V- ± 0.2v V-=Vdd/2, V+=V- ± 0.2v V-=Vdd3/4, V+=V- ± 0.2v V-=VDD-0.8,V+=V± 0.2v Min Vdd=5.0v , V- = Vref V+ = (PA0~PA3) Typ Max Uni t μS μS μS μS 8 8 8 8 11. Operating Current Temperature＝25 ℃, the typical value as followings : 11.1 OSC Type＝RC ﹔WDT－Enable; @Vdd＝5.0 V﹔ PED=Disable Cext. (F) 3P 20P 100P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 11.2 M 1.2 mA 10.0 K 5.94 M 650 µA 47.0 K 1.40M 235 μA 100.0 K 660 K 165 μA 300.0 K 225 K 140 μA 470.0 K 140 K 120 μA 4.7 K 5.43 M 620 µA 10.0 K 2.74 M 368 μA 47.0 K 622 K 170 μA 100.0 K 295 K 140 μA 300.0 K 100 K 125 μA 470.0 K 64 K 120 μA 4.7 K 1.76 M 292 μA 10.0 K 886 K 205μA 47.0 K 193 K 145 μA 100.0 K 92 K 130 μA 300.0 K 31 K 130 μA 470.0 K 20 K 125 μA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2007/8 Ver. 1.6 MDT2030(CF) Cext. (F) Rext. (Ohm) 300P Frequency (Hz) Current (A) 4.7 K 685 K 192 μA 10.0 K 335 K 156 μA 47.0 K 75 K 133 μA 100.0 K 35 K 130 μA 300.0 K 12 K 126 μA 470.0 K 7K 125 μA 11.2 OSC Type＝LF (OSC1&OSC2 External Cap about 10P); WDT－Disable ; PED=Disable Voltage/Frequency 32 K (Ext100p) 455 K (Ext50P) 1M Sleep 40μA ＜1.0 μA 50μA 68μA ＜1.0 μA 35.0μA 88μA 120μA ＜1.0 μA 5.0 V 72.0μA 142μA 180μA ＜1.0 μA 6.0 V 130.0μA 220μA 260μA ＜1.0 μA 2.3 V 7.0μA 3.0 V 15.0μA 4.0 V [email protected] μA 11.3 OSC Type＝XT (OSC1&OSC2 External Cap about 10P); Voltage/Frequency WDT－Enable ;PED=Disable 1M 4M 10 M Sleep 2.1 V 50μA 120μA 290μA ＜1.0 μA 3.0 V 102μA 235μA 500μA 3 μA 4.0 V 215μA 405μA 650μA 6 μA 5.0 V 378μA 600μA 1.3mA 11 μA 6.0 V 650μA 855μA 1.6mA 17 μA 11.4 OSC Type＝HF (OSC1&OSC2 External Cap about 10P); WDT－Enable ; PED=Disable Voltage/Frequency 4M 10 M 20 M Sleep 2.1 V 150μA 320μA X 3.0 V 288μA 555μA 925μA 3 μA 4.0 V 510μA 910μA 1.5mA 6 μA 5.0 V 800μA 1.5mA 2.3mA 11 μA 6.0 V 1.3mA 1.9mA 3.2mA 17 μA ＜1.0 μA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2007/8 Ver. 1.6 MDT2030(CF) 11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd＝5.0 V (PED:Enable) Vpr≦1.6~1.8 V Vpr ﹕Vdd (Power Supply) PS. If PED_Enable then Internal Power_on_reset will be off 12. Port A and Port B Equivalent Circuit D Q I/O Control C Latch Q K B I/O Control Port I/O Pin D Data O/P Latch Write G Q B Data Bus Read D QB Data I/P Latch G TTL Input Level Input Resistor This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2007/8 Ver. 1.6 MDT2030(CF) 13. MCLRB and RTCC Input Equivalent Circuit MCLRB R≒1K Schmitt Trigger R≒1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2007/8 Ver. 1.6 MDT2030(CF) 14. External Capacitor Selection For Crystal Oscillator @ Vdd＝5.0 V Osc. Type Resonator Freq. Capacity Range 20 MHz 10 pF ~ 50 pF 10 MHz 20 pF ~ 50 pF 4 MHz 10 pF ~ 30 pF 10 MHz 10 pF ~ 50 pF 4 MHz 10 pF ~ 50 pF 1 MHz 20 pF ~50 pF 1 MHz 20 pF ~ 30 pF 455 K 20 pF ~30 pF 32 K 20 pF ~30 pF HF XT LF MDT2030 OSC1 C1 OSC2 C2 To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2007/8 Ver. 1.6