2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs AD5346/AD5347/AD5348 FEATURES GENERAL DESCRIPTION AD5346: octal 8-bit DAC AD5347: octal 10-bit DAC AD5348: octal 12-bit DAC Low power operation: 1.4 mA (max) @ 3.6 V Power-down to 120 nA @ 3 V, 400 nA @ 5 V Guaranteed monotonic by design over all codes Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Readback Buffered/unbuffered reference inputs 20 ns WR time 38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging Temperature range: –40°C to +105°C The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit DACs, operating from a 2.5 V to 5.5 V supply. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, and also allow a choice of buffered or unbuffered reference input. The AD5346/AD5347/AD5348 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. A readback feature allows the internal DAC registers to be read back through the digital port. The GAIN pin on these devices allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF. Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control All three parts are pin compatible, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. FUNCTIONAL BLOCK DIAGRAM VDD AGND VREFAB DGND VREFCD POWER-ON RESET AD5348 BUF INPUT REGISTER DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD INPUT REGISTER DAC REGISTER STRING DAC E BUFFER VOUTE A2 INPUT REGISTER DAC REGISTER STRING DAC F BUFFER VOUTF A1 INPUT REGISTER DAC REGISTER STRING DAC G BUFFER VOUTG INPUT REGISTER DAC REGISTER STRING DAC H BUFFER VOUTH GAIN DB11 . . . DB0 CS RD WR A0 INTERFACE LOGIC POWER-DOWN LOGIC LDAC VREFGH VREFEF 03331-0-001 CLR PD Figure 1. 1 Protected by U.S. Patent No. 5,969,657; other patents pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD5346/AD5347/AD5348 TABLE OF CONTENTS Specifications..................................................................................... 3 Power-On Reset.......................................................................... 17 AC Characteristics............................................................................ 4 Power-Down Mode .................................................................... 17 Timing Characteristics..................................................................... 5 Suggested Data Bus Formats..................................................... 18 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 19 ESD Caution.................................................................................. 6 Typical Application Circuits ..................................................... 19 AD5346 Pin Configurations and Function Descriptions ........... 7 Driving VDD from the Reference Voltage................................. 19 AD5347 Pin Configurations and Function Descriptions ........... 8 Bipolar Operation Using the AD5346/AD5347/AD5348..... 19 AD5348 Pin Configurations and Function Descriptions ........... 9 Decoding Multiple AD5346/AD5347/AD5348s.................... 20 Terminology .................................................................................... 10 AD5346/AD5347/AD5348 as Digitally Programmable Window Detectors ...................................................................... 20 Typical Performance Characteristics ........................................... 12 Functional Description .................................................................. 16 Programmable Current Source ................................................ 20 Digital-to-Analog Section ......................................................... 16 Coarse and Fine Adjustment Using the AD5346/AD5347/AD5348 ....................................................... 21 Resistor String ............................................................................. 16 Power Supply Bypassing and Grounding................................ 21 DAC Reference Input................................................................. 16 Outline Dimensions ....................................................................... 23 Output Amplifier ........................................................................ 16 Ordering Guides......................................................................... 24 Parallel Interface ......................................................................... 17 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD5346/AD5347/AD5348 SPECIFICATIONS Table 1. VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted 2 Parameter DC PERFORMANCE3,4 AD5346 Resolution Relative Accuracy Differential Nonlinearity AD5347 Resolution Relative Accuracy Differential Nonlinearity AD5348 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband5 Upper Deadband5 Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6 DAC REFERENCE INPUT6 VREF Input Range VREF Input Range VREF Input Impedance Min B Version1 Typ Max ±1 ±0.25 Bits LSB LSB Guaranteed monotonic by design over all codes 10 ±0.5 ±0.05 ±4 ±0.5 Bits LSB LSB Guaranteed monotonic by design over all codes ±16 ±1 ±3 ±1 60 60 200 1 0.25 VDD VDD >10 90 45 –90 –75 0.001 VDD – 0.001 0.5 25 16 2.5 5 DC Output Impedance Short Circuit Current Power-Up Time Conditions/Comments 8 ±0.15 ±0.02 12 ±2 ±0.2 ±0.4 ±0.1 10 10 –12 –5 –60 Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage4, 7 Maximum Output Voltage4, 7 Unit LOGIC INPUTS Input Current VIL, Input Low Voltage Bits LSB LSB % of FSR % of FSR mV mV ppm of FSR/°C ppm of FSR/°C dB Guaranteed monotonic by design over all codes Lower deadband exists only if offset error is negative VDD = 5 V; upper deadband exists only if VREF = VDD ∆VDD = ±10% µV RL = 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND; Gain = +1 V V MΩ kΩ kΩ dB dB Buffered reference mode Unbuffered reference mode Buffered reference mode and power-down mode Gain = +1; input impedance = RDAC Gain = +2; input impedance = RDAC Frequency = 10 kHz Frequency = 10 kHz V min V max Rail-to-rail operation Ω mA mA µs µs VDD = 5 V VDD = 3 V Coming out of power-down mode; VDD = 5 V Coming out of power-down mode; VDD = 3 V 6 VIH, Input High Voltage Pin Capacitance ±1 0.8 0.7 0.6 1.7 5 µA V V V V pF Rev. 0 | Page 3 of 24 VDD = 5 V ±10% VDD = 3 V ±10% VDD = 2.5 V VDD = 2.5 V to 5.5 V AD5346/AD5347/AD5348 2 Parameter LOGIC OUTPUTS6 VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V B Version1 Typ Max Min Unit Conditions/Comments 0.4 V V ISINK = 200 µA ISOURCE = 200 µA 0.4 V V ISINK = 200 µA ISOURCE = 200 µA 5.5 V 1 0.8 1.65 1.4 mA mA 0.4 0.12 1 1 µA µA VDD – 1 VDD – 0.5 2.5 IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V VIH = VDD, VIL = GND All DACs in unbuffered mode. In buffered mode, extra current is typically x µA per DAC, where x = 5 µA + VREF/RDAC VIH = VDD, VIL = GND See footnotes after the AC Characteristics table. AC CHARACTERISTICS6 Table 2. VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted 2 Parameter Output Voltage Settling Time AD5346 AD5347 AD5348 Slew Rate Major Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Min B Version1 Typ Max Unit 6 7 8 0.7 µs µs µs V/µs 8 9 10 Conditions/Comments VREF = 2 V 1/4 scale to 3/4 scale change (40 H to C0 H) 1/4 scale to 3/4 scale change (100 H to 300 H) 1/4 scale to 3/4 scale change (400 H to C00 H) 8 nV-s 1 LSB change around major carry 0.5 1 1 3.5 200 –70 nV-s nV-s nV-s nV-s kHz dB VREF = 2 V ±0.1 V p-p; unbuffered mode VREF = 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode 1 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. See Terminology section. 3 Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and the offset plus gain error must be positive. 2 200µA VOH(min) + VOL(max) CL 50pF 2 200µA IOH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 4 of 24 03331-0-002 TO OUTPUT PIN IOL AD5346/AD5347/AD5348 TIMING CHARACTERISTICS1, 2, 3 Table 3. VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted Parameter Data Write Mode (Figure 3) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Data Readback Mode (Figure 4) t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 Limit at TMIN, TMAX Unit Condition/Comments 0 0 20 5 4.5 5 5 4.5 5 4.5 20 10 20 20 0 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min CS to WR setup time CS to WR hold time WR pulse width Data, GAIN, BUF setup time Data, GAIN, BUF hold time Synchronous mode. WR falling to LDAC falling. Synchronous mode. LDAC falling to WR rising. Synchronous mode. WR rising to LDAC rising. Asynchronous mode. LDAC rising to WR rising. Asynchronous mode. WR rising to LDAC falling. LDAC pulse width CLR pulse width Time between WR cycles A0, A1, A2 setup time A0, A1, A2 hold time 0 0 0 20 30 0 22 30 4 30 22 30 30 30 30 50 ns min ns min ns min ns min ns min ns min ns max ns max ns min ns max ns max ns max ns min ns min ns min ns min A0, A1, A2 to CS setup time A0, A1, A2 to CS hold time CS to falling edge of RD RD pulse width; VDD = 3.6 V to 5.5 V RD pulse width; VDD = 2.5 V to 3.6 V CS to RD hold time Data access time after falling edge of RD; VDD = 3.6 V to 5.5 V Data access time after falling edge of RD VDD = 2.5 V to 3.6 V Bus relinquish time after rising edge of RD CS falling edge to data; VDD = 3.6 V to 5.5 V CS falling edge to data; VDD = 2.5 V to 3.6 V Time between RD cycles Time from RD to WR Time from WR to RD, VDD = 3.6 V to 5.5 V Time from WR to RD, VDD = 2.5 V to 3.6 V 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. 2 t1 t2 A0–A2 CS t3 t13 t4 DATA, GAIN, BUF LDAC1 t5 CS t18 t6 t7 t9 t20 t19 t8 t24 RD t10 t21 t11 LDAC2 CLR t17 t16 WR t22 DATA t23 t12 t14 t15 t25 WR t26 03331-0-003 NOTES 1. SYNCHRONOUS LDAC UPDATE MODE 2. ASYNCHRONOUS LDAC UPDATE MODE Figure 3. Parallel Interface Write Timing Diagram Figure 4. Parallel Interface Read Timing Diagram Rev. 0 | Page 5 of 24 03331-0-004 A0–A2 AD5346/AD5347/AD5348 ABSOLUTE MAXIMUM RATINGS Table 4. TA = 25°C, unless otherwise noted Parameter VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND VOUT to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 38-Lead TSSOP Package Power Dissipation θJA Thermal Impedance θJC Thermal Impedance 40-Lead LFCSP Package Power Dissipation θJA Thermal Impedance (3-layer board) Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –40°C to +105°C –65°C to +150°C 150°C (TJ max − TA)/ θJA mW 98.3°C/W 8.9°C/W (TJ max − TA)/ θJA mW Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 29.6°C/W 300°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24 AD5346/AD5347/AD5348 36 GAIN 37 WR 38 CLR 39 VREFGH 40 PD VREFEF 36 GAIN VREFCD 37 CLR VREFCD 3 VDD 38 PD 1 VREFEF 2 VREFAB VREFGH VDD AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 35 34 33 32 31 VDD 4 35 WR VOUTA 1 30 RD VREFAB 5 34 RD VOUTB 2 29 CS 33 CS VOUTC 3 28 DB7 32 DB7 VOUTD 4 26 DB1 VOUTH 14 25 DB0 DGND 15 24 DGND BUF 16 23 DGND LDAC 17 22 DGND A0 18 21 DGND A1 19 20 A2 22 DB1 VOUTH 10 21 DB0 11 12 13 14 15 16 17 18 19 20 DGND VOUTG 13 23 DB2 VOUTG 9 DGND 27 DB2 24 DB3 VOUTF 8 DGND VOUTF 12 25 DB4 VOUTE 7 DGND 28 DB3 26 DB5 TOP VIEW (Not to Scale) A2 VOUTE 11 AD5346 AGND 6 A1 29 DB4 Figure 6. AD5346 Pin Configuration—LFCSP 03331-0-005 AGND 10 27 DB6 8-BIT AGND 5 03331-0-006 TOP VIEW 31 DB6 (Not to Scale) 9 30 DB5 VOUTD VOUTC 8 A0 AD5346 LDAC VOUTB 7 BUF 8-BIT DGND VOUTA 6 Figure 5. AD5346 Pin Configuration—TSSOP Table 5. AD5346 Pin Function Descriptions Pin Number TSSOP LFCSP 1 35 2 36 3 37 4 38, 39 Mnemonic VREFGH VREFEF VREFCD VDD VREFAB VOUTX Function Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered output with rail-to-rail operation. AGND DGND Analog Ground. Ground reference for analog circuitry. Digital Ground. Ground reference for digital circuitry. BUF LDAC Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. LSB Address Pin. Selects which DAC is to be written to. Address Pin. Selects which DAC is to be written to. MSB Address Pin. Selects which DAC is to be written to. Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode. 5 6–9, 11–14 10 15, 21–24 16 17 40 1–4, 7–10 5, 6 11, 17–20 12 13 18 19 20 25–32 33 14 15 16 21–28 29 A0 A1 A2 DB0–DB7 CS 34 35 36 37 38 30 31 32 33 34 RD WR GAIN CLR PD Rev. 0 | Page 7 of 24 AD5346/AD5347/AD5348 36 GAIN 37 WR 38 CLR 39 VREFGH 40 PD VREFEF 36 GAIN VREFCD 37 CLR VREFCD 3 VDD 38 PD 1 VREFEF 2 VREFAB VREFGH VDD AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 35 34 33 32 31 VDD 4 35 WR VOUTA 1 30 RD VREFAB 5 34 RD VOUTB 2 29 CS 33 CS VOUTC 3 28 DB9 32 DB9 VOUTD 4 26 DB3 VOUTH 14 25 DB2 DGND 15 24 DB1 BUF 16 23 DB0 LDAC 17 22 DGND A0 18 21 DGND A1 19 20 A2 22 DB3 VOUTH 10 21 DB2 11 12 13 14 15 16 17 18 19 20 DB1 VOUTG 13 23 DB4 VOUTG 9 DB0 27 DB4 24 DB5 VOUTF 8 DGND VOUTF 12 25 DB6 VOUTE 7 DGND 28 DB5 26 DB7 TOP VIEW (Not to Scale) A2 VOUTE 11 AD5347 AGND 6 A1 29 DB6 Figure 8. AD5347 Pin Configuration—LFCSP 03331-0-007 AGND 10 27 DB8 10-BIT AGND 5 03331-0-008 TOP VIEW 31 DB8 (Not to Scale) 30 DB7 VOUTD 9 VOUTC 8 A0 AD5347 LDAC VOUTB 7 BUF 10-BIT DGND VOUTA 6 Figure 7. AD5347 Pin Configuration—TSSOP Table 6. AD5347 Pin Function Descriptions Pin Number TSSOP LFCSP 1 35 2 36 3 37 4 38, 39 5 6–9, 11–14 10 15, 21–22 Mnemonic VREFGH VREFEF VREFCD VDD VREFAB VOUTX Function Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered output with rail-to-rail operation. AGND DGND Analog Ground. Ground reference for analog circuitry. Digital Ground. Ground reference for digital circuitry. BUF LDAC Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. LSB Address Pin. Selects which DAC is to be written to. Address Pin. Selects which DAC is to be written to. MSB Address Pin. Selects which DAC is to be written to. Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits. Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode. 16 17 40 1–4, 7–10 5, 6 11, 17–18 12 13 18 19 20 23–32 33 14 15 16 19–28 29 A0 A1 A2 DB0–DB9 CS 34 35 36 37 38 30 31 32 33 34 RD WR GAIN CLR PD Rev. 0 | Page 8 of 24 AD5346/AD5347/AD5348 36 GAIN 37 WR 38 CLR 39 VREFGH 40 PD VREFEF 36 GAIN VREFCD 37 CLR VREFCD 3 VDD 38 PD 1 VREFEF 2 VREFAB VREFGH VDD AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 35 34 33 32 31 VDD 4 35 WR VOUTA 1 30 RD VREFAB 5 34 RD VOUTB 2 29 CS 33 CS VOUTC 3 28 DB11 32 DB11 VOUTD 4 26 DB5 VOUTH 14 25 DB4 DGND 15 24 DB3 BUF 16 23 DB2 LDAC 17 22 DB1 A0 18 21 DB0 A1 19 20 A2 22 DB5 VOUTH 10 21 DB4 11 12 13 14 15 16 17 18 19 20 DB3 VOUTG 13 23 DB6 VOUTG 9 DB2 27 DB6 24 DB7 VOUTF 8 DB1 VOUTF 12 25 DB8 VOUTE 7 DB0 28 DB7 26 DB9 TOP VIEW (Not to Scale) A2 VOUTE 11 AD5348 AGND 6 A1 29 DB8 Figure 10. AD5348 Pin Configuration—LFCSP 03331-0-009 AGND 10 27 DB10 12-BIT AGND 5 03331-0-010 TOP VIEW 31 DB10 (Not to Scale) 30 DB9 VOUTD 9 VOUTC 8 A0 AD5348 LDAC VOUTB 7 BUF 12-BIT DGND VOUTA 6 Figure 9. AD5348 Pin Configuration—TSSOP Table 7. AD5348 Pin Function Descriptions Pin Number TSSOP LFCSP 1 35 2 36 3 37 4 38, 39 Mnemonic VREFGH VREFEF VREFCD VDD 5 6–9, 11–14 10 15 16 17 40 1–4, 7–10 5, 6 11 12 13 VREFAB VOUTX AGND DGND BUF LDAC 18 19 20 21–32 33 14 15 16 17–28 29 A0 A1 A2 DB0–DB11 CS 34 35 36 37 38 30 31 32 33 34 RD WR GAIN CLR PD Function Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered output with rail-to-rail operation. Analog Ground. Ground reference for analog circuitry. Digital Ground. Ground reference for digital circuitry. Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. LSB Address Pin. Selects which DAC is to be written to. Address Pin. Selects which DAC is to be written to. MSB Address Pin. Selects which DAC is to be written to. Twelve Parallel Data Inputs. DB11 is the MSB of these 12 bits. Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode. Rev. 0 | Page 9 of 24 AD5346/AD5347/AD5348 TERMINOLOGY Relative Accuracy GAIN ERROR AND OFFSET ERROR For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL versus code plots can be seen in Figure 14, Figure 15, and Figure 16. Differential Nonlinearity ACTUAL OUTPUT VOLTAGE IDEAL POSITIVE OFFSET Gain Error 03331-0-012 Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be seen in Figure 17, Figure 18, and Figure 19. DAC CODE This is a measure of the span error of the DAC, including any error in the gain of the buffer amplifier. It is the deviation in slope of the actual DAC transfer characteristic from the ideal and is expressed as a percentage of the full-scale range. This is illustrated in Figure 11. Figure 12. Positive Offset Error and Gain Error Offset Error GAIN ERROR AND OFFSET ERROR IDEAL This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage still positive at zero input code. This is shown in Figure 12. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code there is a dead band over which the output voltage does not change. This is illustrated in Figure 13. OUTPUT VOLTAGE ACTUAL NEGATIVE OFFSET POSITIVE GAIN ERROR NEGATIVE GAIN ERROR ACTUAL DAC CODE DEADBAND CODES AMPLIFIER FOOTROOM (~1mV) OUTPUT VOLTAGE NEGATIVE OFFSET 03331-0-013 IDEAL 03331-0-011 DAC CODE Figure 13. Negative Offset Error and Gain Error Figure 11. Gain Error Rev. 0 | Page 10 of 24 AD5346/AD5347/AD5348 Offset Error Drift Digital Crosstalk This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-s. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. DC Power-Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied ±10%. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in µV. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated, i.e., LDAC is high. It is expressed in dB. Channel-to-Channel Isolation This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference inputs of the other DACs. It is measured by grounding one VREF pin and applying a 10 kHz, 4 V p-p sine wave to the other VREF pins. It is expressed in dB. Major-Code Transition Glitch Energy This is the energy of the impulse injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC pin set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dB. Digital Feedthrough This is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device, but it is measured when the DAC is not being written to, CS held high. It is specified in nV-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. Rev. 0 | Page 11 of 24 AD5346/AD5347/AD5348 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 0.1 0 –0.1 –0.5 –1.0 0 50 100 150 200 03331-0-017 03331-0-014 –0.2 –0.3 250 0 50 100 CODE Figure 14. AD5346 Typical INL Plot 200 250 800 1000 Figure 17. AD5346 Typical DNL Plot 0.6 3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 2 0.4 1 0.2 DNL ERROR (LSB) 0 –1 –3 0 200 400 600 800 –0.2 –0.4 03331-0-015 –2 0 03331-0-018 INL ERROR (LSB) 150 CODE –0.6 0 1000 200 400 600 CODE CODE Figure 15. AD5347 Typical INL Plot Figure 18. AD5347 Typical DNL Plot 1.0 12 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 8 DNL ERROR (LSB) 4 0 –4 0 –12 0 1000 2000 CODE 3000 03331-0-019 –0.5 –8 03331-0-016 INL ERROR (LSB) 0.5 –1.0 0 4000 1000 2000 CODE 3000 Figure 19. AD5348 Typical DNL Plot Figure 16. AD5348 Typical INL Plot Rev. 0 | Page 12 of 24 4000 AD5346/AD5347/AD5348 0.2 0.5 VDD = 5V TA = 25°C 0.4 TA = 25°C VREF = 2V 0.1 MAX INL 0.3 0 GAIN ERROR MAX DNL ERROR (% FSR) ERROR (LSB) 0.2 0.1 0 –0.1 MIN DNL –0.1 –0.2 –0.3 –0.2 MIN INL –0.4 OFFSET ERROR –0.4 –0.5 0 1 2 3 4 03331-0-034 03331-0-031 –0.3 –0.5 –0.6 5 0 1 VREF(V) Figure 20. AD5346 INL and DNL Error vs. VREF 2 3 VDD (V) 4 5 6 Figure 23. Offset Error and Gain Error vs. VDD 5 0.5 VDD = 5V VREF = 2V 0.4 MAX INL 5V SOURCE 0.3 4 0.2 3 VOUT (V) ERROR (LSB) 3V SOURCE MAX DNL 0.1 0 –0.1 2 MIN DNL –0.2 03331-0-032 1 –0.4 –0.5 –40 MIN INL –20 0 60 20 40 TEMPERATURE (°C) 80 0 0 100 Figure 21. AD5346 INL and DNL Error vs. Temperature 1 2 3 4 SINK/SOURCE CURRENT (mA) 5 6 Figure 24. VOUT Source and Sink Current Capability 1.0 1.0 VDD = 5V VREF = 2V 0.9 VDD = 5V TA = 25°C 0.8 0.5 0.7 IDD (mA) 0.6 0 OFFSET ERROR 0.5 0.4 0.3 –0.5 GAIN ERROR –1.0 –40 –20 0 60 20 40 TEMPERATURE (°C) 80 03331-0-036 0.2 03331-0-033 ERROR (% FSR) 3V SINK 5V SINK 03331-0-035 –0.3 0.1 0 100 ZERO SCALE Figure 22. AD5346 Offset Error and Gain Error vs. Temperature HALF SCALE DAC CODE FULL SCALE Figure 25. Supply Current vs. DAC Code Rev. 0 | Page 13 of 24 AD5346/AD5347/AD5348 1.4 TA = 25°C VDD = 5V VREF = 5V VREF = 2V GAIN = 1 UNBUFFERED 1.2 TA = –40°C TA = +25°C 1.0 VOUTA IDD (mA) 0.8 TA = +105°C CH1 0.6 LDAC CH2 03331-0-037 0.2 03331-0-040 0.4 0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 5.5 Figure 29. Half-Scale Settling (¼ to ¾ Scale Code) Figure 26. Supply Current vs. Supply Voltage 1.0 0.9 TA = 25°C VDD = 5V VREF = 2V TA = 25°C CH1 0.7 VDD 0.6 0.5 0.4 VOUTA 0.3 CH2 03331-0-041 0.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 03331-0-038 0.1 5.5 VDD (V) CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV Figure 30. Power-On Reset to 0 V Figure 27. Power-Down Current vs. Supply Voltage 2.5 TA = 25°C VDD = 5V 2.0 VOUT1 CH2 1.5 1.0 PD VDD = 3V 0 0 1 2 3 VLOGIC (V) 4 03331-0-042 0.5 CH1 03331-0-039 IDD (mA) IDD POWER-DOWN (µA) 0.8 CH1 2.00V, CH2 1.00V, TIME BASE = 20µs/DIV 5 Figure 31. Exiting Power-Down to Midscale Figure 28. Supply Current vs. Logic Input Voltage Rev. 0 | Page 14 of 24 AD5346/AD5347/AD5348 0.02 21 VDD = 5V TA = 25°C 15 FREQUENCY VDD = 3V VDD = 5V 12 9 6 0.01 0 –0.01 03331-0-046 FULL-SCALE ERROR (V) 18 0 0.6 0.8 1.0 1.2 03331-0-043 3 1.4 IDD (mA) –0.02 0 1 2 3 VREF (V) 4 5 6 Figure 35. Full-Scale Error vs. VREF Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V 1.999 2.49 1.998 2.48 1.997 2.47 1.996 1µs/DIV 10 0 –10 dB –20 –30 –40 03331-0-045 –60 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 34. Multiplying Bandwidth (Small Signal Frequency Response) Rev. 0 | Page 15 of 24 511 03331-0-047 Figure 36. DAC-to-DAC Crosstalk Figure 33. AD5348 Major Code Transition Glitch Energy –50 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 03331-0-044 VOUT (V) 2.50 AD5346/AD5347/AD5348 FUNCTIONAL DESCRIPTION VREF The AD5346/AD5347/AD5348 are octal resistor-string DACs fabricated by a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers offer rail-to-rail output swing. The gain of the buffer amplifiers can be set to 1 or 2 to give an output voltage range of 0 V to VREF or 0 V to 2 × VREF. The AD5346/ AD5347/AD5348 have reference inputs that may be buffered to draw virtually no current from the reference source. The devices have a power-down feature that reduces current consumption to only 100 nA @ 3 V. R R R Figure 38. Resistor String The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 37 shows a block diagram of the DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by DAC REFERENCE INPUT The DACs operate with an external reference. The AD5346/ AD5347/AD5348 have a reference input for each pair of DACs. The reference inputs may be configured as buffered or unbuffered. This option is controlled by the BUF pin. D × Gain 2N In buffered mode (BUF = 1), the current drawn from an external reference voltage is virtually zero because the impedance is at least 10 MΩ. The reference input range is 1 V to VDD. where: D is the decimal equivalent of the binary code, which is loaded to the DAC register: 0–255 for AD5346 (8 bits) 0–1023 for AD5347 (10 bits) 0–4095 for AD5348 (12 bits) N is the DAC resolution. Gain is the output amplifier gain (1 or 2). VREFAB BUF If using an external buffered reference (such as REF192), there is no need to use the on-chip buffer. The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on VREF, GAIN, the load on VOUT, and offset error. REFERENCE BUFFER RESISTOR STRING VOUTA OUTPUT BUFFER AMPLIFIER 03331-0-020 DAC REGISTER In unbuffered mode (BUF = 0), the user can have a reference voltage as low as 0.25 V and as high as VDD because there is no restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 90 kΩ for 0 V to VREF mode and 45 kΩ for 0 V to 2 × VREF mode. OUTPUT AMPLIFIER (GAIN = +1 OR +2) INPUT REGISTER 03331-0-021 R DIGITAL-TO-ANALOG SECTION VOUT = VREF × TO OUTPUT AMPLIFIER R Figure 37. Single DAC Channel Architecture RESISTOR STRING The resistor string section is shown in Figure 38. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. If a gain of +1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of +2 is selected (GAIN = +1), the output range is 0.001 V to 2 × VREF. However, because of clamping, the maximum output is limited to VDD – 0.001 V. The output amplifier is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in Figure 24. The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB (at 8 bits) of 6 s with the output unloaded. See Figure 29. Rev. 0 | Page 16 of 24 AD5346/AD5347/AD5348 where IDYNAMIC = PARALLEL INTERFACE The AD5346/AD5347/AD5348 load their data as a single 8-, 10-, or 12-bit word. Double-Buffered Interface The AD5346/AD5347/AD5348 DACs all have double-buffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the input register under control of the Chip Select (CS) and Write (WR) pins. Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are updated only when LDAC is taken low. This is useful if the user requires simultaneous updating of all DACs and peripherals. The user can write to all input registers individually and then, by pulsing the LDAC input low, all outputs update simultaneously. cvf and c = capacitance or the data bus v = VDD f = readback frequency Load DAC Input (LDAC) LDAC transfers data from the input register to the DAC register, and therefore updates the outputs. The LDAC function enables double-buffering of the DAC data, GAIN data, and BUF. There are two LDAC modes: • • Synchronous Mode. In this mode, the DAC register is updated after new data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed as shown in Figure 3. Asynchronous Mode. In this mode, the outputs are not updated at the same time that the input register is written to. When LDAC goes low, the DAC register is updated with the contents of the input register. POWER-ON RESET The AD5346/AD5347/AD5348 have a power-on reset function, so that they power up in a defined state. The power-on state is • • • • Normal operation Reference input buffered 0 V to VREF output range Output voltage set to 0 V These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5346/ AD5347/AD5348, the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk. Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. Clear Input (CLR) POWER-DOWN MODE CLR is an active low, asynchronous clear that resets the input and DAC registers. The AD5346/AD5347/AD5348 have low power consumption, dissipating typically 2.4 mW with a 3 V supply and 5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is selected by taking the PD pin low. CS is an active low input that selects the device. Write Input (WR) WR is an active low input that controls writing of data to the device. Data is latched into the input register on the rising edge of WR. Read Input (RD) RD is an active low input that controls when data is read back from the internal DAC registers. On the falling edge of RD, data is shifted onto the data bus. Under the conditions of a high capacitive load and high supplies, the user must ensure that the dynamic current remains at an acceptable level, therefore ensuring that the die temperature is within specification. The die temperature can be calculated as When the PD pin is high, the DACs work normally with a typical power consumption of 1 mA at 5 V (0.8 mA at 3 V). In power-down mode, however, the supply current falls to 400 nA at 5 V (120 nA at 3 V) when the DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the outputs are threestate while the part is in power-down mode, and provides a defined input condition for whatever is connected to the outputs of the DAC amplifiers. The output stage is illustrated in Figure 39. RESISTOR STRING DAC AMPLIFIER VOUT POWER-DOWN CIRCUITRY TDIE = TAMBIENT + VDD (IDD + IDYNAMIC)θJA 03331-0-022 Chip Select Input (CS) Figure 39. Output Stage During Power-Down Rev. 0 | Page 17 of 24 AD5346/AD5347/AD5348 The AD5347 and AD5348 data bus must be at least 10 and 12 bits wide, respectively, and are best suited to a 16-bit data bus system. Examples of data formats for putting GAIN and BUF on a 16-bit data bus are shown in Figure 40. Note that any unused bits above the actual DAC data may be used for GAIN and BUF. AD5347 SUGGESTED DATA BUS FORMATS X X X X BUF GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X BUF GAIN DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AD5348 In many applications, the GAIN and BUF pins are hardwired. However, if more flexibility is required, they can be included in a data bus. This enables the user to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system, GAIN and BUF may be treated as data inputs because they are written to the device during a write operation and take effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines. Note that GAIN and BUF are not read back during an RD operation. X = UNUSED BIT Figure 40. AD5347/AD5348 Data Format for Word Load with GAIN and BUF Data on 16-Bit Bus Table 8. AD5346/AD5347/AD5348 Truth Table CLR LDAC 1 1 1 1 0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 0 X X X = Don’t Care CS WR RD 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 X 1 X 0→1 0→1 0→1 0→1 0→1 0→1 0→1 0→1 1 1 1 1 1 1 1 1 X 0 X 1 X 1 1 1 1 1 1 1 1 1→0 1→0 1→0 1→0 1→0 1→0 1→0 1→0 1 0 A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X A1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X Rev. 0 | Page 18 of 24 A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X Function No Data Transfer No Data Transfer Clear All Registers Load DAC A Input Register Load DAC B Input Register Load DAC C Input Register Load DAC D Input Register Load DAC E Input Register Load DAC F Input Register Load DAC G Input Register Load DAC H Input Register Read Back DAC Register A Read Back DAC Register B Read Back DAC Register C Read Back DAC Register D Read Back DAC Register E Read Back DAC Register F Read Back DAC Register G Read Back DAC Register H Update DAC Registers Invalid Operation 03331-0-048 The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 µs when VDD = 3 V. This is the time from a rising edge on the PD pin to when the output voltage deviates from its power-down voltage. See Figure 31. AD5346/AD5347/AD5348 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUITS The AD5346/AD5347/AD5348 can be used with a wide range of reference voltages, especially if the reference inputs are configured as unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices may be used with a fixed, precision reference voltage. Figure 41 shows a typical setup for the devices when using an external reference connected to the reference inputs. Suitable references for 5 V operation are the AD780, ADR381, and REF192 (2.5 V references). For 2.5 V operation, suitable external references are the AD589 and the AD1580 (1.2 V band gap references). BIPOLAR OPERATION USING THE AD5346/AD5347/AD5348 The AD5346/AD5347/AD5348 have been designed for singlesupply operation, but a bipolar output range is also possible by using the circuit shown in Figure 43. This circuit has an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820, an AD8519, or an OP196 as the output amplifier. 5V R4 20kΩ 0.1µF VIN 10µF ±5V VDD EXT REF VIN –5V R1 10kΩ VOUT* R2 20kΩ VOUT* AD5346/AD5347/ AD5348 GND *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN 03331-0-024 AD780/ADR381/REF192 WITH VDD = 5V OR AD589/AD1580 WITH VDD = 2.5V GND Figure 43. Bipolar Operation with the AD5346/ AD5347/AD5348 *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN The output voltage for any input code can be calculated as follows: Figure 41. AD5346/AD5347/AD5348 Using an External Reference DRIVING VDD FROM THE REFERENCE VOLTAGE If an output range of 0 V to VDD is required, the simplest solution is to connect the reference inputs to VDD. Because this supply may not be very accurate and may be noisy, the devices can be powered from the reference voltage, for example, by using a 5 V reference such as the ADM663 or ADM666, as shown in Figure 42. VOUT = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] – R4 × VREF/R3 where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. VREF is the reference voltage input. with: 6V TO 16V 0.1µF VREF = 5 V R1 = R3 = 10 kΩ R2 = R4 = 20 kΩ VDD = 5 V GAIN = 2 10µF VIN ADM663/ADM666 VDD VREF* 0.1µF VOUT* AD5346/AD5347/ AD5348 GND VOUT = (10 × D/2N) – 5 03331-0-025 SENSE VOUT(2) GND SHDN VSET GND AD5346/AD5347/ AD5348 03331-0-026 VREF* GND EXT REF 0.1µF VDD VOUT AD820/AD8519/ OP196 VREF* VOUT GND EXT REF +5V R3 10kΩ VDD = 2.5V to 5.5V 0.1µF 10µF *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN Figure 42. Using an ADM663/ADM666 as Power and Reference to the AD5346/AD5347/AD5348 Rev. 0 | Page 19 of 24 AD5346/AD5347/AD5348 5V DECODING MULTIPLE AD5346/AD5347/AD5348s The 74HC139 is used as a 2-line to 4-line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 44 shows a diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to reset all DAC outputs to 0 V. AD5346/AD5347 A0 /AD5348 A1 A2 WR DATA INPUTS LD AC CLR CS A0 A1 A2 WR LDAC CLR VIN VDD ENABLE CODED ADDRESS 1G VCC 1Y0 1A 1Y1 74HC139 1B 1Y2 1Y3 DGND AD5346/AD5347 VREFAB 1kΩ 1kΩ FAIL PASS VDD PASS/ FAIL 1/2 CMP04 AD5346/AD5347/ AD5348 VOUTB 03331-0-028 VOUTA 1/6 74HC05 GND Figure 45. Programmable Window Detector PROGRAMMABLE CURRENT SOURCE Figure 46 shows the AD5346/AD5347/AD5348 used as the control element of a programmable current source. In this example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, which gives an adjustment of about ±5%. Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having rail-to-rail operation on their outputs. The current for any digital input code and resistor value can be calculated as follows: I = G × VREF A0 /AD5348 A1 A2 WR DATA LD AC INPUTS CLR CS D mA (2 × R) N where: G is the gain of the buffer amplifier (1 or 2). D is the digital input code. N is the DAC resolution (8, 10, or 12 bits). R is the sum of the resistor plus adjustment potentiometer in kΩ. AD5346/AD5347 VDD = 5V 03331-0-027 A0 /AD5348 A1 A2 WR DATA INPUTS LD AC CLR CS VREF DATA BUS AD5346/AD5347 A0 /AD5348 A1 A2 WR DATA LD AC INPUTS CLR CS 10µF 0.1µF The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and WR pulses, but only the CS to one of the DACs will be active at any one time, so data will only be written to the DAC whose CS is low. 0.1µF Figure 44. Decoding Multiple DAC Devices 10µF VSOURCE VIN A digitally programmable upper/lower limit detector using two of the DACs in the AD5346/AD5347/AD5348 is shown in Figure 45. Any pair of DACs in the device may be used, but for simplicity the description refers to DACs A and B. The upper and lower limits for the test are loaded to DACs A and B which, in turn, set the limits on the CMP04. If a signal at the VIN input is not within the programmed window, an LED indicates the fail condition. 5V VDD EXT REF VOUT GND VREF* 0.1µF LOAD VOUT* AD5346/AD5347/ AD5348 4.7kΩ GND 470Ω *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN Rev. 0 | Page 20 of 24 Figure 46. Programmable Current Source 03331-0-029 AD5346/AD5347/AD5348 AS DIGITALLY PROGRAMMABLE WINDOW DETECTORS AD5346/AD5347/AD5348 COARSE AND FINE ADJUSTMENT USING THE AD5346/AD5347/AD5348 POWER SUPPLY BYPASSING AND GROUNDING Two of the DACs in the AD5346/AD5347/AD5348 can be paired together to form a coarse and fine adjustment function, as shown in Figure 47. As with the window comparator previously described, the description refers to DACs A and B. DAC A provides the coarse adjustment, while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 changes the relative effect of the coarse and fine adjustments. With the resistor values shown, the output amplifier has unity gain for the DAC A output, so the output range is 0 V to (VREF – 1 LSB). For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B a range equal to 2 LSBs of DAC A. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated allow a rail-to-rail output swing. VDD = 5V 0.1µF 10µF VDD VOUT VREFAB 0.1µF AD5346/AD5347/ AD5348 VOUTB R1 390Ω R2 51.2kΩ AD780/ADR381/REF192 WITH VDD = 5V GND Figure 47. Coarse and Fine Adjustment 03331-0-030 VOUTA VOUT GND R3 51.2kΩ 5V VIN EXT REF R4 390Ω In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5346/AD5347/ AD5348 is mounted should be designed so that the analog and digital sections are separated and are confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in one place only. If the AD5346/AD5347/AD5348 is the only device requiring an AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD5346/ AD5347/AD5348. If the AD5346/AD5347/AD5348 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD5346/AD5347/AD5348. The AD5346/AD5347/AD5348 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the device should use the largest trace possible to provide low impedance paths and to reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. Rev. 0 | Page 21 of 24 AD5346/AD5347/AD5348 Table 9. Overview of AD53xx Parallel Devices Part No. SINGLES AD5330 AD5331 AD5340 AD5341 DUALS AD5332 AD5333 AD5342 AD5343 QUADS AD5334 AD5335 AD5336 AD5344 OCTALS AD5346 AD5347 AD4348 Resolution DNL VREF Pins Settling Time 8 10 12 12 ±0.25 ±0.5 ±1.0 ±1.0 1 1 1 1 6 µs 7 µs 8 µs 8 µs 8 10 12 12 ±0.25 ±0.5 ±1.0 ±1.0 2 2 2 1 6 µs 7 µs 8 µs 8 µs 8 10 10 12 ±0.25 ±0.5 ±0.5 ±1.0 2 2 4 4 6 µs 7 µs 7 µs 8 µs 8 10 12 ±0.25 ±0.5 ±1.0 4 4 4 6 µs 7 µs 8 µs Additional Pin Functions BUF GAIN HBEN CLR 9 Package Pins 9 9 9 9 9 TSSOP TSSOP TSSOP TSSOP 20 20 24 20 9 9 9 9 9 TSSOP TSSOP TSSOP TSSOP 20 24 28 20 9 9 9 9 TSSOP TSSOP TSSOP TSSOP 24 24 28 28 9 9 9 9 9 9 TSSOP, LFCSP TSSOP, LFCSP TSSOP, LFCSP 38, 40 38, 40 38, 40 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 Table 10. Overview of AD53xx Serial Devices Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328 Resolution DNL VREF Pins Settling Time Interface Package Pins 8 10 12 8 10 12 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 4 µs 6 µs 8 µs 6 µs 7 µs 8 µs SPI® SPI SPI 2-Wire 2-Wire 2-Wire SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 8 10 12 8 10 12 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 2 2 2 2 2 2 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs SPI SPI SPI SPI SPI SPI MSOP MSOP MSOP TSSOP TSSOP TSSOP 8 8 8 16 16 16 8 10 12 8 10 12 8 10 12 8 10 12 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 1 1 1 1 1 1 4 4 4 2 2 2 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs 6 µs 7 µs 8 µs SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI MSOP MSOP MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP 10 10 10 10 10 10 16 16 16 16 16 16 8 10 12 ±0.25 ±0.5 ±1.0 2 2 2 6 µs 7 µs 8 µs SPI SPI SPI TSSOP TSSOP TSSOP 16 16 16 Rev. 0 | Page 22 of 24 AD5346/AD5347/AD5348 OUTLINE DIMENSIONS 9.80 9.70 9.60 20 38 4.50 4.40 4.30 6.40 BSC 1 19 PIN 1 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.50 BSC 0.27 0.17 SEATING PLANE 0.20 0.09 8° 0° 0.70 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153BD-1 Figure 48. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimensions shown in millimeters 6.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 31 30 40 1 21 20 10 11 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP] (CP-40) Dimensions shown in millimeters Rev. 0 | Page 23 of 24 4.25 4.10 SQ 3.95 BOTTOM VIEW AD5346/AD5347/AD5348 ORDERING GUIDES Table 11. AD5346 Ordering Guide Model AD5346BRU AD5346BRU-REEL AD5346BRU-REEL7 AD5346BCP AD5346BCP-REEL AD5346BCP-REEL7 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) Package Option RU-38 RU-38 RU-38 CP-40 CP-40 CP-40 Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) Package Option RU-38 RU-38 RU-38 CP-40 CP-40 CP-40 Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) Package Option RU-38 RU-38 RU-38 CP-40 CP-40 CP-40 Table 12. AD5347 Ordering Guide Model AD5347BRU AD5347BRU-REEL AD5347BRU-REEL7 AD5347BCP AD5347BCP-REEL AD5347BCP-REEL7 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Table 13. AD5348 Ordering Guide Model AD5348BRU AD5348BRU-REEL AD5348BRU-REEL7 AD5348BCP AD5348BCP-REEL AD5348BCP-REEL7 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03331–0–11/03(0) Rev. 0 | Page 24 of 24