PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD720200 USB 3.0 HOST CONTROLLER The PD720200 is the Universal Serial Bus 3.0 host controller, which complies with Universal Serial Bus 3.0 Specification, and Intel’s eXtensible Host Controller Interface (xHCI). The PD720200 has PCI Express® bus interface, and it is applicable for PCI Express solution for host PC system. The PD720200 works up to 5 Gbps for data transfer when connecting to USB 3.0 compliant peripherals, while maintaining compatibility with existing USB peripheral devices. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. PD720200 User’s Manual : TBD FEATURES Compliant with Universal Serial Bus 3.0 specification Revision 1.0, which is released by USB Implementers Forum, Inc - Supports the following speed data rate as follows; Low-speed (1.5 Mbps) / Full-speed (12 Mbps) / High-speed (480 Mbps) / Super-speed (5 Gbps) - Supports 2 downstream ports for all speeds - Supports all USB compliant data transfer type as follows; Control / Bulk / Interrupt / Isochronous transfer Compliant with Intel’s eXtensible Host Controller Interface (xHCI) Specification revision 0.95 Support USB legacy function Compliant with PCI Express® Base Specification 2.0 TM Supports ExpressCard Standard Release1.0 Supports PCI Express® Card Electromechanical Specification Revision 2.0 Supports PCI Bus Power Management Interface Specification revision 1.2 Operational registers are direct-mapped to PCI memory space Supports Serial Peripheral Interface (SPI) type ROM System clock: 24 MHz crystal or 48MHz external clock. 3.3 V and 1.05 V power supply ORDERING INFORMATION Part Number PD720200F1-DAK-A Package 176-pin plastic FBGA (10 10) Remark Lead-free product No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Corporation. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. Date Published ISG-YD1-000127-05 April , 2009 CP (N) 2009 PD720200 BLOCK DIAGRAM Super-speed Controller Interface PCI Express Gen2 Interface (x 1) PCI Express Port xHCI Controller PCI Express Gen2 Interface 1.05V USB3.0 SS Root hub USB3.0 (Super-speed) PHY Power SW I/F High-speed Controller Interface Full/Low-speed Controller Interface 3.3V USB3.0 SS Link OSC/PLL SPI Interface 24MHz Xtal 48MHz clock input External Serial ROM USB2.0 SIE USB2.0 Root hub USB2.0 (HS/FS/LS) PHY USB Port1 (SS) USB Port2 (SS) Port Power Control USB Port1 (HS/FS/LS) USB Port2 (HS/FS/LS) : complies with PCI Express Gen2 interface, with 1 lane. This block includes link and PHY layer. xHCI Controller : handles all supped required for USB 3.0, super-/high-/full-/low-speed. This block Super-speed : handles super-speed operation in xHCI control block. includes register interface from system. Controller I/F High-speed : handles high-speed operation in xHCI control block. Controller I/F Full/Low-speed : handles full-/low-speed operation in xHCI control block. Controller I/F USB3.0 SS Link : is link layer defined in USB 3.0 specification, which maintains Link connectivity with USB3.0 SS : is a hub function in host controller for USB 3.0 port managing. USB devices. Root hub USB3.0 PHY : for super-speed Tx/Rx USB2.0 SIE : is Serial Interface Engine, which controls USB 2.0 protocol sequence. USB2.0 : is a hub function in host controller for USB 2.0 port managing. Root hub 2 USB2.0 PHY : for high-/full-/low-speed Tx/Rx Power SW I/F : is connected to external power switch for port power control and over current detection. SPI Interface : is connected to external serial ROM. PLL : Internal PLL. OSC : Internal oscillator block. Preliminary Data Sheet PD720200 PIN CONFIGURATION 176-pin plastic FBGA (10 10) PD720200F1-DAK-A Bottom View GND GND U3RXDN1 GND U3TXDN1 GND U3RXDN2 GND U3TXDN2 GND GND GND GND GND A GND GND U3RXDP1 GND U3TXDP1 GND U3RXDP2 GND U3TXDP2 GND GND GND PECLKP PECLKN B GND GND GND GND GND VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 GND GND GND C GND GND GND GND VDD33 VDD10 VDD10 U3AVDD33 U3AVSS VDD10 GND GND PETXP PETXN D GND GND VDD10 VDD10 VDD10 VDD10 GND GND E VDD33 VDD33 GND GND GND GND GND GND GND VDD33 PERXP PERXN F OCI2B GND GND GND GND GND GND GND VDD33 VDD33 GND GND G PPON2 OCI1B GND VDD10 GND GND GND GND VDD10 VDD10 PERSTB SMIB H PPON1 GND GND GND GND GND GND GND GND GND AUXDET PSEL J GND GND VDD10 VDD10 GND GND VDD33 VDD33 GND GND VDD33 VDD33 VDD10 GND GND VDD10 GND GND GND GND L XT2 GND GND GND GND GND GND GND GND GND GND GND SPISCK SPISO M XT1 GND U2AVSS U2PVSS U2DM1 GND U2DM2 GND VDD33 VDD33 VDD33 GND SPICSB SPISI N GND U2AVDD33 RREF GND U2DP1 GND U2DP2 GND CSEL PONRSTB GND VDD33 GND GND P 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Preliminary Data Sheet PECREQB PEWAKEB K 3 PD720200 1. PIN FUNCTIONS This section describes each pin functions. Power supply Pin Name VDD33 Ball No. Buffer Type Function D10, F3, F13, F14, G3, G4, L9, L10, L13, Power +3.3 V power supply Power +1.05 V power supply. L14, N4, N5, N6, P3 VDD10 C4, C5, C6, C7, C8, C9, D5, D8, D9, E3, E4, E11, E12, H3, H4, H11, K11, K12, L5, L8 U3AVDD33 D7 Power +3.3 V power supply for analog circuit. U2AVDD33 P13 Power +3.3 V power supply for analog circuit. VSS A1, A2, A3, A4, A5, A7, A9, A11, A13, Power Ground. A14, B3, B4, B5, B7, B9, B11, B13, B14, C1, C2, C3, C10, C11, C12, C13, C14, D3, D4, D11, D12, D13, D14, E1, E2, E13, E14, F4, F6, F7, F8, F9, F11, F12, G1, G2, G6, G7, G8, G9, G11, G12, G13, H6, H7, H8, H9, H12, J3, J4, J6, J7, J8, J9, J11, J12, J13, K3, K4, K13, K14, L1, L2, L3, L4, L6, L7, L11, L12, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, N3, N7, N9, N13, P1, P2, P4, P7, P9, P11, P14 U3AVSS D6 Power Ground for USB3.0 analog circuit. U2AVSS N12 Power Ground for USB2.0 analog circuit U2PVSS N11 Power Ground for internal PLL. The mark shows major revised points. Analog Signal Pin Name RREF 4 Ball No. P12 Direction Buffer Type Active Level － Analog － Function Reference resistor connection. Preliminary Data Sheet PD720200 System clock Pin Name XT1 Ball No. N14 Direction Buffer Type Active Level I OSC － Function Oscillator in During 24 MHz crystal mode, connect to 24 MHz crystal. In using external 48 MHz clock, this pin must be clamped to low. XT2 M14 I/O OSC － Oscillator out or external clock input During 24 MHz crystal mode, connect to 24 MHz crystal. In using external 48 MHz clock, this pin is used for external 48 MHz clock input signal.. CSEL P6 I 3.3V Input － Clock select signal 0: 24 MHz crystal mode 1: 48 MHz external clock input System Interface signal Pin Name Ball No. Direction Buffer Type Active Level Function PONRSTB P5 I 3.3V Schmitt Input Low Power on reset signal. When supporting wakeup from D3cold, this signal should be pulled high with system auxiliary power supply. SMIB H1 O 3.3V Output Low System management Interrupt signal “SMI#”. (6mA) Preliminary Data Sheet 5 PD720200 PCI express Interface Pin Name Ball No. Direction Buffer Type Active Level Function PECLKP B2 I PCIE － PCI Express / USB3.0 100 MHz Reference Clock. PECLKN B1 I PCIE － PCI Express / USB3.0 100 MHz Reference Clock. PETXP D2 O PCIE － PCI Express Transmit Data. PETXN D1 O PCIE － PCI Express Transmit Data. PERXP F2 I PCIE － PCI Express Receive Data. PERXN F1 I PCIE － PCI Express Receive Data. PERSTB H2 I 3.3V Low PCI Express “PERST#” signal. Schmitt Input PEWAKEB K1 O Open Drain Low (6mA) PCI Express “WAKE#” signal. This signal is used for remote wakeup mechanism, and requests the recovery of power and reference clock input. PECREQB K2 O Open Drain (6mA) Low PCI Express “CLKREQ#” signal. This signal is used to request run/stop of reference clock for ExpressCard or Mini Card. AUXDET J2 I 3.3V Input High Auxiliary Power detect signal. This signal should be connected to auxiliary power line, when system supports remote wakeup from D3cold. PSEL J1 I 3.3V Input － PCI Express/ExpressCard select signal. １: Others ０: ExpressCard or Mini card USB Interface Pin Name Ball No. Direction Buffer Type Active Level Function U3TXDP (2:1) B6, B10 O USB3 － USB3.0 Transmit data D+ signal for super-speed U3TXDN (2:1) A6, A10 O USB3 － USB3.0 Transmit data D- signal for super-speed U3RXDP (2:1) B8, B12 I USB3 － USB3.0 Receive data D+ signal for super-speed U3RXDN (2:1) A8, A12 I USB3 － USB3.0 Receive data D- signal for super-speed U2DP (2:1) P8, P10 I/O USB2 － USB2.0 D signal for high-/full-/low-speed U2DM (2:1) N8, N10 I/O USB2 － USB2.0 D signal for high-/full-/low-speed OCI1B H13 I 3.3V Input Low OCI2B G14 Over-current status input signal for each downstream facing port. 0: Over-current condition is detected 1: No over-current condition is detected. PPON (2:1) H14, J14 O 3.3V Output (6mA) High USB port power supply control signal for each downstream facing ports. 0: Power supply OFF 1: Power supply ON 6 Preliminary Data Sheet PD720200 SPI Interface Pin Name SPISCK Ball No. M2 Direction Buffer Type Active Level O 3.3V Function － SPI serial flash ROM clock signal. － SPI serial flash ROM chip select signal. － SPI serial flash ROM data write signal. Output (6mA) SPICSB N2 O 3.3V Output (6mA) SPISI N1 O 3.3V Output (6mA) SPISO M1 I 3.3V Input SPI serial flash ROM data read signal. Preliminary Data Sheet 7 PD720200 2. ELECTRICAL SPECIFICATIONS Buffer List 3.3 V input buffer CSEL, AUXDET, OCI1B, OCI2B, PSEL 3.3 V input schmitt buffer PONRSTB, PERSTB 3.3 V IOL = 6mA output buffer SMIB, PPON(2:1) 3.3 V IOL = 6mA bi-directional buffer SPISO, SPISI, SPISCK, SPICSB N-ch open drain buffer PEWAKEB, PECREQB 3.3 V oscillator interface XT1, XT2 USB Classic interface U2DP(2:1), U2DN(2:1), RREF PCI Express Serdes USB Superspeed interface PECLKP, PECLKN, PETXP, PETXN, PERXP, PERXN U3TXDP(2:1), U3TXDN(2:1), U3RXDP(2:1), U3RXDN(2:1) 8 Preliminary Data Sheet PD720200 Terminology Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Input voltage Symbol Meaning VDD33, VDD10, Indicates the voltage range within which damage or reduced reliability will not U2AVDD33, U3AVDD33 result when power is applied to a VDD pin. VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into output pin. Operating temperature TA Indicates the ambient temperature range for normal logic operations. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current is applied to the device. Terms Used in Recommended Operating Range Parameter Power supply voltage Symbol VDD33, VDD10, U2AVDD33, Meaning Indicates the voltage range for normal logic operations occur when V SS = 0 V. U3AVDD33 High-level input voltage VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Term Used in DC Characteristics Parameter Symbol Meaning Off-state output leakage current IOZ Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. Preliminary Data Sheet 9 PD720200 Electrical Specifications Absolute Maximum Ratings Parameter Power supply voltage Symbol Condition Rating Units VDD33, U2AVDD33 U3AVDD33 0.5 ~ 4.6 V VDD10 0.5 ~ 1.4 V Input voltage, 3.3 V buffer VI VI < VDD33 + 0.5V 0.5 ~ 4.6 V Output voltage, 3.3 V buffer VO VO <VDD33 + 0.5V 0.5 ~ 4.6 V Output current IO 15 mA Storage temperature Tstg 65 ~ 125 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges Parameter Operating voltage Symbol Condition VDD33, U2AVDD33 U3AVDD33 VDD10 Min. Typ. Max. Units 3.0 3.3 3.6 V 0.9975 1.05 1.1025 V High-level input voltage VIH 2.0 VDD330.3 V Low-level input voltage VIL 0.3 0.8 V Operating ambient temperature TA 0 85 C DC Characteristics (V DD33 = 3.3V 10%, VDD10 = 1.05V 5%, TA = 0 to +85C) Parameter Symbol Condition Min. Max. Units Off-state output current IOZ VI = VDD or VSS 10 A Input leakage current II VI = VDD or VSS 10 A Low-level output voltage VOL IOL = 6mA 0.4 V High-level output voltage VOH IOH = 6mA 2.4 V Pin capacitance Parameter SPI Interface Pin capacitance 10 Symbol Condition CSPI Preliminary Data Sheet Min. Max. Units 5 pF PD720200 AC Characteristics (VDD33 = 3.3V 10%, VDD10 = 1.05V 5%, TA = 0 to 85C) System clock (XT1/XT2) ratings Parameter Symbol Clock frequency Condition FCLK Clock duty cycle Min. Typ. Max. Units Crystal 100 ppm 24 100 ppm MHz Oscillator block 100 ppm 48 100 ppm MHz 40 50 60 % TDUTY Remarks 1. Required accuracy of crystal or oscillator block is including initial frequency accuracy, the spread of Crystal capacitor loading, supply voltage, temperature and aging, etc. Power on Reset (PONRSTB) Timings Parameter Power on reset time Symbol Condition TPONRST Min. Figure 2-1 Max. 1 Units ms Remarks 1. There is no order to power-on of VDD33, U2AVDD33, U3AVDD33 and VDD10. 2. All power sources should be stable within 100ms from the fastest rising edge of power sources. 3. PONRSTB shall be de-asserted after all power sources and the system clock become stable. PCI Express Interface - Reference Clock (PECLKP and PECLKN) Timings Parameter Symbol Condition Min. Max. Units Rising Edge Rate TRISE Figure 2-5 0.6 4.0 V/ns Falling Edge Rate TFALL Figure 2-5 0.6 4.0 V/ns Differential Input High Voltage VIH Figure 2-8 150 Differential Input Low Voltage VIL Figure 2-8 Absolute crossing point voltage VCROSS Figure 2-3 Variation of VCROSS over all rising clock edge VCROSS DELTA Figure 2-4 Ring-back Voltage Margin VRB Figure 2-8 100 Time before VRB is allowed TSTABLE Figure 2-8 500 Average Clock Period Accuracy TPERIOD AVG 300 2800 ppm Absolute Period (including Jitter and Spread TPERIOD ABS 9.847 10.203 ps 150 ps 250 mV 150 mV 550 mV 140 mV 100 mV ps Spectrum) Cycle to Cycle Jitter VCCJITTER Absolute Max input voltage VMAX Figure 2-3 1.15 V Absolute Min input voltage VMIN\ Figure 2-3 0.3 V 60 % 20 % 60 Duty Cycle 40 Rising edge rate (PECLKP) to falling edge rate (PECLKN) matching Clock source DC impedance ZC-DC Figure 2-2 Preliminary Data Sheet 40 11 PD720200 PCI Express Interface - PERSTB and PEWAKEB Signal Timings Parameter Symbol Condition Min. Max. Units Power stable to PERSTB inactive TPVPERL Figure 2-1 100 ms PECLKP/PECLKN stable before PERSTB TPERST- Figure 2-1 100 s inactive CLK PCI Express Interface – Power-Up and PECREQB Signal Timings Parameter Symbol Condition Min. Max. Units 100 s Power Valid to PECREQB Output active TPVCRL Figure 2-9 Power Valid to PERSTB input inactive TPVPGL Figure 2-9 1 ms PECLKP/PECLKN stable before PERSTB TPE_RSTB- Figure 2-9 100 s inactive CLK PCI Express Interface – PECREQB Clock Control Timings Parameter Symbol Condition PECREQB de-asserted high to clock parked TCRHOFF Figure 2-10 PECREQB asserted low to clock active TCRLON Figure 2-10 12 Preliminary Data Sheet Min. Max. 0 Units ns 400 ns PD720200 PCI Express Interface – Differential Transmitter (TX) Specifications (Refer to PCI Express TM Base Specification Revision 2.0 for more information) (1/2) Parameter Unit Interval Symbol UI Differential Peak to Peak(p-p) Tx voltage swing VTX-DIFFp-p Low power differential p-p Tx voltage swing VTX-DIFFp-p-LOW Tx de-emphasis level ration Tx de-emphasis level ration VTX-DE-RATIO-3.5dB VTX-DE-RATIO-6dB 2.5GT/s 5.0GT/S. Units 399.88(min) 199.94(min) ps 400.12(max) 200.06(max) 0.8(min) 0.8(min) 1.2(max) 1.2(max) 0.4(min) 0.4(min) 1.2(max) 1.2(max) 3.0(min) 3.0(min) 4.0(max) 4.0(max) Not specified 5.5(min) V V dB dB 6.5(max) Instantaneous lone pulse width TMIN-PULSE Not specified 0.9(min) UI Transmitter Eye including all jitter sources TTX-EYE 0.75(min) 0.75(min) UI Maximum time between the jitter median and max deviation from the median TTX-EYE-MEDIAN-to- 0.125(max) Not specified UI Tx deterministic jitter >1.5MHz TTX-HF-DJ-DD Not specified 0.15(max) UI Tx RMS jitter > 1.5MHz TTX-LF-RMS Not specified 3.0 ps RMS Transmitter rise and fall time TTX-RISE-FALL 0.125(min) 0.15(max) UI Tx rise/fall mismatch TRF-MISMATCH Not specified 0.1(max) UI Maximum Tx PLL bandwidth BWTX-PLL 22(max) 16(max) MHz Minimum Tx PLL BW for 3dB peaking BWTX-PLL-LO-3DB 1.5(min) 8(min) MHz Minimum Tx PLL BW for 1dB peaking BWTX-PLL-LO-1DB Not specified 5(min) MHz Tx PLL peaking with 8MHz min BW PKGTX-PLL1 Not specified 3.0(max) dB Tx PLL peaking with 5MHz min BW PKGTX-PLL2 Not specified 1.0(max) dB Tx package plus Si differential return loss RLTX-DIFF 10(min) 10(min) for 0.05 – 1.25GHz dB MAX-JITTER 8(min) for 1.25 – 2.5GHz Tx package plus Si common mode return loss RLTX-CM 6(min) 6(min) dB DC differential Tx impedance ZTX-DIFF-DC 80(min) 120(max) 120(max) Tx AC common mode voltage (5GT/s) VTX-CM-AC-PP Not specified 100(max) mVPP Tx AC common mode voltage (2.5GT/s) VTX-CM-AC-P 20 Not specifed mV Transmitter short-circuit current limit ITX-SHORT 90(max) 90(max) mA Transmitter DC common-mode voltage VTX-DC-CM 0(min) 0(min) V 3.6(max) 3.6(max) 0(min) 0(min) 100(max) 100(max) Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle VTX-CM-DC-ACTIVEIDLE-DELTA Preliminary Data Sheet mV 13 PD720200 (2/2) Parameter Symbol Absolute Delta of DC Common Mode Voltage between PETXP and PETXN VTX-CM-DC-LINE- Electrical Idle Differential Peak Output Voltage VTX-IDLE-DIFF-AC-p DC Electrical Idle Differential Output Voltage VTX-IDLE-DIFF-DC The amount of voltage change allowed during Receiver Detection VTX-RCV-DETECT Minimum time spent in Electrical Idle Maximum time to transition to a valid DELTA 2.5GT/s 5.0GT/S. Units 0(min) 0(min) mV 25(max) 25(max) 0(min) 0(min) 20(max) 20(max) Not specified 0(min) mV mV 5(max) 600(max) 600(max) mV TTX-IDLE-MIN 20(min) 20(min) ns TTX-IDLE-SET-TO-IDLE 8(max) 8(max) ns Maximum time to transition to valid diff TTX-IDLE-TO-DIFF- 8(max) 8(max) ns signaling after leaving Electrical Idle DATA Crosslink random timeout TCROSSLINK 1.0(max) 1.0(max) ns Lane-to-Lane Output Skew LTX-SKEW 500ps + 2UI(max) 500ps + 4UI(max) ps AC Coupling Capacitor CTX 75(min) 75(min) nF 200(max) 200(max) Electrical Idle after sending an EIOS 14 Preliminary Data Sheet PD720200 PCI Express Interface – Differential Receiver (RX) Specifications (Refer to PCI Express TM Base Specification Revision 2.0 for more information) Parameter Unit Interval Symbol UI Differential Rx peak-peak voltage for common Reference clock Rx architecture VRX-DIFF-PP-CC Differential Rx peak-peak voltage for data VRX-DIFF-PP-DC clocked Rx architecture 2.5GT/s 5.0GT/S. Units 399.88(min) 199.94(min) ps 400.12(max) 200.06(max) 0.175(min) 0.120(min) 1.2(max) 1.2(max) 0.175(min) 0.100(min) 1.2(max) 1.2(max) V V Receiver eye time opening tRX-EYE 0.40(min) Not specified UI Max Rx inherent timing error tRX-TJ-CC Not specified 0.40(max) UI Max Rx inherent timing error tRX-TJ-DC Not specified 0.34(max) UI Max Rx inherent deterministic timing error tRX-DJ-DD-CC Not specified 0.30(max) UI Max Rx inherent deterministic timing error tRX-DJ-DD-DC Not specified 0.24(max) UI Max time delta between median and deviation from median tRX-EYE-MEDIAN-to- 0.3(max) Not specified UI Minimum width pulse at Rx tRX-MIN-PULSE Not specified 0.6(min) UI Min/max pulse voltage on consecutive UI tRX-MAX-MIN-RATIO Not specified 5(max) - Maximum Rx PLL bandwidth BWRX-PLL-HI 22(max) 16(max) MHz Minimum Rx PLL BW for 3dB peaking BWRX-PLL-LO-3DB 1.5(min) 8(min) MHz Minimum Rx PLL BW for 1dB peaking BWRX-PLL-LO-1DB Not specified 5(min) MHz Rx PLL peaking with 8 MHz min BW PKGRX-PLL1 Not specified 3.0 dB Rx PLL peaking with 5MHz min BW PKGRX-PLL2 Not specified 1.0 dB Rx package plus Si differential return loss RLRX-DIFF 10(min) 10(min) for 0.05 – dB MAX-JITTER 1.25GHz 8(min) for 1.25 – 2.5GHz Common mode Rx return loss RLRX-CM 6(min) 6(min) dB Receiver DC single ended impedance ZRX-DC 40(min) 40(min) 60(max) 60(max) 80(min) Not specified DC differential impedance ZRX-DIFF-DC 120(max) Rx AC common mode voltage VRX-CM-AC-P 150(max) 150(max) mVP DC input CM input Impedance for V>0 durin ZRX-HIGH-IMP-DC-POS 50k(min) 50k(min) DC input CM input Impedance for V<0 during Reset or power down ZRX-HIGH-IMP-DC-NEG 1.0k(min) 1.0k(min) Electrical Idle Detect Threshold VRX-IDLE-DET-DIFFp-p 65(min) 65(min) mV 175(max) 175(max) 10(max) 10(max) ms 20(max) 8(max) ns Reset or power down Unexpected Electrical Idle Enter Detect Threshold Integration Time tRX-IDLE-DET-DIFF- Lane to Lane skew LRX-SKEW ENTERTIME Preliminary Data Sheet 15 PD720200 USB3.0 SuperSpeed Interface – Differential Transmitter (TX) Specifications (Refer to Universal Serial Bus 3.0 Specification Revision 1.0 for more information) Transmitter Normative Electrical Parameters Parameter Symbol Min Max Units 199.94 200.06 ps Unit Interval UI Differential p-p Tx voltage swing VTX-DIFF-PP 0.8 1.2 V Low-Power Differential p-p Tx voltage VTX-DIFF-PP-LOW 0.4 1.2 V Tx de-emphasis VTX-DE-RATIO 3.0 4.0 dB DC differential impedance RTX-DIFF-DC 72 120 The amount of voltage change allowed during Receiver Detection VTX-RCV-DETECT 0.6 V AC Coupling Capacitor CAC-COUPLING 200 nF Maximum slew rate tCDR-SLEW-MAX swing 75 10 ms/s Max Units Transmitter Informative Electrical Parameters Parameter Symbol Min Deterministic min pulse tMIN-PULSE-Dj 0.96 UI Tx min pulse tMIN-PULSE-Tj 0.90 UI Transmitter Eye tTX-EYE 0.625 UI Tx deterministic jitter tTX-DJ-DD 0.205 UI Tx input capacitance for return loss CTX-PARASITIC 1.25 pf Transmitter DC common mode impedance RTX-DC 30 Transmitter short-circuit current limit ITX-SHORT 60 mA Transmitter DC common-mode voltage VTX-DC-CM 2.2 V Tx AC common mode voltage VTX-CM-AC-PP-ACTIVE 100 mVp-p Absolute DC Common Mode Voltage between U1 and U0 VTX-CM-DC-ACTIVE- 200 mV Electrical Idle Differential Peak- Peak VTX-IDLE-DIFF-AC-pp 0 10 mV VTX-IDLE-DIFF-DC 0 10 mV 18 0 IDLE-DELTA Output voltage DC Electrical Idle Differential Output Voltage 16 Preliminary Data Sheet PD720200 USB3.0 SuperSpeed Interface – Differential Receiver (RX) Specifications (Refer to Universal Serial Bus 3.0 Specification Revision 1.0 for more information) Receiver Normative Electrical Parameters Parameter Symbol Min Max Units 199.94 200.06 ps Unit Interval UI Receiver DC common mode impedance RRX-DC 18 30 DC differential impedance RRX-DIFF-DC 72 120 DC Input CM Input Impedance for V>0 during Reset of Power down ZRX-HIGH-IMP-DC-POS 25k LFPS Detect Threshold VRX-LFPS-DET-DIFF-p-p 100 300 mV Min Max Units Receiver Informative Electrical Parameters Parameter Symbol Differential Rx peak-to-peak voltage VRX-DIFF-PP-POST-EQ 30 mV Max Rx inherent timing error TRX-Tj 0.45 UI Max Rx inherent deterministic timing error TRX-DJ-DD 0.285 UI Rx input capacitance for return loss CRX-PARASITIC 1.1 pf Rx AC common mode voltage VRX-CM-AC-P 150 mVPeak Rx AC common mode voltage during the U1 to U0 transition VRX-CM-DC-ACTIVE-IDLE- 200 mVPeak DELTA-P Preliminary Data Sheet 17 PD720200 USB2.0 interface (Refer to Universal Serial Bus Specification Revision 2.0 for more information) Low-speed Source Electrical Characteristics Parameter Symbol Min Max Units Driver Characteristics: Transition Time: Rise Time TLR 75 300 ns Fall Time TLF 75 300 ns Rise and Fall Time Matching TLRFM 80 125 % 1.49925 1.50075 Mb/s TLDEOP 40 100 ns To Next Transition TDDJ1 25 25 ns For Paired Transitions TDDJ2 14 14 ns To Next Transition TUJR1 152 152 ns For Paired Transitions TUJR2 200 200 ns Source SE0 interval of EOP TLEOPT 1.25 1.50 s Receiver SE0 interval of EOP TLEOPR 670 Width of SE0 interval during differential transition TLST Clock Timings: Low-speed Data Rate TLDRATHS Low-speed Data Timing: Source Jitter for Differential Transition to SE0 Transition Source Jitter total (including frequency tolerance): Differential Receiver Jitter: 18 ns 210 Preliminary Data Sheet ns PD720200 Full-speed Source Electrical Characteristics Parameter Symbol Min Max Units Driver Characteristics: Rise Time TFR 4 20 ns Fall Time TFF 4 20 ns Differential Rise and Fall Time Matching TFRFM 90 111.11 % Clock Timings: Full-speed Data Rate TFDRATHS 11.9940 12.0060 Mb/s Frame Interval TFRAME 0.9995 1.0005 ms Consecutive Frame Interval Jitter TRFI 42 ns 2 5 ns Full-speed Data Timing: Source Jitter for Differential Transition to TFDEOP SE0 Transition Source Jitter total (including frequency tolerance): To Next Transition TDJ1 3.5 3.5 ns For Paired Transitions TDJ2 4 4 ns To Next Transition TJR1 18.5 18.5 ns For Paired Transitions TJR2 9 9 ns Source SE0 interval of EOP TFEOPT 160 175 ns Receiver SE0 interval of EOP TFEOPR 82 Width of SE0 interval during differential transition TFST Receiver Jitter: ns 14 Preliminary Data Sheet ns 19 PD720200 High-speed Source Electrical Characteristics Parameter Symbol Min Max Units Driver Characteristics: Rise Time (10% - 90%) THSR 500 ps Fall Time (10% - 90%) THSF 500 ps Driver waveform requirements Figure 2-14 Clock Timings: High-speed Data Rate THSDRAT 497.760 480.240 Mb/s Microframe Interval THSFRAME 124.9375 125.0625 s Consecutive Microframe Interval Difference THSRFI 4 high-speed bit times High-speed Data Timing: Data source jitter Figure 2-14 Receiver jitter tolerance Figure 2-12 Hub Event Timings Parameter Time to detect a downstream facing port Symbol Min Max Units TDCNN 2.5 2000 s TDDIS 2 2.5 s TDRSMDN 20 connect event Time to detect a disconnect event at a hub’s downstream facing port Duration of driving resume to a ms downstream port Time from detecting downstream resume to rebroadcast TURSM Inter-packet delay for packets traveling in THSIPDSD 1.0 88 ms Bit same direction times Inter-packet delay for packets traveling in opposite direction THSIPDOD 8 Inter-packet delay for root hub response for high-speed THSRSPIPD1 Time for which a Chirp J or Chirp K must be continuously detected by hub during TFILT Bit times 192 Bit times s 2.5 Reset handshake Time after end of device Chirp K by which hub must start driving first Chirp K in the hub’s chirp sequence TDCHBIT Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream by hub during reset TDCHBIT Time before end of reset by which a hub must end its downstream chirp sequence TDCHSE0 20 Preliminary Data Sheet 100 s 40 60 s 100 500 s PD720200 SPI Type Serial ROM Interface SPI Type Serial ROM Interface Signals Timing (SPI Mode 0) Parameter Symbol Min. SPISCK Clock Frequency Max. Units 32 MHz Clock pulses width Low tSCLLOW Clock pulses width high tSCLHIGH 9 ns SPICSB disable time tSCSDIS 25 ns SPICSB setup time tSCSSU 25 ns SPICSB hold time tSCSH 10 ns SPISI setup time to SPISCK rising edge tSDWSU 5 ns SPISI hold time from SPISCK rising edge tSDWH 5 ns SPISO validate time from SPISCK falling edge tSDRVALID SPISO hold time from SPISCK falling edge tSDRH SPISO disable time from SPICSB disabled tSDRDIS Preliminary Data Sheet ns 9 0 ns ns 100 ns 21 PD720200 Figure 2-1. Power Up and Reset Power Stable VDD33 & VDD10 XT1/XT2 Stable XT1/XT2 PONRSTB TPONRST PECLKP(N) Stable PECLKP PECLKN PERSTB TPERST-CLK TPVPERL Figure 2-2. PCI Express Single-Ended Measurement Points for Absolute Cross Point and Swing PECLKP PECLKN Figure 2-3. PCI Express Single-Ended Measurement Points for Absolute Cross Point and Swing PECLKN PECLKP 22 Preliminary Data Sheet PD720200 Figure 2-4. PCI Express Single-Ended Measurement Points for Delta Cross Point PECLKN PECLKP Figure 2-5. PCI Express Single-Ended Measurement Points for Rise and Fall Time Matching PECLKN PECLKN PECLKP PECLKP Figure 2-6. PCI Express Differential Measurement Points for Duty Cycle and Period PECLKP PECLKN Figure 2-7. PCI Express Differential Measurement Points for Rise and Fall Time PECLKP PECLKN Preliminary Data Sheet 23 PD720200 Figure 2-8. PCI Express Differential Measurement Points for Ring-back PECLKP PECLKN Figure 2-9. PCI Express Power-Up PECREQB Timing VDD33 & VDD10 PECRQB TPERSTB-CLK PERSTB PECLKP PECLKN VDD33 VDD10 Figure 2-10. PCI Express PECREQB Clock Control Timing High VDD33 & VDD10 PECRQB PECLKP PECLKN 24 Preliminary Data Sheet PD720200 Figure 2-11. Differential Input Sensitivity Range for Low-/Full-speed Figure 2-12. Receiver Sensitivity for Transceiver at U2DP/U2DM Figure 2-13. Receiver Measurement Fixtures Preliminary Data Sheet 25 PD720200 Figure 2-14. Transmit Waveform for Transceiver at U2DP/U2DM Figure 2-15. Transmitter Measurement Fixtures Figure 2-16. Differential data jitter for low-/full-speed TPERIOD Differential Data Lines Crossover Points Consecutive Transitions N * TPERIOD + TxDJ1 Paired Transitions N * TPERIOD + TxDJ2 26 Preliminary Data Sheet PD720200 Figure 2-17. Differential-to-EOP transition skew and EOP width for low-/full-speed Crossover Points Extended TPERIOD Crossover Points Differential Data Lines Diff.Data-toSE0 Skew N * TPERIOD + TxDEOP Source EOP Width: TFEOPT TLEOPT Receiver EOP Width: TFEOPR TLEOPR Figure 2-18. Receiver jitter tolerance for low-/full-speed TPERIOD Differential Data Lines TxJR TxJR1 TxJR2 Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2 Figure 2-19. SPI Type Serial ROM Signal Timing SPICSB SPISCK SPISI SPISO Preliminary Data Sheet 27 PD720200 3. PACKAGE DRAWINGS PD720200F1-DAK-A 28 Preliminary Data Sheet PD720200 4. RECOMMENDED SOLDERING CONDITIONS The PD720200 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.htm l) PD720200F1-DAK-A: 176-pin plastic FBGA (10 × 10) Soldering Method Infrared reflow Soldering Conditions Peak package’s surface temperature: 260°C, Reflow time: 60 seconds or less (220°C Symbol IR60-107-3 or higher), Maximum allowable number of reflow processes: 3, Note Exposure limit : 7 days (10 hours pre-backing is required at 125°C afterwards), Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Note The Maximum number of days during which the product can be stored at a temperature of 25°C and a relative humidity of 65% or less after dry-pack package is opened. Preliminary Data Sheet 29 PD720200 [MEMO] 30 Preliminary Data Sheet PD720200 Preliminary Data Sheet 31 All logo, trademarks or registered trademarks mentioned in this document are the intellectual property of their respective owners.