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DATA SHEET MOS INTEGRATED CIRCUIT µPD720101 USB 2.0 HOST CONTROLLER The µPD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The µPD720101 is integrated 3 host controller cores with PCI interface and USB 2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. µPD720101 User’s Manual: S16336E FEATURES • • • • • • • • • • • • • • • Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps) Compliant with Open Host Controller Interface Specification for USB Rev 1.0a Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0 PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling. Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores. All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. Configurable number of downstream facing ports (2 to 5) 32-bit 33 MHz host interface compliant to PCI Specification release 2.2 Supports PCI Mobile Design Guide Revision 1.1 Supports PCI-Bus Power Management Interface Specification release 1.1 PCI bus bus-master access System clock is generated by 30 MHz X’tal or 48 MHz clock input. − System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see µPD720101 User’s Manual. Operational registers direct-mapped to PCI memory space Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation. 3.3 V power supply, PCI signal pins have 5 V tolerant circuit. ORDERING INFORMATION Part Number µPD720101GJ-UEN µPD720101GJ-UEN-A µPD720101F1-EA8 µPD720101F1-EA8-A Package Remark 144-pin plastic LQFP (Fine pitch) (20 × 20) 144-pin plastic LQFP (Fine pitch) (20 × 20) Lead-free product 144-pin plastic FBGA (12 × 12) 144-pin plastic FBGA (12 × 12) Lead-free product The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16265EJ5V0DS00 (5th edition) Date Published March 2005 NS CP (N) Printed in Japan The mark shows major revised points. 2002 µPD720101 BLOCK DIAGRAM PCI Bus PME0 INTA0 INTB0 INTC0 PCI Bus Interface WakeUp_Event WakeUp_Event WakeUp_Event Arbiter OHCI Host Controller #1 OHCI Host Controller #2 EHCI Host Controller SMI0 Root Hub PHY Port 1 Port 2 Port 3 Port 4 USB Bus Remark INTB0/INTC0 can be shared with INTA0 through BIOS setting. (Planning) 2 Data Sheet S16265EJ5V0DS Port 5 µPD720101 PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target function which comply with PCI specification release 2.2. The number of enabled ports is set by bit in configuration space. Arbiter : arbitrates among two OHCI host controller cores and one EHCI host controller core. OHCI Host Controller #1 : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5. OHCI Host Controller #2 : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4. EHCI Host Controller : handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5. Root Hub : handles USB hub function in host controller and controls connection (routing) between PHY : consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, INTA0 : is the PCI interrupt signal for OHCI Host Controller #1. INTB0 : is the PCI interrupt signal for OHCI Host Controller #2. INTC0 : is the PCI interrupt signal for EHCI Host Controller. SMI0 : is the interrupt signal which is specified by Open Host Controller Interface Specification host controller core and port. etc. for USB Rev 1.0a and Enhanced Host Controller Interface Specification Rev 1.0. The SMI signal of each OHCI Host Controller and EHCI Host Controller appears at this signal. PME0 : is the interrupt signal which is specified by PCI-Bus Power Management Interface Specification release 1.1. Wakeup signal of each host controller core appears at this signal. COMPARISON WITH THE µPD720100A µPD720100A µPD720101 (2nd generation) EHCI revision 0.95 1.0 EHCI 1 1 OHCI 2 2 Legacy support Parallel IRQ out support No parallel IRQ support Clock 48 MHz OSC or 30 MHz OSC/X’tal 48 MHz OSC or 30 MHz X’tal Package 176-pin BGA (FP) or 160-pin LQFP 144-pin BGA (FP) or 144-pin LQFP Data Sheet S16265EJ5V0DS 3 µPD720101 PIN CONFIGURATION • 144-pin plastic LQFP (Fine pitch) (20 × 20) µPD720101GJ-UEN µPD720101GJ-UEN-A 110 115 120 125 130 135 140 1 105 5 100 10 95 15 90 20 85 25 80 30 75 70 65 60 55 50 VSS VSS AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 CBE20 FRAME0 IRDY0 TRDY0 DEVSEL0 STOP0 VSS VDD VDD_PCI PERR0 SERR0 PAR CBE10 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 CBE00 AD7 VSS VSS 45 35 40 VDD VDD OCI1 PPON1 OCI2 PPON2 OCI3 PPON3 OCI4 PPON4 OCI5 PPON5 VCCRST0 PME0 PCLK VBBRST0 VDD_PCI VSS VDD INTA0 INTB0 INTC0 GNT0 REQ0 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 CBE30 IDSEL VSS VDD 144 VSS VSS RSDP5 DP5 VDD DM5 RSDM5 VSS RSDP4 DP4 VDD DM4 RSDM4 VSS RSDP3 DP3 VDD DM3 RSDM3 VSS VDD VSS VSS RSDP2 DP2 VDD DM2 RSDM2 VSS RSDP1 DP1 VDD DM1 RSDM1 VSS VSS Top View 4 Data Sheet S16265EJ5V0DS VDD AVSS AVDD AVSS AVSS(R) RREF AVDD VSS VSS NANDTEST SRDTA SRMOD SRCLK XT1/SCLK XT2 VDD NTEST1 TEST LEGC SMC TEB AMC SMI0 N.C. N.C. CRUN0 AD0 AD1 VDD_PCI AD2 AD3 AD4 AD5 AD6 VDD VDD µPD720101 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VDD 37 VSS 73 VDD 109 VSS 2 VDD 38 VSS 74 VDD 110 VSS 3 OCI1 39 AD23 75 AD6 111 RSDM1 4 PPON1 40 AD22 76 AD5 112 DM1 5 OCI2 41 AD21 77 AD4 113 VDD 6 PPON2 42 AD20 78 AD3 114 DP1 7 OCI3 43 VDD 79 AD2 115 RSDP1 8 PPON3 44 AD19 80 VDD_PCI 116 VSS 9 OCI4 45 AD18 81 AD1 117 RSDM2 10 PPON4 46 AD17 82 AD0 118 DM2 11 OCI5 47 AD16 83 CRUN0 119 VDD 12 PPON5 48 CBE20 84 N.C. 120 DP2 13 VCCRST0 49 FRAME0 85 N.C. 121 RSDP2 14 PME0 50 IRDY0 86 SMI0 122 VSS 15 PCLK 51 TRDY0 87 AMC 123 VSS 16 VBBRST0 52 DEVSEL0 88 TEB 124 VDD 17 VDD_PCI 53 STOP0 89 SMC 125 VSS 18 VSS 54 VSS 90 LEGC 126 RSDM3 19 VDD 55 VDD 91 TEST 127 DM3 20 INTA0 56 VDD_PCI 92 NTEST1 128 VDD 21 INTB0 57 PERR0 93 VDD 129 DP3 22 INTC0 58 SERR0 94 XT2 130 RSDP3 23 GNT0 59 PAR 95 XT1/SCLK 131 VSS 24 REQ0 60 CBE10 96 SRCLK 132 RSDM4 25 AD31 61 AD15 97 SRMOD 133 DM4 26 AD30 62 AD14 98 SRDTA 134 VDD 27 AD29 63 AD13 99 NANDTEST 135 DP4 28 AD28 64 AD12 100 VSS 136 RSDP4 29 AD27 65 AD11 101 VSS 137 VSS 30 AD26 66 AD10 102 AVDD 138 RSDM5 31 AD25 67 AD9 103 RREF 139 DM5 32 AD24 68 AD8 104 AVSS(R) 140 VDD 33 CBE30 69 CBE00 105 AVSS 141 DP5 34 IDSEL 70 AD7 106 AVDD 142 RSDP5 35 VSS 71 VSS 107 AVSS 143 VSS 36 VDD 72 VSS 108 VDD 144 VSS Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Pins 84 and 85 must be clamped high on the board. Data Sheet S16265EJ5V0DS 5 µPD720101 • 144-pin plastic FBGA (12 × 12) µPD720101F1-EA8 µPD720101F1-EA8-A Bottom View 25 26 27 28 29 30 31 32 33 34 35 36 24 71 72 73 74 75 76 77 78 79 80 81 82 37 13 23 70 111 112 113 114 115 116 117 118 119 120 83 38 12 22 69 110 137 138 139 140 121 84 39 11 21 68 109 122 85 40 10 20 67 108 136 141 123 86 41 9 19 66 107 135 142 124 87 42 8 18 65 106 134 143 125 88 43 7 17 64 105 133 144 126 89 44 6 16 63 104 127 90 45 5 15 62 103 128 91 46 4 14 61 102 101 13 60 59 12 N P 6 14 132 131 130 129 100 99 98 97 96 95 94 93 92 47 3 58 57 56 55 54 53 52 51 50 49 48 2 11 10 9 8 7 6 5 4 3 2 1 M L K J H G F E D C B Data Sheet S16265EJ5V0DS 1 A µPD720101 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 37 VDD 73 VDD 109 NANDTEST 2 AD23 38 VDD 74 RSDP1 110 VSS 3 AD20 39 PPON2 75 VDD 111 AVSS 4 AD18 40 OCI4 76 VDD 112 VSS 5 CBE20 41 PPON5 77 DP3 113 DM2 6 TRDY0 42 PCLK 78 VDD 114 RSDP2 7 SERR0 43 INTC0 79 RSDM5 115 VSS 8 AD15 44 AD31 80 VDD 116 VDD 9 AD12 45 AD28 81 DP5 117 RSDM4 10 AD9 46 AD25 82 VSS 118 DP4 11 AD7 47 VDD 83 OCI1 119 VSS 12 VSS 48 VSS 84 OCI2 120 PPON1 13 VDD 49 VSS 85 OCI3 121 PPON3 14 VDD 50 AD22 86 OCI5 122 PPON4 15 AD3 51 AD21 87 VBBRST0 123 VCCRST0 16 AD1 52 VDD 88 INTB0 124 VDD_PCI 17 N.C. 53 AD16 89 AD30 125 INTA0 18 AMC 54 DEVSEL0 90 AD26 126 REQ0 19 XT2 55 PERR0 91 AD24 127 AD29 20 SRMOD 56 AD14 92 IDSEL 128 AD27 21 VSS 57 AD10 93 CBE30 129 IRDY0 22 RREF 58 AD8 94 AD19 130 VSS 23 VDD 59 CBE00 95 AD17 131 VDD 24 AVSS 60 VSS 96 FRAME0 132 PAR 25 VSS 61 AD6 97 STOP0 133 SMI0 26 RSDM1 62 AD4 98 VDD_PCI 134 LEGC 27 DP1 63 AD2 99 CBE10 135 TEST 28 RSDM2 64 CRUN0 100 AD13 136 XT1/SCLK 29 DP2 65 TEB 101 AD11 137 VSS 30 VSS 66 VDD 102 AD5 138 RSDM3 31 RSDP3 67 SRDTA 103 VDD_PCI 139 DM3 32 DM4 68 AVDD 104 AD0 140 VSS 33 RSDP4 69 AVSS(R) 105 N.C. 141 PME0 34 DM5 70 AVDD 106 SMC 142 VSS 35 RSDP5 71 VSS 107 NTEST1 143 VDD 36 VSS 72 DM1 108 SRCLK 144 GNT0 Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Pins 17 and 105 must be clamped high on the board. Data Sheet S16265EJ5V0DS 7 µPD720101 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Function Level 8 AD (31 : 0) I/O 5 V PCI I/O PCI “AD [31 : 0]” signal CBE (3 : 0)0 I/O 5 V PCI I/O PCI “C/BE [3 : 0]” signal PAR I/O 5 V PCI I/O PCI “PAR” signal FRAME0 I/O 5 V PCI I/O PCI “FRAME#” signal IRDY0 I/O 5 V PCI I/O PCI “IRDY#” signal TRDY0 I/O 5 V PCI I/O PCI “TRDY#” signal STOP0 I/O 5 V PCI I/O PCI “STOP#” signal IDSEL I 5 V PCI input PCI “IDSEL” signal DEVSEL0 I/O 5 V PCI I/O PCI “DEVSEL#” signal REQ0 O 5 V PCI output PCI “REQ#” signal GNT0 I 5 V PCI input PCI “GNT#” signal PERR0 I/O 5 V PCI I/O PCI “PERR#” signal SERR0 O 5 V PCI N-ch open drain PCI “SERR#” signal INTA0 O 5 V PCI N-ch open drain Low PCI “INTA#” signal INTB0 O 5 V PCI N-ch open drain Low PCI “INTB#” signal INTC0 O 5 V PCI N-ch open drain Low PCI “INTC#” signal PCLK I 5 V PCI input VBBRST0 I 5 V tolerant input PCI “CLK” signal Low Hardware reset for chip CRUN0 I/O 5 V PCI I/O PCI “CLKRUN#” signal PME0 O 5 V PCI N-ch open drain Low PCI “PME#” signal VCCRST0 I 5 V tolerant input Low Reset for power management SMI0 O 5 V tolerant N-ch open drain Low System management interrupt output XT1/SCLK I Input System clock input or oscillator in XT2 O Output oscillator out DP (5 : 1) I/O USB high speed D+ I/O USB high speed D+ signal DM (5 : 1) I/O USB high speed D− I/O USB high speed D− signal RSDP (5 : 1) O USB full speed D+ Output USB full speed D+ signal RSDM (5 : 1) O USB full speed D− Output USB full speed D− signal OCI (5 : 1) I (I/O) Input Low USB root hub port’s overcurrent status input PPON (5 : 1) O (I/O) Output High USB root hub port’s power supply control output LEGC I (I/O) Input High Legacy support switch SRCLK O Output Serial ROM clock out SRDTA I/O I/O Serial ROM data SRMOD I Input with 50 kΩ pull down R RREF A Analog NTEST1 I Input with 12 kΩ pull down R High Serial ROM input enable Reference resistor High Data Sheet S16265EJ5V0DS Test pin µPD720101 (2/2) Pin Name I/O Buffer Type Active Function Level SMC I Input with 50 kΩ pull down R High Scan mode control TEB I Input with 50 kΩ pull down R High BIST enable AMC I Input with 50 kΩ pull down R High ATG mode control TEST I Input with 50 kΩ pull down R High Test control NANDTEST I Input with 50 kΩ pull down R High NAND tree test enable AVDD VDD for analog circuit VDD VDD VDD_PCI 5 V (5 V PCI) or 3.3 V (3.3 V PCI) AVSS VSS for analog circuit VSS VSS N.C. No connection Remarks 1. “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit. 2. “5 V PCI” indicates a PCI buffer, which complies with the 3 V PCI standard, has a 5 V tolerant circuit. It does not indicate that this buffer fully complies with 5 V PCI standard. However, this function can be used for evaluating the operation of a device on a 5 V add-in card. 3. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use. Data Sheet S16265EJ5V0DS 9 µPD720101 2. 2.1 HOW TO CONNECT TO EXTERNAL ELEMENTS Handling Unused Pins To realize less than 5 ports host controller implementation, appropriate value shall be set to Port No field in EXT1 register. And unused pins shall be connected as shown below. Pin 2.2 Direction Connection Method DPx I/O Tied to "low". DMx I/O Tied to "low". RSDPx O No connection (Open) RSDMx O No connection (Open) OCIx I “H” clamp PPONx O No connection (Open) USB Port Connection Figure 2-1. USB Downstream Port Connection from Power switch output LSI Downstream port USB A receptacle connector RSDM DM DP RSDP Rs = 36 Ω ±1% VBUS DD+ GND Rs = 36 Ω ±1% 1 2 3 4 15 kΩ ±5% Rs + Ron (Resistance for internal driver which is active) = 45 Ω ±10% 10 Data Sheet S16265EJ5V0DS µPD720101 2.3 PLL Capacitor Connection Figure 2-2. RREF Connection LSI RREF 9.1kΩ ±1% AVSS(R) AVSS 2.4 X’tal Connection Figure 2-3. X’tal Connection LSI XT1/SCLK R X'tal XT2 C2 C1 Vss The following crystals are evaluated on our reference design board. Table 2-1 shows the external parameters. Data Sheet S16265EJ5V0DS 11 µPD720101 Table 2-1. External Parameters Vender KDS Note 1 NDK Note 2 X’tal R C1 C2 AT-49 30.000 MHz 100 Ω 12 pF 10 pF AT-41 30.000 MHz 100 Ω 10 pF 10 pF AT-41CD2 30.000 MHz 100 Ω 10 pF 10 pF NX3225DA 30.000 MHz 100 Ω 10 pF 10 pF NX5032GA 30.000 MHz 100 Ω 10 pF 10 pF NX8045GB 30.000 MHz 100 Ω 10 pF 10 pF Notes 1. DAISHINKU CORP. 2. NIHON DEMPA KOGYO CO., LTD. In using these crystals, contact KDS or NDK to get the specification on external components to be used in conjunction with the crystal. KDS's home page: http://www.kdsj.co.jp NDK's home page: http://www.ndk-j.co.jp 2.5 External Serial ROM Connection Figure 2-4. External Serial ROM Connection LSI SRMOD 3.3V External seriral ROM 1.5 kΩ VDD A0 WP A1 SRCLK SCL A2 SRDTA SDA GND C SRMOD/SRCLK/SRDTA can be opened, when serial ROM is not necessary on board. 12 Data Sheet S16265EJ5V0DS µPD720101 3. ELECTRICAL SPECIFICATIONS 3.1 Buffer List • 3 V input buffer with pull down resistor NTEST1, TEST, SRMOD, NANDTEST, SMC, AMC, TEB • 3 V PCI IOL = 9 mA 3-state output buffer PPON(5:1), SRCLK • 3 V IOL = 9 mA bi-directional buffer LEGC, SRDTA • 3 V IOL = 9 mA bi-directional buffer with enable (OR type) OCI(5:1) • 3 V oscillator interface XT1/SCLK, XT2 • 5 V input buffer VBBRST0, VCCRST0 • 5 V IOL = 12 mA N-ch open drain buffer SMI0, PME0, INTA0, INTB0, INTC0, SERR0 • 5 V PCI input buffer with enable (OR type) PCLK, GNT0, IDSEL • 5 V PCI IOL = 12 mA 3-state output buffer REQ0 • 5 V PCI IOL = 9 mA bi-directional buffer with input enable (OR-type) AD(31:0), CBE(3:0)0, PAR, FRAME0, IRDY0, TRDY0, STOP0, DEVSEL0, PERR0, CRUN0 • USB interface, analog signal DP(5:1), DM(5:1), RSDP(5:1), RSDM(5:1), RREF Above, “5 V” refers to a 3 V buffer with 5 V tolerant circuit. Therefore, it is possible to have a 5 V connection for an external bus, but the output level will be only up to 3 V, which is the VDD voltage. Similarly, “5 V PCI” above refers to a PCI buffer that has a 5 V tolerant circuit, which meets the 3 V PCI standard; it does not refer to a PCI buffer that meets the 5 V PCI standard. Data Sheet S16265EJ5V0DS 13 µPD720101 3.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Input voltage Symbol Meaning VDD, AVDD, Indicates voltage range within which damage or reduced reliability will not VDD_PCI result when power is applied to a VDD pin. VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Operating ambient temperature TA Indicates the ambient temperature range for normal logic operations. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. Terms Used in Recommended Operating Range Parameter Power supply voltage High-level input voltage Symbol Meaning VDD, AVDD, Indicates the voltage range for normal logic operations occur when VSS = 0 VDD_PCI V. VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Terms Used in DC Characteristics Parameter Off-state output leakage current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Output short circuit current IOS Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that flows from the output pins when the rated highlevel output voltage is being applied. 14 Data Sheet S16265EJ5V0DS µPD720101 3.3 Electrical Specifications Absolute Maximum Ratings Parameter Power supply voltage Input voltage, 5 V buffer Symbol Condition Rating Unit VDD −0.5 to +4.6 V AVDD −0.5 to +4.6 V VDD_PCI −0.5 to +6.0 V −0.5 to +6.6 V −0.5 to +4.6 V −0.5 to +6.6 V −0.5 to +4.6 V 3.0 V ≤ VDD ≤ 3.6 V VI VI < VDD + 3.0 V Input voltage, 3.3 V buffer 3.0 V ≤ VDD ≤ 3.6 V VI VI < VDD + 0.5 V Output voltage, 5 V buffer 3.0 V ≤ VDD ≤ 3.6 V VO VO < VDD + 3.0 V Output voltage, 3.3 V buffer 3.0 V ≤ VDD ≤ 3.6 V VO VO < VDD + 0.5 V Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges Parameter Operating voltage Symbol Min. Typ. Max. Unit VDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V In 3.3 V PCI 3.0 3.3 3.6 V In 5 V PCI 4.75 5.0 5.25 V VDD_PCI High-level input voltage Condition VIH 3.3 V high-level input voltage 2.0 VDD V 5.0 V high-level input voltage 2.0 5.5 V 3.3 V low-level input voltage 0 0.8 V 5.0 V low-level input voltage 0 0.8 V Low-level input voltage VIL Data Sheet S16265EJ5V0DS 15 µPD720101 DC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°C) Control pin block Parameter Off-state output current Symbol IOZ Output short circuit current IOS Low-level output current IOL Condition Min. VO = VDD or VSS Note Max. Unit ±10 µA −250 mA 3.3 V low-level output current VOL = 0.4 V 9.0 mA 3.3 V low-level output current VOL = 0.4 V 3.0 mA 5.0 V low-level output current VOL = 0.4 V 12.0 mA 5.0 V low-level output current VOL = 0.4 V 6.0 mA 3.3 V high-level output current VOH = 2.4 V −9.0 mA 3.3 V high-level output current VOH = 2.4 V −3.0 mA 5.0 V high-level output current VOH = 2.4 V −2.0 mA 5.0 V high-level output current VOH = 2.4 V −2.0 mA High-level output current Input leakage current IOH II 3.3 V buffer VI = VDD or VSS ±10 µA 3.3 V buffer with 50 kΩ PD VI = VDD 191 µA 5.0 V buffer VI = VDD or VSS ±10 µA Min. Max. Unit Note The output short circuit time is one second or less and is only for one pin on the LSI. PCI interface block Parameter Symbol Condition High-level input voltage VIH 2.0 5.25 V Low-level input voltage VIL 0 0.8 V Low-level output current IOL VOL = 0.4 V 12.0 mA High-level output current IOH VOH = 2.4 V −2.0 mA Input high leakage current IIH VIN = 2.7 V 70 µA Input low leakage current IIL VIN = 0.5 V −70 µA PME0 leakage current IOFF VO < 3.6 V 1 µA VCC off or floating 16 Data Sheet S16265EJ5V0DS µPD720101 USB interface block Parameter Serial resistor between DP (DM) and Symbol Conditions RS Min. Max. Unit 35.64 36.36 Ω 40.5 49.5 Ω RSDP (RSDM) Output pin impedance ZHSDRV Includes RS resistor Input Levels for Low-/full-speed: High-level input voltage (drive) VIH 2.0 V High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI (D+) − (D−) 0.2 Differential common mode range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to GND 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V SE1 VOSE1 0.8 Output signal crossover point voltage VCRS 1.3 2.0 V VHSSQ 100 150 mV VHSDSC 525 625 mV VHSCM −50 +500 mV 3.6 V 0.8 V V Output Levels for Low-/full-speed: V Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling See Figure 3-4. level Output Levels for High-speed: High-speed idle state VHSOI −10 +10 mV High-speed data signaling high VHSOH 360 440 mV High-speed data signaling low VHSOL −10 +10 mV Chirp J level (differential signal) VCHIRPJ 700 1100 mV Chirp K level (differential signal) VCHIRPK −900 −500 mV Data Sheet S16265EJ5V0DS 17 µPD720101 Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range −1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Input Voltage Range (V) Figure 3-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver VDD−3.3 VDD−2.8 VDD−2.3 VDD−1.8 VDD−1.3 VDD−0.8 VDD−0.3 VDD 0 IOUT (mA) −20 −40 Min. −60 Max. −80 VOUT (V) Figure 3-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver 80 Max. IOUT (mA) 60 Min. 40 20 0 0 0.5 1 1.5 2 VOUT (V) 18 Data Sheet S16265EJ5V0DS 2.5 3 4.6 µPD720101 Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 0V Differential Point 2 Point 6 Point 5 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-5. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 50 Ω Coax 15.8 Ω 143 Ω 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Pin capacitance Parameter Symbol Condition Min. Max. Unit Input capacitance CI VDD = 0 V, TA = 25°C 6 8 pF Output capacitance CO fC = 1 MHz 10 12 pF I/O capacitance CIO Unmeasured pins returned to 0 V 10 12 pF PCI input pin capacitance Cin 8 pF PCI clock input pin capacitance Cclk 8 pF 8 pF PCI IDSEL input pin capacitance CIDSEL Data Sheet S16265EJ5V0DS 6 19 µPD720101 Power consumption Parameter Symbol Condition Typ. Typ. Unit (30 MHz X’tal) (48 MHz OSC) Power Consumption PWD0-0 Device state = D0, All the ports does not connect to 31.4 10.4 mA any function, and each OHCI controller is under Note1 UsbSuspend and EHCI controller is stopped. PWD0-2 The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 2. PWD0-3 Full- or low-speed device(s) is (are) on the port. 53.1 31.9 mA High-speed device(s) is (are) on the port. 204.6 204.2 mA The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 3. PWD0-4 Full- or low-speed device(s) is (are) on the port. 55.3 34.2 mA High-speed device(s) is (are) on the port. 253.8 255.5 mA The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 4. PWD0-5 Full- or low-speed device(s) is (are) on the port. 57.4 36.7 mA High-speed device(s) is (are) on the port. 301.6 300.1 mA The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 5. PWD0_C Full- or low-speed device(s) is (are) on the port. 59.8 38.8 mA High-speed device(s) is (are) on the port. 349.1 345.2 mA 30.5 10.4 mA The power consumption under suspend state during PCI clock is stopped by CRUN0. Device state = D0. Device state = D1, Analog PLL output is stopped. Note 3 7.7 10.4 mA PWD2 Device state = D2, Analog PLL output is stopped. Note 3 7.7 10.4 mA PWD3H Device state = D3hot, VCCRST0 = High, Analog PLL 7.7 10.4 mA 0.03 3.81 mA PWD1 output is stopped. PWD3C Note 3 Device state = D3cold, VCCRST0 = Low. Note 4 Notes 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend on the number of active ports. 2. The number of active ports is set by the value of Port No Field in PCI configuration space EXT register. 3. This is the case when PCI bus state is B0. 4. This is the case when PCI bus state is B3. Remark These are estimated value on Windows™ XP environment. 20 Data Sheet S16265EJ5V0DS µPD720101 System clock ratings Parameter Clock frequency Symbol fCLK Condition X’tal Min. Typ. Max. Unit −500 30 +500 MHz ppm Oscillator block −500 ppm 48 ppm Clock duty cycle tDUTY 40 +500 MHz ppm 50 60 % Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply voltage, temperature, and aging, etc. Data Sheet S16265EJ5V0DS 21 µPD720101 AC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°C) PCI interface block Parameter Symbol Condition Min. Max. Unit PCI clock cycle time tcyc 30 ns PCI clock pulse, high-level width thigh 11 ns PCI clock pulse, low-level width tlow 11 ns PCI clock, rise slew rate Scr 0.2VDD to 0.6VDD 1 4 V/ns PCI clock, fall slew rate Scf 0.2VDD to 0.6VDD 1 4 V/ns PCI reset active time (vs. power supply trst 1 ms 100 µs stability) PCI reset active time (vs. CLK start) trst-clk Output float delay time (vs. RST0↓) trst-off PCI reset rise slew rate Srr 50 PCI bus signal output time (vs. PCLK↑) tval 2 11 ns PCI point-to-point signal output time (vs. tval (ptp) 2 12 ns 40 REQ0 ns mV/ns PCLK↑) Output delay time (vs. PCLK↑) ton 2 Output float delay time (vs. PCLK↑) toff Input setup time (vs. PCLK↑) tsu Point-to-point input setup time (vs. tsu (ptp) ns 28 GNT0 ns 7 ns 10 ns 0 ns PCLK↑) Input hold time 22 th Data Sheet S16265EJ5V0DS µPD720101 USB interface block (1/2) Parameter Symbol Conditions Min. Max. Unit 75 300 ns 75 300 ns 80 125 % 1.49925 1.50075 Mbps tDDJ1 tDDJ2 −25 −14 +25 +14 ns ns tLDEOP −40 +100 ns To next transition For paired transitions tUJR1 tUJR2 −152 −200 +152 +200 ns ns Source SE0 interval of EOP tLEOPT 1.25 1.50 µs Receiver SE0 interval of EOP tLEOPR 670 Width of SE0 interval during differential tFST Low-speed Source Electrical Characteristics Rise time (10 to 90%) tLR CL = 200 to 600 pF, RS = 36 Ω Fall time (90 to 10%) tLF CL = 200 to 600 pF, RS = 36 Ω Differential rise and fall time matching tLRFM (tLR/tLF) Low-speed data rate tLDRATHS Average bit rate Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to SE0 transition Receiver jitter: ns 210 ns 4 20 ns 4 20 ns 90 111.11 % 11.9940 12.0060 Mbps 0.9995 1.0005 ms 42 ns −3.5 −4.0 +3.5 +4.0 ns ns −2 +5 ns −18.5 −9 +18.5 +9 ns ns 175 ns transition Full-speed Source Electrical Characteristics Rise time (10 to 90%) tFR CL = 50 pF, RS = 36 Ω Fall time (90 to 10%) tFF CL = 50 pF, RS = 36 Ω Differential rise and fall time matching tFRFM (tFR/tFF) Full-speed data rate tFDRATHS Average bit rate Frame interval tFRAME Consecutive frame interval jitter tRFI No clock adjustment Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to tDJ1 tDJ2 tFDEOP SE0 transition Receiver jitter: To next transition For paired transitions tJR1 tJR2 Source SE0 interval of EOP tFEOPT 160 Receiver SE0 interval of EOP tFEOPR 82 Width of SE0 interval during differential tFST ns 14 ns transition Data Sheet S16265EJ5V0DS 23 µPD720101 (2/2) Parameter Symbol Conditions Min. Max. Unit High-speed Source Electrical Characteristics Rise time (10 to 90%) tHSR 500 ps Fall time (90 to 10%) tHSF 500 ps Driver waveform See Figure 3-6. High-speed data rate tHSDRAT 479.760 480.240 Mbps Microframe interval tHSFRAM 124.9375 125.0625 µs Consecutive microframe interval difference tHSRFI Data source jitter See Figure 3-6. Receiver jitter tolerance See Figure 3-4. 4 high- Bit speed times Hub Event Timings Time to detect a downstream facing port tDCNN 2.5 2000 µs tDDIS 2.0 2.5 µs connect event Time to detect a disconnect event at a hub’s downstream facing port Duration of driving resume to a tDRSMDN Nominal 20 ms downstream port Time from detecting downstream resume tURSM 1.0 ms to rebroadcast Inter-packet delay for packets traveling in tHSIPDSD 88 Bit same direction for high-speed Inter-packet delay for packets traveling in times tHSIPDOD 8 Bit opposite direction for high-speed Inter-packet delay for root hub response for times tHSRSPIPD1 192 high-speed Time for which a Chirp J or Chirp K must Bit times tFILT µs 2.5 be continuously detected during reset handshake Time after end of device Chirp K by which tWTDCH 100 µs hub must start driving first Chirp K Time for which each individual Chirp J or tDCHBIT 40 60 µs tDCHSE0 100 500 µs Chirp K in the chirp sequence is driven downstream during reset Time before end of reset by which a hub must end its downstream chirp sequence 24 Data Sheet S16265EJ5V0DS µPD720101 Figure 3-6. Transmit Waveform for Transceiver at DP/DM +400 mV Differential Level 1 Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-7. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 15.8 Ω 143 Ω 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Data Sheet S16265EJ5V0DS 25 µPD720101 3.4 Timing Diagram PCI clock tcyc thigh tlow 0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD 0.4VDD (ptp:min) PCI reset PCLK 100 ms (typ.) PWR_GOOD trst-clk trst VBBRST0 trst-off PCI Signals 26 Valid Data Sheet S16265EJ5V0DS µPD720101 PCI output timing measurement condition 0.6VDD PCLK 0.4VDD 0.2VDD tval , tval (ptp) 0.615VDD (for falling edge) Output delay 0.285VDD (for falling edge) Output ton toff PCI input timing measurement condition 0.6VDD 0.4VDD PCLK 0.2VDD tsu , tsu (ptp) th 0.6VDD Input 0.4VDD 0.2VDD Data Sheet S16265EJ5V0DS 27 µPD720101 USB differential data jitter for full-speed tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N × tPERIOD + txDJ1 Paired Transitions N × tPERIOD + txDJ2 USB differential-to-EOP transition skew and EOP width for low-/full-speed tPERIOD Differential Data Lines Crossover Point Extended Crossover Point Diff. Data-toSE0 Skew N × tPERIOD + txDEOP Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR USB receiver jitter tolerance for low-/full-speed tPERIOD Differential Data Lines txJR txJR1 Consecutive Transitions N × tPERIOD + txJR1 Paired Transitions N × tPERIOD + txJR2 28 Data Sheet S16265EJ5V0DS txJR2 µPD720101 Low-/full-speed disconnect detection D+/D− VIZH (min) VIL D−/D+ VSS tDDIS Device Disconnected Disconnect Detected Full-/high-speed device connect detection D+ VIH D− VSS tDCNN Device Connected Connect Detected Low-speed device connect detection D− VIH D+ VSS tDCNN Device Connected Connect Detected Data Sheet S16265EJ5V0DS 29 µPD720101 4. PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 22.0±0.2 B C 20.0±0.2 20.0±0.2 D 22.0±0.2 F 1.25 G 1.25 H 0.22±0.05 I 0.08 J 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.03 −0.07 N P 0.08 1.4 Q 0.10±0.05 R 3° +4° −3° S 1.5±0.1 S144GJ-50-UEN 30 Data Sheet S16265EJ5V0DS µPD720101 144-PIN PLASTIC FBGA (12x12) ZD E B ZE w S B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A D INDEX MARK P NM L K J HG F E D C B A w S A A y1 A2 S S y S e φb φx M A1 S AB ITEM D MILLIMETERS 12.00±0.10 E 12.00±0.10 w 0.20 A 1.48±0.10 A1 0.35±0.06 A2 1.13 e 0.80 b 0.50 +0.05 –0.10 x 0.08 y 0.10 y1 0.20 ZD 0.80 ZE Data Sheet S16265EJ5V0DS 0.80 P144F1-80-EA8 31 µPD720101 5. RECOMMENDED SOLDERING CONDITIONS The µPD720101 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) µPD720101GJ-UEN: 144-pin plastic LQFP (Fine pitch) (20 × 20) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-103-3 Count: Three times or less Note Exposure limit: 3 days Partial heating (after that, prebake at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. µPD720101GJ-UEN-A: 144-pin plastic LQFP (Fine pitch) (20 × 20) Lead-free product Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher), Symbol IR60-103-2 Count: Two times or less Note Exposure limit: 3 days Partial heating (after that, prebake at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. µPD720101F1-EA8: 144-pin plastic FBGA (12 × 12) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-107-3 Count: Three times or less Note Exposure limit: 7 days (after that, prebake at 125°C for 10 hours) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. µPD720101F1-EA8-A: 144-pin plastic FBGA (12 × 12) Lead-free product Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher), Symbol IR60-103-2 Count: Two times or less Exposure limit: 3 days Note (after that, prebake at 125°C for 10 hours) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. 32 Data Sheet S16265EJ5V0DS µPD720101 [MEMO] Data Sheet S16265EJ5V0DS 33 µPD720101 [MEMO] 34 Data Sheet S16265EJ5V0DS µPD720101 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S16265EJ5V0DS 35 µPD720101 USB logo is a trademark of USB Implementers Forum, Inc. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. • The information in this document is current as of Macrh, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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