DATA SHEET MOS INTEGRATED CIRCUIT µPD720130 USB2.0 to IDE Bridge The µPD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI. The µPD720130 complies with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The µPD720130 is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine (SIE), and USB2.0 transceiver into a single chip. The USB2.0 protocol and class specific protocol (bulk only protocol) are handled by USB2.0 transceiver, SIE, and EPC. And the transport layer is performed by V30MZ CISC processor which is in the µPD720130. The software to control the µPD720130 is located in an embedded ROM. In the future, the µPD720130 will be released to support external Flash Memory / EEPROM™ option to update function by firmware. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. µPD720130 User’s Manual: S16412E FEATURES • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps) • Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4) • USB2.0 high-speed bus powered device capability • Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125) • One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver • USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine) • Automatic chirp assertion and full-/high-speed mode change • USB Reset, Suspend and Resume signaling detection • Supports power control functionality for IDE device as CD-ROM and HDD • Supports set feature (TEST_MODE) functionality • System Clock is generated by 30 MHz X’tal • 2.5 V and 3.3 V power supply ORDERING INFORMATION Part Number Package µPD720130GC-9EU 100-pin plastic TQFP (fine pitch) (14 × 14) µPD720130GC-9EU-SIN 100-pin plastic TQFP (fine pitch) (14 × 14) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S16302EJ3V0DS00 (3rd edition) Date Published June 2003 NS CP (K) Printed in Japan The mark shows major revised points. 2002 µPD720130 BLOCK DIAGRAM CPU Core (V30MZ) EPC2_V2 RAM 4 Kbytes×2 PHY_V2 USB Bus ROM 8 Kbytes DCC 16-bit Bus 16-bit Bus Bus Bridge DMAC IDEC_V2 IDE Bus GPIO Timer 8-bit Bus INTC GPIO or FSIO FSIO PIO Direct Bus Direct Command Bus Ext. Bus (Data 8-bit Bus) or PIO V30MZ : CISC CPU core RAM : 8-Kbyte work RAM for firmware ROM : 8-Kbyte ROM for built-in firmware PHY_V2 : USB2.0 transceiver with serial interface engine EPC_V2 : Endpoint controller IDEC_V2 : IDE controller DCC : ATA direct command controller Bus Bridge : Internal / external bus controller and DMA controller INTC : Interrupt controller (82C59 like) GPIO : General purpose 8-bit I/O controller PIO : Multipurpose 14-bit I/O controller FSIO : Flexible serial I/O 2 Data Sheet S16302EJ3V0DS Serial ROM µPD720130 PIN CONFIGURATION (TOP VIEW) • 100-pin plastic TQFP (fine pitch) (14 × 14) µPD720130GC-9EU 80 85 90 95 1 5 75 70 10 65 15 60 20 50 45 40 35 25 30 55 VDD25 VDD33 CMB_STATE PIO5 CMB_BSY PWR CLC SPD VSS DV0 DV1 DCC PIO14 PIO15 GPIO0 VSS GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VDD33 VDD25 VSS IDEIOWB IDEDRQ IDED15 IDED0 VDD33 IDED14 IDED1 IDED13 IDED2 VDD25 VSS IDED12 IDED3 IDED11 IDED4 IDED10 VDD33 IDED5 IDED9 IDED6 IDED8 IDED7 IDERSTB VSS VDD25 VDD33 XIN XOUT VSS RESETB VDD33 IRQ0 MD0 MD1 IDECS1B IDECS0B IDEA2 IDEA0 IDEA1 VSS IDEINT IDEDAKB IDEIORDY IDEIORB TEST0 TEST1 TEST3 VDD33 VDD25 100 VSS SMC VBUS VDD25 AVSS AVDD25 AVSS(R) RREF AVSS AVDD25 VSS RSDM DM VDD33 DP RSDP VSS VDD25 RPU VDD25 TEST2 SCL SDA DPC VSS µPD720130GC-9EU-SIN Data Sheet S16302EJ3V0DS 3 µPD720130 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VDD25 26 VSS 51 VDD25 76 VSS 2 VDD33 27 IDEIOWB 52 VDD33 77 DPC 3 XIN 28 IDEDRQ 53 GPIO7 78 SDA 4 XOUT 29 IDED15 54 GPIO6 79 SCL 5 VSS 30 IDED0 55 GPIO5 80 TEST2 6 RESETB 31 VDD33 56 GPIO4 81 VDD25 7 VDD33 32 IDED14 57 GPIO3 82 RPU 8 IRQ0 33 IDED1 58 GPIO2 83 VDD25 9 MD0 34 IDED13 59 GPIO1 84 VSS 10 MD1 35 IDED2 60 VSS 85 RSDP 11 IDECS1B 36 VDD25 61 GPIO0 86 DP 12 IDECS0B 37 VSS 62 PIO15 87 VDD33 13 IDEA2 38 IDED12 63 PIO14 88 DM 14 IDEA0 39 IDED3 64 DCC 89 RSDM 15 IDEA1 40 IDED11 65 DV1 90 VSS 16 VSS 41 IDED4 66 DV0 91 AVDD25 17 IDEINT 42 IDED10 67 VSS 92 AVSS 18 IDEDAKB 43 VDD33 68 SPD 93 RREF 19 IDEIORDY 44 IDED5 69 CLC 94 AVSS(R) 20 IDEIORB 45 IDED9 70 PWR 95 AVDD25 21 TEST0 46 IDED6 71 CMB_BSY 96 AVSS 22 TEST1 47 IDED8 72 PIO5 97 VDD25 23 TEST3 48 IDED7 73 CMB_STATE 98 VBUS 24 VDD33 49 IDERSTB 74 VDD33 99 SMC 25 VDD25 50 VSS 75 VDD25 100 VSS Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 kΩ. 4 Data Sheet S16302EJ3V0DS µPD720130 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Level Function XIN I 2.5 V Input System clock input or oscillator In XOUT O 2.5 V Output Oscillator out RESETB I 3.3 V Schmitt Input MD(1:0) I 3.3 V Input Low Asynchronous reset signaling Function mode setting IDECS(1:0)B O (I/O) 5 V tolerant Output IDEA(2:0) O (I/O) 5 V tolerant Output IDEINT I (I/O) 5 V tolerant Input High IDE interrupt request from device to host IDEDAKB O (I/O) 5 V tolerant Output Low IDE DMA acknowledge IDEIORDY I (I/O) 5 V tolerant Input High IDE IO channel ready IDEIORB O (I/O) 5 V tolerant Output Low IDE IO read strobe IDEIOWB O (I/O) 5 V tolerant Output Low IDE IO write strobe IDEDRQ I (I/O) 5 V tolerant Input High IDE DMA request from device to host IDED(15:0) I/O Low IDE host chip select IDE address bus 5 V tolerant I/O IDE data bus IDERSTB O (I/O) 5 V tolerant Output DCC I (I/O) 3.3 V Input IDE controller operational mode setting DV(1:0) I (I/O) 3.3 V Input Device select CLC I (I/O) 3.3 V Input System clock setting PWR I (I/O) 3.3 V Input Bus powered /self-powered select CMB_BSY O (I/O) 3.3 V Output Combo IDE bus busy CMB_STATE I (I/O) 3.3 V Input Combo IDE bus state DPC O (I/O) 3.3 V Output Power control signaling for IDE device SDA I/O 3.3 V I/O Serial ROM data signaling SCL I/O 3.3 V I/O VBUS I 5 V Schmitt Input Low IDE reset from host to device Serial ROM clock signaling Note VBUS monitoring DP I/O USB high speed D+ I/O USB’s high speed D+ signal DM I/O USB high speed D− I/O USB’s high speed D− signal RSDP O USB full speed D+ Output USB’s full speed D+ signal RSDM O USB full speed D− Output USB’s full speed D− signal RPU A USB Pull-up control USB’s 1.5 kΩ pull-up resistor control RREF A Analog Reference resistor SPD I (I/O) 3.3 V Input NEC private SMC I 3.3 V Input Scan mode control TEST(3:0) I 3.3 V Input Test mode setting Note VBUS pin may be used to monitor for VBUS line even if VDD33, VDD25, and AVDD25 are shut off. System must ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is not exceeded. Data Sheet S16302EJ3V0DS 5 µPD720130 (2/2) Pin Name I/O Buffer Type Active Level Function GPIO(7:0) I/O 3.3 V Schmitt I/O General purpose IO port (for future extension) PIO(15:14) I/O 3.3 V I/O IO port (for future extension) PIO(5) I/O 3.3 V Schmitt I/O IO port (for future extension) IRQ0 I 3.3 V Schmitt Input High External interrupt input (for future extension) AVDD25 2.5 V VDD for Analog circuit VDD25 2.5 V VDD VDD33 3.3 V VDD AVSS VSS for Analog circuit VSS VSS Remarks 1. “5 V tolerant“ means that the buffer is 3.3 V buffer with 5 V tolerant circuit. 2. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use. 6 Data Sheet S16302EJ3V0DS µPD720130 2. FUNCTION INFORMATION USB to IDE system can be realized by the µPD720130, Serial ROM which has USB vender ID, product ID, etc, and power control circuit. The µPD720130 can be selected bus powered mode or self powered mode. If all power consumption for USB to IDE system is less than the specification of bus powered device, it will be possible to realize high-speed capable bus powered system. The µPD720130 has some features for bus powered system. Also, some system may control target IDE device by two IDE controllers. At the time, IDE bus arbitration should be required to each IDE controller. The µPD720130 has a feature of IDE bus arbitration, too. The setting of IDE controller in the µPD720130 is controlled by data in serial ROM or external pin setting. If there is any inconsistency between data in serial ROM and external pin setting, the data in serial ROM is higher priority than external pin setting. 2.1 Data in Serial ROM The µPD720130 loads some data such as Vendor ID, Product ID and some additional USB related information, etc from serial ROM when the µPD720130 is initialized. Example of data in serial ROM is as follows. ExPinReset and ExPinSet fields hold data which is related to the external pin setting. Table 2-1. Data in Serial ROM Data size Symbol Description 1 Word Flags Control for descriptor overwrite 1 Byte ExPinReset PWR, CLC, DCC, DV[1:0] Reset bit map field 1 Byte ExPinSet PWR, CLC, DCC, DV[1:0] Set bit map field 1 Word idVendor idVendor field in Device descriptor 1 Word idProduct idProduct field in Device descriptor 1 Word bcdDevice bcdDevice field in Device descriptor 1 Byte MaxPower BUS MaxPower field in Configuration descriptor for Bus powered mode 1 Byte MaxPower Self MaxPower field in Configuration descriptor for Self powered mode 1 Byte bInterfaceClass bInterfaceClass field in Interface descriptor 1 Byte bInterfaceSubClass bInterfaceSubClass field in Interface descriptor 1 Byte bInterfaceProtocol bInterfaceProtocol field in Interface descriptor 1 Word TxMode Reset IDE transmission type such as Ultra DMA 66 Reset bit map field 1 Word TxMode Set IDE transmission type such as Ultra DMA 66 Set bit map field 32 Bytes ManufactureString String descriptor for Manufacturer 32 Bytes ProductString String descriptor for Product 32 Bytes SerialString String descriptor for Device serial number Data Sheet S16302EJ3V0DS 7 µPD720130 2.2 External Pin Setting Usually, serial ROM should be used to keep Vendor ID, Product ID and some additional USB related information. And then, the external pin setting of the µPD720130 is not so important to realize USB to IDE bridge system. The recommended external pin setting is as follows. Table 2-2. Recommended External Pin Setting Pin Name Setting MD1 1 MD0 0 SCL Pull Up Note 1 SDA Pull Up DV1 “L” clamp DV0 “L” clamp CLC “L” clamp PWR “L” clamp DCC Pull Down Note 2 GPIO(7:0) “L” clamp PIO(14:15) “L” clamp PIO5 “L” clamp SPD “H” clamp TEST(3:0) “L” clamp SMC “L” clamp IRQ0 “L” clamp Notes 1. If serial ROM size is more than 2 Kbytes, SCL should be pull down. 2. If target IDE device is not fixed, it is preferable that DCC pin can switch pull-up or pull-down. The setting for any other pins such as CMB_BSY, CMB_STATE depends on USB2.0 to IDE Bridge system. For example, if two IDE controllers control one target IDE device and one of two IDE controllers is the µPD720130, CMB_BSY and CMB_STATE are used to handshake between two IDE controller chips. On the other hand, when the µPD720130 is only controller of target IDE device, CMB_BSY should be opened and CMB_STATE should be clamped to “L”. 8 Data Sheet S16302EJ3V0DS µPD720130 2.3 Control Bit in Serial ROM or External Pin Setting The following tables show IDE status and control bit in serial ROM or external pin setting. Table 2-3. DV1/DV0, CLC, PWR Setting No. Device Power Internal Clock ATA/ATAPI Setting in Serial ROM or External Pin PWR CLC DV1 DV0 No device connected 1 1 1 1 1 ATA 1 1 1 0 2 ATAPI 1 1 0 1 3 Reserved 1 1 0 0 No device connected 1 0 1 1 5 ATA 1 0 1 0 6 ATAPI 1 0 0 1 7 Reserved 1 0 0 0 No device connected 0 1 1 1 9 Combo (ATA) 0 1 1 0 10 Combo (ATAPI) 0 1 0 1 11 Reserved 0 1 0 0 12 No device connected 0 0 1 1 13 ATA 0 0 1 0 14 ATAPI 0 0 0 1 15 Auto device detect 0 0 0 0 0 Bus Powered 4 8 7.5 MHz 60 MHz Self Powered Remark 60 MHz Setting No. 0, 3, 4, 7, 8, 11, and 12 are prohibited to use. Data Sheet S16302EJ3V0DS 9 µPD720130 Table 2-4. DV1/DV0, DCC Setting Condition DV1 DV0 1 0 0 0 1 0 Mode ATA ATAPI Auto device detect Target Device ATA ATAPI ATA ATAPI Remark 10 DCC Pin Setting Description DCC Setting in Serial ROM 0 No setting Ultra, Multi Word DMA are disabled 0 Reset Ultra, Multi Word DMA are disabled 0 Set Ultra, Multi Word DMA are enabled. 1 No setting Ultra, Multi Word DMA are enabled. 1 Reset Ultra, Multi Word DMA are disabled 1 Set Ultra, Multi Word DMA are enabled. 0 No setting Ultra DMA is disabled 0 Reset Ultra DMA is disabled 0 Set Ultra, Multi Word DMA are enabled. 1 No setting Ultra, Multi Word DMA are enabled. 1 Reset Ultra DMA is disabled 1 Set Ultra, Multi Word DMA are enabled. 0 No setting Ultra, Multi Word DMA are disabled 0 Reset Ultra, Multi Word DMA are disabled 0 Set Ultra, Multi Word DMA are enabled. 1 No setting Ultra, Multi Word DMA are enabled. 1 Reset Ultra, Multi Word DMA are disabled 1 Set Ultra, Multi Word DMA are enabled. 0 No setting Ultra DMA is disabled 0 Reset Ultra DMA is disabled 0 Set Ultra, Multi Word DMA are enabled. 1 No setting Ultra, Multi Word DMA are enabled. 1 Reset Ultra DMA is disabled 1 Set Ultra, Multi Word DMA are enabled. PIO mode 0-4 are always enabled. Data Sheet S16302EJ3V0DS µPD720130 2.4 Combo Mode Function The µPD720130 can be used to realize that two IDE controller chips control one target IDE device in one system. To realize IDE bus arbitration between two IDE controller chips, the µPD720130 has CMB_BSY and CMB_STATE. Combo mode is enabled when PWR = 0 and CLC = 1. CMB_BSY and CMB_STATE connect to other IDE controller chip as follows. Figure 2-1. CMB_BSY and CMB_STATE Connection between Two IDE Controller Chips µ PD720130 Other IDE controller IDE Bus Grant CMB_STATE IDE Bus Request CMB_BSY Table 2-5. Description of CMB_BSY and CMB_STATE Pin Name CMB_STATE CMB_BSY Direction IN OUT Value Description 0 Other IDE controller does not require or does not use IDE bus. 1 Other IDE controller requires or is using IDE bus. 0 The µPD720130 does not require or does not use IDE bus. 1 The µPD720130 requires or is using IDE bus. Data Sheet S16302EJ3V0DS 11 µPD720130 The IDE bus arbitration will be done by following sequence. The µPD720130 will confirm whether other IDE controller requires or is using IDE bus or not. If other IDE controller does not require or does not use IDE bus, the µPD720130 will use IDE bus. Figure 2-2. IDE Bus Arbitration Sequence START Chip Init Other IDE controller requires or is using IDE bus. CMB_STATE = 1? Yes. No. CMB_BSY = 1 CMB_STATE = 0? Yes. No. The µPD720130 can not use IDE bus CMB_BSY = 0 IDE bus is used by the µ PD720130 END 12 Data Sheet S16302EJ3V0DS µPD720130 2.5 Power Control To realize bus-powered or high performance self-powered USB2.0 to IDE Bridge system, the µPD720130 has two internal system clock mode. One is 7.5 MHz for bus-powered mode and the other is 60 MHz for self-powered mode. The µPD720130 controls the power state by events as follows. The word with under line shows event. The Italic word shows the power state. Figure 2-3. Power State Control (a) Bus-powered Mode Power OFF Vbus OFF Power OFF Vbus ON Connect Hardware Reset Idle Mode Power = PRESET Bus Reset Default State FS CONNECT FS Enumeration State Power = PENUM_FS Set Configuration HS CONNECT HS Enumeration State Resume Suspend Set Configuration Suspend Configured State Suspend Mode Resume Configured State Power = PSPND Suspend Resume Power = PENUM_HS Suspend Suspend Suspend Mode Resume Power = PSPND Suspend Resume Resume FS Operation State HS Operation State Power = PFS_B Power = PHS_B (b) Self-powered Mode Power OFF Power OFF Power ON Hardware Reset Idle Mode Power = PRESET CMB_STATE = 0 CMB_STATE = 1 Vbus ON Connect Bus Reset IDE Bus Release State Vbus OFF Disconnect Mode Default State FS CONNECT HS CONNECT Power = PCOMBO FS Enumeration State Power = PENUM_FS Set Configuration Suspend Suspend Configured State HS Enumeration State Resume Resume Suspend Power = PENUM_HS Set Configuration Suspend Mode Suspend Configured State Power = PSPND Power = PFS_S Suspend Mode Resume Suspend Power = PSPND Resume Resume FS Operation State Resume Suspend HS Operation State Power = PHS_S Data Sheet S16302EJ3V0DS 13 µPD720130 To realize bus-powered USB2.0 to IDE Bridge system, the power consumption for IDE device should be controlled by the power state of the µPD720130. The µPD720130 has DPC pin to control IDE device’s power circuit. DPC pin’s output level relates to USB device states. DPC should be pull up to 3.3 V because DPC output becomes high impedance state until the µPD720130 is initialized. Figure 2-4. DPC Pin to Control IDE Device’s Power Circuit High impedance state Default Un-configured Configured Suspend Configured Normal Operation Normal Operation DPC Power ON Hardware Reset Set Configuration Bus Reset Suspend Occured Resume Occured Following reference circuit can cut off power supply to IDE device during the µPD720130 is under default and un-configured state. Also, the power supply to IDE device is disabled during suspend state, too. Power consumption of total system under default, un-configured, and suspend state can be reduced by DPC pin. Figure 2-5. Power Control Circuit Example Power supply rail IDE Device µ PD720130 3.3 V Pull Up DPC 14 IN OUT P-Channel Switch ON Data Sheet S16302EJ3V0DS Regulator Power µPD720130 3. ELECTRICAL SPECIFICATIONS 3.1 Buffer List • 2.5 V oscillator interface • XIN, XOUT 3.3 V input buffer • MD(1:0), TEST(3:0), SMC 3.3 V schmitt input buffer • RESETB, IRQ0 3.3 V input buffer with enable (OR type) • DCC, DV(1:0), SPD, CLC, PWR, CMB_STATE 3.3 V IOL = 6 mA 3-state output buffer • CMB_BSY, DPC 3.3 V IOL = 3 mA bi-directional schmitt buffer with input enable (OR-type) • GPIO(7:0), PIO5, SDA, SCL 3.3 V IOL = 6 mA bi-directional buffer with input enable (OR-type) • PIO(15:14) 5 V schmitt input buffer • VBUS 5 V IOL = 6 mA 3-state output buffer • IDECS(1:0)B, IDEA(2:0), IDEDAKB, IDEIORB, IDEIOWB, IDERSTB 5 V IOL = 6 mA bi-directional buffer with input enable (OR-type) • IDED(15:0), IDEINT, IDEIORDY, IDEDRQ USB interface DP, DM, RSDP, RSDM, RREF, RPU Remark Above, “5 V” refers to a 3.3 V buffer with 5-V tolerant circuit. Therefore, it is possible to have a 5-V connection for an external bus, but the output level will be only up to 3.3 V, which is the VDD33 voltage. Data Sheet S16302EJ3V0DS 15 µPD720130 3.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Meaning Power supply voltage VDD33, VDD25 Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance value for DC current to prevent damage or reduced reliability when a current flows out of or into an output pin. Operating temperature TA Indicates the ambient temperature range for normal logic operations. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. Terms Used in Recommended Operating Range Parameter Symbol Meaning Power supply voltage VDD33, VDD25 Indicates the voltage range for normal logic operations occur when VSS = 0 V. High-level input voltage VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Hysteresys voltage VH Indicates the differential between the positive trigger voltage and the negative trigger voltage. Input rise time tri Indicates allowable input rise time to input pins. Input rise time is transition time from 0.1 × VDD to 0.9 × VDD. Input fall time tfi Indicates allowable input fall time to input pins. Input fall time is transition time from 0.9 × VDD to 0.1 × VDD. Terms Used in DC Characteristics Parameter Symbol Meaning Off-state output leakage current IOZ Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Output short circuit current IOS Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that flows from the output pins when the rated high-level output voltage is being applied. 16 Data Sheet S16302EJ3V0DS µPD720130 3.3 Electrical Specifications Absolute Maximum Ratings Parameter Rating Unit 3.3 V power supply rail −0.5 to +4.6 V VDD25 2.5 V power supply rail −0.5 to +3.6 V Input voltage, 5 V buffer VI 3.0 V ≤ VDD33 ≤ 3.6 V VI < VDD33 + 3.0 V −0.5 to +6.6 V Input voltage, 3.3 V buffer VI 3.0 V ≤ VDD33 ≤ 3.6 V VI < VDD33 + 1.0 V −0.5 to +4.6 V Input voltage, 2.5 V buffer VI 2.3 V ≤ VDD25 ≤ 2.7 V VI < VDD25 + 0.9 V −0.5 to +3.6 V Output voltage, 5 V buffer VO 3.0 V ≤ VDD33 ≤ 3.6 V VO < VDD33 + 3.0 V −0.5 to +6.6 V Output voltage, 3.3 V buffer VO 3.0 V ≤ VDD33 ≤ 3.6 V VO < VDD33 + 1.0 V −0.5 to +4.6 V Output voltage, 2.5 V buffer VO 2.3 V ≤ VDD25 ≤ 2.7 V VO < VDD25 + 0.9 V −0.5 to +3.6 V Output current, 5 V buffer IO IOL = 6 mA 20 mA Output current, 3.3 V buffer IO IOL = 6 mA 20 mA IOL = 3 mA 10 mA Power supply voltage Symbol VDD33 Condition Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Two Power Supply Rails Limitation The µPD720130 has two power supply rails (2.5 V, 3.3 V). The system will require the time when power supply rail is stable at VDD level. And, there will be difference between the time of VDD25 and VDD33. The µPD720130 requires that VDD25 should be stable before VDD33 becomes stable. At this case, the system must ensure that the absolute maximum ratings for VI / VO are not exceeded. System reset signaling should be asserted more than specified time after both VDD25 and VDD33 are stable. Data Sheet S16302EJ3V0DS 17 µPD720130 Recommended Operating Ranges Parameter Operating voltage High-level input voltage Symbol Condition Min. Typ. Max. Unit VDD33 3.3 V for VDD33 pins 3.0 3.3 3.6 V VDD25 2.5 V for VDD25 pins 2.3 2.5 2.7 V VDD25 2.5 V for AVDD25 pins 2.3 2.5 2.7 V VIH 5.0 V high-level input voltage 2.0 5.5 V 3.3 V high-level input voltage 2.0 VDD33 V 2.5 V high-level input voltage 1.7 VDD25 V 5.0 V low-level input voltage 0 0.8 V 3.3 V low-level input voltage 0 0.8 V 2.5 V low-level input voltage 0 0.7 V 5 V hysteresis voltage 0.3 1.5 V 3.3 V hysteresis voltage 0.2 1.0 V Normal buffer 0 200 ns Schmitt buffer 0 10 ms Normal buffer 0 200 ns Schmitt buffer 0 10 ms Low-level input voltage Hysteresis voltage Input rise time Input fall time 18 VIL VH tri tfi Data Sheet S16302EJ3V0DS µPD720130 DC Characteristics (VDD33 = 3.0 to 3.6 V, VDD25 = 2.3 to 2.7 V, TA = 0 to +70°°C) Control Pin Block Parameter Symbol Off-state output current IOZ Output short circuit current IOS Note Low-level output current IOL Condition Min. VO = VDD33, VDD25 or VSS Max. Unit ±10 µA −250 mA 5.0 V low-level output current VOL = 0.4 V 6.0 mA 3.3 V low-level output current VOL = 0.4 V 6.0 mA 3.3 V low-level output current VOL = 0.4 V 3.0 mA 5.0 V high-level output current VOH = 2.4 V −2.0 mA 3.3 V high-level output current VOH = 2.4 V −6.0 mA 3.3 V high-level output current VOH = 2.4 V −3.0 mA High-level output current Input leakage current IOH II 3.3 V buffer VI = VDD or VSS ±10 µA 5.0 V buffer VI = VDD or VSS ±10 µA Note The output short circuit time is one second or less and is only for one pin on the LSI. Data Sheet S16302EJ3V0DS 19 µPD720130 USB Interface Block Parameter Symbol Conditions Min. Max. Unit 38.61 39.39 Ω Serial Resistor between DP (DM) and RSDP (RSDM) RS Output pin impedance ZHSDRV Includes RS resistor 40.5 49.5 Ω Bus pull-up resistor on upstream facing port RPU 1.5 kΩ ±5% consists of 1.485 1.515 Ω Termination voltage for upstream facing port pull-up VTERM 3.0 3.6 V High-level input voltage (drive) VIH 2.0 High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI (D+) − (D−) 0.2 Differential common mode range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to VSS 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V SE1 VOSE1 0.8 Output signal crossover point voltage VCRS 1.3 2.0 V High-speed squelch detection threshold (differential signal) VHSSQ 100 150 mV High-speed disconnect detection threshold (differential signal) VHSDSC 525 625 mV High-speed data signaling common mode voltage range VHSCM −50 +500 mV High-speed differential input signaling level See Figure 3-4. resistance of transistor and pull-up resistor Input Levels for Full-speed: V 3.6 0.8 V V Output Levels for Full-speed: V Input Levels for High-speed: Output Levels for High-speed: High-speed idle state VHSOI −10.0 +10.0 mV High-speed data signaling high VHSOH 360 440 mV High-speed data signaling low VHSOL −10.0 +10.0 mV Chirp J level (differential signal) VCHIRPJ 700 1100 mV Chirp K level (differential signal) VCHIRPK −900 −500 mV 20 Data Sheet S16302EJ3V0DS µPD720130 Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6 Input Voltage Range (V) Figure 3-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver VDD−3.3 VDD−2.8 VDD−2.3 VDD−1.8 VDD−1.3 VDD−0.8 VDD−0.3 VDD 0 IOUT (mA) −20 −40 Min. −60 Max. −80 VOUT (V) Figure 3-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver 80 Max. 60 IOUT (mA) −1.0 Min. 40 20 0 0 0.5 1 1.5 2 2.5 3 VOUT (V) Data Sheet S16302EJ3V0DS 21 µPD720130 Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 0V Differential Point 2 Point 6 Point 5 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-5. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 50 Ω Coax 15.8 Ω 143 Ω 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Pin Capacitance Parameter Symbol Condition Min. Max. Unit Input capacitance CIN VDD = 0 V, TA = 25°C 4 6 pF Output capacitance COUT fC = 1 MHz 4 6 pF I/O capacitance CIO Unmeasured pins returned to 0 V 4 6 pF 22 Data Sheet S16302EJ3V0DS µPD720130 Power Consumption (1) The power consumption when device works as bus-powered mode Symbol PENUM-BUS Condition Max. VDD33 AVDD25 57 23 3 4 10 10 mA mA 110 113 22 13 10 10 mA mA 10 235 5 µA The power consumption when device works High-speed operating Full-speed operating PW_SPD-BUS VDD25 The power consumption under unconfigured stage High-speed operating Full-speed operating PW-BUS Unit The power consumption under suspend state (2) The power consumption when device works as self-powered mode Symbol PENUM-SELF Condition Max. VDD25 VDD33 AVDD25 85 60 5 5 10 10 mA mA 120 113 25 13 10 10 mA mA The power consumption under unconfigured stage High-speed operating Full-speed operating PW-SELF Unit The power consumption when device works High-speed operating Full-speed operating PW_SPD-SELF The power consumption under suspend state 50 5 5 mA PW_UNP The power consumption under unplug state 87 3 10 mA PW_COM The power consumption under combo mode 90 5 10 mA The device is releasing the IDE bus. Data Sheet S16302EJ3V0DS 23 µPD720130 AC Characteristics (VDD33 = 3.0 to 3.6 V, VDD25 = 2.3 to 2.7 V, TA = 0 to +70°°C) System Clock Ratings Parameter Symbol Clock frequency fCLK Condition X’tal Min. Typ. Max. Unit −500 30 +500 MHz ppm Oscillator block ppm −500 30 ppm Clock duty cycle tDUTY +500 MHz ppm 45 50 55 % Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or Oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply voltage, temperature, and aging, etc. System Reset signaling Parameter Symbol Reset active time Conditions Min. trst Max. Unit µs 2 USB Interface Block (1/2) Parameter Symbol Conditions Min. Max. Unit Full-speed Source Electrical Characteristics Rise time (10% - 90%) tFR CL = 50 pF, RS = 36 Ω 4 20 ns Fall time (90% - 10%) tFF CL = 50 pF, RS = 36 Ω 4 20 ns Differential rise and fall time matching tFRFM (tFR/tFF) 90 111.11 % Full-speed data rate for device which are high-speed capable tFDRATHS Average bit rate 11.9940 12.0060 Mbps Frame interval tFRAME 0.9995 1.0005 ms Consecutive frame interval jitter tRFI 42 ns Source jitter total (including frequency tolerance): To next transition For paired transitions tDJ1 tDJ2 −3.5 −4.0 +3.5 +4.0 ns ns −2 +5 ns −18.5 −9 +18.5 +9 ns ns 175 ns Source jitter for differential transition to SE0 transition No clock adjustment tFDEOP Receiver jitter: To next transition For paired transitions tJR1 tJR2 Source SE0 interval of EOP tFEOPT 160 Receiver SE0 interval of EOP tFEOPR 82 Width of SE0 interval during differential transition tFST 24 ns 14 Data Sheet S16302EJ3V0DS ns µPD720130 (2/2) Parameter Symbol Conditions Min. Max. Unit High-speed Source Electrical Characteristics Rise time (10% - 90%) tHSR 500 ps Fall time (90% - 10%) tHSF 500 ps Driver waveform See Figure 3-6. High-speed data rate tHSDRAT 479.760 480.240 Mbps Microframe interval tHSFRAM 124.9375 125.0625 µs Consecutive microframe interval difference tHSRFI 4 highspeed Bit times Data source jitter See Figure 3-6. Receiver jitter tolerance See Figure 3-4. Device Event Timings Time from internal power good to device pulling D+ beyond VIHZ (min.) (signaling attached) tSIGATT 100 ms Debounce interval provided by USB system software after attach tATTDB 100 ms Inter-packet delay for full-speed tIPD Inter-packet delay for device response w/detachable cable for full-speed tRSPIPD1 High-speed detection start time from suspend tSCA 2.5 Sample time for suspend vs reset tCSR 100 875 µs Time to detect bus suspend state tSPD 3.000 3.125 ms Power down under suspend tSUS 10 ms Reversion time from suspend to highspeed tRHS 1.333 µs Drive Chirp K width tCKO Finish Chirp K assertion tFCA 7 ms Start sequencing Chirp K-J-K-J-K-J tSSC 100 µs Finish sequencing Chirp K-J tFSC −500 −100 µs Detect sequencing Chirp K-J width tCSI 2.5 Sample time for sequencing Chirp tSCS 1 Reversion time to high-speed tRHA High-speed detection start time tHDS 2.5 Reset completed time tDRS 10 2 Bit times 6.5 µs 1 Data Sheet S16302EJ3V0DS Bit times ms µs 2.5 ms 500 µs 3000 µs ms 25 µPD720130 IDE Interface Block PIO mode Parameter Symbol Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Unit Cycle time (min.) t0 600 383 240 180 120 ns Address setup time (min.) t1 70 50 30 30 25 ns 16 bits DIOR/DIOW pulse width (min.) t2 165 125 100 80 70 ns 290 290 290 80 70 ns 8 bits DIOR/DIOW pulse width (min.) DIOR/DIOW recovery time (min.) t2i − − − 70 25 ns DIOW data setup time (min.) t3 60 45 30 30 20 ns DIOW data hold time (min.) t4 30 20 15 10 10 ns DIOR data setup time (min.) t5 50 35 20 20 20 ns DIOR data hold time (min.) t6 5 5 5 5 5 ns DIOR 3-state delay time (max.) t6Z 30 30 30 30 30 ns t9 20 15 10 10 10 ns tRD 0 0 0 0 0 ns tA 35 35 35 35 35 ns tB 1250 1250 1250 1250 1250 ns tC 5 5 5 5 5 ns Address hold time (min.) IORDY read data valid time (min.) IORDY setup time (min.) Note Note IORDY pulse width (max.) Note IORDY Inactive to Hi-Z time (max.) Note Note IORDY is an option in mode 0 - 2. IORDY is essential in modes 3 and 4. Multi Word DMA mode Parameter Symbol Mode 0 Mode 1 Mode 2 Unit Cycle time (min.) t0 480 150 120 ns DIOR/DIOW pulse width (min.) tD 215 80 70 ns DIOR data access time (max.) tE 150 60 50 ns DIOR data hold time (min.) tF 5 5 5 ns DIOR data setup time (min.) tGr 100 30 20 ns DIOW data setup time (min.) tGw 100 30 20 ns DIOW data hold time (min.) tH 20 15 10 ns DMACK setup time (min.) tI 0 0 0 ns DMACK hold time (min.) tJ 20 5 5 ns DIOR negate pulse width (min.) tKr 50 50 25 ns DIOW negate pulse width (min.) tKw 215 50 25 ns DIOR-DMARQ delay time (max.) tLr 120 40 35 ns DIOW-DMARQ delay time (max.) tLw 40 40 35 ns DMACK 3-state delay time (max.) tZ 20 25 25 ns CS setup time (min.) tM 50 30 25 ns CS hold time (min.) tN 15 10 10 ns 26 Data Sheet S16302EJ3V0DS µPD720130 Ultra DMA mode Parameter Symbol Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Average cycle time for 2 cycles t2CYC 240 - 160 - 120 - 90 - 60 - ns Minimum cycle time for 2 cycles t2CYC 235 - 156 - 117 - 86 - 57 - ns Cycle time for 1 cycle tCYC 114 - 75 - 55 - 39 - 25 - ns Data setup time on receive side tDS 15 - 10 - 7 - 7 - 5 - ns Data hold time on receive side tDH 5 - 5 - 5 - 5 - 5 - ns Data setup time on transmit side tDVS 70 - 48 - 34 - 20 - 6 - ns Data hold time on transmit side tDVH 6 - 6 - 6 - 6 - 6 - ns First STROBE time tFS 0 230 0 200 0 170 0 130 0 120 ns Interlock time with limitation tLI 0 150 0 150 0 150 0 100 0 100 ns Minimum interlock time tMLI 20 - 20 - 20 - 20 - 20 - ns Interlock time without limitation tUI 0 - 0 - 0 - 0 - 0 - ns Output release time tAZ - 10 - 10 - 10 - 10 - 10 ns Output delay time tZAH 20 - 20 - 20 - 20 - 20 - ns Output stabilization time (from release) tZAD 0 - 0 - 0 - 0 - 0 - ns Envelope time tENV 20 70 20 70 20 70 20 55 20 55 ns STROBE DMARDY delay time tSR - 50 - 30 - 20 - NA - NA ns Last STROBE time tRFS - 75 - 60 - 50 - 60 - 60 ns Pause time tRP 160 - 125 - 100 - 100 - 100 - ns IORDY pull-up time tIORYZ - 20 - 20 - 20 - 20 - 20 ns IORDY wait time tZIORY 0 - 0 - 0 - 0 - 0 - ns DMACK setup/hold time tACK 20 - 20 - 20 - 20 - 20 - ns STROBE STOP time tSS 50 - 50 - 50 - 50 - 50 - ns Data Sheet S16302EJ3V0DS 27 µPD720130 Serial ROM interface Block Parameter Symbol Conditions Min. Max. Unit 100 KHz Clock frequency tSCL Clock pulse width low tLOW 4.7 µs Clock pulse width high tHIGH 4.0 µs Clock Low to data valid tAA 100 Start hold time tHD.STA 4.0 µs Start setup time tSU.STA 4.7 µs Data in hold time tHD.DAT 0 ns Data in setup time tSU.DAT 0.2 µs Data out hold time tDH 50 ns Stop setup time tSU.STO 4.7 µs Time the bus must be free before a new transmission can start tBUF 10 µs Write cycle time tWR 10 ms 28 Data Sheet S16302EJ3V0DS 4500 ns µPD720130 Figure 3-6. Transmit Waveform for Transceiver at DP/DM +400 mV Differential Level 1 Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-7. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 15.8 Ω 143 Ω 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Data Sheet S16302EJ3V0DS 29 µPD720130 Timing Diagram System reset timing trst RESETB Remark After RESET is negated, this chip read the serial ROM first. Do not reset while the serial ROM is read. The serial ROM is completed to read below time, after RESET is negated. 5 + 0.1197 × bytes (serial ROM size) + 0.5678 (ms) Example In the case of 512 bytes: 66.855 ms, in the case of 8 Kbytes: 986.15 ms USB power-on and connection events Hub port power OK Hub port power-on Reset recovery time Attatch detected ≥ 4.01 V USB system software reads device speed VBUS VIH(min) VIH D+ or D− tSIGATT tATTDB USB differential data jitter for full-speed tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N × tPERIOD + tDJ1 Paired Transitions N × tPERIOD + tDJ2 30 Data Sheet S16302EJ3V0DS 10 ms µPD720130 USB differential-to-EOP transition skew and EOP width for full-speed tPERIOD Crossover Point Extended Crossover Point Differential Data Lines Diff. Data-toSE0 Skew N × tPERIOD + tFDEOP Source EOP Width: tFEOPT Receiver EOP Width: tFEOPR USB receiver jitter tolerance for full-speed tPERIOD Differential Data Lines tJR tJR1 tJR2 Consecutive Transitions N × tPERIOD + tJR1 Paired Transitions N × tPERIOD + tJR2 USB connection sequence on full-speed system bus Pull-up is active. Reversion to full-speed mode Chirp K device out FSJ FSJ USB bus tHDS tCKO tSCA tSCS tFCA tDRS T0 USB connection sequence on high-speed system bus Pull-up is active. Chirp K device out USB bus K FSJ tHDS tSCA tFCA tCKO Reversion to high-speed mode Chirp state from host/hub J K J K J K Reset Complete J tRHA tSSC tCSI tSCS tFSC T0 Data Sheet S16302EJ3V0DS 31 µPD720130 USB reset sequence from suspend state on full-speed system bus Pull-up is active. USB bus Chirp K device out FSJ FSJ tSCA tCKO tSCS tFCA tDRS T0 USB reset sequence from suspend state on high-speed system bus Pull-up is active. USB bus Chrip state from host/hub Chirp K device out FSJ K tSCA tCKO tSSC tCSI tFCA J K J K J K Reversion to high-speed mode Reset Complete J tRHA tFSC tSCS T0 USB suspend and resume on full-speed system bus FS EOP USB bus FSJ FSK FSJ tSPD tSUS Power will be down Note time required to relock PLL and stabilize oscillator. USB suspend and resume on high-speed system bus Reversion to full-speed mode Reversion to high-speed mode High-speed packet High-speed packet FSJ USB bus tSPD t tCSR tSUS tRHS Power will be down T0 32 FSK Data Sheet S16302EJ3V0DS Note time required to relock PLL and stabilize oscillator. µPD720130 IDE PIO mode timing IDECS1B, IDECS0B IDEEA2-IDEEA0 H L IDEIORB IDEIOWB H L t1 t9 t0 t2i t4 t2 t3 IDED15-IDED0 (WRITE) H L t6Z t6 t5 IDED15-IDED0 (READ) H L IDEIORDY H L tA tRD tC tB IDE multi word DMA mode timing IDECS1B, IDECS0B H L IDEDRQ H L IDEDAKB H L IDEIORB IDEIOWB H L IDED15-IDED0 (READ) H L IDED15-IDED0 (WRITE) H L tM tN tLr/tLw tI tD tE t0 tKr/tKw tGr tJ tF tGw tZ tH IDE ultra DMA mode data-in timing IDEDRQ H L IDEDAKB H L IDEIOWB (STOP) IDEIORDY (HDMARDY) H L IDEIORB (DSTROBE) H L IDED15-IDED0 H L IDECS1B, IDECS0B H L IDEA2-IDEA0 H L H L tUI tSS tACK tENV tFS tZAD tACK tENV tFS tZAD tLI tMLI t2CYC tDVS Data tCYC tDVH Data tACK tACK tLI tZIORY tAZ tLI tIORYZ tZAH tDVS tCYC Data tAZ tDVH CRC tACK tACK tACK tACK Data Sheet S16302EJ3V0DS 33 µPD720130 IDE ultra DMA mode data-in stop timing IDEDRQ H L IDEDAKB H L IDEIOWB (STOP) H L IDEIORB (HDMARDY) H L IDEIORDY (DSTROBE) H L IDED15-IDED0 H L tRP tSR tRFS IDE ultra DMA mode data-in end timing IDEDRQ H L IDEDAKB H L IDEIOWB (STOP) H L tLI tMLI tACK tZAH tRP tACK tAZ IDEIORB (HDMARDY) H L IDEIORDY (DSTROBE) H L tDVS tDVH IDED15-IDED0 H L CRC IDECS1B, IDECS0B IDEA2-IDEA0 H L tRPS tLI tIORYZ tMLI tACK IDE ultra DMA mode data-out timing 34 IDEDRQ H L IDEDAKB H L IDEIOWB (STOP) IDEIORDY (DDMARDY) H L IDEIORB (HSTROBE) H L IDED15-IDED0 H L IDECS1B, IDECS0B H L IDEA2-IDEA0 H L H L tRP tUI tACK tENV tLI tUI tLI tACK tMLI tIORYZ tRFS tZIORY tACK tLI t2CYC tDVS tCYC tDVH Data tDVS tCYC Data tACK tMLI Data tDVH CRC tACK tACK tACK tACK Data Sheet S16302EJ3V0DS µPD720130 IDE ultra DMA mode data-out stop timing IDEDRQ H L IDEDAKB H L IDEIOWB (STOP) H L IDEIORB (HDMARDY) H L IDEIORDY (DSTROBE) H L IDED15-IDED0 H L tRP tSR tRFS IDE ultra DMA mode data-out end timing IDEDRQ H L IDEDAKB H L IDEIOWB (STOP) tLI tMLI tLI tACK H L IDEIORB (HDMARDY) H L IDEIORDY (DSTROBE) H L IDED15-IDED0 H L IDECS1B, IDECS0B IDEA2-IDEA0 H L tIORYZ tLI tSS tACK tDVS tDVH CRC tACK IDE ultra DMA mode data skew timing t2CYC IDEIORB (Output side) H L tCYC tDVH tDVS H IDED15-IDED0 L (Output side) ↓Delay, skew, etc., by cable IDEIORDY (Input side) IDED15-IDED0 (Input side) H L Data tDS tCYC Data Data tDH H L Output side Input side xSTROBE DD0 : : DD15 Data Sheet S16302EJ3V0DS 35 µPD720130 Serial ROM access timing tHIGH tLOW tLOW SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO SDA (Output) tAA tDH tBUF SDA (Input) Serial ROM write cycle timing PIO1 8th bit PIO0 ACK Word n tWR Stop condition 36 Data Sheet S16302EJ3V0DS Start condition µPD720130 4. PACKAGE DRAWING • µPD720130GC-9EU 100-PIN PLASTIC TQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D P T R 100 1 26 25 L U Q F J G H I M K S N S M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B MILLIMETERS 16.0±0.2 14.0±0.2 C 14.0±0.2 D F 16.0±0.2 1.0 G 1.0 H 0.22±0.05 I 0.08 J 0.5 (T.P.) 1.0±0.2 K L 0.5 M 0.17 +0.03 −0.07 N 0.08 P 1.0 Q 0.1±0.05 R 3° +4° −3° S 1.1±0.1 T 0.25 U 0.6±0.15 P100GC-50-9EU Data Sheet S16302EJ3V0DS 37 µPD720130 • µPD720130GC-9EU-SIN 100-PIN PLASTIC TQFP (FINE PITCH) (14x14) A B 51 50 75 76 detail of lead end S C D Q 100 1 R 26 25 F G J I H M K P N S L M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 16.0±0.2 B 14.0±0.2 C 14.0±0.2 D 16.0±0.2 F 1.0 G 1.0 H 0.22 +0.05 −0.04 I J 0.10 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.145+0.055 −0.045 N 0.10 P 1.0±0.1 Q 0.1±0.05 R 3° +7° −3° S 1.27 MAX. S100GC-50-9EU-2 38 Data Sheet S16302EJ3V0DS µPD720130 5. RECOMMENDED SOLDERING CONDITIONS The µPD720130 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) µPD720130GC-9EU: 100-pin plastic TQFP (Fine pitch) (14 × 14) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-103-2 Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds or less (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. µPD720130GC-9EU-SIN: 100-pin plastic TQFP (Fine pitch) (14 × 14) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-103-2 Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds or less (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet S16302EJ3V0DS 39 µPD720130 [MEMO] 40 Data Sheet S16302EJ3V0DS µPD720130 [MEMO] Data Sheet S16302EJ3V0DS 41 µPD720130 [MEMO] 42 Data Sheet S16302EJ3V0DS µPD720130 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16302EJ3V0DS 43 µPD720130 EEPROM is a trademark of NEC Electronics Corporation. USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1