FREESCALE MC9S08QE8C32

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MC9S08QE8
Rev. 3, 1/2008
MC9S08QE8 Series
20-Pin SOIC
751D-07
Covers: MC9S08QE8 and
MC9S08QE4
32-Pin LQFP
Case 873A
Features
28-Pin SOIC
751F-05
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of
–40°C to 85°C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Flash read/program/erase over full operating voltage and
temperature
– Random-Access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash contents
• Power-Saving Modes
– Two low power stop modes
– Reduced power wait mode
– Low power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents
– Very low power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to real time counter
– 6 μs typical wake-up time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-Control Pierce oscillator; crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to
16 MHz
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of internal reference
allows 0.2% resolution and 2% deviation over temperature and
voltage; supporting bus frequencies from 1 MHz to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset with option to
run from dedicated 1 kHz internal clock source or bus clock
– Low-Voltage warning with interrupt
– Low-Voltage detection with reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-Wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip debug
module)
– On-Chip in-circuit emulator (ICE) debug module containing two
comparators and nine trigger modes; eight deep FIFO for storing
change-of-flow addresses and event-only data; debug module
supports both tag and force breakpoints
16-Pin PDIP
648
• Peripherals
– ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time;
automatic compare function; 1.7 mV/°C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V
– ACMPx — Two analog comparators with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
– SCI — Full-Duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break detection;
wake-up on active edge
– SPI — Full-Duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or
LSB-first shifting
– IIC — Up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven
byte-by-byte data transfer; supporting broadcast mode and 10-bit
addressing
– TPMx — Two 3-channel (TPM1 and TPM2); selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel
– RTC — (Real-time counter) 8-bit modulus counter with binary or
decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
• Input/Output
– 26 GPIOs, one output-only pin and one input-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
• Package Options
– 32-pin LQFP, 28-pin SOIC, 20-pin SOIC, 16-pin PDIP,
16-pin TSSOP
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007–2008. All rights reserved.
Preliminary
Subject to Change Without Notice
16-Pin TSSOP
948F
Table of Contents
1
2
3
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 8
3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 8
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . 9
3.5 ESD Protection and Latch-Up Immunity . . . . . . 10
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 11
3.7 Supply Current Characteristics . . . . . . . . . . . . . 15
3.8 External Oscillator (XOSCVLP) Characteristics 16
3.9 Internal Clock Source (ICS) Characteristics . . . 17
3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 19
3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 20
3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .20
Analog Comparator (ACMP) Electricals . . . . . . .23
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .24
Flash Specifications . . . . . . . . . . . . . . . . . . . . . .27
EMC Performance . . . . . . . . . . . . . . . . . . . . . . .28
3.14.1Conducted Transient Susceptibility. . . . . .28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .29
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .29
3.11
3.12
3.13
3.14
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
2
7 Nov 2007
Initial preliminary product preview release.
3
22 Jan 2008
Initial public release.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08QE8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QE8 Series, Rev. 3
2
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of MC9S08QE8 series MCU.
BKGD/MS
HCS08 CORE
DEBUG MODULE (DBG)
BDC
REAL-TIME COUNTER
(RTC)
HCS08 SYSTEM CONTROL
IRQ
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
LVD
USER FLASH
(MC9S08QE8 = 8192 BYTES)
(MC9S08QE4 = 4096 BYTES)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER RAM
(MC9S08QE8 = 512 BYTES)
(MC9S08QE4 = 256 BYTES)
16-BIT TIMER PWM
MODULE (TPM1)
20 MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSCVLP)
16-BIT TIMER PWM
MODULE (TPM2)
EXTAL
XTAL
VSSA
VDDA
VSS
VDD
VOLTAGE REGULATOR
VSSA
VDDA
RxD
TxD
PORT A
IRQ
SDA
SS
MISO
MOSI
SPSCK
TCLK
TPM1CH0
TPM1CH1
PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
PTA5/IRQ/TCLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PORT B
COP
SCL
IIC MODULE (IIC)
PTB4/TPM2CH1/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
PTB1/KBIP5/TxD/ADP5
TPM1CH2
PTB0/KBIP4/RxD/ADP4
TCLK
TPM2CH0
PTC7/ACMP2–
TPM2CH1
PTC6/ACMP2+
TPM2CH2
PTC5/ACMP2O
ANALOG COMPARATOR
(ACMP1)
ACMP1O
ACMP1–
ACMP1+
ANALOG COMPARATOR
(ACMP2)
ACMP2O
ACMP2–
ACMP2+
PORT C
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PTC4
PTC3
PTC2
PTC1/TPM2CH2
PTC0/TPM1CH2
PTD3
VSSA/VREFL
VDDA/VREFH
VREFL
VREFH
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC12)
ADP9–ADP0
KEYBOARD INTERRUPT
MODULE (KBI)
KBIP7–KBIP0
PORT D
CPU
PTD2
PTD1
PTD0
pins not available on 16-pin packages
pins not available on 16-pin or 20-pin packages
pins not available on 16-pin, 20-pin or 28-pin packages
Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.
When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 16-pin and 20-pin packages, VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively.
Figure 1. MC9S08QE8 Series Block Diagram
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
3
Pin Assignments
2
Pin Assignments
PTA4/ACMP1O/BKGD/MS
PTA5/IRQ/TCLK/RESET
PTC4
PTC5/ACMP2O
PTC6/ACMP2+
PTC7/ACMP2–
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTA1/KBIP1/TPM2CH0ADP1/ACMP1–
This section shows the pin assignments for the MC9S08QE8 series devices.
32
31
30
29
28
27
26
25
PTD1 1
24 PTA2/KBIP2/SDA/ADP2
PTD0 2
23 PTA3/KBIP3/SCL/ADP3
VDD 3
22 PTD2
VDDA/VREFH 4
21 PTD3
VSSA/VREFL 5
20 PTA6/TPM1CH2/ADP8
VSS 6
19 PTA7/TPM2CH2/ADP9
9
10
11
12
13
14
15
16
PTC2
PTC1/TPM2CH2
PTC0/TPM1CH2
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
17 PTB1/KBIP5/TxD/ADP5
PTC3
PTB6/SDA/XTAL 8
PTB4/TPM2CH1/MISO
18 PTB0/KBIP4/RxD/ADP4
PTB5/TPM1CH1/SS
PTB7/SCL/EXTAL 7
Pins shown in bold type are lost in the next lower pin count package.
Figure 2. MC9S08QE8 Series in 32-LQFP
MC9S08QE8 Series, Rev. 3
4
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Pin Assignments
PTC5/ACMP2O
1
28
PTC6/ACMP2+
PTC4
2
27
PTC7/ACMP2–
PTA5/IRQ/TCLK/RESET
3
26
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTA4/ACMP1O/BKGD/MS
4
25
PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–
VDD
5
24
PTA2/KBIP2/SDA/ADP2
VDDA/VREFH
6
23
PTA3/KBIP3/SCL/ADP3
VSSA/VREFL
7
22
PTA6/TPM1CH2/ADP8
VSS
8
21
PTA7/TPM2CH2/ADP9
PTB7/SCL/EXTAL
9
20
PTB0/KBIP4/RxD/ADP4
PTB6/SDA/XTAL
10
19
PTB1/KBIP5/TxD/ADP5
PTB5/TPM1CH1/SS
11
18
PTB2/KBIP6/SPSCK/ADP6
PTB4/TPM2CH1/MISO
12
17
PTB3/KBIP7/MOSI/ADP7
PTC3
13
16
PTC0/TPM1CH2
PTC2
14
15
PTC1/TPM2CH2
Pins shown in bold type are lost in the next lower pin count package.
Figure 3. MC9S08QE8 Series in 28-pin SOIC Package
PTA5/IRQ/TCLK/RESET
1
20
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTA4/ACMP1O/BKGD/MS
2
19
PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–
VDD
3
18
PTA2/KBIP2/SDA/ADP2
VSS
4
17
PTA3/KBIP3/SCL/ADP3
PTB7/SCL/EXTAL
5
16
PTB0/KBIP4/RxD/ADP4
PTB6/SDA/XTAL
6
15
PTB1/KBIP5/TxD/ADP5
PTB5/TPM1CH1/SS
7
14
PTB2/KBIP6/SPSCK/ADP6
PTB4/TPM2CH1/MISO
8
13
PTB3/KBIP7/MOSI/ADP7
PTC3
9
12
PTC0/TPM1CH2
PTC2
10
11
PTC1/TPM2CH2
Pins shown in bold type are lost in the next lower pin count package.
Figure 4. MC9S08QE8 Series in 20-pin SOIC Package
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
5
Pin Assignments
PTA5/IRQ/TCLK/RESET
1
16
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTA4/ACMP1O/BKGD/MS
2
15
PTA1/KBIP1/TPM2CH0ADP1/ACMP1–
VDD
3
14
PTA2/KBIP2/SDA/ADP2
VSS
4
13
PTA3/KBIP3/SCL/ADP3
PTB7/SCL/EXTAL
5
12
PTB0/KBIP4/RxD/ADP4
PTB6/SDA/XTAL
6
11
PTB1/KBIP5/TxD/ADP5
PTB5/TPM1CH1/SS
7
10
PTB2/KBIP6/SPSCK/ADP6
PTB4/TPM2CH1/MISO
8
9
PTB3/KBIP7/MOSI/ADP7
Figure 5. MC9S08QE8 Series in 16-pin PDIP and TSSOP Packages
MC9S08QE8 Series, Rev. 3
6
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Pin Assignments
Table 2-1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest
--> Highest
Alt 2
Alt 3
32
28
20
16
1
—
—
—
PTD1
2
—
—
—
PTD0
3
5
3
3
VDD
4
6
—
—
VDDA/VREFH
5
7
—
—
VSSA/VREFL
6
8
4
4
7
9
5
5
Port Pin
Priority
Alt 1
VSS
PTB7
8
10
6
6
PTB6
1
EXTAL
1
XTAL
SCL
SDA
9
11
7
7
PTB5
TPM1CH1
SS
10
12
8
8
PTB4
TPM2CH1
MISO
11
13
9
—
PTC3
12
14
10
—
PTC2
13
15
11
—
PTC1
TPM2CH22
14
16
12
—
PTC0
TPM1CH23
15
17
13
9
PTB3
KBIP7
MOSI
ADP7
16
18
14
10
PTB2
KBIP6
SPSCK
ADP6
17
19
15
11
PTB1
KBIP5
TxD
ADP5
18
20
16
12
PTB0
KBIP4
RxD
ADP4
19
21
—
—
Alt 4
PTA7
20
22
—
—
PTA6
21
—
—
—
PTD3
22
—
—
—
PTD2
23
23
17
13
PTA3
2
ADP9
3
ADP8
TPM2CH2
TPM1CH2
KBIP3
SCL1
ADP3
1
ADP2
24
24
18
14
PTA2
KBIP2
SDA
25
25
19
15
PTA1
KBIP1
TPM2CH0 ADP14
ACMP1–4
KBIP0
ADP04
ACMP1+4
26
26
20
16
PTA0
TPM1CH0
27
27
—
—
PTC7
ACMP2–
28
28
—
—
PTC6
ACMP2+
ACMP2O
29
1
—
—
PTC5
30
2
—
—
PTC4
31
3
1
1
PTA5
IRQ
TCLK
RESET
32
4
2
2
PTA4
ACMP1O
BKGD
MS
1
IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2, default reset locations
are PTA3 and PTA2.
2 TPM2CH2 pin can be repositioned using TPM2CH2PS in SOPT2, default reset location is
PTA7.
3 TPM1CH2 pin can be repositioned using TPM1CH2PS in SOPT2, default reset location is
PTA6.
4 If ADC and ACMP1 are enabled, both modules will have access to the pin.
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
7
Electrical Characteristics
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08QE8 series of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled.
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to 3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
±25
mA
Tstg
–55 to 150
°C
Storage temperature range
MC9S08QE8 Series, Rev. 3
8
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Maximum junction temperature
Symbol
Value
Unit
TA
TL to TH
–40 to 85
°C
TJM
95
°C
Thermal resistance
Single-layer board
32-pin LQFP
66
28-pin SOIC
57
20-pin SOIC
θJA
71
16-pin PDIP
64
16-pin TSSOP
108
°C/W
Thermal resistance
Four-layer board
32-pin LQFP
47
28-pin SOIC
42
20-pin SOIC
θJA
52
16-pin PDIP
47
16-pin TSSOP
78
°C/W
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
9
Electrical Characteristics
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Description
Symbol
Value
Unit
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
—
Series resistance
R1
0
Ω
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
Latch-up
Table 6. ESD and Latch-Up Protection Characteristics
No.
Rating1
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
±2000
—
V
2
Machine model (MM)
VMM
±200
—
V
MC9S08QE8 Series, Rev. 3
10
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics (continued)
1
3.6
3
Charge device model (CDM)
VCDM
±500
—
V
4
Latch-up current at TA = 85°C
ILAT
±100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C
1
Characteristic
P
Output high
voltage
D
All I/O pins,
high-drive strength
Output high
current
Max total IOH for all ports
4
P
Output low
voltage
All I/O pins,
high-drive strength
C
5
D
6
VOH
IOHT
All I/O pins,
low-drive strength
C
Output low
current
Min.
Typical1
1.8
All I/O pins,
low-drive strength
C
3
Condition
Operating Voltage
C
2
Symbol
VOL
Max.
Unit
3.6
V
VDD > 1.8 V,
ILoad = –2 mA
VDD – 0.5
—
—
VDD > 2.7 V,
ILoad = –10 mA
VDD – 0.5
—
—
VDD > 1.8V,
ILoad = –2 mA
VDD – 0.5
—
—
—
—
—
100
VDD > 1.8 V,
ILoad = 0.6 mA
—
—
0.5
VDD > 2.7 V,
ILoad = 10 mA
—
—
0.5
VDD > 1.8 V,
ILoad = 3 mA
—
—
0.5
—
—
—
100
VDD > 2.7 V
0.70 x VDD
—
—
VDD > 1.8 V
0.85 x VDD
—
—
VDD > 2.7 V
—
—
0.35 x VDD
VDD > 1.8 V
—
—
0.30 x VDD
V
mA
V
Max total IOL for all ports
IOLT
P Input high
C voltage
all digital inputs
VIH
7
P Input low
C voltage
all digital inputs
VIL
8
C
all digital inputs
Vhys
—
0.06 x VDD
—
—
mV
9
Input
P leakage
current
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
—
0.1
1
μA
10
Hi-Z
(off-state)
P
leakage
current
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
0.1
1
μA
11a
Pullup,
P Pulldown
resistors
all digital inputs, when
enabled (all I/O pins other
than
PTA5/IRQ/TCLK/RESET
RPU,
RPD
—
17.5
—
52.5
kΩ
Input
hysteresis
mA
V
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
11
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
11b
12
Characteristic
Pullup,
C Pulldown
resistors
DC injection
C current 3, 4,
5
Symbol
Condition
Min.
Typical1
Max.
Unit
RPU,
RPD
—
17.5
—
52.5
kΩ
–0.2
—
0.2
mA
–5
—
5
mA
(PTA5/IRQ/TCLK/RESET)
2
(Note )
Single pin limit
Total MCU limit, includes
sum of all stressed pins
13
C Input Capacitance, all pins
14
C RAM retention voltage
6
IIC
VIN < VSS, VIN > VDD
CIn
—
—
—
8
pF
VRAM
—
—
0.6
1.0
V
—
0.9
1.4
2.0
V
15
C POR re-arm voltage
VPOR
16
D POR re-arm time
tPOR
—
10
—
—
μs
1.80
1.88
1.84
1.92
1.88
1.96
V
17
P Low-voltage detection threshold
VLVD
VDD falling
VDD rising
18
P Low-voltage warning threshold
VLVW
VDD falling
VDD rising
2.08
2.14
2.24
V
19
P
Vhys
—
—
80
—
mV
20
P Bandgap Voltage Reference7
VBG
—
1.15
1.17
1.18
V
1
Low-voltage inhibit reset/recover
hysteresis
Typical values are measured at 25°C. Characterized, not tested
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when
measured externally on the pin.
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 3.0 V, Temp = 25 °C
3
4
5
6
7
PULLUP RESISTOR TYPICALS
PULL-UP RESISTOR (kΩ)
40
85°C
25°C
–40°C
35
30
25
20
1.8
2
2.2
2.4
2.6 2.8
VDD (V)
3
3.2
3.4
3.6
PULLDOWN RESISTANCE (kΩ)
2
PULLDOWN RESISTOR TYPICALS
40
85°C
25°C
–40°C
35
30
25
20
1.8
2.3
2.8
VDD (V)
3.3
3.6
Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
MC9S08QE8 Series, Rev. 3
12
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.0 V
1.2
1
0.15
VOL (V)
0.8
VOL (V)
TYPICAL VOL VS VDD
0.2
85°C
25°C
–40°C
0.6
0.4
0.2
0.1
85°C, IOL = 2 mA
25°C, IOL = 2 mA
–40°C, IOL = 2 mA
0.05
0
0
0
5
10
IOL (mA)
15
1
20
2
3
VDD (V)
4
Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
85°C
25°C
–40°C
0.8
85°C
25°C
–40°C
0.3
VOL (V)
VOL (V)
0.6
0.4
0.2
0.2
IOL = 10 mA
IOL = 6 mA
0.1
0
IOL = 3 mA
0
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
1.2
85°C
25°C
–40°C
85°C, IOH = 2 mA
25°C, IOH = 2 mA
–40°C, IOH = 2 mA
0.2
VDD – VOH (V)
VDD – VOH (V)
1
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.25
0.8
0.6
0.4
0.15
0.1
0.05
0.2
0
0
0
–5
–10
IOH (mA))
–15
–20
1
2
VDD (V)
3
4
Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
13
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.4
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
0.3
85°C
25°C
–40°C
0.6
VDD – VOH (V)
VDD – VOH (V)
0.8
0.4
0.2
0
0
–5
–10
–15
–20
IOH (mA)
85°C
25°C
–40°C
–25
–30
0.2
IOH = –10 mA
IOH = –6 mA
0.1
IOH = –3 mA
0
1
2
3
4
VDD (V)
Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
MC9S08QE8 Series, Rev. 3
14
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Num
1
2
P
T
T
T
T
3
T
T
4
T
T
5
T
6
7
8
9
Parameter
C
T
T
T
P
C
P
C
Symbol
Run supply current
FEI mode, all modules on
RIDD
Run supply current
FEI mode, all modules off
RIDD
Run supply current
LPRS=0, all modules off
RIDD
Run supply current
LPRS=1, all modules off; running
from Flash
RIDD
Run supply current
LPRS=1, all modules off; running
from RAM
RIDD
Wait mode supply current
FEI mode, all modules off
WIDD
Wait mode supply current
LPRS = 1, all modules off
WIDD
Stop2 mode supply current
S2IDD
Stop3 mode supply current
no clocks active
S3IDD
Bus
Freq
VDD
(V)
10 MHz
1 MHz
3
10 MHz
1 MHz
16 kHz
FBILP
16 kHz
FBELP
16 kHz
FBILP
16 kHz
FBELP
16 kHz
FBILP
16 kHz
FBELP
10 MHz
1 MHz
3
Typical1
Max
Unit
5.60
8.2
mA
0.80
—
3.60
—
0.51
—
165
—
105
—
77
—
3
3
21
—
77
—
7.3
—
570
—
290
—
3
3
16 kHz
FBELP
3
1
—
—
3
300
2500
—
2
250
2000
—
3
400
6000
—
2
350
5500
–40 to 85°C
μA
–40 to 85°C
μA
–40 to 85°C
μA
–40 to 85°C
μA
–40 to 85°C
μA
–40 to 85°C
nA
nA
—
—
—
200
—
nA
RTC using low
power crystal
oscillator
—
—
—
500
—
nA
T
EREFSTEN=1
—
—
300
—
nA
T
IREFSTEN=1
—
—
70
—
μA
100
—
μA
T
11
T
12
13
14
T
15
16
Stop2 and
Stop 3 adders:
3
–40 to 85°C
–40 to 85°C
–40 to 85°C
–40 to 85°C
–40 to 85°C
LVD
—
—
T
ACMP2
—
—
20
—
μA
T
ADC3
—
—
0.007
—
μA
Stop3 adders:
–40 to 85°C
mA
RTC using LPO
10
Temp
(°C)
–40 to 85°C
–40 to 85°C
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Also applies to LPRun and LPWait modes.
3 ADC current measured on V
DDA pin on 28-pin and 32-pin devices, adder to VDD on 16-pin and 20-pin packages.
2
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
15
Electrical Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Refer to Figure 11 and Figure 12 for crystal or resonator circuits.
Table 9. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
2
D
3
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
D
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
4
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
5
6
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
Crystal start-up time 4
Low range, low power
Low range, high gain
C
High range, low power
High range, high gain
Symbol
Min.
flo
fhi
fhi
32
1
1
RS
t
t
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
D
FBE or FBELP mode
CSTL
CSTH
fextal
—
—
—
38.4
16
8
Unit
kHz
MHz
MHz
See Note2
See Note3
C1,C2
RF
Typical1 Max.
—
—
—
—
10
1
—
—
—
—
—
—
—
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
600
400
5
15
—
—
—
—
ms
0.03125
0
—
—
20
20
MHz
MHz
MΩ
kΩ
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0.
3 See crystal or resonator manufacturer’s recommendation.
4
Proper PC board layout procedures must be followed to achieve specifications.
2
MC9S08QE8 Series, Rev. 3
16
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Symbol
Min.
Typical1
Max.
Unit
Average internal reference frequency — factory trimmed
at VDD = 3.6 V and temperature = 25°C
fint_ft
—
32.768
—
kHz
P
Internal reference frequency — user trimmed
fint_ut
31.25
—
39.06
kHz
3
T
Internal reference start-up time
tIRST
—
60
100
μs
4
P
DCO output frequency range — trimmed2
fdco_u
48
—
60
MHz
5
P
DCO output frequency2
Reference = 32768 Hz and DMX32 = 1
fdco_DMX32
—
59.77
—
MHz
6
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
—
± 0.1
± 0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
Δfdco_res_t
—
± 0.2
± 0.4
%fdco
Num
C
1
P
2
Characteristic
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
17
Electrical Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Symbol
Min.
Typical1
Max.
Unit
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δfdco_t
—
+ 0.5
-1.0
±2
%fdco
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C
Δfdco_t
—
± 0.5
±1
%fdco
tAcquire
—
—
1
ms
CJitter
—
0.02
0.2
%fdco
Num
C
Characteristic
8
C
9
C
10
C FLL acquisition time3
11
C
Long term jitter of DCO output clock (averaged over 2-ms
interval)4
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
2
1.00%
0.50%
Deviation (%)
0.00%
-60
-40
-20
0
20
40
60
80
100
120
-0.50%
-1.00%
TBD
-1.50%
-2.00%
Temperature
Figure 13. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08QE8 Series, Rev. 3
18
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.10.1
Control Timing
Table 11. Control Timing
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
dc
—
10
MHz
D
Internal low power oscillator period
tLPO
700
—
1300
μs
3
D
External reset pulse width2
textrst
100
—
—
ns
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
μs
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 × tcyc
—
—
—
—
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 × tcyc
—
—
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
16
23
—
—
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
5
9
—
—
Num
C
1
D
2
9
Rating
ns
C
ns
1
Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
2
textrst
RESET PIN
Figure 14. Reset Timing
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
19
Electrical Characteristics
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 15. IRQ/KBIPx Timing
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 12. TPM Input Timing
No.
C
1
D
2
Function
Symbol
Min
Max
Unit
External clock frequency
fTCLK
0
fBus/4
Hz
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 16. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 17. Timer Input Capture Pulse
3.10.3
SPI Timing
Table 13 and Figure 18 through Figure 21 describe the timing requirements for the SPI system.
MC9S08QE8 Series, Rev. 3
20
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 13. SPI Timing
No.
C
Function
Symbol
Min
Max
Unit
—
D
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
1
D
SPSCK period
Master
Slave
tSPSCK
2
4
2048
—
tcyc
tcyc
2
D
Enable lead time
Master
Slave
tLead
1/2
1
—
—
tSPSCK
tcyc
3
D
Enable lag time
Master
Slave
tLag
1/2
1
—
—
tSPSCK
tcyc
4
D
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
5
D
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
6
D
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
D
Slave access time
ta
—
1
tcyc
8
D
Slave MISO disable time
tdis
—
1
tcyc
9
D
Data valid (after SPSCK edge)
Master
Slave
tv
—
—
25
25
ns
ns
10
D
Data hold time (outputs)
Master
Slave
tHO
0
0
—
—
ns
ns
11
D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
21
Electrical Characteristics
SS1
(OUTPUT)
11
1
2
SPSCK
(CPOL = 0)
(OUTPUT)
3
4
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
9
MOSI
(OUTPUT)
LSB IN
10
9
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN(2)
BIT 6 . . . 1
10
9
MOSI
(OUTPUT) PORT DATA
LSB IN
MASTER MSB OUT(2)
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI Master Timing (CPHA =1)
MC9S08QE8 Series, Rev. 3
22
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
BIT 6 . . . 1
MSB OUT
SLAVE
10
10
9
SEE
NOTE
SLAVE LSB OUT
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 20. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SPSCK
(CPOL = 0)
(INPUT)
4
SPSCK
(CPOL = 1)
(INPUT)
4
SEE
NOTE
SLAVE
11
12
8
BIT 6 . . . 1
MSB OUT
5
7
MOSI
(INPUT)
11
10
9
MISO
(OUTPUT)
12
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 21. SPI Slave Timing (CPHA = 1)
3.11
Analog Comparator (ACMP) Electricals
Table 14. Analog Comparator Electrical Specifications
C
Characteristic
D
Supply voltage
P
Supply current (active)
Symbol
Min
Typical
Max
Unit
VDD
1.8
—
3.6
V
IDDAC
—
20
35
μA
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
23
Electrical Characteristics
Table 14. Analog Comparator Electrical Specifications (continued)
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
P
Analog input offset voltage
VAIO
—
20
40
mV
C
Analog comparator hysteresis
VH
3.0
9.0
15.0
mV
P
Analog input leakage current
IALKG
—
—
1.0
μA
C
Analog comparator initialization delay
tAINIT
—
—
1.0
μs
3.12
ADC Characteristics
Table 15. 12-bit ADC Operating Conditions
Symb
Min
Typ1
Max
Unit
Comment
Absolute
VDDAD
1.8
—
3.6
V
—
Delta to VDD (VDD-VDDAD)2
ΔVDDAD
–100
0
+100
mV
—
Ground voltage
Delta to VSS (VSS-VSSAD)2
ΔVSSAD
–100
0
+100
mV
—
Ref Voltage
High
—
VREFH
1.8
VDDAD
VDDAD
V
—
Input Voltage
—
VADIN
VREFL
—
VREFH
V
—
Input
Capacitance
—
CADIN
—
4.5
5.5
pF
—
Input
Resistance
—
RADIN
—
5
7
kΩ
—
—
—
—
—
2
5
kΩ
External to MCU
—
—
—
—
5
10
—
—
10
0.4
—
8.0
MHz
—
0.4
—
4.0
Characteristic
Supply voltage
Analog Source
Resistance
Conditions
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
RAS
8 bit mode (all valid fADCK)
ADC
Conversion
Clock Freq.
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADCK
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
DC potential difference.
1
MC9S08QE8 Series, Rev. 3
24
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
CAS
+
–
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 22. ADC Input Impedance Equivalency Diagram
Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Symbol
Min.
Typical1
Max.
Unit
Comment
—
IDDAD
—
120
—
μA
—
T
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
—
IDDAD
—
202
—
μA
—
T
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
—
IDDAD
—
288
—
μA
—
P
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
—
IDDAD
—
0.532
1
mA
—
2
3.3
5
1.25
2
3.3
C
Characteristic
T
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
P
ADC
Asynchronous
Clock Source
C
Conditions
High Speed
(ADLPC=0)
Low Power
(ADLPC=1)
fADACK
MHz
tADACK =
1/fADACK
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
25
Electrical Characteristics
Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
C
P
Characteristic
Conversion
Time (Including
sample time)
Conditions
Short Sample
(ADLSMP=0)
C
Long Sample
(ADLSMP=1)
P
Short Sample
(ADLSMP=0)
Sample Time
Long Sample
(ADLSMP=1)
C
T
P
T
T
P
T
Total
Unadjusted
Error
(28-pin and
32-pin
packages)
Total
Unadjusted
Error
(16-pin and
20-pin
package)
T
P
Differential
Non-Linearity
Symbol
Min.
Typical1
Max.
—
20
—
ADCK
cycles
tADC
—
40
—
—
3.5
—
23.5
—
—
±3.0
—
—
±1
±2.5
8 bit mode
—
±0.5
±1.0
Includes
quantization
12 bit mode
—
±4.0
—
—
±1.5
±3.5
For 16-pin and
20-pin packages
only.
8 bit mode
—
±0.7
±1.5
12 bit mode
—
±1.75
—
—
±0.5
±1.0
12 bit mode
10 bit mode
ETUE
10 bit mode
ETUE
10 bit mode3
DNL
—
±0.3
±0.5
T
12 bit mode
—
±1.5
—
—
±0.5
±1.0
10 bit mode
INL
T
8 bit mode
—
±0.3
±0.5
T
12 bit mode
—
±1.5
—
—
±0.5
±1.5
8 bit mode
—
±0.5
±0.5
12 bit mode
—
±1.0
—
—
±0.5
±1
8 bit mode
—
±0.5
±0.5
12 bit mode
—
–1 to 0
—
—
—
±0.5
—
—
±0.5
P
Zero-Scale
Error
T
T
P
Full-Scale
Error
T
D
Quantization
Error
See ADC
chapter in the
QE8 Reference
Manual for
conversion time
variances
—
8 bit mode3
Integral
Non-Linearity
Comment
ADCK
cycles
tADS
T
C
Unit
10 bit mode
10 bit mode
10 bit mode
8 bit mode
EZS
EFS
EQ
LSB2
LSB2
For 28-pin and
32-pin packages
only.
Includes
quantization
LSB2
—
LSB2
—
LSB2
VADIN = VSSAD
LSB2
VADIN = VDDAD
LSB2
—
MC9S08QE8 Series, Rev. 3
26
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
C
Characteristic
D
Input Leakage
Error
Conditions
Symbol
Min.
Typical1
Max.
—
±2
—
—
±0.2
±4
—
±0.1
±1.2
—
1.646
—
—
1.769
—
—
701.2
—
12 bit mode
10 bit mode
EIL
8 bit mode
D
D
–40°C to 25°C
Temp Sensor
Slope
m
25°C
Comment
LSB2
Pad leakage4
*RAS
mV/°C
25°C to 85°C
Temp Sensor
Voltage
Unit
VTEMP25
mV
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2 1 LSB = (V
N
REFH – VREFL)/2
3
Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
4 Based on input pad leakage current. Refer to pad electricals.
1
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section.
Table 17. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
3.6
V
D
Supply voltage for program/erase
–40°C to 85°C
Vprog/erase
1.8
D
Supply voltage for read operation
VRead
1.8
—
3.6
V
fFCLK
150
—
200
kHz
tFcyc
5
—
6.67
μs
frequency1
D
Internal FCLK
D
Internal FCLK period (1/FCLK)
P
P
P
P
Byte program time (random
Byte program time (burst
location)2
mode)2
—
tprog
9
tFcyc
tBurst
4
tFcyc
Page erase
time2
tPage
4000
tFcyc
Mass erase
time2
tMass
20,000
tFcyc
Byte program
Page erase
current3
current3
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
—
10,000
—
100,000
—
—
cycles
tD_ret
15
100
—
years
endurance4
1
2
C
Program/erase
TL to TH = –40°C to + 85°C
T = 25°C
C
Data retention5
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
27
Electrical Characteristics
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
3.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.14.1
Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 18.
Table 18. Conducted Susceptibility, EFT/B
Parameter
Symbol
Conducted susceptibility, electrical
fast transient/burst (EFT/B)
1
VCS_EFT
Conditions
VDD = 3.3 V
TA = +25oC
package type
32 LQFP
fOSC/fBUS
8 MHz
crystal
8 MHz bus
Result
Amplitude1
(Min)
A
2.3
B
4.0
C
>4.0
D
>4.0
Unit
kV
Data based on qualification test results. Not tested in production.
The susceptibility performance classification is described in Table 19.
Table 19. Susceptibility Performance Classification
Result
Performance Criteria
A
No failure
B
Self-recovering
failure
C
Soft failure
The MCU performs as designed during and after exposure.
The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
MC9S08QE8 Series, Rev. 3
28
Preliminary
Subject to Change Without Notice
Freescale Semiconductor
Ordering Information
Table 19. Susceptibility Performance Classification (continued)
Result
Performance Criteria
D
Hard failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
E
Damage
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
4
Ordering Information
This section contains ordering information for the device numbering system.
Example of the device numbering system:
MC 9 S08 QE 8
C XX
Status
(MC = Fully Qualified)
Package designator (see Table 20)
Temperature range
(C = –40°C to 85°C)
Memory
(9 = Flash-based)
Core
Approximate flash size in Kbytes
Family
5
Package Information
Table 20. Package Descriptions
Pin Count
5.1
Package Type
Abbreviation
Designator
Case No.
Document No.
873A
98ASH70029A
32
Low Quad Flat Package
LQFP
LC
28
Small Outline Integrated Circuit
SOIC
WL
751F
98ASB42345B
20
Small Outline Integrated Circuit
SOIC
WJ
751D
98ASB42343B
PDIP
PG
648
98ASB42431B
TSSOP
TG
948F
98ASH70247A
16
Plastic Dual In-line Package
16
Thin Shrink Small Outline Package
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 20.
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
29
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Document Number: MC9S08QE8
Rev. 3
1/2008
Preliminary
Subject to Change Without Notice
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