PD -95622
IRL2505PbF
Logic-Level Gate Drive
l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
Description
HEXFET® Power MOSFET
l
D
VDSS = 55V
RDS(on) = 0.008Ω
G
ID = 104A
S
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
HEXFET Power MOSFETs are well known for, provides the
designer with an extremely efficient and reliable device for
use in a wide variety of applications.
The TO-220 is universally preferred for all commercialIndustrial applications at power dissipation levels to
approximately 50 watts. The low thermal resistance and
low package cost of the TO-220 contribute to its wide
acceptance throughout the industry.
TO-220AB
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
104
74
360
200
1.3
± 16
500
54
20
5.0
55 to + 175
Mounting torque, 6-32 or M3 srew
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Juction-to-Ambient
Typ.
Max.
Units
–––
0.50
–––
0.75
–––
62
°C/W
1
8/3/04
IRL2505PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
1.0
59
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V (BR)DSS
RDS(on)
Static Drain-to-Source On-Resistance
V GS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Typ. Max. Units
Conditions
V
VGS = 0V, ID = 250µA
0.035 V/°C Reference to 25°C, ID = 1mA
0.008
VGS = 10V, ID = 54A
0.010 Ω
VGS = 5.0V, ID = 54A
0.013
VGS = 4.0V, ID = 45A
2.0
V
VDS = VGS, ID = 250µA
S
VDS = 25V, ID = 54A
25
VDS = 55V, VGS = 0V
µA
250
VDS = 44V, VGS = 0V, T J = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
130
ID = 54A
25
nC
VDS = 44V
67
VGS = 5.0V, See Fig. 6 and 13
12
VDD = 28V
160
ID = 54A
ns
43
RG = 1.3Ω, VGS = 5.0V
84
RD = 0.50Ω, See Fig. 10
Between lead,
7.5
nH
and center of die contact
5000
VGS = 0V
1100
pF
VDS = 25V
390
= 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 240µH
RG = 25Ω, IAS = 54A. (See Figure 12)
ISD ≤ 54A, di/dt ≤ 230A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
2
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
104
showing the
A
G
integral reverse
360
S
p-n junction diode.
1.3
V
TJ = 25°C, IS = 54A, VGS = 0V
140 210
ns
TJ = 25°C, IF = 54A
650 970
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the
package refer to Design Tip # 93-4
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IRL2505PbF
1000
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
100
10
2.5V
20µs PULSE WIDTH
T J = 25°C
1
0.1
1
10
A
100
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 175°C
10
V DS= 25V
20µs PULSE WIDTH
4.5
5.5
6.5
7.5
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
A
2.5
ID = 90A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
A
100
Fig 2. Typical Output Characteristics
TJ = 25°C
3.5
1
VDS , Drain-to-Source Voltage (V)
1000
1
20µs PULSE WIDTH
T J = 175°C
1
0.1
Fig 1. Typical Output Characteristics
100
2.5V
10
VDS , Drain-to-Source Voltage (V)
2.5
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
TOP
VGS = 5V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL2505PbF
10000
VGS , Gate-to-Source Voltage (V)
8000
C, Capacitance (pF)
15
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
Ciss
6000
Coss
4000
2000
Crss
0
1
10
100
I D = 54A
VDS = 44V
VDS = 28V
12
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
0
VDS , Drain-to-Source Voltage (V)
80
120
160
A
200
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10µs
100
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
40
TJ = 175°C
TJ = 25°C
VGS = 0V
10
0.4
0.8
1.2
1.6
2.0
2.4
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
A
2.8
100
100µs
1ms
10
10ms
TC = 25°C
TJ = 175°C
Single Pulse
1
1
A
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL2505PbF
120
LIMITED BY PACKAGE
V GS
I D , Drain Current (A)
100
D.U.T.
RG
80
+
-V DD
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60
Fig 10a. Switching Time Test Circuit
40
VDS
20
0
90%
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
td(on)
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
PDM
0.05
t1
0.02
0.01
0.01
0.00001
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.01
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
L
VDS
D.U.T.
RG
+
V
- DD
IAS
5.0 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
VDD
EAS , Single Pulse Avalanche Energy (mJ)
IRL2505PbF
1200
TOP
1000
BOTTOM
ID
22A
38A
54A
800
600
400
200
0
VDD = 25V
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
VDS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
5.0 V
QGS
QGD
D.U.T.
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
A
175
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRL2505PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
V DD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS
ISD
= 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRL2505PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
4- DRAIN
14.09 (.555)
13.47 (.530)
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
IGBTs, CoPACK
1 - GATE
2 - DRAIN
1- GATE
1- GATE
3 - SOURCE 2- COLLECTOR
2- DRAIN
3- SOURCE
3- EMITTER
4 - DRAIN
HEXFET
1.40 (.055)
1.15 (.045)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010
LOT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y LINE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/04
8
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