LT4256-3 Positive High Voltage Hot Swap Controller with Open-Circuit Detect U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltage from 10.8V to 80V Foldback Current Limiting Open Circuit and Overcurrent Fault Detect Drives an External N-Channel MOSFET Automatic Retry or Latched Off Operation After Overcurrent Fault Programmable Supply Voltage Power-Up Rate Open MOSFET Detection 1% Over and Undervoltage Detection Accuracy Available in a 16-Lead SSOP Package U APPLICATIO S ■ ■ ■ ■ ■ ■ Hot Board Insertion Electronic Circuit Breaker/Power Bussing Industrial High Side Switch/Circuit Breaker 24V/48V Industrial/Alarm Systems Ideally Suited for 12V, 24V and 48V Distributed Power Systems 48V Telecom Systems TM The LT®4256-3 is a high voltage Hot Swap controller that allows a board to be safely inserted and removed from a live backplane. An internal driver controls the high side N-channel MOSFET gate for supply voltages ranging from 10.8V to 80V. The part features an open-circuit detect (OPEN) output that indicates abnormally low load current conditions. The LT4256-3 also features an adjustable analog foldback current limit. If the supply remains in current limit for more than a programmable time, the N-channel MOSFET shuts off, the PWRGD output asserts low and the LT4256-3 either automatically restarts after a time-out delay or latches off until the UV pin is cycled low (depending on the status of the RETRY pin). The PWRGD output indicates when the output voltage rises above a programmed level. An external resistor string from VCC provides programmable undervoltage and overvoltage protection. The LT4256-3 is available in a 16-lead SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO 48V, 2A Hot Swap Controller 0.020Ω VIN 48V IRF540 + SMAT70A VCC 64.9k 0.01µF SENSE 10Ω UV 4.02k CL CMPZ5241BS 11V (SHORT PIN) 100Ω 10nF GATE LT4256-3 VOUT 36.5k 51k 4.02k PWRGD 50V/DIV 4.02k PWRGD PWRGD 4256 TA01 TIMER 33nF CONTACT BOUNCE VOUT 50V/DIV INRUSH CURRENT 500mA/DIV FB GND LT4256-3 Start-Up Behavior VIN 50V/DIV OV OPEN VOUT 48V 2A RETRY GND 2.5ms/DIV 42563 TA02 UV = 36V OV = 73V PWRGD = 40V 42563f 1 LT4256-3 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCC) ................................ – 0.3 to 100V SENSE, PWRGD ....................................... – 0.3 to 100V GATE Voltage (Note 2) .................... – 0.3V to VCC + 10V GATE Maximum Current ..................................... 200µA VOUT .......................................................... –3V to 100V FB, UV, OPEN ............................................. – 0.3 to 44V OV .............................................................. – 0.3 to 18V RETRY ........................................................ – 0.3 to 15V TIMER Voltage ......................................... – 0.3V to 4.3V Maximum Input Current (TIMER) ....................... 100µA Operating Temperature LT4256-3C ............................................. 0°C to 70°C LT4256-3I ......................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW UV 1 16 VCC OV 2 15 SENSE NC 3 14 NC OPEN 4 13 GATE PWRGD 5 12 VOUT NC 6 11 NC RETRY 7 10 FB GND 8 9 LT4256-3CGN LT4256-3IGN GN PART MARKING TIMER 42563 42563I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VCC Operating Voltage ICC Operating Current VUVLH Undervoltage Threshold VUVHYS Hysteresis IINUV UV Input Current VUVRTH Fault Latch Reset Threshold Voltage VOVLH Overvoltage Threshold VOVHYS Hysteresis IINOV OV Input Current VOPEN Open-Circuit Voltage Threshold (VCC – VSENSE) VOLOPEN OPEN Output Low Voltage IINOPEN Leakage Current VOPEN = 5V VSENSETRIP SENSE Pin Trip Voltage (VCC – VSENSE) FB = 0V FB ≥ 2V IINSNS SENSE Pin Input Current VSENSE = VCC IPU GATE Pull-Up Current Charge Pump On, ∆VGATE = 7V IPD GATE Pull-Down Current Any Fault, VGATE > VOUT IPDL VOUT Pull-Down Current, Fault Condition Any Fault, VGATE = VOUT + ∆VGATEL, VOUT = 48V ∆VGATE External N-Channel Gate Drive (Note 2) VGATE – VOUT, 10.8V ≤ VCC ≤ 20V 20V ≤ VCC ≤ 80V ∆VGATEL External N-Channel Gate Drive, Fault Condition VGATE – VOUT, VOUT = 48V VCC Low-to-High Transition MIN ● 10.8 ● 3.96 0.25 UV ≥ 1.2V UV = 0V VCC Low-to-High Transition TYP MAX UNITS 80 V 1.8 3.9 mA 4 4.04 V 0.4 0.55 V –0.1 –1.5 –1 –3 µA µA 0.85 1.2 V ● 0.4 ● 3.96 4 4.04 V 0.25 0.4 0.55 V 0.1 1 µA 3 6.5 mV 0.20 0.75 0.5 1.3 V V 0V ≤ OV < 7V ● 1.5 IO = 2mA IO = 5mA ● ● ● 0.1 1 µA 14 55 22 65 mV mV 40 70 µA –16 – 30 – 55 µA 40 62 80 mA 7 45 µA 130 ● ● 4.5 10 8.8 11.6 –2 12.5 12.8 V V V 42563f 2 LT4256-3 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VFB FB Voltage Threshold FB High-to-Low Transition FB Low-to-High Transition VFBHYS FB Hysteresis Voltage VOLPGD PWRGD Output Low Voltage IO = 1.6mA IO = 5mA IPWRGD PWRGD Pin Leakage Current VPWRGD = 80V IINFB FB Input Current FB = 4.5V –0.1 –1 µA ITIMERPU TIMER Pull-Up Current ● – 85 – 115 –145 µA ITIMERPD TIMER Pull-Down Current ● 1.5 3 5 µA VTHTIMER TIMER Shutdown Threshold ● 4.3 4.65 5 V DTIMER Duty Cycle (RETRY Mode) ● 1.5 3 4.5 % VRETRYTH RETRY Threshold ● 0.4 0.85 1.2 V IINRTR RETRY Input Current RETRY = GND –87 –130 µA tPHLUV UV Low to GATE Low CGATE = 100pF 1.7 3 µs tPLHUV UV High to GATE High CGATE = 100pF 6 9 µs tPHLFB FB Low to PWRGD Low 0.8 2 µs tPLHFB FB High to PWRGD High tPHLSENSE (VCC – VSENSE) High to GATE Low ● ● CTIMER = 10nF MIN TYP MAX UNITS 3.95 4.20 3.99 4.45 4.03 4.65 V V 0.3 0.45 0.60 V 0.25 0.60 0.4 1.0 V V 0.1 1 µA VCC – VSENSE = 275mV Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 3.2 5 µs 1 3 µs Note 2: An internal clamp limits the GATE pin to a minimum of 10V above VCC. Driving this pin to a voltage beyond the clamp voltage may damage the part. U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at TA = 25°C unless otherwise noted. SENSE Regulation Voltage vs Temperature ICC vs VCC ICC vs Temperature 3.5 58 2.5 VCC = 48V 3.0 53 2.0 48 20 ICC (mA) 2.5 ICC (mA) SENSE REGULATION VOLTAGE (mV) FB > 2V 2.0 1.5 1.5 1.0 1.0 FB = 0V 15 10 –50 0.5 0.5 0 –25 0 25 50 TEMPERATURE (°C) 75 100 42563 G01 10 20 30 50 40 VCC (V) 60 70 80 42563 G02 0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 42563 G03 42563f 3 LT4256-3 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at TA = 25°C unless otherwise noted. GATE Pull-Down Current vs Temperature GATE Pull-Down Capability vs VCC Below Minimum Operating Voltage 0 63 60 –5 62 50 GATE PULL-DOWN CURRENT (mA) –15 –20 –25 –30 –35 –40 –50 –25 0 25 50 TEMPERATURE (°C) 75 61 40 IGATE (mA ) –10 60 59 20 10 57 56 –50 100 0 –25 0 25 50 TEMPERATURE (°C) 75 100 VGATE – VOUT Voltage vs Temperature 6 VCC (V) 8 VCC = 18V 10 12 TIMER Currents vs Temperature 5.0 14.0 PULL-DOWN CURRENT 13.5 VGATE – VOUT VOLTAGE (V) VGATE – VOUT VOLTAGE (V) 4 2 42563 G17 VGATE – VOUT Voltage vs Temperature 14 2.5 13.0 10 6 0 12.5 VCC = 12V 8 VCC = 10.8V 4 2 12.0 VCC = 20V VCC = 80V 11.5 VCC = 48V –25 0 25 50 TEMPERATURE (°C) 75 –100 –25 0 25 50 TEMPERATURE (°C) 75 42563 G06 –140 –50 100 UV Current vs UV Voltage –80 –100 PULL-UP CURRENT –120 –140 10 20 30 50 40 VCC (V) 60 70 80 42563 G09 0.2 5.2 0 5.0 –0.2 4.8 IUV (µA) TIMER SHUTDOWN THRESHOLD (V) 0 100 0.4 5.4 5.0 75 42563 G08 TIMER Shutdown Threshold vs Temperature PULL-DOWN CURRENT 0 25 50 TEMPERATURE (°C) –25 42563 G07 TIMER Currents vs VCC 2.5 PULL-UP CURRENT –120 10.0 –50 100 –80 11.0 10.5 0 –50 ITIMER (µA) 0 42563 G05 42563 G04 12 30 58 ITIMER (µA) GATE PULL-UP CURRENT (µA) GATE Pull-Up Current vs Temperature 4.6 –0.4 –0.6 –0.8 4.4 –1.0 4.2 0 –50 –1.2 –1.4 –25 0 25 50 TEMPERATURE (°C) 75 100 42563 G10 0 1 2 3 4 10 20 30 40 50 VUV (V) 42563 G18 42563f 4 LT4256-3 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at TA = 25°C unless otherwise noted. UV Thresholds vs Temperature OV Current vs OV Voltage OV Thresholds vs Temperature 250 4.1 4.0 200 4.0 3.9 150 4.1 3.8 OV THRESHOLDS (V) IOV (µA) UV THRESHOLDS (V) L-H THRESHOLD 100 50 3.7 0 0 25 50 TEMPERATURE (°C) 75 0 100 5 10 VOV (V) 15 3.7 3.5 –50 20 5.0 9 4.5 6 5 4 3 2 1 75 100 PWRGD Output Voltage vs IPWRGD 6 5 4.0 3.5 4 VCC – VSENSE VPWRGD (V) OPEN THRESHOLD VOLTAGE (mV) 10 7 0 25 50 TEMPERATURE (°C) 42563 G12 OPEN Threshold Voltage vs Temperature OPEN Output Voltage vs IOPEN 8 –25 42563 G19 42563 G11 3.0 2.5 2.0 3 2 1.5 1.0 1 0.5 0 2 4 6 8 IOPEN (mA) 10 0 0 –50 12 –25 75 0 25 50 TEMPERATURE (°C) 42563 G13 0 4 2 6 8 IPWRGD (mA) FB Thresholds vs Temperature 10 12 42563 G15 42563 G14 FB Current vs FB Voltage 0.2 4.5 L-H THRESHOLD 4.4 0.1 0 4.3 –0.1 4.2 –0.2 4.1 H-L THRESHOLD 4.0 3.9 –50 100 IFB (µA) 0 FB THRESHOLDS (V) VOPEN (V) 3.8 3.6 –50 –25 3.9 H-L THRESHOLD H-L THRESHOLD 3.6 3.5 –50 L-H THRESHOLD –0.3 –0.4 –25 0 25 50 TEMPERATURE (°C) 75 100 42563 G16 0 10 20 30 VFB (V) 40 50 42563 G20 42563f 5 LT4256-3 U U U PI FU CTIO S UV (Pin 1): Undervoltage Sense Input. UV is an input that enables the output voltage. When UV is driven above 4V, GATE will start charging and the output turns on. When UV goes below 3.6V, GATE discharges and the output shuts off. Pulsing UV to below 0.4V for at least 5µs after a current limit fault cycle resets the fault latch (when RETRY pin is low, commanding latch off operation) and allows the part to turn back on. This command is only accepted after TIMER is discharged below 0.65V. To disable UV sensing, connect the pin to a voltage between 5V and 44V. OV (Pin 2): Overvoltage Sense Input. OV is an input that disables the output voltage. If OV ever goes above 4V, GATE is discharged and the output shuts off. When OV goes below 3.6V, GATE starts charging and the output turns back on. To disable overvoltage sensing, connect pin to ground. NC (Pins 3, 6, 11, 14): No Connect. Not connected to any internal circuitry. OPEN (Pin 4): Open Circuit Detect Output. This pin is an open collector output that releases and is pulled high through an external resistor if the load current is less than (3mV)/R5. PWRGD (Pin 5): Power Good Output. PWRGD is pulled low whenever the voltage on FB falls below the high-to-low threshold voltage. It goes into a high impedance state when the voltage on FB exceeds the low-to-high threshold voltage. An external pull-up resistor can pull PWRGD to a voltage higher or lower than VCC. RETRY (Pin 7): Current Fault Retry Input. RETRY commands the operational mode of the current limit. If RETRY is floating, the LT4256-3 automatically restarts after a current fault. If it is connected to a voltage below 0.4V, it will latch off after a current fault (which requires that UV be cycled low in order to start normal operation again). GND (Pin 8): Device Ground. This pin must be tied to a ground plane for best performance. TIMER (Pin 9): Timing Input. An external timing capacitor from TIMER to GND programs the maximum time the part is allowed to remain in current limit. When the part goes into current limit, a 115µA pull-up current source starts to charge the timing capacitor. When the voltage on TIMER reaches 4.65V (typ), GATE is pulled low; the TIMER pullup current will be turned off and the capacitor is discharged by a 3µA pull-down current. When TIMER falls below 0.65V (typ), GATE turns on again if RETRY is high (if RETRY is low, UV must be pulsed low to reset the internal fault latch before GATE will turn on). If RETRY is grounded and UV is not cycled low, GATE remains latched off and TIMER will be discharged to near ground. UV must be cycled low after TIMER has discharged below 0.65V (typ) to reset the part. If RETRY is floating or connected to a voltage above its 1.2V threshold, the LT4256-3 automatically restarts after a current fault. Under an output short-circuit condition, the LT4256-3 cycles on and off with a 3% on-time duty cycle. FB (Pin 10): Power Good Comparator Input. FB monitors the output voltage through an external resistive divider. When the voltage on FB is lower than the high-to-low threshold of 3.99V, PWRGD is pulled low and released when FB is pulled above the 4.45V low-to-high threshold. The voltage present on FB affects foldback current limit (see Figure␣ 8 and related discussion). VOUT (Pin 12): Output Voltage Sense Input. This pin should be connected to the source of the external MOSFET. It is used to sense when the MOSFET is shut off (during any fault mode) and to reduce the pull-down current on GATE. This protects the LT4256-3 from excessive power dissipation when large output capacitors are used. 42563f 6 LT4256-3 U U U PI FU CTIO S GATE (Pin 13): High Side Gate Drive for the External N-Channel MOSFET. An internal charge pump guarantees at least 10V of gate drive for VCC supply voltages above 20V and 4.5V of gate drive for VCC supply voltages between 10.8V and 20V. The rising slope of the voltage on GATE is set by an external capacitor connected from GATE to GND and an internal 30µA pull-up current source from the charge pump output. If the current limit is reached, the GATE voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. If the TIMER voltage ever exceeds 4.65V, GATE is pulled low. GATE is also pulled to GND whenever UV is pulled low; the VCC supply voltage drops below the externally programmed undervoltage threshold, above the overvoltage threshold or below the internal UVLO threshold (9.8V). GATE is clamped internally to a maximum voltage of 11.6V (typ) above VOUT under normal operating conditions. Driving this pin beyond the clamp voltage may damage the part. GATE is also clamped to 2V (typ) below VOUT. When the gate is commanded off due to a fault condition, it is discharged quickly by a 62mA (typ) capable switch until GATE is 2V (typ) below VOUT. When GATE is below VOUT by 2V, the 62mA is reduced to 130µA to protect the LT4256-3 against damage if VOUT has large capacitance. A Zener diode is needed between the gate and source of the external MOSFET to protect its gate oxide under instantaneous short-circuit conditions. See Applications Information. SENSE (Pin 15): Current Limit Sense Input. A sense resistor is placed in the supply path between V CC and SENSE. The current limit circuit regulates the voltage across the sense resistor (VCC – SENSE) to 55mV while in current limit when FB is 2V or higher. If FB drops below 2V, the regulated voltage across the sense resistor decreases linearly and stops at 14mV when FB is 0V. The OPEN output also uses SENSE to detect when the output current is less than (3mV)/R5. To defeat current limit, connect SENSE to VCC. VCC (Pin 16): Input Supply Voltage. The positive supply input ranges from 10.8V to 80V for normal operation. ICC is typically 1.8mA. An internal circuit disables the LT4256-3 for inputs less than 9.8V (typ). 42563f 7 LT4256-3 W BLOCK DIAGRA VCC SENSE 16 15 + OPEN CIRCUIT 3mV 4 OPEN – VP VP GEN FB 10 – 14mV TO 55mV CURRENT LIMIT CHARGE PUMP AND GATE DRIVER + + FOLDBACK REF GEN 2V 12 VOUT 13 GATE + – 4V 4V 7V 5 PWRGD 9 TIMER – 100k RETRY 7 UV 1 OV 2 VCC – INTERNAL UV 9.8V + 4V – UV 0.65V LOGIC + + TIMER LOW – VP – 118µA OV + 4V + TIMER HIGH 4.65V – 3µA 8 4256 BD GND 42563f 8 LT4256-3 TEST CIRCUIT PWRGD OPEN 3V –+ 48V VCC +– SENSE FB GATE OV VOUT UV TIMER RETRY GND 100pF 48V +– 3V +– 4256 F01 Figure 1 W UW TI I G DIAGRA S 4V 3.6V UV tPHLUV tPLHUV GATE 2V 2V 4256 F02 Figure 2. UV to GATE Timing 4V 3.65V FB tPLHFB PWRGD 1V tPHLFB 1V 4256 F03 Figure 3. VOUT to PWRGD Timing VCC – SENSE 55mV tPHLSENSE GATE VCC 4256 F04 Figure 4. SENSE to GATE Timing 42563f 9 LT4256-3 U W U U APPLICATIO S I FOR ATIO Hot Circuit Insertion When the power pins first make contact, transistor Q1 is held off. If the voltage on VCC is between the externally programmed undervoltage and overvoltage thresholds, VCC is above 9.8V and the voltage on TIMER is less than 4.65V (typ), transistor Q1 will be turned on (Figure 6). The voltage on GATE rises with a slope equal to 30µA/C1 and the supply inrush current is set at: When circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. The transient currents can permanently damage the connector pins and glitch the system supply, causing other boards in the system to reset. IINRUSH = CL • 30µA/C1 The LT4256-3 is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage and overvoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. where CL is the total load capacitance. IOUT 500mA/DIV PWRGD 50V/DIV Power-Up Sequence An external N-channel MOSFET pass transistor (Q1) is placed in the power path to control the power up of the supply voltage (Figure 5). Resistor R5 provides current detection and capacitor C1 controls the GATE slew rate. Resistor R7 compensates the current control loop while R6 prevents high frequency oscillations in Q1. VOUT 50V/DIV GATE 50V/DIV (SHORT PIN) Figure 6. Start-Up Waveforms Q1 IRF530 R1 64.9k VCC 1 15 SENSE GATE UV 13 LT4256-3 C3 0.01µF R2 4.02k 2 OV R3 4.02k VOUT FB 4 9 C2 33nF OPEN TIMER RETRY PWRGD GND 8 + D1 CMPZ5241BS 11V D2 SMAT70A 16 4256 F06 5ms/DIV R5 0.025Ω VIN 48V GND (1) 12 CL VOUT 48V 1.6A R8 36.5k R6 10Ω R7 100Ω C1 10nF R4 51k 10 R9 4.02k 7 5 PWRGD 4256 F05 UV = 36V OV = 73V PWRGD = 40V Figure 5. 1.6A, 48V Latchoff Application 42563f 10 LT4256-3 U W U U APPLICATIO S I FOR ATIO To reduce inrush current, increase C1 or decrease load capacitance. If the voltage across the current sense resistor R5 reaches VSENSETRIP, the inrush current will be limited by the internal current limit circuitry. The voltage on GATE is adjusted to maintain a constant voltage across the sense resistor and TIMER begins to charge. noise spikes and capacitively coupled glitches from shutting down the LT4256-3 output erroneously. To calculate UV and OV thresholds, use the following equations: When the FB voltage goes above the low-to-high VFB threshold, PWRGD goes high. Undervoltage and Overvoltage Detection The LT4256-3 uses UV and OV to monitor the VCC voltage to determine when it is safe to turn on the load and allow the user the greatest flexibility for setting the operational thresholds. UV and OV are internally connected to an analog window comparator. Any time that UV goes below 3.6V or OV goes above 4V, GATE will be pulled low until the UV/OV voltages return to the normal operation voltage window (4V and 3.6V, respectively). (4) VCC 1 C3 0.01µF Q1 IRF540 SENSE 13 2 OV VOUT FB 4 9 C2 33nF OPEN TIMER R6 10Ω VOUT 48V 4A + CL R8 36.5k R7 100Ω LT4256-3 R2 4.02k R3 4.02k D1 CMPZ5241BS 11V 15 GATE UV (3) Figure 7 shows how the LT4256-3 is commanded to shut off with a logic signal. This is accomplished by pulling the gate of the open-drain MOSFET, Q2, (tied to UV) high. 16 R1 64.9k (2b) where VTHULH and VTHOVLH are the desired UV and OV threshold voltages when VCC is rising (L – H). D2 SMAT70A (SHORT PIN) GND R1 VTHUVHL = 3.6 V 1 + ; R2 + R3 R5 0.010Ω VCC 48V Q2 VN2222 (2a) R1 + R2 VTHOVHL = 3.6 V 1 + R3 The UV threshold should never be set below the internal UVLO threshold (9.8V typically) because the benefit of the UV’s hysteresis will be lost, making the LT4256-3 more susceptible to noise (VCC must be at least 9.8V when UV is at its 3.6V threshold). UV is filtered with C3 to prevent OFF SIGNAL FROM MPU V R1 = (R2 + R3) THUVLH – 1 4V R1 + R2 R3 = VTHOVLH –1 4 20kΩ ≤ R1 + R2 + R3 ≤ 200kΩ RETRY PWRGD GND 8 12 C1 10nF 10 R9 4.02k 7 R4 51k 5 4256 F07 UV = 36V OV = 73V PWRGD = 40V Figure 7. How to Use a Logic Signal to Control the LT4256-3 Turn On/Off 42563f 11 LT4256-3 U U W U APPLICATIO S I FOR ATIO Short-Circuit Protection The LT4256-3 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. The current limit is set by placing a sense resistor (R5) between VCC and SENSE. The current limit threshold is calculated as: ILIMIT = 55mV/R5 (5) To limit excessive power dissipation in the pass transistor and to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed internally on FB. If the LT4256-3 goes into current limit when the voltage on FB is 0V, the current limit circuit drives GATE to force a constant 14mV drop across the sense resistor. As the output at FB increases, the voltage across the sense resistor increases until FB reaches 2V, at which point the voltage across the sense resistor is held constant at 55mV (see Figure 8). For a 0.025Ω sense resistor, the typical current limit is set at 2200mA and folds back to 560mA when the output is shorted to ground. Thus, MOSFET peak power dissipation under short-circuit conditions is reduced from 106W to 27W. See the Layout Considerations section for important information about board layout to minimize current limit threshold error. The LT4256-3 also features a variable overcurrent response time. The time required for the part to regulate the GATE voltage is a function of the voltage across the sense resistor connected between VCC and SENSE. This helps to eliminate sensitivity to current spikes and transients that might otherwise unnecessarily trigger a current limit response and increase MOSFET dissipation. Figure 9 shows the response time as a function of the overdrive at SENSE. VCC – VSENSE RESPONSE TIME (µs) 12 55mV 10 8 6 4 2 14mV 0V 2V FB 4256 F08 Figure 8. Current Limit Sense Voltage vs Feedback Pin Voltage 0 50 100 150 VCC – VSENSE (mV) 200 4256 F09 Figure 9. Response Time to Overcurrent 42563f 12 LT4256-3 U W U U APPLICATIO S I FOR ATIO TIMER TIMER provides a method for programming the maximum time the part is allowed to operate in current limit. When the current limit circuitry is not active, TIMER is pulled to GND by a 3µA current source. When the current limit circuitry becomes active, a 118µA pull-up current source is connected to TIMER and the voltage will rise with a slope equal to 115µA/CTIMER as long as the circuitry stays active. Once the desired maximum current limit time is known, the capacitor value is: C[nF ] = 25 • t[ms]; C = 115µA •t 4.65V (6) Whenever TIMER reaches 4.65V (typ), the internal fault latch is set causing GATE to be pulled low and TIMER to be discharged to GND by the 3µA current source. The part is not allowed to turn on again until the voltage on TIMER falls below 0.65V (typ). Whenever GATE is commanded off by any fault condition, it is discharged with a high current, turning off the external MOSFET. The waveform in Figure 10 shows how the output latches off following a current fault. The drop across the sense resistor is held at 55mV as the timer ramps up. Once TIMER reaches its shutdown threshold (4.65V typically), the circuit latches off. Automatic Restart If RETRY is floating, then the device automatically restarts after a current overload fault. When the voltage at TIMER ramps back down to 0.65V (typ), the LT4256-3 turns on again. If the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. The duty cycle under short-circuit conditions is 3% which prevents Q1 from overheating. Figure␣ 11 shows representative waveforms during a short circuit. Latch Off Operation ␣ If RETRY is grounded, the LT4256-3 will latch off after a current fault. After the part latches off, it may be commanded to start back up. This is accomplished by cycling UV to ground and then back high (this command can only be accepted after TIMER discharges below the 0.65V typ threshold, which prevents overheating transistor Q1). IOUT 500mA/DIV IOUT 500mA/DIV TIMER 5V/DIV TIMER 5V/DIV VOUT 50V/DIV VOUT 50V/DIV GATE 50V/DIV GATE 50V/DIV 10ms/DIV Figure 10. Latch Off Waveforms 4256 F10 10ms/DIV 4256 F11 Figure 11. RETRY Waveforms 42563f 13 LT4256-3 U U W U APPLICATIO S I FOR ATIO Therefore, using RETRY only, the LT4256-3 will either latch off after an overcurrent fault condition or it will go into a hiccup mode. V R8 = THPWRGD – 1 • R9, high to low 3.99 V 20kΩ ≤ R8 + R9 ≤ 200kΩ Power Good Detection R8 VTHPWRGD = 4.45V 1+ , low to high R9 The LT4256-3 includes a comparator for monitoring the output voltage. The output voltage is sensed through the FB pin via an external resistor string. The comparator’s output (PWRGD) is an open collector capable of operating from a pull-up as high as 80V. Open-circuit MOSFETs are detected with the LT4256-3 by monitoring the voltage across R5 with OPEN while monitoring the output voltage with PWRGD. An open FET condition is signalled when OPEN is high and PWRGD is low (after the part has completed its start-up cycle). R5 100mΩ Q1 IRFZ34VS VCC R1 32.4k 1 C3 0.01µF R3 4.02k 15 SENSE GATE UV R2 4.02k 13 4 9 C2 33nF VOUT OV OPEN TIMER R6 10Ω FB RETRY PWRGD GND 8 12 CL VLOGIC C1 10nF R8 14k 10 7 VOUT 24V 400mA + R10 51k R7 100Ω LT4256-3 2 GND D1 CMPZ5241BS 11V D2 SMAT70A 16 (8b) OPEN is an output which signals abnormally low load currents. When the voltage across the sense resistor is less than 3mV, the open collector pull-down device is shut off allowing OPEN to be externally pulled high. OPEN is always active when VCC is above 9.8V. If VCC is below 9.8V (the internal UVLO threshold), OPEN is pulled low. The thresholds for the FB pin are 4.45V (low to high) and 3.99V (high to low). To calculate the PWRGD thresholds, use the following equations: (SHORT PIN) (8a) OPEN Pin/Open FET Detection PWRGD can be used to directly enable/disable a power module with an active high enable input. Figure␣ 12 shows how to use PWRGD to control an active low enable input power module. Signal inversion is accomplished by transistor Q2 and R10. VCC 24V (7) R9 4.02k PWRGD R4 27k 5 UV = 20V OV = 40V PWRGD = 18V Q2 ZN3904 4256 F12 Figure 12. Active Low Enable PWRGD Application 42563f 14 LT4256-3 U U W U APPLICATIO S I FOR ATIO This open FET condition can be falsely signalled during start-up if the load is not activated until after PWRGD goes high. To avoid this false indication, OPEN and PWRGD should not be polled for a period of time, tSTARTUP, given by: tSTARTUP = 3 • VCC • C1 30µA (9) This can be accomplished either by a microcontroller (if available) or by placing an RC filter as shown in Figure 13. Once the OPEN voltage exceeds the monitoring logic threshold, VTHRESH, and PWRGD is low, an open FET condition is signalled. In order to prevent a false indication, the RC product should be set with the following equation: RC > 3 • VCC • C1 VLOGIC 30µAln VLOGIC – VTHRESH (10) Another condition that can cause a false indication is if the LT4256-3 goes into current limit during start-up. This will cause tSTARTUP to be longer than calculated. Also, if the LT4256-3 stays in current limit long enough for TIMER to fully charge up to its threshold, the LT4256-3 will either latch off (RETRY = 0) or go into the current limit hiccup mode (RETRY = floating). In either case, an open FET condition will be falsely signalled. If the LT4256-3 does go into current limit during start-up, C1 can be increased (see Power-Up Sequence). Supply Transient Protection The LT4256-3 is 100% tested and guaranteed to be safe from damage with supply voltages up to 80V. However, voltage transients above 100V may cause permanent damage. During a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed 100V. To minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a bypass capacitor should be placed between VCC and GND. A surge suppressor (TransZorb®) at the input can also prevent damage from voltage transients. GATE Pin A curve of gate drive vs VCC is shown in Figure 14. GATE is clamped to a maximum voltage of 12.8V above VOUT. This clamp is designed to withstand the internal charge pump current. An external Zener diode must be used as shown in all applications. At a minimum input supply voltage of 10.8V, the minimum gate drive voltage is 4.5V. When the input supply voltage is higher than 20V, the gate drive voltage is at least 10V and a standard threshold MOSFET can be used. In applications from 12V to 15V range, a logic level MOSFET must be used. TransZorb is a registered trademark of General Instruments, GSI. 13 12 11 ∆VGATE (V) 10 VLOGIC OPEN INTERNAL OPEN COLLECTOR PULL-DOWN 8 7 6 R LT4256-3 9 TO MONITORING LOGIC 4 C 5 4 3 10 4256 F13 20 30 50 40 VCC (V) 60 70 80 4256 F14 Figure 13. Delay Circuit for OPEN FET Detection Figure 14. ∆VGATE vs VCC 42563f 15 LT4256-3 U U W U APPLICATIO S I FOR ATIO In some applications it may be possible for VOUT to ring below ground (due to the parasitic trace inductance). Higher current applications, especially where the output load is physically far away from the LT4256-3 will be more susceptible to these transients. This is normal and the LT4256-3 has been designed to allow for some ringing below ground. However, if the application is such that VOUT can ring more than 3V below ground, damage may occur to the LT4256-3 and an external diode, D2, from ground (anode) to VOUT (cathode) will have to be added to the circuit as shown in Figure 15 (it is critical that the reverse breakdown voltage of the diode be higher than the highest expected VCC voltage). A capacitor placed from ground to VOUT directly at the LT4256-3 pins can help reduce the amount of ringing on VOUT but it may not be enough for some applications. LT4256-3 becomes active and pulls down on GATE). This is due to the MOSFET intrinsic drain to gate capacitance forcing current into R7 and C1 when the drain voltage steps up from ground to VCC with an extremely fast rise time. To alleviate this situation, a diode, D3, should be put across R7 with the cathode connected to C1 as shown in Figure 16. Whenever the LT4256-3 turns the MOSFET off, GATE pulls the MOSFET gate to ground with an open collector capable of sinking 62mA. If the output is held up by a large reservoir capacitor, the stored energy is dissipated in the pull-down transistor via a sneak path through the (now forward biased) Zener, D1. The LT4256-3 has a proprietary feature that reduces on-chip power dissipation by sensing when the MOSFET is off and reducing the pulldown current significantly. See VGATE Turn-Off for more information about using this feature. During a fault condition, the LT4256-3 pulls down on GATE with a switch capable of sinking about 62mA. Once GATE drops below the output voltage by a diode forward voltage, the external Zener will forward bias and VOUT will also be discharged to GND. In addition to the GATE capacitance, the output capacitance will be discharged through the LT4256-3. VGATE Turn-Off The LT4256-3 has a proprietary feature that reduces power dissipation by sensing when the MOSFET is off and reducing the pull-down current significantly. As the GATE pin is discharged during any fault, the LT4256-3 monitors the GATE pin and VOUT pin. When the GATE pin is 2V below VOUT, the pull-down current is reduced from 62mA to about 130µA. In applications utilizing very large external N-channel MOSFETs, the possibility exists for the MOSFET to turn on when initially inserted into a live backplane (before the Q1 IRF540 R5 0.010Ω VCC 48V (SHORT PIN) 16 VCC R1 64.9k 1 C3 0.01µF 15 SENSE GATE UV 4 9 GND C2 33nF OV OPEN TIMER R6 10Ω CL R8 36.5k D3 MRA4003T3 R7 100Ω VOUT 2 R3 4.02k 13 LT4256-3 R2 4.02k + D1 CMPZ5241BS 11V D2 SMAT70A FB RETRY PWRGD GND 8 12 VOUT 48V 4A C1 10nF 10 R9 4.02k 7 R4 51k 5 4256 F14 UV = 36V OV = 73V PWRGD = 40V Figure 15. Negative Output Voltage Protection Diode Application 42563f 16 LT4256-3 U U W U APPLICATIO S I FOR ATIO In order to use this feature as designed, a bidirectional Zener diode is needed for D1. When the LT4256-3 commands the MOSFET off (and a bidirectional Zener is used), the output discharges very slowly (tOFF = (CLOAD • VOUT)/ 130µA). Several variations can be implemented to discharge the output faster. The recommeded method is shown in Figure 17 and uses an external PNP transistor, diode and resistor to discharge the output quickly. The equation to set the nominal discharge current is: 5000 (130µA) RPROG where RPROG must be less than 1k. IDISCHG = The maximum current equation is: IMAX = D2 SMAT70A (SHORT PIN) 16 1 C3 0.1µF SENSE GATE UV R2 4.02k FB 4 9 C2 33nF GND R7 100Ω VOUT OV R3 4.02k OPEN TIMER RETRY PWRGD GND 8 CL R6 10Ω 13 LT4256-3 2 (12) + D1 CMPZ5241BS 11V 15 VCC R1 64.9k 7000 (350µA) RPROG Q1 IRF530 R5 0.033Ω VCC 48V (11) VOUT 48V 1.2A R8 36.5k D3 1N4148W C1 10nF 12 10 R4 27k R9 4.02k 7 5 4256 F16 UV = 36V OV = 73V PWRGD = 40V Figure 16. High dV/dt MOSFET Turn-On Protection Circuit Q1 IRF540 R5 0.010Ω VCC 48V (SHORT PIN) D2 SMAT70A 16 R1 64.9k VCC 1 C3 0.01µF 15 GATE UV 13 2 OV VOUT FB 4 9 C2 33nF OPEN TIMER + RPROG CL Q2 2N4920 R7 100Ω LT4256-3 R2 4.02k R3 4.02k GND R6 1k SENSE D1 CMPZ5241BS 11V RB 18k D3 1N4148 VOUT 48V 4A RETRY PWRGD GND 8 12 C1 10nF 10 R8 36.5k 7 R9 4.02k R4 51k 5 4256 F17 UV = 36V OV = 73V PWRGD = 40V Figure 17. Enhanced Output Pull-Down Circuit 42563f 17 LT4256-3 U U W U APPLICATIO S I FOR ATIO Layout Considerations To achieve accurate current sensing, a Kelvin connection to the current sense resistor (R5 in typical application circuit) is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µΩ/o. Small resistances can cause large errors in high current applications. Noise immunity will be improved significantly by locating resistor dividers close to the pins with short VCC and GND traces. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. Figure 18 shows a layout that meets these requirements. D1 Q1 VIN R6 R5 R1 D2 VOUT R7 R2 LT4256-3 R3 R8 R9 GND C1 42563 F18 Figure 18. Recommended Component Placement 42563f 18 LT4256-3 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .0532 – .0688 (1.35 – 1.75) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 42563f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT4256-3 U U W U APPLICATIO S I FOR ATIO Dual 48V Supply Sequencing Application R5 0.020Ω Q2 IRF540 + D3 CMPZ5241BS 11V R1 64.9k VCC C1 R7 10nF 100Ω R6 10Ω GATE LT4256-3 VOUT UV C3 0.01µF SENSE R2 4.02k CL2 R8 36.5k VOUT2 48V 2A R4 51k R9 4.02k FB VIN 50V/DIV OV R3 4.02k OPEN PWRGD TIMER RETRY GND 33nF R5 0.020Ω VIN 48V UV R2 4.02k + D1 CMPZ5241BS 11V VCC R1 64.9k VOUT1 50V/DIV Q1 IRF540 D2 SMAT70A (SHORT PIN) C3 0.01µF PWRGD2 UV = 36V OV = 73V PWRGD = 40V SENSE C1 R7 10nF 100Ω R6 10Ω GATE LT4256-3 VOUT CL1 R8 36.5k VOUT1 48V 2A R4 51k PWRGD1 50V/DIV VOUT2 50V/DIV 5ms/DIV R9 4.02k 4256 TA04 FB OV R3 4.02k OPEN PWRGD TIMER RETRY PWRGD1 4256 TA03 C2 33nF GND UV = 36V OV = 73V PWRGD = 40V GND RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1641-1/LT1641-2 Positive 48V Hot Swap Controller in SO-8 9V to 80V Operation, Active Current Limit, Autoretry/Latchoff LTC4211 Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Active Inrush Limiting, Dual Level Cicuit Breaker LTC4251 – 48V Hot Swap Controller in SOT-23 Floating Supply from –15V, Active Current Limiting, Fast Circuit Breaker LTC4252-1/LTC4252-2 – 48V Hot Swap Controller in MSOP Floating Supply from –15V, Active Current Limiting, Power Good Output LTC4253 – 48V Hot Swap Controller and Supply Sequencer Floating Supply from –15V, Active Current Limiting, Enables Three DC/DC Converters LT4254 Positive High Voltage Hot Swap Controller 10.8V to 36V Operation, Open-Circuit Detection LT4256-1/LT4256-2 Positive High Voltage Hot Swap Controller 10.8V to 80V Operation, Active Current Limit, Autoretry/Latchoff 42563f 20 Linear Technology Corporation LT/TP 0304 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2004