MAXIM MAX5949AESA+

19-3494; Rev 1; 8/11
-48V Hot-Swap Controllers
with External RSENSE
The MAX5949A/MAX5949B are hot-swap controllers that
allow a circuit card to be safely hot plugged into a live
backplane. The MAX5949A/MAX5949B operate from
-20V to -80V and are well-suited for -48V power systems.
These devices are pin and function compatible with the
LT4250 and pin compatible with the LT1640.
The MAX5949A/MAX5949B provide a controlled turn-on
to circuit cards preventing glitches on the power-supply
rail and damage to board connectors and components.
The MAX5949A/MAX5949B provide undervoltage, overvoltage, and overcurrent protection. These devices
ensure the input voltage is stable and within tolerance
before applying power to the load.
Both the MAX5949A and MAX5949B protect a system
against overcurrent and short-circuit conditions by turning off the external MOSFET in the event of a fault condition. The MAX5949A/MAX5949B also provide
protection against input voltage steps. During an input
voltage step, the MAX5949A/MAX5949B limit the current drawn by the load to a safe level without turning off
power to the load.
Both devices feature an open-drain power-good status
output (PWRGD for the MAX5949A or PWRGD for the
MAX5949B) that can be used to enable downstream
converters.
The MAX5949A/MAX5949B are available in an 8-pin SO
package. Both devices are specified for the extended
-40°C to +85°C temperature range.
Applications
Features
o Allow Safe Board Insertion and Removal
from a Live -48V Backplane
o Pin and Function Compatible with LT4250L
(MAX5949A)
o Pin Compatible with LT1640L (MAX5949A)
o Pin and Function Compatible with LT4250H
(MAX5949B)
o Pin Compatible with LT1640H (MAX5949B)
o Circuit-Breaker Immunity to Input Voltage Steps
and Current Spikes
o Withstand -100V Input Transients with No
External Components
o Programmable Inrush and Short-Circuit Current
Limits
o Operate from -20V to -80V
o Programmable Overvoltage Protection
o Programmable Undervoltage Lockout
o Power Up into a Shorted Load
o Power-Good Control Output
Ordering Information
TEMP RANGE
PIN-PACKAGE
Telecom Line Cards
MAX5949AESA+
-40°C to +85°C
8 SO
Network Switches/Routers
MAX5949BESA+
-40°C to +85°C
8 SO
Central-Office Line Cards
PART
+Denotes a lead(Pb)-free/RoHS-compliant package.
Server Line Cards
Pin Configuration
Base-Station Line Cards
Central-Office Switching
TOP VIEW
-48V Distributed Power Systems
Negative Power-Supply Controls
1
OV
2
UV
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
+
PWRGD
(PWRGD)
3
MAX5949A
MAX5949B
VEE 4
8
VDD
7
DRAIN
6
GATE
5
SENSE
SO
( ) FOR MAX5949B.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX5949A/MAX5949B
General Description
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
ABSOLUTE MAXIMUM RATINGS
(All voltages are referenced to VEE, unless otherwise noted.)
Supply Voltage (VDD - VEE ) .................................-0.3V to +100V
PWRGD, PWRGD .................................................-0.3V to +100V
DRAIN (Note 1)........................................................-2V to +100V
PWRGD to DRAIN .............................................… -0.3V to +95V
PWRGD to VDD ........................................................-95V to +85V
SENSE (Internally Clamped) .................................-0.3V to +1.0V
GATE (Internally Clamped) ....................................-0.3V to +18V
UV and OV..............................................................-0.3V to +60V
Note 1:
Current Through SENSE ...................................................±40mA
Current into GATE...........................................................±300mA
Current into DRAIN .........................................-100mA to +20mA
Current into Any Other Pin................................................±20mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Test condition per Figure 1. DRAIN current must be limited to the specified 100mA maximum.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = 0V, VDD = 48V, TA = -40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) (Notes 2, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Operating Input Voltage Range
VDD
Supply Current
IDD
20
(Note 3)
80
V
0.7
2
mA
GATE DRIVE AND CLAMPING CIRCUITS
GATE Pin Pullup Current
IPU
Gate drive on, VGATE = VEE
-30
-45
-60
µA
GATE Pin Pulldown Current
IPD
Gate drive off, VGATE = 2V, TA = +25°C
24
50
70
mA
VGATE - VEE, 20V ≤ VDD ≤ 80V
10
13.5
18
V
VGATE - VEE, IGS = 30mA
15
16.4
18
V
External Gate Drive
GATE to VEE Clamp Voltage
∆VGATE
VGSCLMP
CIRCUIT BREAKER
Current-Limit Trip Voltage
VCL
VCL = VSENSE - VEE
40
50
60
mV
SENSE Input Bias Current
ISENSE
VSENSE = 50mV
0
-0.2
-2
µA
Internal Undervoltage-Lockout
Voltage High
VUVLOH
VDD increasing
13.8
15.4
17.0
V
Internal Undervoltage-Lockout
Voltage Low
VUVLOL
VDD decreasing
11.8
13.4
15.0
V
VUVH
UV voltage increasing
1.240
1.255
1.270
V
VUVL
UV voltage decreasing
1.105
1.125
1.145
UNDERVOLTAGE LOCKOUT
UV PIN
UV High Threshold
UV Low Threshold
UV Hysteresis
UV Input Bias Current
VUVHY
130
IINUV
VUV = VEE
OV High Threshold
VOVH
OV voltage increasing
OV Low Threshold
VOVL
OV voltage decreasing
V
mV
0
-0.5
µA
1.235
1.255
1.275
V
1.210
1.235
1.255
V
OV PIN
OV Hysteresis
OV Input Bias Current
2
VOVHY
IINOV
20
VOV = VEE
0
_______________________________________________________________________________________
mV
-0.5
µA
-48V Hot-Swap Controllers
with External RSENSE
(VEE = 0V, VDD = 48V, TA = -40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) (Notes 2, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDRAIN = 48V
10
80
250
µA
1.1
1.4
2.0
V
1.0
1.4
2.0
V
10
µA
PWRGD OUTPUT SIGNAL REFERENCED TO DRAIN
DRAIN Input Bias Current
IDRAIN
DRAIN Threshold for Power-Good
VDL
VDRAIN - VEE threshold for power-good
condition, DRAIN decreasing
GATE High Threshold
VGH
∆VGATE - VGATE threshold for power-good
condition, ∆VGATE - VGATE decreasing
PWRGD, PWRGD Output
Leakage
IOH
PWRGD (MAX5949A) = 80V, VDRAIN = 48V,
PWRGD (MAX5949B) = 80V, VDRAIN = 0V
PWRGD Output Low Voltage
VOL
V PWRGD - VEE; VDRAIN - VEE < VDL,
ISINK = 5mA (MAX5949A)
0.11
0.4
V
PWRGD Output Low Voltage
VOL
VPWRGD - VDRAIN; VDRAIN = 5V,
ISINK = 1mA (MAX5949B)
0.11
0.4
V
AC PARAMETERS
OV High to GATE Low
tPHLOV
Figures 2a, 3
0.5
µs
UV Low to GATE Low
tPHLUV
Figures 2a, 4
0.4
µs
OV Low to GATE High
tPLHOV
Figures 2a, 3
4
µs
UV High to GATE High
tPLHVL
Figures 2a, 4
5.5
SENSE High to GATE Low
tPHLSENSE
Figures 2a, 5a
1
3
µs
Current Limit to GATE Low
tPHLCB
Figures 2b, 5b
500
650
µs
DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD - DRAIN)
High
tPHLDL
GATE High to PWRGD Low
GATE High to (PWRGD - DRAIN)
High
tPHLGH
350
MAX5949A, Figures 2a, 6a
1.8
MAX5949B, Figures 2a, 6a
3.4
MAX5949A, Figures 2a, 6b
1.6
MAX5949B, Figures 2a, 6b
2.5
µs
µs
µs
TURN-OFF
Latch-Off Period
Note 2:
Note 3:
Note 4:
Note 5:
tOFF
(Note 4)
51
64
78
ms
All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE,
unless otherwise specified.
Current into VDD with UV = 3V, OV = DRAIN = PWRGD = SENSE = VEE, GATE = open.
Minimum duration of GATE pulldown following a circuit-breaker fault. The circuit breaker can be reset during this time by
toggling UV low, but the GATE pulldown does not release until tOFF has elapsed.
Limits are 100% tested at TA = +25°C and +85°C. Limits at -40°C are guaranteed by design.
_______________________________________________________________________________________
3
MAX5949A/MAX5949B
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VDD = 48V, VEE = 0V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
14
600
500
TA = -40°C
400
300
53
13
TA = -45°C
52
TA = +25°C
TRIP VOLTAGE (mV)
GATE VOLTAGE (V)
700
TA = +85°C
MAX5949 toc03
15
MAX5949 toc02
TA = +25°C
TA = +85°C
800
CURRENT-LIMIT TRIP VOLTAGE
vs. TEMPERATURE
GATE VOLTAGE vs. SUPPLY VOLTAGE
MAX5949 toc01
900
SUPPLY CURRENT (µA)
12
11
51
50
49
10
48
9
47
200
100
0
46
8
20
40
60
80
100
20
0
SUPPLY VOLTAGE (V)
40
60
80
44.6
44.4
44.2
44.0
43.8
43.6
43.4
70
43.0
55
50
45
40
35
25
-15
10
35
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
PWRGD OUTPUT LOW VOLTAGE
vs. TEMPERATURE (MAX5949A)
PWRGD OUTPUT IMPEDANCE
vs. TEMPERATURE (MAX5949B)
IOUT = 1mA
OUTPUT IMPEDANCE (GΩ)
40
10,000
35
30
25
20
15
10
85
MAX5949 toc07
MAX5920 toc06
-40
45
60
30
43.2
50
VGATE = 2V
65
GATE PULLDOWN CURRENT (mA)
VGATE = 0V
35
GATE PULLDOWN CURRENT
vs. TEMPERATURE
MAX5949 toc04
GATE PULLUP CURRENT (µA)
44.8
10
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
GATE PULLUP CURRENT
vs. TEMPERATURE
45.0
-15
-40
100
MAX5949 toc05
0
PWRGD OUTPUT LOW VOLTAGE (mV)
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
1000
100
10
5
0
1
-40
-15
10
35
TEMPERATURE (°C)
4
60
85
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
-48V Hot-Swap Controllers
with External RSENSE
R
5kΩ
V+
5V
PWRGD/PWRGD
VDD
VDD
UV
VEE
SENSE
GATE
48V
VOV
MAX5949_
OV
VS
DRAIN
OV
PWRGD/PWRGD
MAX5949A
MAX5949B
DRAIN
VUV
100mA MAX
VDRAIN
UV
GATE
VEE
SENSE
TEST VOLTAGE
2V
VSENSE
Figure 2a. Test Circuit 1
Figure 1. -2V DRAIN Voltage Test Circuit
PWRGD/PWRGD
VDD
DRAIN
OV
VS
48V
VS
20V
10kΩ
UV
MAX5949A
MAX5949B
10Ω
GATE
0.1µF
N
IRF530
VUV
VEE
SENSE
10Ω
Figure 2b. Test Circuit 2
_______________________________________________________________________________________
5
MAX5949A/MAX5949B
Test Circuits
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
Timing Diagrams
2V
2V
1.255V
1.235V
OV
1.255V
1.125V
UV
0V
tPLHUV
tPHLUV
0V
tPHLOV
tPLHOV
GATE
GATE
Figure 3. OV to GATE Timing
100mV
1V
1V
1V
1V
Figure 4. UV to GATE Timing
60mV
UV
SENSE
tPHLCB
VEE
tPHLSENSE
GATE
GATE
1V
50mV
1V
SENSE
Figure 5a. SENSE to GATE Timing
6
Figure 5b. Active Current-Limit Threshold
_______________________________________________________________________________________
1V
-48V Hot-Swap Controllers
with External RSENSE
1.4V
DRAIN
1.4V
∆VGATE - VGATE = 0V
GATE
VEE
tPHLDL
tPHLGH
PWRGD
1V
PWRGD
VEE
1V
VEE
1.4V
DRAIN
∆VGATE - VGATE = 0V
1.4V
GATE
VEE
tPHLDL
VEE
tPHLGH
PWRGD
PWRGD
1V
VPWRGD - VDRAIN = 0V
1V
VPWRGD - VDRAIN = 0V
Figure 6a. DRAIN to PWRGD/PWRGD Timing
Figure 6b. GATE to PWRGD/PWRGD Timing
Block Diagram
VDD
UVLO
VCC AND
REFERENCE
GENERATOR
UV
MAX5949A
MAX5949B
VCC
REF
PWRGD
PWRGD
OUTPUT DRIVE
REF
LOGIC
500µs
DELAY
OV
GATE
DRIVER
50mV
VGH
VDL
∆VGATE
VEE
VEE
SENSE
GATE
DRAIN
_______________________________________________________________________________________
7
MAX5949A/MAX5949B
Timing Diagrams (continued)
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
Pin Description
PIN
MAX5949A MAX5949B
1
—
NAME
FUNCTION
PWRGD
Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced
to VEE. PWRGD is latched low when VDRAIN - VEE ≤ VDL and VGATE > (∆VGATE - VGH),
indicating a power-good condition. PWRGD is open drain otherwise.
—
1
PWRGD
Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced
to DRAIN. PWRGD latches in a high-impedance state when VDRAIN - VEE ≤ VDL and
VGATE > (∆VGATE - VGH), indicating a power-good condition. PWRGD is pulled low to
DRAIN otherwise.
2
2
OV
Input Pin for Overvoltage Detection. OV is referenced to VEE. When OV is pulled above the
VOVH voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the
OV pin voltage reduces to VOVL.
3
3
UV
4
4
VEE
Input Pin for Undervoltage Detection. UV is referenced to VEE. When UV is pulled above the
VUVH voltage, the GATE is enabled. When UV is pulled below VUVL, GATE is pulled low.
UV is also used to reset the circuit breaker after a fault condition. To reset the circuit
breaker, pull UV below VUVL. The reset command can be issued immediately after a fault
condition; however, the device does not restart until a tOFF delay time has elapsed after
the fault.
Device Negative Power-Supply Input. Connect to the negative power-supply rail.
5
5
SENSE
Current-Sense Voltage Input. Connect to an external sense resistor and the external
MOSFET source. The voltage drop across the external sense resistor is monitored to detect
overcurrent or short-circuit fault conditions. Connect SENSE to VEE to disable the currentlimiting feature.
6
6
GATE
Gate-Drive Output. Connect to the gate of the external n-channel MOSFET.
7
7
DRAIN
Output-Voltage Sense Input. Connect to the output-voltage node (drain of the external
n-channel MOSFET).
8
8
VDD
Positive Power-Supply Rail Input. This is the power ground in the negative-supply voltage
system. Connect to the higher potential of the power-supply inputs.
Detailed Description
The MAX5949A/MAX5949B are integrated hot-swap
controllers for -48V power systems. They allow circuit
boards to be safely hot plugged into a live backplane
without causing a glitch on the power-supply rail. When
circuit boards are inserted into a live backplane without
hot-swap control, the bypass capacitors at the input of
the board’s power module or switching power supply
can draw large inrush currents as they charge. The
inrush currents can cause glitches on the system
power-supply rail and damage components on the
board.
8
The MAX5949A/MAX5949B provide a controlled turn-on
to circuit cards, preventing glitches on the power-supply
rail and damage to board connectors and components.
Both the MAX5949A and MAX5949B provide undervoltage, overvoltage, and overcurrent protection. The
MAX5949A/MAX5949B ensure the input voltage is stable and within tolerance before applying power to the
load. The devices also provide protection against input
voltage steps. During an input voltage step, the
MAX5949A/MAX5949B limit the current drawn by the
load to a safe level without turning off power to the load.
_______________________________________________________________________________________
-48V Hot-Swap Controllers
with External RSENSE
Capacitor C2 provides a feedback signal to accurately
limit the inrush current. The value of C 2 can be
calculated:
I
x CL
C2 = PU
IINRUSH
where CL is the total load capacitance, C3 + C4, and
IPU is the MAX5949_ gate pullup current.
Figure 7b shows the inrush current waveform. The current through C2 controls the GATE voltage. At the end
of the DRAIN ramp, the GATE voltage is charged to its
final value. The GATE-to-SENSE clamp limits the maximum VGS to about 18V under any condition.
Power-Supply Ramping
Board Removal
The MAX5949_ can reside either on the backplane or
the removable circuit board (Figure 7a). Power is delivered to the load by placing an external n-channel
MOSFET pass transistor in the power-supply path.
If the card is removed from a live backplane, the output
capacitor on the card may not be immediately discharged. While the output capacitor is discharging, the
MAX5949_ continues to operate as if the input supply
were still connected because the output capacitor temporarily supplies operating current to the IC. If the circuit is connected as in Figure 7a, the voltage at the UV
pin falls below the VUVL, and the MAX5949_ turns off
the external MOSFET. If R4 in the circuit is connected
directly to the -48V return, the external MOSFET
remains on until the capacitor is discharged sufficiently
to drop the UV pin voltage to VUVL.
After the circuit board is inserted into the backplane
and the supply voltage at VEE is stable and within the
undervoltage and overvoltage tolerance, the MAX5949_
turn on Q1. The MAX5949_ gradually turn on the external MOSFET by charging the gate of Q1 with a 45µA
current source.
-48V RTN
(SHORT PIN)
-48V RTN
R4
549kΩ
1%
VDD
UV
R5
6.49kΩ
1%
*
10nF
R6
10kΩ
1%
PWRGD
MAX5949B
OV
VEE
SENSE
GATE
DRAIN
R3
1kΩ
5%
R1
0.02Ω
5%
C1**
470nF
25V
R2
10Ω
5%
C2
15nF
100V
GATE IN
VIN+
C3
0.1µF
100V
C4
100µF
100V
VICOR
VI-J3D-CY
C5
100µF
10V
-48V
*DIODES INC. SMAT70A.
**OPTIONAL.
Q1
IRF530
VIN-
Figure 7a. Inrush Control Circuitry
_______________________________________________________________________________________
9
MAX5949A/MAX5949B
Board Insertion
Figure 7a shows a typical hot-swap circuit for -48V systems. When the circuit board first makes contact with
the backplane, the DRAIN to GATE capacitance (Cgd)
of Q1 pulls up the GATE voltage to roughly IVEE x Cgd /
(C gd + C gs )I. The MAX5949_ features an internal
dynamic clamp between GATE and VEE to keep the
gate-to-source voltage of Q1 low during hot insertion,
preventing Q1 from passing an uncontrolled current to
the load. For most applications, the internal dynamic
clamp between GATE and V EE of the MAX5949A/
MAX5949B eliminates the need for an external gate-tosource capacitor C1. Resistor R3 limits the current into
the clamp circuitry during card insertion.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
the device waits until tOFF has elapsed before turning
on the gate of the external FET.
INRUSH
CURRENT
1A/div
GATE - VEE
10V/div
DRAIN
50V/div
VEE
50V/div
CONTACT
BOUNCE
4ms/div
Figure 7b. Input Inrush Current
In either case, when the MOSFET is turned off, the output capacitor continues to discharge by the IC supply
current, IDD. The IDD flows into the IC at the VDD terminal, out at the VEE terminal, and back to the capacitor
through the external MOSFET’s substrate diode. There
is also a parallel current path between the VEE and
DRAIN terminals through multiple internal ESD-protection diodes. Protection circuits built into the IC allow the
DRAIN terminal voltage to drop below that of the VEE
terminal so long as the allowed absolute-maximum
DRAIN terminal current (-100mA) is not exceeded. As
IDD is only 2mA maximum, this limiting current will not
even be approached.
Current Limit and Electronic
Circuit Breaker
The MAX5949_ provides current-limiting and circuitbreaker features that protect against excessive load current and short-circuit conditions. The load current is
monitored by sensing the voltage across an external
sense resistor connected between VEE and SENSE.
If the voltage between VEE and SENSE reaches the current-limit trip voltage (VCL), the MAX5949_ pulls down
the GATE pin and regulates the current through the
external MOSFET so VSENSE - VEE < VCL. If the current
drawn by the load drops below VCL / RSENSE limit, the
GATE pin voltage rises again. However, if the load current is at the regulation limit of VCL / RSENSE for a period
of tPHLCB, the electronic circuit breaker trips, causing the
MAX5949A/MAX5949B to turn off the external MOSFET.
After an overcurrent fault condition, the circuit breaker
is reset by pulling the UV pin low and then pulling UV
high or by cycling power to the MAX5949A/MAX5949B.
Unless power is cycled to the MAX5949A/MAX5949B,
10
Overcurrent Fault Integrator
The MAX5949_ features an overcurrent fault integrator.
When an overcurrent condition exists, an internal digital
counter increments its count. When the counter reaches
500µs (the maximum current-limit duration) for the
MAX5949_, an overcurrent fault is generated. If the
overcurrent fault does not last 500µs, then the counter
begins decrementing at a rate 128 (maximum currentlimit duty cycle) times slower than the counter was
incrementing. Repeated overcurrent conditions will generate a fault if duty cycle of the overcurrent condition is
greater than 1/128.
Load-Current Regulation
The MAX5949_ accomplishes load-current regulation by
pulling current from the GATE pin whenever VSENSE - VEE
> VCL (see the Typical Operating Characteristics). This
decreases the gate-to-source voltage of the external
MOSFET, thereby reducing the load current. When
VSENSE - VEE < VCL, the MAX5949A/MAX5949B pull the
GATE pin high by a 45µA (IPU) current.
Driving into a Shorted Load
In the event of a permanent short-circuit condition, the
MAX5949_ limits the current drawn by the load to VCL /
RSENSE for a period of tPHLCB, after which the circuit
breaker trips. Once the circuit breaker trips, the GATE
of the external FET is pulled low by 50mA (IPD) turning
off power to the load.
Immunity to Input Voltage Steps
The MAX5949_ guards against input voltage steps on the
input supply. A rapid increase in the input supply voltage
(VDD - VEE increasing) causes a current step equal to I =
CL x ∆VIN / ∆T. If the load current exceeds VCL / RSENSE
during an input voltage step, the MAX5949A/MAX5949B
current limit activates, pulling down the gate voltage and
limiting the load current to VCL / RSENSE. The DRAIN
voltage (VDRAIN) then slews at a slower rate than the
input voltage. As the drain voltage starts to slew down,
the drain-to-gate feedback capacitor C2 pushes back on
the gate, reducing the gate-to-source voltage (VGS) and
the current through the external MOSFET. Once the input
supply reaches its final value, the DRAIN slew rate (and
therefore the inrush current) is limited by the capacitor
C2 just as it is limited in the startup condition. To ensure
correct operation, RSENSE must be chosen to provide a
current limit larger than the sum of the load current and
the dynamic current into the load capacitance in the
slewing mode.
If the load current plus the capacitive charging current is
______________________________________________________________________________________
-48V Hot-Swap Controllers
with External RSENSE
MAX5949A/MAX5949B
DRAIN
50V/div
VEE
20V/div
GATE - VEE
10V/div
DRAIN
20V/div
ID (Q1)
5A/div
ID (Q1)
5A/div
1ms/div
400µs/div
Figure 8. Short-Circuit Protection Waveform
Figure 9. Voltage Step on Input Supply
-48V RTN
(SHORT PIN)
-48V RTN
R4
549kΩ
1%
VDD
UV
R5
6.49kΩ
1%
*
R6
10kΩ
1%
PWRGD
MAX5949A
OV
VEE
SENSE
GATE
R3
1kΩ
5%
R7
220Ω
5%
R1
0.02Ω
5%
-48V
DRAIN
D1
BAT85
C2
3.3nF
100V
C3
0.1µF
100V
C4
22µF
100V
R2
10Ω
5%
C1
150nF
25V
*DIODES INC. SMAT70A.
Q1
IRF530
Figure 10. Circuit for Input Steps with Small C1
below the current limit, the circuit breaker does not trip.
For C2 values less than 10nF, a positive voltage step on
the input supply can result in Q1 turning off momentarily,
which can shut down the output. By adding an additional
resistor and diode, Q1 remains on during the voltage
step. This is shown as D1 and R7 in Figure 10. The purpose of D1 is to shunt current around R7 when the power
pins first make contact and allow C1 to hold the GATE
low. The value of R7 should be sized to generate an
R7 x C1 time constant of 33µs.
Undervoltage and Overvoltage
Protection
The UV and OV pins can be used to detect undervoltage
and overvoltage conditions. The UV and OV pins are
internally connected to analog comparators with 130mV
(UV) and 20mV (OV) of hysteresis. When the UV voltage
falls below its threshold or the OV voltage rises above its
threshold, the GATE pin is immediately pulled low. The
GATE pin is held low until UV goes high and OV is low,
indicating that the input supply voltage is within specification. The MAX5949_ includes an internal lockout (UVLO)
that keeps the external MOSFET off until the input supply
voltage exceeds 15.4V, regardless of the UV input.
______________________________________________________________________________________
11
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
-48V RTN
(SHORT PIN)
-48V RTN
R7
1MΩ
5%
C4
1µF
100V
NODE2
R6
549kΩ
1%
R4
549kΩ
1%
VDD
UV
NODE2
50V/div
PWRGD
MAX5949A
*
R9
6.49kΩ
1%
OV
VEE
R5
10kΩ
1%
SENSE
GATE
DRAIN
R3
1kΩ
5%
Q2
2N2222
D1
1N4148
Q3
ZVN3310
R8
510kΩ
5%
R1
0.02Ω
5%
-48V
C1
470nF
25V
R2
10Ω
5%
C3
100µF
100V
C2
15nF
100V
GATE
2V/div
1s/div
N
Q1
IRF530
*DIODES INC. SMAT70A.
Figure 11. Automatic Restart After Current Fault
-48V RTN
(SHORT PIN)
-48V RTN
R4
VUV = 1.255
8
3
R4 + R5 + R6
R5 + R6
VDD
UV
R5
R4 + R5 + R6
VOV = 1.255
R6
2
MAX5949A
MAX5949B
OV
VEE
R6
4
-48V
Figure 12. Undervoltage and Overvoltage Sensing
12
The UV pin is also used to reset the circuit breaker after
a fault condition has occurred. The UV pin can be pulled
below VUVL to reset the circuit breaker.
Figure 12 shows how to program the undervoltage and
overvoltage trip thresholds using three resistors. With R4
= 549kΩ, R5 = 6.49kΩ, and R6 = 10kΩ, the undervoltage
threshold is set to 38.5V (with a 43V release from undervoltage), and the overvoltage is set to 71V. The resistordivider also increases the hysteresis of the overvoltage
and overvoltage lockout, to 4.5V and 1.1V at the input
supply, respectively.
PWRGD/PWRGD Output
The PWRGD (PWRGD) output can be used directly to
enable a power module after hot insertion. The
MAX5949A (PWRGD) can be used to enable modules
with an active-low enable input (Figure 14), while the
MAX5949B (PWRGD) is used to enable modules with
an active-high enable input (Figure 13).
The PWRGD signal is referenced to the DRAIN terminal, which is the negative supply of the power module.
The PWRGD signal is referenced to VEE.
______________________________________________________________________________________
-48V Hot-Swap Controllers
with External RSENSE
MAX5949A/MAX5949B
ACTIVE-HIGH
ENABLE MODULE
-48V RTN
(SHORT PIN)
-48V RTN
VIN+
VOUT+
VDD
R4
MAX5949B
GATE
PWRGD
I1
ON/OFF
UV
N Q2
C3
N
VGH
R5
Q3
*
VIN-
VOUT-
VEE
∆VGATE
VDL
OV
DRAIN
R6
VEE
SENSE
GATE
R3
C2
R2
C1
R1
-48V
Q1
*DIODES INC. SMAT70A.
Figure 13. Active-High Enable Module
ACTIVE-LOW
ENABLE MODULE
-48V RTN
(SHORT PIN)
-48V RTN
VIN+
VOUT+
VDD
R4
MAX5949A
GATE
PWRGD
ON/OFF
UV
C3
N
VGH
R5
Q2
VIN-
*
OV
VOUT-
VEE
∆VGATE
VDL
DRAIN
R6
VEE
SENSE
GATE
R3
C2
R2
C1
R1
-48V
*DIODES INC. SMAT70A.
Q1
Figure 14. Active-Low Enable Module
______________________________________________________________________________________
13
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
-48V RTN
(SHORT PIN)
PWRGD
-48V RTN
R7**
51kΩ
5%
R4
549kΩ
1%
VDD
UV
R5
6.49kΩ
1%
*
R6
10kΩ
1%
PWRGD
MAX5949A
OV
VEE
SENSE
GATE
DRAIN
R3
1kΩ
5%
R1
0.02Ω
5%
C1**
470nF
25V
R2
10Ω
5%
MOC207
C2
15nF
100V
C3
100µF
100V
-48V
*DIODES INC. SMAT70A.
**OPTIONAL.
Q1
IRF530
Figure 15. Using PWRGD to Drive an Optoisolator
When the DRAIN voltage of the MAX5949A is high with
respect to VEE or the GATE voltage is low, the internal
pulldown MOSFET Q2 is off and the PWRGD pin is in a
high-impedance state (Figure 14). The PWRGD pin is
pulled high by the module’s internal pullup current
source, turning the module off. When the DRAIN voltage drops below VDL and the GATE voltage is greater
than ∆VGATE - VGH, Q2 turns on and the PWRGD pin
pulls low, enabling the module.
The PWRGD signal can also be used to turn on an LED
or optoisolator to indicate that the power is good
(Figure 15) (see the Component Selection Procedure
section).
When the DRAIN voltage of the MAX5949B is high with
respect to VEE (Figure 13) or the GATE voltage is low, the
internal MOSFET Q3 is turned off so that I1 and the internal MOSFET Q2 clamp the PWRGD pin to the DRAIN pin.
MOSFET Q2 sinks the module’s pullup current, and the
module turns off.
When the DRAIN voltage drops below V DL and the
GATE voltage is greater than ∆VGATE - VGH, MOSFET
Q3 turns on, shorting I1 to VEE and turning Q2 off. The
pullup current in the module pulls the PWRGD pin high,
enabling the module.
14
GATE Pin Voltage Regulation
The GATE pin goes high when the following startup conditions are met: the UV pin is high, the OV pin is low, the
supply voltage is above VUVLOH, and (VSENSE - VEE) is
less than 50mV. The gate is pulled up with a 45µA current
source and is regulated at 13.5V above V EE . The
MAX5949A/MAX5949B include an internal clamp that
ensures the GATE voltage of the external MOSFET never
exceeds 18V. During a fast-rising VDD, the clamp also
keeps the GATE and SENSE potentials as close as possible to prevent the FET from accidentally turning on. When
a fault condition is detected, the GATE pin is pulled low
with a 50mA current.
Applications Information
Sense Resistor
The circuit-breaker current-limit threshold is set to 50mV
(typically). Select a sense resistor that causes a drop
equal to or above the current-limit threshold at a current
level above the maximum normal operating current.
Typically, set the overload current to 1.5 to 2.0 times the
nominal load current plus the load-capacitance charging
current during startup. Choose the sense-resistor power
rating to be greater than (VCL)2 / RSENSE.
______________________________________________________________________________________
-48V Hot-Swap Controllers
with External RSENSE
•
•
•
•
Determine load capacitance:
CL = C2 + C3 + module input capacitance
Determine load current, ILOAD.
Select circuit-breaker current; for example:
ICB = 2 x ILOAD
Calculate RSENSE:
50mV
RSENSE =
ICB
Realize that ICB varies ±20% due to trip-voltage
tolerance.
Set allowable inrush current:
40mV
− ILOAD or
RSENSE
IINRUSH + ILOAD ≤ 0.8 x ICB(MIN)
IINRUSH ≤ 0.8 x
•
Determine value of C2:
45µA x CL
C2 =
IINRUSH
•
Calculate value of C1:
⎛ VIN(MAX) − VGS( TH) ⎞
C1 = (C2 + Cgd ) x ⎜
⎟
VGS( TH)
⎝
⎠
•
Determine value of R3:
150µs
R3 ≤
(typically 1kΩ)
C2
• Set R2 = 10Ω.
• If an optocoupler is utilized as in Figure 15, determine the LED series resistor:
VIN(NOMINAL) − 2V
R7 =
3mA ≤ ILED ≤ 5mA
Although the suggested optocoupler is not specified for
operation below 5mA, its performance is adequate for
36V temporary low-line voltage where LED current
would then be ≈2.2mA to 3.7mA. If R7 is set as high as
51kΩ, optocoupler operation should be verified over
the expected temperature and input voltage range to
ensure suitable operation when LED current ≈0.9mA for
48V input and ≈0.7mA for 36V input.
If input transients are expected to momentarily raise the
input voltage to >100V, select an input transient-voltage-suppression diode (TVS) to limit maximum voltage
on the MAX5949 to less than 100V. A suitable device is
the Diodes Inc. SMAT70A telecom-specific TVS.
Select Q1 to meet supply voltage, load current, efficiency, and Q1 package power-dissipation requirements:
BVDSS ≥ 100V
ID(ON) ≥ 3 x ILOAD
DPAK, D2PAK, or TO-220AB
The lowest practical RDS(ON), within budget constraints
and with values from 14mΩ to 540mΩ, are available at
100V breakdown.
Ensure that the temperature rise of Q1 junction is not
excessive at normal load current for the package selected. Ensure that ICB current during voltage transients
does not exceed allowable transient-safe operating-area
limitations. This is determined from the SOA and transient-thermal-resistance curves in the Q1 manufacturer’s
data sheet.
Example 1:
ILOAD = 2.5A, efficiency = 98%, then VDS = 0.96V is
acceptable, or RDS(ON) ≤ 384mΩ at operating temperature is acceptable. An IRL520NS 100V NMOS with
R DS(ON) ≤ 180mΩ and I D(ON) = 10A is available in
D2PAK. (A Vishay Siliconix SUD40N10-25 100V NMOS
with RDS(ON) ≤ 25mΩ and ID(ON) = 40A is available in
DPAK, but may be more costly because of a larger die
size.)
Using the IRL520NS, VDS ≤ 0.625V even at +80°C so
efficiency ≥ 98.6% at 80°C. PD ≤ 1.56W and junction
temperature rise above case temperature would be 5°C
due to the package θJC = 3.1°C/W thermal resistance.
Of course, using the SUD40N10-25 would yield an efficiency greater than 99.8% to compensate for the
increased cost.
______________________________________________________________________________________
15
MAX5949A/MAX5949B
Component Selection Procedure
•
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
If ICB is set to twice ILOAD, or 5A, VDS momentarily doubles to ≤1.25V. If COUT = 4000µF, transient-line input
voltage is ∆36V, and the 5A charging-current pulse is:
4000µF x 1.25V
= 1ms
5A
Entering the data sheet transient-thermal-resistance
curves at 1ms provides a θJC = 0.9°C/W. PD = 6.25W,
so ∆tJC = 5.6°C. Clearly, this is not a problem.
Example 2:
ILOAD = 10A, efficiency = 98%, allowing VDS = 0.96V
but RDS(ON) ≤ 96mΩ. An IRF530 in a D2PAK exhibits
RDS(ON) ≤ 90mΩ at +25°C and ≤ 135mΩ at +80°C.
Power dissipation is 9.6W at +25°C or 14.4W at +80°C.
Junction-to-case thermal resistance is 1.9W/°C, so the
junction-temperature rise would be approximately 5°C
above the +25°C case temperature. For higher efficiency, consider IRL540NS with R DS(ON) ≤ 44mΩ. This
allows η = 99%, PD ≤ 4.4W, and TJC = +4°C (θJC =
1.1°C/W) at +25°C.
Thermal calculations for the transient condition yield
I CB = 20A, V DS = 1.8V, t = 0.5ms, transient θ JC =
0.12°C/W, PD = 36W and ∆tJC = 4.3°C.
HIGH-CURRENT PATH
t =
SENSE RESISTOR
SENSE VEE
MAX5949A
MAX5949B
Figure 16. Recommended Layout for Kelvin-Sensing Current
Through Sense Resistor
Selector Guide
PART
16
PWRGD POLARITY
FAULT MANAGEMENT
MAX5949AESA
Active low (PWRGD)
Latched
MAX5949BESA
Active high (PWRGD)
Latched
______________________________________________________________________________________
-48V Hot-Swap Controllers
with External RSENSE
BACKPLANE
CIRCUIT CARD
-48V RTN
-48V RTN
(SHORT PIN)
R4
549kΩ
1%
VDD
UV
R5
649kΩ
1%
0.1µF
10V
-48V (INPUT1)
R6
10kΩ
1%
INPUT1
PWRGD
MAX5949A
OV
VEE
SENSE
R1
0.02Ω
5%
C1
490nF
25V
GATE
DRAIN
R3
1kΩ
5%
R2
10Ω
5%
C2
15nF
100V
VIN+
C3
0.1µF
100V
C4
100µF
100V
LUCENT
JW050A1-E
N
VIN-
-48V (INPUT2)
INPUT2
Package Information
Chip Information
PROCESS: BiCMOS
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
8 SO
S8+5
21-0041
90-0096
______________________________________________________________________________________
17
MAX5949A/MAX5949B
Typical Operating Circuit
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/04
Initial release
1
8/11
Updated the Electrical Characteristics and Figure 11.
DESCRIPTION
PAGES
CHANGED
—
3, 12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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