High Power, Low Distortion Upstream CATV Line Driver ADA4320-1 FUNCTIONAL BLOCK DIAGRAM Supports CableLabs® DOCSIS 3.0/2.0 and EuroDOCSIS 3.0/2.0 specifications for customer premises equipment (CPE) upstream transmission 5 V single-supply operation Excellent adjacent channel rejection performance −66 dBc ACPR for a single QPSK channel −63 dBc ACPR for 4× QAM64 channels Gain programmable in 1 dB steps over a 59 dB range Gain range: −27 dB to +32 dB Current-scaled output stage Low between-burst output noise level −70 dB mV in 160 kHz bandwidth Maintains constant output impedance in enable, disable, and sleep conditions Selectable low power modes 12 mA in Tx disable 12 μA in sleep mode (full power-down) 3-wire, SPI-compatible interface 4 mm × 5 mm 24-lead LFCSP, RoHS compliant VIN– VIN+ VOUT+ DIFF OR SINGLE INPUT AMP ATTENUATION CORE VERNIER VOUT– 8 ZIN (SINGLE) = 320Ω ZIN (DIFF) = 640Ω DECODE 8 DATA LATCH ZOUT DIFF = 300Ω POWER-DOWN LOGIC RAMP 8 ADA4320-1 GND POWER AMP SHIFT REGISTER DATEN SDATA CLK TXEN SLEEP 08707-001 FEATURES Figure 1. APPLICATIONS DOCSIS 3.0 and EuroDOCSIS cable modems/E-MTAs DOCSIS 3.0 set-top boxes CATV telephony modems Coaxial or twisted pair line drivers GENERAL DESCRIPTION The ADA4320-1 is a high power, ultralow distortion amplifier designed for CATV reverse channel line driving. Its features and specifications make the ADA4320-1 ideally suited for DOCSIS 3.0and EuroDOCSIS 3.0-based applications. Both gain and output stage current are controlled via a 3-wire (SPI-compatible) interface. A single 8-bit serial word selects one of four available supply current presets and one of sixty gain codes. The ADA4320-1 has been tailored to address both the high output drive and stringent fidelity requirements of DOCSIS 3.0. The part is able to maintain excellent adjacent channel rejection performance over the full 5 MHz to 85 MHz range, even with multiple bonded channels at maximum specified output levels. The ADA4320-1 accepts a differential or single-ended input signal. The output is specified for driving a single-ended 75 Ω load through a 4:1 impedance transformer. The ADA4320-1 features an output driver stage that scales quiescent current consumption according to gain setting. In multichannel mode at maximum gain (32 dB), the device draws 260 mA from a single 5 V supply, enabling the high power, ultralow distortion performance required by multiple DOCSIS 3.0 upstream channels. For lifeline E-MTA applications, the ADA4320-1 output stage current can be throttled via SPI commands, reducing the power requirement for single-channel transmission by up to 30%. In transmit-disable mode, the ADA4320-1 draws only 12 mA. The device also features a full power-down sleep mode that further reduces current draw to12 μA typical. The ADA4320-1 is packaged in a RoHS-compliant, 24-lead exposed pad LFCSP and is rated for operation over the −40°C to +85°C temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved. ADA4320-1 TABLE OF CONTENTS Features .............................................................................................. 1 General Applications ................................................................. 11 Applications ....................................................................................... 1 Circuit Description .................................................................... 11 Functional Block Diagram .............................................................. 1 Programming .............................................................................. 11 General Description ......................................................................... 1 Current Level and Gain Adjustment ....................................... 11 Revision History ............................................................................... 2 Power Saving Features ............................................................... 12 Specifications..................................................................................... 3 Input Bias, Impedance, and Termination................................ 12 Logic Inputs (TTL-/CMOS-Compatible Logic) ....................... 4 Output Bias, Impedance, and Termination ............................ 12 Timing Requirements .................................................................. 5 Power Supply............................................................................... 12 Absolute Maximum Ratings............................................................ 6 Signal Integrity Layout Considerations ................................... 12 Thermal Resistance ...................................................................... 6 Initial Power-Up ......................................................................... 12 Maximum Power Dissipation ..................................................... 6 RAMP Pin Feature...................................................................... 13 ESD Caution .................................................................................. 6 Output Transformer ................................................................... 13 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 14 Applications Information .............................................................. 11 REVISION HISTORY 4/10—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADA4320-1 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 75 Ω, VIN (differential) = 29 dB mV sinusoidal, f = 5 MHz to 85 MHz, gain, VOUT (single-ended) measured at output of Coilcraft PWB-4-BL transformer, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Input Resistance Input Capacitance GAIN CONTROL Gain Range Maximum Gain Minimum Gain Output Step Size OUTPUT CHARACTERISTICS Gain Flatness At Maximum Gain At Minimum Gain 1 dB Compression Point (P1dB) Output Noise in 160 kHz Bandwidth At Maximum Gain At Minimum Gain Transmit Disabled Output Impedance (Measured at Transformer Output) Output Return Loss (Measured at Transformer Output) OVERALL PERFORMANCE Adjacent Channel Power Ratio (ACPR) Single QPSK Channel 4x QAM64 Channels Output Third-Order Intercept Point (OIP3) Input-to-Output Isolation Conditions Min Balanced (differential) input Unbalanced (single-ended) input Typ Max 640 320 2.0 Unit Ω Ω pF Current Level 3 57.5 30.5 Gain Code 60 Gain Code 01 0.6 Referenced to 10 MHz f = 42 MHz, Gain Code 60, Current Level 3 f = 65 MHz, Gain Code 60, Current Level 3 f = 85 MHz, Gain Code 60, Current Level 3 f = 42 MHz, Gain Code 01, Current Level 0 f = 65 MHz, Gain Code 01, Current Level 0 f = 85 MHz, Gain Code 01, Current Level 0 f = 10 MHz, Gain Code 60, Current Level 3, output referred f = 10 MHz, 294 Ω resistor across VIN+ and VIN− pins Gain Code 60, Current Level 3, TXEN = high (1) Gain Code 60, Current Level 0, TXEN = high (1) Gain Code 01, Current Level 3, TXEN = high (1) Gain Code 01, Current Level 0, TXEN = high (1) TXEN = low (0) TXEN = high (1) or TXEN = low (0) or SLEEP = low (0) 59 32 −27 1.0 60 −25.5 1.4 dB dB dB dB/LSB −0.3 −0.7 −1.1 −0.4 −0.8 −1.8 70 dB dB dB dB dB dB dB mV −20 −21 −60 −61 −70 75 dB mV dB mV dB mV dB mV dB mV Ω SLEEP = high (1), TXEN = high (1) SLEEP = high (1), TXEN = low (0) SLEEP = low (0) 12 11 10 dB dB dB f = 5 MHz to 85 MHz, output level = 61 dB mV, Gain Code 60, Current Level 3, channel width = 6.4 MHz, adjacent channel width = 6.4 MHz f = 5 MHz to 85 MHz, output level = 53 dB mV/channel, Gain Code 60, Current Level 3, channel width = 1.6 MHz, adjacent channel width = 1.6 MHz f1 = 84 MHz, f2 = 85 MHz, Gain Code 60, Current Level 3 f1 = 84 MHz, f2 = 85 MHz, Gain Code 60, Current Level 0 f = 85 MHz, Gain Code 60, TXEN = Low (0) −66 dBc −63 dBc 93 87 107 dB mV dB mV dB −19 −20 −59 −60 −68 f = 85 MHz Rev. 0 | Page 3 of 16 ADA4320-1 Parameter POWER CONTROL Transmit Enable Settling Time Transmit Disable Settling Time Output Switching Transients POWER SUPPLY Operating Range Quiescent Current At Maximum Gain At Minimum Gain Conditions Min TXEN = 0 to 1, Gain Code 60, no input signal TXEN = 1 to 0, Gain Code 60, no input signal Gain Code 60 Gain Code 01 Typ Max 5.5 7 20 2 4.75 Gain Code 60, Current Level 3 Gain Code 60, Current Level 2 Gain Code 60, Current Level 1 Gain Code 60, Current Level 0 Gain Code 01, Current Level 3 Gain Code 01, Current Level 2 Gain Code 01, Current Level 1 Gain Code 01, Current Level 0 TXEN = 0, all gain codes, all current levels SLEEP = 0 (power-down) OPERATING TEMPERATURE RANGE −40 Unit μs μs mV p-p mV p-p 5.00 5.25 V 260 235 210 180 77 73 70 65 12 12 300 270 250 210 100 95 90 80 15 80 mA mA mA mA mA mA mA mA mA μA +85 °C LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) DATEN, CLK, SDATA, TXEN, SLEEP, VS = 5 V; full temperature range. Table 2. Parameter Logic 1 Voltage Logic 0 Voltage Digital Input Leakage Current (Both Logic Levels, All Digital Pins) Rev. 0 | Page 4 of 16 Min 2.0 0 −5 Typ Max VS 0.8 +5 Unit V V μA ADA4320-1 TIMING REQUIREMENTS Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted. Table 3. Parameter Clock Pulse Width (tWH) Clock Period (tC) Setup Time SDATA vs. Clock (tDS) Setup Time DATEN vs. Clock (tES) Hold Time SDATA vs. Clock (tDH) Hold Time DATEN vs. Clock (tEH) Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock Min 16 32 5 16 5 3 Typ 10 tDS SDATA VALID DATA-WORD G1 MSB...LSB tWH VALID DATA-WORD G2 tC CLK tES tEH 8 CLOCK CYCLES DATEN Max GAIN TRANSFER (G1) GAIN TRANSFER (G2) TXEN 08707-002 ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB MSB – 1 tDH 08707-003 tDS MSB – 2 CLK Figure 3. SDATA Timing Rev. 0 | Page 5 of 16 Unit ns ns ns ns ns ns ns ADA4320-1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 4. Parameter Supply Voltage Maximum Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 5.5 V 1.65 W −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the device soldered to a high thermal conductivity 4-layer (2s2p) circuit board, as described in EIA/JESD 51-7. The maximum safe power dissipation in the ADA4320-1 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4320-1. Exceeding a junction temperature of 150°C for an extended time can result in changes in the silicon devices, potentially causing failure. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes, reduces the θJA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane to achieve the specified θJA. ESD CAUTION Table 5. Thermal Resistance Package Type 24-lead LFCSP θJA 31.2 θJC 5.7 Unit °C/W Rev. 0 | Page 6 of 16 ADA4320-1 24 23 22 21 20 COMP VOUT+ VOUT– VOUT+ VOUT– PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 ADA4320-1 TOP VIEW (Not to Scale 19 18 17 16 15 14 13 GND GND GND SLEEP CLK SDATA DATEN NOTES 1. EXPOSED THERMAL PAD MUST BE ELECTRICALLY AND THERMALLY CONNECTED TO PCB GROUND (GND) PLANE. 08707-005 GND GND VIN– VIN+ GND 8 9 10 11 12 GND GND VCC VCC VCC RAMP TXEN Figure 4. Pin Configuration, Top View Table 6. Pin Function Descriptions Pin No. 1, 2, 8, 9, 12, 17, 18, 19, EPAD 3, 4, 5 6 7 10 11 13 Mnemonic GND Description Common External Ground Reference. VCC RAMP TXEN VIN− VIN+ DATEN 14 SDATA 15 CLK 16 SLEEP 20, 22 21, 23 24 VOUT− VOUT+ COMP Common Positive External Supply Voltage. External RAMP Capacitor (Optional). Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward transmission. Inverting Input. DC-biased to approximately VCC/2. This pin should be ac-coupled with a 0.1 μF capacitor. Noninverting Input. DC-biased to approximately VCC/2. This pin should be ac-coupled with a 0.1 μF capacitor. Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous, and simultaneously enables the register for serial data load). Serial Data Input. This digital input allows an 8-bit serial control word to be loaded into the internal register with the most significant bit (MSB) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. A Logic 0-to-1 transition latches the data bit, and a Logic 1-to-0 transition transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. Low Power Sleep Mode. In sleep mode, the supply current is reduced to 12 μA typical. Logic 0 powers down the device, and Logic 1 powers up the device. Negative Output Signal. This pin must be biased to VCC. Positive Output Signal. This pin must be biased to VCC. Internal Compensation. This pin must be externally decoupled (0.1 μF capacitor). Rev. 0 | Page 7 of 16 ADA4320-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, RL = 75 Ω, VIN (differential) = 29 dBmV sinusoidal, f = 5 MHz to 85 MHz, Gain Code 60 (maximum), Current Level 3 (maximum), VOUT (single-ended) measured at output of Coilcraft PWB-4-BL transformer, unless otherwise noted. 300 CURRENT CURRENT CURRENT CURRENT 3 2 1 0 60 VIN = 29dBmV CURRENT LEVEL 3 VIN = 29dBmV 45 GAIN CODE 60 30 GAIN CODE 40 15 200 GAIN (dB) SUPPLY CURRENT (mA) 250 LEVEL LEVEL LEVEL LEVEL 150 0 GAIN CODE 20 –15 GAIN CODE 01 –30 100 0 6 12 18 24 30 36 42 48 54 60 GAIN CODE –60 1M 08707-006 50 10M Figure 5. Supply Current vs. Gain Code 270 Figure 8. Gain vs. Frequency 1.0 GAIN CODE 60 CURRENT LEVEL 3 0.5 NORMALIZED GAIN (dB) SUPPLY CURRENT (mA) 5.00V 265 4.75V 255 250 245 LEVEL LEVEL LEVEL LEVEL 3 2 1 0 GAIN CODE 60 (MAXIMUM) VIN = 29dBmV 0 –0.5 –1.0 –1.5 240 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) –2.0 08707-007 235 –60 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 FREQUENCY (MHz) Figure 9. Normalized Frequency Response at Maximum Gain Figure 6. Supply Current vs. Ambient Temperature at Maximum Gain 75 CURRENT CURRENT CURRENT CURRENT 5.25V 260 1G 08707-010 275 100M FREQUENCY (Hz) 08707-009 –45 1.0 GAIN CODE 01 CURRENT LEVEL 0 +85°C +25°C –40°C 0.5 GAIN CODE 60 (MAXIMUM) VIN = 29dBmV NORMALIZED GAIN (dB) SUPPLY CURRENT (mA) 70 5.25V 65 5.00V 60 4.75V 0 –0.5 –1.0 –1.5 –2.0 55 –40 –20 0 20 40 60 AMBIENT TEMPERATURE (°C) 80 100 –3.0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 FREQUENCY (MHz) Figure 10. Normalized Frequency Response over Temperature Figure 7. Supply Current vs. Ambient Temperature at Minimum Gain Rev. 0 | Page 8 of 16 08707-011 50 –60 08707-008 –2.5 ADA4320-1 80 –30 –40 –50 –60 –70 –80 24 30 36 42 48 54 60 GAIN CODE 40 30 20 0 ADJACENT CHANNEL POWER RATIO (dBc) OUTPUT RETURN LOSS (dB) –40 –10 –15 –20 –30 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 FREQUENCY (MHz) –45 –50 –65 –66 –67 –68 25 35 45 55 65 60 54 75 FREQUENCY (MHz) 80 70 60 ACPR 40 –65 30 –70 20 OUTPUT LEVEL –75 10 6 12 18 24 30 36 42 48 54 0 60 GAIN CODE –52 CURRENT LEVEL 0 CURRENT LEVEL 1 CURRENT LEVEL 2 CURRENT LEVEL 3 –64 15 48 Figure 15. ACPR and Output Level vs. Gain Code –63 5 42 50 –60 ADJACENT CHANNEL POWER RATIO (dBc) –62 36 –55 0 85 08707-015 ADJACENT CHANNEL POWER RATIO (dBc) SINGLE QPSK CHANNEL OUTPUT LEVEL = 61dBmV GAIN CODE 60 (MAXIMUM) CHANNEL WIDTH = 6.4MHz ADJACENT CHANNEL WIDTH = 6.4MHz 30 SINGLE QPSK CHANNEL INPUT LEVEL = 29dBmV CURRENT LEVEL 3 CHANNEL WIDTH = 6.4MHz DRIVEN CHANNEL CENTER = 42MHz ADJACENT CHANNEL WIDTH = 6.4MHz ADJACENT CHANNEL CENTER = 48.4MHz Figure 12. Output Return Loss (S22) vs. Frequency –61 24 –80 08707-012 –25 5 18 Figure 14. Output 1 dB Compression Point vs. Gain Code SLEEP TX DISABLE TX ENABLE –5 12 GAIN CODE Figure 11. Noise Power vs. Gain Code 0 6 OUTPUT LEVEL (dBmV) 18 50 08707-017 12 60 4× QAM64 CHANNELS (UNCORRELATED) OUTPUT LEVEL = 53dBmV/CHANNEL GAIN CODE 60 (MAXIMUM) CHANNEL WIDTH = 1.6MHz ADJACENT CHANNEL WIDTH = 1.6MHz –54 –56 CURRENT CURRENT CURRENT CURRENT –58 LEVEL LEVEL LEVEL LEVEL 0 1 2 3 –60 –62 –64 –66 5 15 25 35 45 55 65 75 FREQUENCY (MHz) Figure 16. ACPR vs. Frequency for 4× QAM64 Channels Figure 13. ACPR vs. Frequency for Single QPSK Channel Rev. 0 | Page 9 of 16 85 08707-016 6 70 08707-014 –20 0 CURRENT LEVEL 3 CURRENT LEVEL 0 OUTPUT 1dB COMPRESSION POINT (dBmV) TXEN = 1, ALL CURRENT LEVELS TXEN = 0 08707-013 NOISE POWER IN 160kHz BANDWIDTH (dBmV) –10 ADA4320-1 –22 CURRENT LEVEL 0 CURRENT LEVEL 1 CURRENT LEVEL 2 CURRENT LEVEL 3 –48 –52 –56 –60 –64 –68 –72 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 INPUT LEVEL (dBmV) –46 –52 –58 –64 –70 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INPUT LEVEL (dBmV/CHANNEL) Figure 17. ACPR vs. Input Level for a Single QPSK Channel –30 –40 ADJACENT CHANNEL POWER RATIO (dBc) –20 –10 SINGLE QPSK CHANNEL GAIN CODE 60 (MAXIMUM) CHANNEL WIDTH = 6.4MHz DRIVEN CHANNEL CENTER = 42MHz ADJACENT CHANNEL WIDTH = 6.4MHz ADJACENT CHANNEL CENTER = 48.4MHz CURRENT LEVEL 0 CURRENT LEVEL 1 CURRENT LEVEL 2 CURRENT LEVEL 3 –50 –60 –70 –80 59 60 61 62 63 64 65 66 67 68 69 70 71 OUTPUT LEVEL (dBmV) OUTPUT GLITCH AMPLITUDE (mV p-p) 0 –2 –4 PEAK OUTPUT ENVELOPE –8 –2 0 2 4 6 8 10 12 14 TIME (µs) 16 18 08707-022 OUTPUT AMPLITUDE (V) 2 –6 CURRENT LEVEL 0 CURRENT LEVEL 1 CURRENT LEVEL 2 CURRENT LEVEL 3 –40 –50 –60 –70 120 TXEN 4 –30 46 48 50 52 54 56 58 60 62 Figure 21. ACPR vs. Output Level for 4x QAM64 Channels 4× QAM64 CHANNELS (UNCORRELATED) OUTPUT LEVEL = 53dBmV/CHANNEL CHANNEL WIDTH = 1.6MHz CHANNEL CENTERS = 39.6MHz, 41.2MHz, 42.8MHz, 44.4MHz) 6 –20 OUTPUT LEVEL (dBmV/CHANNEL) Figure 18. ACPR vs. Output Level for a Single QPSK Channel 8 4× QAM64 CHANNELS (UNCORRELATED) GAIN CODE 60 (MAXIMUM) CHANNEL WIDTH = 1.6MHz DRIVEN CHANNEL CENTER = 77.8MHz, 79.4MHz, 81.0MHz, 82.6MHz ADJACENT CHANNEL WIDTH = 1.6MHz ADJACENT CHANNEL CENTER = 84.2MHz –80 44 08707-020 ADJACENT CHANNEL POWER RATIO (dBc) –10 Figure 20. ACPR vs. Input Level for 4× QAM64 Channels 08707-021 –44 81.0MHz, 82.6MHz ADJACENT CHANNEL WIDTH = 1.6MHz –34 ADJACENT CHANNEL CENTER = 84.2MHz CURRENT LEVEL 0 CURRENT LEVEL 1 –40 CURRENT LEVEL 2 CURRENT LEVEL 3 Figure 19. Transmit Enable/Disable Response TXEN = 1 TXEN = 0 DOCSIS 3.0 LIMIT (FOR 29dBmV INPUT) 100 80 60 40 20 0 0 6 12 18 24 30 36 42 48 54 GAIN CODE Figure 22. Output Glitch Amplitude vs. Gain Code Rev. 0 | Page 10 of 16 60 08707-023 –40 4× QAM64 CHANNELS (UNCORRELATED) GAIN CODE 42 (14dB) CHANNEL WIDTH = 1.6MHz –28 DRIVEN CHANNEL CENTER = 77.8MHz, 79.4MHz, 08707-019 ADJACENT CHANNEL POWER RATIO (dBc) SINGLE QPSK CHANNEL –28 GAIN CODE 42 (14dB) CHANNEL WIDTH = 6.4MHz –32 DRIVEN CHANNEL CENTER = 42 MHz ADJACENT CHANNEL WIDTH = 6.4 MHz –36 ADJACENT CHANNEL CENTER = 48.4 MHz 08707-018 ADJACENT CHANNEL POWER RATIO (dBc) –24 ADA4320-1 APPLICATIONS INFORMATION Table 7. Data-Word for Setting Current and Gain Levels Varying distances between the CPE and the cable modem termination system (CMTS), as well as diplexers and splitters that may exist in the signal path, require the amplifier to provide a wide range of output power. The combination of a high output level, excellent linearity, and 59 dB gain range of the ADA4320-1 enables the CPE to overcome inline losses and ensures adequate signal strength at the upstream termination. CIRCUIT DESCRIPTION In power-up mode, the ADA4320-1 comprises three analog functions. The input amplifier (preamp) can be used single-ended or balanced (differential). If the input is used in the balanced configuration, it is imperative that the input signals be 180° out of phase and of equal amplitude. A Vernier adjustment amplifier controls the 1 dB gain steps. The digital attenuator (DA) stage provides coarse adjustment in 6 dB steps. It also scales the current supplied to the output stage. Both the preamp and DA are differential (balanced) to improve power supply rejection and linearity. CL 3 2 1 0 Gain[5:0] (Hex) 3C to 01 3C to 01 3C to 01 3C to 01 Cain Code (Dec) 60 to 01 60 to 01 60 to 01 60 to 01 Typical Gain (dB) +32 to −27 +32 to −27 +32 to −27 +32 to −27 CURRENT LEVEL AND GAIN ADJUSTMENT Gain adjustment and current scaling allow the PA to achieve the high output levels and linearity required for multiple-channel DOCSIS 3.0 compliance, while offering significantly reduced power consumption in single-channel and lifeline battery-backup modes of operation. There are two methods of adjusting the output stage current of the ADA4320-1. The first is performed automatically, lowering output current as attenuation is increased (gain is reduced). As shown in Figure 23, for every 6 dB reduction in gain, output stage current is decreased. At higher gain settings, this is more pronounced. At maximum gain and maximum current level, a step down of 6 dB reduces the supply current by 33%. The second method, which allows the user to program one of four preset current levels (CL3 to CL0) at any gain setting, is shown by the individual traces in Figure 23. 300 CURRENT CURRENT CURRENT CURRENT GAIN 250 SUPPLY CURRENT (mA) The ADA4320-1 is controlled via a unidirectional, 3-wire serial interface (SPI-compatible) consisting of CLK, DATEN, and SDATA signals. An 8-bit data-word containing the output stage current level (Bits[7:6]) and desired gain code (Bits[5:0]) is clocked into the SDATA port, MSB first. CL[7:6] (Bin) 11 10 01 00 The sequence of loading the SDATA register starts on the falling edge of the DATEN pin, which activates the CLK line. Data on the SDATA line is clocked into the serial shift register on the rising edge of CLK, MSB first. The data-word is latched into the attenuator core on the rising edge of DATEN. Serial interface timing for the ADA4320-1 is shown in Figure 2 and Figure 3. The differential current is output from the DA to the output stage. The output stage, with its 300 Ω balanced output impedance, maintains proper matching to a 75 Ω load when used with a 2:1 (turns ratio) balun transformer. PROGRAMMING Typical Current (mA) 260 to 77 235 to 73 210 to 70 180 to 65 The programmable current level (CL) range of the ADA4320-1 is CL3 (highest) to CL0 (lowest). The programmable gain range is +32 dB (Gain Code 60) to −27 dB (Gain Code 01), in steps of 1 dB per least significant bit (LSB), providing a total gain range of 59 dB. Rev. 0 | Page 11 of 16 LEVEL LEVEL LEVEL LEVEL 30 3 2 1 0 18 200 6 150 –6 100 –18 50 0 12 24 36 48 GAIN CODE Figure 23. Gain and Current Scaling –30 60 GAIN (dB) The ADA4320-1 is primarily intended for use as the reverse channel power amplifier (PA) in DOCSIS® 3.0 customer premises equipment (CPE), including cable modems, E-MTAs, and DOCSIS-enabled set-top boxes. The signals are typically QPSK or QAM waveforms generated by the upstream modulator and DAC. To sufficiently attenuate DAC images, a low-pass reconstruction filter is recommended between the DAC output and the ADA4320-1. A differential filter is preferred, and its output impedance should match the 640 Ω input impedance of the ADA4320-1. 08707-024 GENERAL APPLICATIONS ADA4320-1 POWER SAVING FEATURES OUTPUT BIAS, IMPEDANCE, AND TERMINATION The ADA4320-1 incorporates three distinct methods for reducing power consumption that include the following: The output stage of the ADA4320-1 requires a bias of 5 V. The 5 V power supply should be applied to the center tap of the output transformer through a 100 nH series inductor. This supply should also be decoupled with a 0.1 μF capacitor, as shown in Figure 24. • Transmit disable for between-burst periods • Sleep (shutdown) mode • Output stage current scaling The asynchronous TXEN pin is used to place the ADA4320-1 into between-burst mode. In this reduced current state, the 300 Ω differential output impedance is maintained. Applying Logic 0 to the TXEN pin deactivates the amplifier, providing up to 95% reduction in consumed power. For 5 V operation at maximum gain and current level, supply current is typically reduced from 260 mA to 12 mA. In this mode of operation, between-burst noise is minimized and over 100 dB of input to output isolation is achieved. Additionally, the ADA4320-1 incorporates an asynchronous SLEEP pin that can be used to further reduce supply current to approximately 12 μA. Applying Logic 0 to the SLEEP pin places the amplifier into sleep mode. Entering/exiting sleep mode can result in a transient voltage at the output of the amplifier. It is recommended to perform transitions on the SLEEP pin with TXEN held low. Additional power savings are possible by optimizing the output stage current for different operating conditions. Typically, at lower frequencies (5 MHz to 42 MHz), the full specified output can be maintained in CL0 (see Figure 13 and Figure 16). For lower input levels, the same is true, as shown in Figure 17 and Figure 20. For per-channel output levels less than 65 dBmV (QPSK) and 50 dBmV (4× QAM64), the ADA4320-1 can maintain an ACPR of better than −60 dBc (see Figure 18 and Figure 21) at Current Level 0 (CL0). At higher gain settings, operating in CL0 reduces current consumption by 30%, compared to operating in CL3. As an example, operating in CL0, the ADA4320-1 can drive a single QPSK channel at 61 dBmV, at maximum gain, maintaining a worst-case ACPR of −66 dBc. It does this while drawing only 180 mA from a 5 V supply. INPUT BIAS, IMPEDANCE, AND TERMINATION The VIN+ and VIN− inputs have a dc bias level of VCC/2; therefore, the input signal should be ac-coupled as seen in the typical application circuit (see Figure 24). The differential input impedance of the ADA4320-1 is approximately 640 Ω, and the single-ended input is 320 Ω. The ADA4320-1 exhibits optimum performance when driven with a balanced (differential) signal. The output impedance of the ADA4320-1 is 300 Ω differential, regardless of whether the amplifier is in transmit enable, transmit disable, or sleep mode. This, when combined with a 4:1 impedance transformer, provides a 75 Ω output match and eliminates the need for external back termination resistors. If the output signal is being evaluated using standard 50 Ω test equipment, a minimum loss 75 Ω to 50 Ω pad should be used to provide the test circuit with the proper impedance match. POWER SUPPLY The 5 V supply should be delivered to each of the VCC pins via a low impedance power bus. The power bus should be decoupled with a 10 μF tantalum capacitor located close to the ADA4320-1. Additionally, the VCC pins require decoupling to ground with ceramic chip capacitors located close to the pins. Pin 24 (COMP), should also be decoupled. The ideal printed circuit board (PCB) has a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the ADA4320-1 and the output transformer. All device GND pins, as well as the exposed pad, must contact the PCB ground plane to ensure proper grounding of all internal nodes. SIGNAL INTEGRITY LAYOUT CONSIDERATIONS Careful attention to PCB layout details can prevent problems due to board parasitics. Proper RF design techniques are highly recommended. All balanced input/output traces should be kept as short as possible. This minimizes parasitic capacitance and inductance, which is most critical between the outputs of the ADA4320-1 and the 4:1 output transformer. It is also recommended that all balanced signal paths be symmetrical in length and width. Additionally, input and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. Following these guidelines optimizes the overall performance of the ADA4320-1 in all applications. INITIAL POWER-UP When supply voltage is applied to the ADA4320-1, the gain of the amplifier is initially undetermined. During amplifier powerup, the TXEN pin should be held low (Logic 0) to prevent forward signal transmission. Gain must then be set to the desired level, followed by TXEN driven high. Forward signal transmission is enabled at the resultant gain level. Rev. 0 | Page 12 of 16 ADA4320-1 RAMP PIN FEATURE OUTPUT TRANSFORMER The RAMP pin (Pin 6) can be optionally used to control the length of the burst on and off transients. By default, leaving the RAMP pin unconnected results in a transient that is fully compliant with DOCSIS 3.0. Adding capacitance to the RAMP pin slows the dissipation even more. Matching the 300 Ω differential output impedance to unbalanced 75 Ω requires a 4:1 impedance (2:1 turns) ratio transformer. The transformer should have minimal insertion loss over the 5 MHz to 85 MHz band and have a maximum dc current rating of at least 200 mA. Characterization of the ADA4320-1 was performed using a Coilcraft PWB-4-BL surface-mount wide-band RF transformer. Alternate choices for the output transformer are the Toko 458PT-1565 and the Tyco Electronics (M/A-COM) ABACT0018. 5V 10µF + 100pF TO TUNER OR SPLITTER TRANSMIT ENABLE/DISABLE CONTROL GND GND VCC VCC VCC RAMP VIN– ADA4320-1 DIPLEXER 20 2:1* GND VOUT– GND GND GND VOUT+ F-CONNECTOR UPSTREAM VOUT– VIN+ SLEEP DOWNSTREAM 0.1µF 0.1µF 13 3-WIRE (SPI-COMPATIBLE) CONTROL *COILCRAFT PWB-4-BL ALTERNATES: TOKO 458PT-1565 TYCO MABACT0018 POWER-DOWN CONTROL Figure 24. Typical Application Rev. 0 | Page 13 of 16 08707-025 TXEN VOUT+ CLK 0.1µF COMP GND DATEN LPF GND SDATA DAC 100nH 1 8 QPSK/QAM BURST MODULATOR 0.1µF ADA4320-1 OUTLINE DIMENSIONS 2.75 2.65 2.50 4.00 BSC PIN 1 INDICATOR 20 PIN 1 INDICATOR 1 19 5.00 BSC 0.50 BSC 3.75 3.65 3.50 EXPOSED PAD 7 13 1.00 0.90 0.80 0.30 0.25 0.20 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 8 12 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 122409-B TOP VIEW (Chamfer 0.225) 24 Figure 25. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 5 mm Body, Very Thin Quad (CP-24-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4320-1ACPZ-R2 ADA4320-1ACPZ-R7 ADA4320-1ACPZ-RL 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 Package Option CP-24-5 CP-24-5 CP-24-5 Ordering Quantity 250 1,500 5,000 ADA4320-1 NOTES Rev. 0 | Page 15 of 16 ADA4320-1 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08707-0-4/10(0) Rev. 0 | Page 16 of 16