WCMA2016U4X WCMA2016U4X 128K x 16 Static RAM Features more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). • Low Voltage range: — 2.7V-3.3V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1MHz Functional Description The WCMA2016U4X is a high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This device is ideal for portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The WCMA2016U4X is available in a 48-ball FBGA package. Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 10 128K x 16 RAM Array 2048 x 1024 SENSE AMPS • • • • Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). — Typical active current: 7 mA @ f = fmax Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power I/O0 – I/O7 I/O8 – I/O15 BHE WE CE OE BLE A12 A13 A14 A15 A16 A11 COLUMN DECODER Power -Down Circuit CE BHE BLE WCMA2016U4X Pin Configuration[1, 2] FBGA (Top View) 4 5 3 6 A1 A2 NC A A3 A4 CE I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 DNU A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 1 2 BLE OE A0 I/O8 BHE I/O9 Maximum Ratings NC H Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current.................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ...–0.5V to Vccmax + 0.5V Device Range DC Voltage Applied to Outputs in High Z State[3] ....................................–0.5V to VCC + 0.5V WCMA2016U4X Industrial Ambient Temperature VCC –40°C to +85°C 2.7V to 3.3V DC Input Voltage[3] .................................-0.5V to VCC + 0.5V Product Portfolio Power Dissipation (Industrial) VCC Range Product Speed VCC(min.) VCC(typ.)[4] VCC(max.) WCMA2016U4X 2.7V 3.0V 3.3V 70 ns Operating, ICC f = 1 MHz f = fmax Standby (ISB2) Typ.[4] Max. Typ.[4] Max. Typ.[4] Max. 1 mA 2 mA 7 mA 15 mA 1 µA 15 µA Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or Vss to ensure proper application. 3. VIL(min.) = –2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 2 WCMA2016U4X Electrical Characteristics Over the Operating Range WCMA2016U4X Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V VOL Output LOW Voltage IOL = 2.1mA VCC = 2.7V VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = fmax ISB2 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, Vcc=3.3V f = fMAX = 1/tRC f = 1 MHz Typ.[4] Max. 2.4 Unit V 0.4 V 2.2 VCC + 0.5V V –0.3 0.8 V –1 +1 µA –1 +1 µA VCC = 3.6V IOUT = 0 mA CMOS Levels 7 15 1 2 mA 100 1 15 µA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Test Conditions Symbol BGA Units Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 55 °C/W ΘJC 16 °C/W Thermal Resistance (Junction to Case)[5] Note: 5. Tested initially and after any design or process changes that may affect these parameters. 3 WCMA2016U4X AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC Typ OUTPUT GND Rise TIme: 1 V/ns R2 30 pF 90% 10% 90% 10% Fall Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V Unit R1 1.105 KOhms R2 1.550 KOhms RTH 0.645 KOhms VTH 1.75V Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR Description Conditions VCC for Data Retention Min. Typ.[4] 1.0 VCC= 1.0V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0.5 Max. Unit 3.6 V 7.5 µA ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time 0 ns tR[6] Operation Recovery Time 70 ns Data Retention Waveform[7] DATA RETENTION MODE VCC VCC(min) VDR > 1.0 V VCC(min) tR tCDR CE or BHE.BLE Note: 6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 4 WCMA2016U4X Switching Characteristics Over the Operating Range[8] 70 ns Parameter Description Min Max Unit READ CYCLE tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns OE LOW to Low tHZOE OE HIGH to High Z[9, 11] tLZCE CE LOW to Low 70 Z[9] tLZOE ns 10 ns 5 ns 25 Z[9] 10 Z[9, 11] ns ns ns tHZCE CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 70 ns tDBE BHE / BLE LOW to Data Valid 70 ns tLZBE[10] tHZBE BHE / BLE LOW to Low 25 0 Z[9] BHE / BLE HIGH to High ns 5 Z[9, 11] ns ns 25 ns WRITE CYCLE[12] tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW BHE / BLE Pulse Width 60 ns tSD Data Set-Up to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High Z[9, 11] WE HIGH to Low Z[9] 25 10 ns ns Notes: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10ns 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.. 5 WCMA2016U4X Switching Waveforms Read Cycle No. 1 (Address Transistion Controlled) [13, 14] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) [14, 15] ADDRESS tRC CE tPD tHZCE tACE OE BHE/BLE ttLZOE LZOE tHZOE tDOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. 6 WCMA2016U4X Switching Waveforms (continued) Write Cycle No. 1(WE Controlled) [12, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Write Cycle No. 2 (CE Controlled) [12, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O DATAIN VALID NOTE 18 tHZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied. 7 tHD WCMA2016U4X Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [17] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATAI/O NOTE 18 tHD DATAIN VALID tLZWE tHZWE [17] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O DATAIN VALID NOTE 18 8 tHD WCMA2016U4X Typical DC and AC Parameters (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C) Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 14.0 12.0 12.0 10.0 (f = fmax) 60 10.0 50 8.0 40 6.0 TAA (ns) 8.0 ISB (µA) ICC (mA) Access Time vs. Supply Voltage 6.0 4.0 4.0 2.0 0 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) 20 10 2.0 (f = 1 MHz) 30 0 3.0 2.7 3.3 2.7 SUPPLY VOLTAGE (V) 3.0 3.3 SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE Inputs/Outputs H X X X X High Z Deselect/Power-Down Standby (ISB) X X X H H High Z Deselect/Power-Down Standby (ISB) L H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/OO–I/O15) Write Active (ICC) L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) 9 Mode Power WCMA2016U4X Ordering Information Speed (ns) 70 Ordering Code WCMA2016U4X-FF70 Package Name Package Type F 48-Ball Fine Pitch BGA Package Diagrams 48-Ball (7.0 mm x 7.0 mm x 1.2 mm) Fine Pitch BGA, F 10 . Operating Range Industrial WCMA2016U4X Document Title: WCMA2016U4X, 128K x 16 STATIC RAM Document Number: 38-05212 REV. ECN NO. Issue Date Orig. of Change ** 112910 1/17/02 MGN Description of Change New Datasheet 11