PMWD16UN Dual N-channel µTrenchMOS™ ultra low level FET Rev. 02 — 24 March 2005 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology. 1.2 Features ■ Surface mounting package ■ Very low threshold voltage ■ Low profile ■ Fast switching 1.3 Applications ■ Portable appliances ■ Battery management ■ PCMCIA cards ■ Load switching 1.4 Quick reference data ■ VDS ≤ 20 V ■ Ptot ≤ 3.1 W ■ ID ≤ 9.9 A ■ RDSon ≤ 19 mΩ 2. Pinning information Table 1: Pinning Pin Description 1 drain1 (D1) 2, 3 source1 (S1) 4 gate1 (G1) 5 gate2 (G2) 6, 7 source2 (S2) 8 drain2 (D2) Simplified outline Symbol 8 5 D1 S1 D2 G1 S2 G2 msd901 1 4 SOT530-1 (TSSOP8) PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 3. Ordering information Table 2: Ordering information Type number PMWD16UN Package Name Description Version TSSOP8 plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 20 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 20 V VGS gate-source voltage - ±10 V Tsp = 25 °C; VGS = 4.5 V; Figure 2 and 3 [1] - 9.9 A Tsp = 100 °C; VGS = 4.5 V; Figure 2 [1] - 5.9 A peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 [1] - 39.5 A Ptot total power dissipation Tsp = 25 °C; Figure 1 [1] - 3.1 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C drain current (DC) ID IDM Source-drain diode IS source (diode forward) current (DC) Tsp = 25 °C [1] - 2.6 A ISM peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs [1] - 10 A [1] Single device conducting. 9397 750 14724 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 2 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 03aa17 120 03aa25 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 Tsp (°C) 200 0 50 100 150 Tsp (°C) 200 VGS ≥ 4.5 V P tot P der = ------------------------ × 100 % P ° ID I der = --------------------- × 100 % I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature Fig 2. Normalized continuous drain current as a function of solder point temperature 003aaa359 102 ID (A) Limit RDSon = VDS / ID tp = 10 µ s 10 1 ms 10 ms 1 DC 100 ms 1s 10-1 10-2 10-1 1 102 10 VDS (V) Tsp = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9397 750 14724 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 3 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-sp) thermal resistance from junction to solder point Figure 4 - - 40 K/W Rth(j-a) thermal resistance from junction to ambient mounted on a printed-circuit board; minimum footprint; vertical in still air - 100 - K/W 003aaa267 102 Zth(j-sp) (K/W) 10 δ = 0.5 0.2 0.1 0.05 0.02 δ= P 1 tp T single pulse t tp 10-1 10-4 T 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration 9397 750 14724 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 4 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 20 - - V Tj = −55 °C 18 - - V 0.45 0.7 - V Tj = 25 °C - - 1 µA Tj = 150 °C - - 100 µA - - 100 nA Tj = 25 °C - 16 19 mΩ Tj = 150 °C - 27 32 mΩ VGS = 1.8 V; ID = 3.5 A; Figure 7 and 8 - 22 30 mΩ VGS = 2.5 V; ID = 3.5 A; Figure 7 and 8 - 18 22 mΩ ID = 4 A; VDS = 16 V; VGS = 4.5 V; Figure 13 - 23.6 - nC - 2.1 - nC - 6.7 - nC VGS = 0 V; VDS = 16 V; f = 1 MHz; Figure 11 - 1366 - pF - 339 - pF - 239 - pF Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 and 10 IDSS drain-source leakage current VDS = 20 V; VGS = 0 V IGSS gate-source leakage current VGS = ±10 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 4.5 V; ID = 3.5 A; Figure 7 and 8 Dynamic characteristics Qg(tot) total gate charge Qgs gate-source charge Qgd gate-drain (Miller) charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) tf VDS = 10 V; RL = 10 Ω; VGS = 4.5 V; RG = 6 Ω - 14 - ns - 22 - ns turn-off delay time - 56 - ns fall time - 33 - ns - 0.67 1.2 V - 45 - ns - 33 - nC Source-drain diode VSD source-drain (diode forward) voltage IS = 4 A; VGS = 0 V; Figure 12 trr reverse recovery time Qr recovered charge IS = 4 A; dIS/dt = −100 A/µs; VGS = 0 V; VR = 20 V 9397 750 14724 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 5 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 003aaa268 10 1.8 4.5 ID (A) 003aaa269 10 ID (A) 8 8 VGS (V)= 1.3 Tj = 150 °C 6 6 4 1.2 4 2 1.1 2 25 °C 1.0 0 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 0 Tj = 25 °C 1.5 VGS (V) 2 Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aaa270 1.1 RDSon (mΩ) 1 Tj = 25 °C and 150 °C; VDS > ID × RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 80 0.5 1.2 03aa27 2 1.3 a 60 1.5 40 1 VGS (V) = 1.8 20 0.5 2.5 4.5 0 0 2 4 6 8 ID (A) 10 0 -60 Tj = 25 °C 60 120 Tj (°C) 180 R DSon a = ----------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature 9397 750 14724 Product data sheet 0 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 6 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 03aj65 1.2 VGS(th) 03aj64 10−3 ID (A) (V) max 0.9 10−4 typ 0.6 min min 10−5 typ max 0.3 0 -60 10−6 0 60 120 Tj (°C) 0 180 0.2 0.4 0.6 0.8 1 VGS (V) Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature 003aaa271 104 Fig 10. Sub-threshold drain current as a function of gate-source voltage 003aaa272 10 IS (A) C (pF) 8 150 °C 6 Ciss 103 Tj = 25 °C 4 Coss 2 Crss 102 10-1 1 102 10 0 0 0.2 0.4 0.6 VDS (V) 1 VSD (V) Tj = 25 °C and 150 °C; VGS = 0 V VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values 9397 750 14724 Product data sheet 0.8 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 7 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 003aaa273 5 VGS (V) 4 3 2 1 0 0 5 10 15 20 25 QG (nC) ID = 4 A; VDD = 16 V Fig 13. Gate-source voltage as a function of gate charge; typical values 9397 750 14724 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 8 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 7. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 E A D X c y HE v M A Z 8 5 A2 A (A3) A1 pin 1 index θ Lp L detail X 1 4 e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.85 0.25 0.30 0.19 0.20 0.13 3.1 2.9 4.5 4.3 0.65 6.5 6.3 0.94 0.7 0.5 0.1 0.1 0.1 0.70 0.35 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT530-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-24 03-02-18 MO-153 Fig 14. Package outline SOT530-1 (TSSOP8) 9397 750 14724 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 9 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 8. Revision history Table 6: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes PMWD16UN_2 20050324 Product data sheet - PMWD16UN-01 Modifications: PMWD16UN-01 • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • • • • • ID and Ptot data revised in Section 1.4 “Quick reference data”. ID, IDM, Ptot, IS and ISM data revised in Table 3 “Limiting values”. Figure 3 revised in Section 4 “Limiting values”. Rth(j-sp) data revised in Table 4 “Thermal characteristics”. Figure 4 revised in Section 5 “Thermal characteristics” Figure 5, 7 and 12 revised in Section 6 “Characteristics” 20021220 Product data - 9397 750 14724 Product data sheet 9397 750 14724 9397 750 10831 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 10 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 9. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 11. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 13. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14724 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 24 March 2005 11 of 12 PMWD16UN Philips Semiconductors Dual N-channel µTrenchMOS™ ultra low level FET 14. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 24 March 2005 Document number: 9397 750 14724 Published in The Netherlands