AD AD9876-EB

a
A
FEATURES
Low Cost 3.3 V CMOS Mixed-Signal Front End (MxFE™)
Converter for Broadband Modems
10-/12-Bit D/A Converter (TxDAC+®)
64/32 MSPS Input Word Rate
2/4 Interpolating LPF or BPF Transmit Filter
128 MSPS DAC Output Update Rate
Wide (26 MHz) Transmit Bandwidth
Power-Down Mode
10-/12-Bit 50 MSPS A/D Converter
Fourth Order Low-Pass Filter 12 MHz or 26 MHz
with Bypass
–6 dB to +36 dB Programmable Gain Amplifier
Internal Clock Multiplier (PLL)
Clock Outputs
Voltage Regulator Controller
48-Lead LQFP Package
APPLICATIONS
Powerline Networking
Home Phone Networking
xDSL
Broadband Wireless
Home RF
PRODUCT DESCRIPTION
The AD9876 is a single-supply broadband modem mixed-signal
front end (MxFE) IC. The device contains a transmit path
interpolation filter and DAC and a receive path PGA, LPF, and
ADC supporting a variety of broadband modem applications.
Also on-chip is a PLL clock multiplier that provides all required
clocks from a single crystal or clock input. The AD9876 provides
12-bit converter performance on both the Tx and Rx path.
The TxDAC+ uses a selectable digital 2× or 4× interpolation
low-pass or band-pass filter to further oversample transmit data
and reduce the complexity of analog reconstruction filtering.
The transmit path signal bandwidth can be as high as 26 MHz
at an input data rate of 64 MSPS. The 12-bit DAC provides
differential current outputs for optimum noise and distortion
performance. The DAC full-scale current can be adjusted from
2 to 20 mA by a single resistor, providing 20 dB of additional
gain range.
The receive path consists of a PGA, LPF, and ADC. The PGA has
a gain range of –6 dB to +36 dB, programmable in 2 dB steps,
adding 42 dB of dynamic range to the receive path. The receive
Broadband Modem
Mixed-Signal Front End
AD9876
FUNCTIONAL BLOCK DIAGRAM
PWR DN
AD9876
Tx QUIET
GAIN
Tx [5:0]
Tx SYNC
Tx
MUX
12
Kx INTERPOLATION
LPF/BPF
12
PLL-A
L
CLK-A
Tx+
TxDAC+
Tx–
VREF
CLOCK GEN
GATE
FB
VRC
OSCIN
CLK-B
PLL-B
M/N
Rx SYNC
Rx
MUX
Rx [5:0]
SPORT
3
12
ADC
XTAL
PGA
LPF
PGA
Rx+
Rx–
REGISTER
CONTROL
path LPF cutoff frequency can be programmed to either 12 MHz
or 26 MHz. The filter cutoff frequency can also be tuned or
bypassed where filter requirements differ. The 12-bit ADC uses
a multistage differential pipeline architecture to achieve excellent
dynamic performance with low power consumption.
The AD9876 provides a voltage regulator controller (VRC) that
can be used with an external power MOSFET transistor to form
a cost-effective 1.3 V linear regulator.
The digital transmit and receive ports are each multiplexed to a
bus width of six bits and are clocked at a frequency of twice the
12-bit word rate.
The AD9876 ADC and/or DAC can also be used at sampling
rates as high as 64 MSPS in a 6-bit resolution nonmultiplexed mode.
The AD9876 is pin compatible with the 10-bit AD9875. Both are
available in a space-saving 48-lead LQFP package. They are specified over the industrial (–40°C to +85°C) temperature range.
MxFE is a trademark of Analog Devices, Inc.
TxDAC+ is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
2Fax: 781/326-8703
© Analog Devices, Inc., 2002
f
= 32 MHz, f = 128 MHz, Gain = –6 dB, R
single-ended load, unless otherwise noted. )
AD9876–SPECIFICATIONS (V100=3.3DACV 10%,
S
OSCIN
DAC
SET =
4.02 k,
Parameter
Temp
Test
Level
OSCIN CHARACTERISTICS
Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
Full
Full
25°C
25°C
II
II
III
III
CLOCK OUTPUT CHARACTERISTICS
CLK A Jitter (fCLKA Derived from PLL)
CLK A Duty Cycle
CLK B Jitter (fCLKB Derived from PLL)
CLK B Duty Cycle
25°C
25°C
25°C
25°C
III
III
III
III
14
50 ± 5
33
50 ± 5
ps rms
%
ps rms
%
Full
II
86
fDAC Cycles
Full
Full
II
II
13
26
MHz
MHz
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
II
II
II
II
II
II
III
III
III
III
Full
25°C
25°C
25°C
I
III
III
III
25°C
25°C
III
III
NA
Full
NA
NA
II
NA
7.5
Full
Full
II
II
–1.0
–4.5
± 0.25
± 0.5
Full
Full
25°C
25°C
25°C
I
I
III
III
III
60.8
9.8
63.2
10.2
64
–70
72
dB
Bits
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
56
9.3
59
–63
68
dB
Bits
dB
dB
dB
Tx CHARACTERISTICS
Tx Path Latency, 4× Interpolation
Interpolation Filter Bandwidth (–0.1 dB)
4× Interpolation, LPF
2× Interpolation, LPF
TxDAC
Resolution
Conversion Rate
Full-Scale Output Current
Voltage Compliance Range
Gain Error
Output Offset (Single-Ended)
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 10 MHz Signal
Signal-to-Noise and Distortion (SINAD)
10 MHz Analog Out AD9876 (20 MHz BW)
Wideband SFDR (to Nyquist, 64 MHz Max)
5 MHz Analog Out
10 MHz Analog Out
Narrow-Band SFDR (3 MHz Window):
10 MHz Analog Out
IMD (f1 = 6.9 MHz, f2 = 7.1 MHz)
Rx PATH CHARACTERISTICS
Resolution
Conversion Rate
Pipeline Delay, ADC Clock Cycles
DC Accuracy
Differential Nonlinearity
Integral Nonlinearity
Dynamic Performance (ADC Clocked Direct)
(AIN = –0.5 dBFS, f = 5 MHz)
@ fOSCIN = 32 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Dynamic Performance (ADC Clocked, PLLB/2)
(AIN = –0.5 dBFS, f = 5 MHz)
@ FPLLB/2 = 50 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
–2–
Min
10
40
Typ
50
3
100
Max
Unit
64
60
MHz
%
pF
M⍀
12
10
2
–0.5
–5
0
62.5
10
±2
2
±1
±2
5
–100
128
20
+1.5
+5
5
Bits
MHz
mA
V
% FS
µA
LSB
LSB
pF
dBc/Hz
65
dB
80
74
dBc
dBc
88
–80
dBc
dBFS
12
64
Bits
MHz
Cycles
+1.0
+3.5
LSB
LSB
5.5
REV. A
AD9876
Parameter
Temp
Test
Level
Rx PATH GAIN/OFFSET
Minimum Programmable Gain
Maximum Programmable Gain (12 MHz Filter)
Maximum Programmable Gain (26 MHz Filter)
Gain Step Size
Gain Step Accuracy
Gain Range Error
Offset Error, PGA Gain = 0 dB
Absolute Gain Error
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
III
III
III
–6
36
30
2
± 0.4
± 1.0
± 10
± 0.8
dB
dB
dB
dB
dB
dB
LSB
dB
Rx PATH INPUT CHARACTERISTICS
Input Voltage Range
Input Capacitance
Differential Input Resistance
Input Bandwidth (–3 dB)
Input Referred Noise (at –36 dB Gain with Filter)
Input Referred Noise (at –6 dB Gain with Filter)
Common-Mode Rejection
Full
25°C
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
III
III
4
4
270
50
16
684
40
Vppd
pF
Ω
MHz
µV rms
µV rms
dB
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
12
±7
20
± 1.0
30
MHz
%
dB
dB
ns
25°C
25°C
III
III
150
–68
ns
dBc
Rx PATH LPF (Low Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 22 MHz
Pass-Band Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
Min
Typ
Max
Unit
Rx PATH LPF (High Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 44 MHz
Pass-Band Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
26
±7
20
± 1.2
15
MHz
%
dB
dB
ns
25°C
25°C
III
III
80
–65
ns
dBc
Rx PATH DIGITAL HPF
Latency (ADC Clock Source Cycles)
Roll-Off in Stop Band
–3 dB Frequency
Full
Full
Full
II
II
II
1
6
fADC /400
Cycle
dB/Octave
Hz
Rx PATH DISTORTION PERFORMANCE
IMD: f1 = 6.5 MHz, f2 = 7.7 MHz
12 MHz Filter : 0 dB Gain
: 30 dB Gain
26 MHz Filter : 0 dB Gain
: 30 dB Gain
25°C
25°C
25°C
25°C
III
III
III
III
–65
–57
–65
–56
dBc
dBc
dBc
dBc
Full
Full
II
II
200
1
ns
µs
Full
Full
II
II
400
200
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
II
40
10
1000
1
1
200
2
5
µs
µs
µs
µs
µs
ns
µs
fOSCIN Cycles
POWER-DOWN/DISABLE TIMING
DAC IOUT OFF after Tx QUIET Asserted
DAC IOUT ON after Tx QUIET De-Asserted
Power-Down Delay (Active to Power-Down)
DAC
Interpolator
Power-Up Delay (Power-Down to Active)
DAC
PLL
ADC
PGA
LPF
Interpolator
VRC
Minimum RESET Pulsewidth Low (tRL)
REV. A
–3–
AD9876
Parameter
Temp
Test
Level
Min
Tx PATH INTERFACE
Maximum Input Nibble Rate, 2× Interpolation
Tx Setup Time (tSU)
Tx Hold Time (tHD)
Full
Full
Full
II
II
II
128
3.0
0
Rx PATH INTERFACE
Maximum Output Nibble Rate
Rx Data Valid Time (tVT)
Rx Data Hold Time (tHT)
Full
Full
Full
II
II
II
110
SERIAL CONTROL BUS
Maximum SCLK Frequency (fSCLK)
Clock Pulsewidth High (tPWH)
Clock Pulsewidth Low (tPWL)
Clock Rise/Fall Time
Data/Chip-Select Setup Time (tDS)
Data Hold Time (tDH)
Data Valid Time (tDV)
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
25
18
18
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
25°C
II
II
II
II
III
VDRVDD – 0.7
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage
Logic “0” Voltage
Digital Output Rise/Fall Time
Full
Full
Full
II
II
II
VDRVDD – 0.6
Full
25°C
25°C
25°C
I
III
III
III
262
172
77
185
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
III
III
III
110
55
2
33
18
8
24
1
Full
Full
II
II
19
10
25°C
25°C
III
III
62
54
dB
dB
RECEIVE-TO-TRANSMIT ISOLATION
(10 MHz, Full-Scale Sine Wave Output/Output)
Isolation: Tx Path to Rx Path, Gain = +36 dB
Isolation: Rx Path to Tx Path, Gain = –6 dB
25°C
25°C
III
III
–75
–70
dB
dB
VOLTAGE REGULATOR CONTROLLER
Output Voltage (VFB with SI2301 Connected)
Line Regulation (∆VFB%/∆VDVDD% × 100%)
Load Regulation (∆VFB/∆ILOAD)
Maximum Load Current (ILOAD)
Full
25°C
25°C
Full
I
III
III
II
POWER SUPPLY
All Blocks Powered Up
IS_TOTAL (Total Supply Current)
IS_TOTAL (Tx QUIET Pin Asserted)
Digital Supply Current (IDRVDD + IDVDD)
Analog Supply Current (IAVDD)
Power Consumption of Functional Blocks:
Rx LPF
ADC and SPGA
Rx Reference
Interpolator
DAC
PLL-B
PLL-A
Voltage Regulator Controller
All Blocks Powered Down
Supply Current IS, fOSCIN = 32 MHz
Supply Current IS, fOSCIN Idle
Power Supply Rejection
Tx Path (∆VS = ⫾10%)
Rx Path (∆VS = ⫾10%)
Typ
Max
MHz
ns
ns
3.0
MHz
ns
ns
1
MHz
ns
ns
ms
ns
ns
ns
1.5
25
0
20
0.4
12
12
3
0.4
2.5
1.5
1.25
250
Unit
1.30
100
60
288
V
V
µA
µA
µF
V
V
ns
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
22
12
1.35
mA
mA
V
%
mΩ
mA
Specifications subject to change without notice.
–4–
REV. A
AD9876
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Power Supply (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V
Analog Inputs . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
I – Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for industrial
operating temperature range (–40°C to +85°C).
II – Parameter is guaranteed by design and/or characterization testing.
III – Parameter is a typical value only.
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Resistance
THERMAL CHARACTERISTICS
48-Lead LQFP
␪JA = 57°C/W
␪JC = 28°C/W
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9876BST
AD9876-EB
AD9876BSTRL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
48-Lead LQFP
Evaluation Board
BST Reel
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9876 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
WARNING!
ESD SENSITIVE DEVICE
AD9876
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
2
3
4
5, 38, 47
6, 9, 39, 42, 43, 46
7
8
10
11
12
13
14
15
16
17
18
19–24
25
26
27
28
29–34
35
36
37
40
41
44
45
48
OSCIN
SENABLE
SCLK
SDATA
AVDD
AVSS
Tx+
Tx–
FSADJ
REFIO
PWR DN
DVSS
DVDD
FB
GATE
GAIN
Tx QUIET
Tx [5:0]
Tx SYNC
CLK-A
CLK-B
Rx SYNC
Rx[5:0]
DRVDD
DRVSS
RESET
REFB
REFT
Rx+
Rx–
XTAL
Crystal Oscillator Inverter Input
Serial Bus Enable Input
Serial Bus Clock Input
Serial Bus Data I/O
Analog 3.3 V Power Supply
Analog Ground
Transmit DAC+ Output
Transmit DAC– Output
DAC Full-Scale Output Current Adjust with External Resistor
DAC Band Gap Decoupling Node
Power-Down Input
Digital Ground
Digital 3.3 V Power Supply
Regulator Feedback Input
Regulator Output to FET Gate
Transmit Data Port (Tx [5:0]) Mode Select Input
Transmit Quiet Input
Transmit Data Input
Transmit Synchronization Strobe Input
L × fOSCIN Clock Output
M/N × fOSCIN Clock Output
Receive Data Synchronization Strobe Output
Receive Data Output
Digital I/O 3.3 V Power Supply
Digital I/O Ground
Reset Input
ADC Reference Decoupling Node
ADC Reference Decoupling Node
Receive Path + Input
Receive Path – Input
Crystal Oscillator Inverter Output
RESET
AVDD
AVSS
REFB
REFT
AVSS
AVSS
Rx+
Rx–
AVSS
AVDD
XTAL
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
OSCIN 1
SENABLE 2
36
DRVSS
35
DRVDD
SCLK 3
34
Rx [0]
SDATA 4
33
Rx [1]
AVDD 5
32
Rx [2]
31
Rx [3]
30
Rx [4]
Tx– 8
29
Rx [5]
AVSS 9
28
Rx SYNC
FSADJ 10
27
CLK-B
REFIO 11
26
CLK-A
PWR DN 12
25
Tx SYNC
PIN 1
IDENTIFIER
AD9876
AVSS 6
TOP VIEW
(Not to Scale)
Tx+ 7
–6–
Tx [0]
Tx [1]
Tx [2]
Tx [3]
Tx [4]
Tx [5]
Tx QUIET
GAIN
GATE
FB
DVSS
DVDD
13 14 15 16 17 18 19 20 21 22 23 24
REV. A
AD9876
DEFINITIONS OF SPECIFICATIONS
CLOCK JITTER
The clock jitter is a measure of the intrinsic jitter of the PLL
generated clocks. It is a measure of the jitter from one rising
and of the clock with respect to another edge of the clock nine
cycles later.
DIFFERENTIAL NONLINEARITY ERROR
(DNL, NO MISSING CODES)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes, respectively, must be present over all operating ranges.
OFFSET ERROR
First transition should occur for an analog value 1/2 LSB above
negative full scale. Offset error is defined as the deviation of the
actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur for an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between the first and
last code transitions and the ideal difference between the first
and last code transitions.
INPUT REFERRED NOISE
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
PHASE NOISE
Single-sideband phase noise power density is specified relative to
the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly on a generated
single tone with a spectrum analyzer that supports noise marker
measurements. It detects the relative power between the carrier
and the offset (1 kHz) sideband noise and takes the resolution
bandwidth (rbw) into account by subtracting 10 log(rbw). It also
adds a correction factor that compensates for the implementation
of the resolution bandwidth, log display, and detector characteristic.
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in LSB
and converted to an equivalent voltage. This results in a noise
figure that can be directly referred to the Rx input of the AD9876.
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
SINAD is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula:
N = (SINAD – 1.76) dB 6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
SIGNAL-TO-NOISE RATIO (SNR)
OUTPUT COMPLIANCE RANGE
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation, resulting in nonlinear performance or breakdown.
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
SPURIOUS–FREE DYNAMIC RANGE (SFDR)
The difference, in dB, between the rms amplitude of the DACs
output signal (or ADCs input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth, unless
otherwise noted).
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available.
REV. A
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
POWER SUPPLY REJECTION
Power supply rejection specifies the converters maximum
full-scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.
–7–
AD9876 –Typical Tx Digital Filter Performance Characteristics
10
10
0
0
INTERPOLATION
FILTER
–10
–10
–30
–40
INCLUDING SIN(X)/X
–50
–60
–30
INCLUDING SIN(X)/X
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
NORMALIZED – fs
0.8
0.9
–100
0.0
1.0
TPC 1. 4 Low-Pass Interpolation Filter
0.2
0.3
0.4
0.5
0.6
0.7
NORMALIZED – fS
0.8
0.9
1.0
10
INTERPOLATION
FILTER
0
INTERPOLATION
FILTER
0
–10
–10
–20
MAGNITUDE – dB
–20
MAGNITUDE – dB
0.1
TPC 4. 2 Band-Pass Interpolation Filter, fS /2 Modulation, Adjacent Image Preserved
10
INCLUDING SIN(X)/X
–30
–40
–50
–60
–30
–50
–60
–70
–80
–80
–90
–90
0.1
0.2
0.3
0.4
0.5
0.6
0.7
NORMALIZED – fS
0.8
0.9
–100
0.0
1.0
TPC 2. 2 Low-Pass Interpolation Filter
INCLUDING SIN(X)/X
–40
–70
–100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
NORMALIZED – fS
0.8
0.9
1.0
TPC 5. 4 Band-Pass Interpolation Filter, fS /4 Modulation,
Lower Image Preserved
10
10
INTERPOLATION
FILTER
0
–10
–10
–20
–20
–30
INCLUDING SIN(X)/X
–40
–50
–60
–30
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
NORMALIZED – fS
0.8
0.9
INTERPOLATION INCLUDING SIN(X)/X
FILTER
0
MAGNITUDE – dB
MAGNITUDE – dB
INTERPOLATION
FILTER
–20
MAGNITUDE – dB
MAGNITUDE – dB
–20
–100
0.0
1.0
TPC 3. 4 Band-Pass Interpolation Filter, fS /2 Modulation, Adjacent Image Preserved
0.1
0.2
0.3
0.4
0.5
0.6
0.7
NORMALIZED – fS
0.8
0.9
1.0
TPC 6. 4 Band-Pass Interpolation Filter, fS /4 Modulation,
Upper Image Preserved
–8–
REV. A
AD9876
Typical AC Characteristics Curves for TxDAC+( (R
SET
= 4.02 k, RDAC = 100 )
10
80
0
75
–10
MAGNITUDE – dBc
MAGNITUDE – dBc
–20
–30
–40
–50
–60
70
fDATA = 50MSPS
65
60
–70
fDATA = 32MSPS
55
–80
–90
0
13
26
38
51
64
77
90
102
115
50
128
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
fOUT – MHz
FREQUENCY – MHz
TPC 7. Single-Tone Spectral Plot @ fDATA = 32 MSPS,
fOUT = 5 MHz, 4 LPF
TPC 10. Out-of-Band SFDR vs. fOUT @ fDATA = 32 MSPS
and 50 MSPS
10
90
0
85
–20
MAGNITUDE – dBc
MAGNITUDE – dBc
–10
–30
–40
–50
–60
80
fDATA = 32MSPS
75
70
fDATA = 50MSPS
–70
65
–80
–90
0
10
20
30
40
50
60
70
FREQUENCY – MHz
80
90
60
100
1
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
TPC 11. In-Band SFDR vs. fOUT @ fDATA = 32 MSPS
and 50 MSPS
10
10
0
0
–10
–10
–20
–20
MAGNITUDE – dBc
MAGNITUDE – dBc
3
fOUT – MHz
TPC 8. Single-Tone Spectral Plot @ fDATA = 50 MSPS,
fOUT = 11 MHz, 2 LPF
–30
–40
–50
–60
–30
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
6.5
–100
6.5
6.6
6.7
6.8
6.9
7.0
7.1
7.2
FREQUENCY – MHz
7.3
7.4
7.5
6.6
6.7
6.8
6.9
7.0
7.1
7.2
7.3
7.4
7.5
FREQUENCY – MHz
TPC 9. Dual-Tone Spectral Plot @ fDATA = 32 MSPS,
fOUT = 6.9 MHz and 7.1 MHz, 4 LPF
REV. A
2
TPC 12. Dual-Tone Spectral Plot @ fDATA = 50 MSPS,
fOUT = 6.9 MHz and 7.1 MHz, 2 LPF
–9–
AD9876
Typical AC Characteristics Curves for TxDAC (R
SET
= 4.02 k, RDAC = 100 )
10
10
0
0
–10
–10
MAGNITUDE – dBc
MAGNITUDE – dBc
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–80
–60
–90
–100
–70
–1
0
1
2
3
4
5
6
FREQUENCY OFFSET – kHz
7
8
3
9
TPC 13. Phase Noise Plot @ fDATA = 32 MSPS,
fOUT = 10 MHz, 4 LPF
5
7
9
11
13
15
17
FREQUENCY – MHz
19
21
23
TPC 15. In-Band Multitone Spectral Plot
@ fDATA = 50 MSPS, fOUT = k 195 kHz, 2 LPF
10
10
0
0
–10
–10
MAGNITUDE – dBc
MAGNITUDE – dBc
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–80
–60
–90
–100
–70
–1
0
1
2
3
4
5
6
FREQUENCY OFFSET – kHz
7
8
3
9
TPC 14. Phase Noise Plot @ fDATA = 50 MSPS,
fOUT = 10 MHz, 2 LPF
11
21
31
41
51
61
71
FREQUENCY – MHz
81
91
101
TPC 16. Wideband Multitone Spectral Plot
@ fDATA = 50 MSPS, fOUT = k 195 kHz, 2 LPF
–10–
REV. A
AD9876
40
18
38
17
36
16
34
15
FREQUENCY – MHz
FREQUENCY – MHz
Typical Tx Digital Filter Performance Characteristics
32
30
28
26
14
13
12
11
24
10
22
9
20
8
64
80
96
112
128
144
160
176
192
48
TPC 17. Rx vs. Tuning Target, fADC = 32 MHz,
LPF with Wideband Rx LPF = 1
64
80
96
112
128
144
160
176
192
TPC 19. fC vs. Tuning Target, fADC = 32 MHz,
LPF with Wideband Rx LPF = 0
2.5
0.60
2.4
0.40
2.3
2.2
MAGNITUDE – dB
MAGNITUDE – dB
0.20
0.00
–0.20
–0.40
2.1
2.0
1.9
1.8
1.7
–0.60
1.6
1.5
–6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
VGA GAIN – dB
–0.80
–6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
VGA GAIN – dB
TPC 20. PGA Gain Step Size vs. Gain
TPC 18. PGA Gain Error vs. Gain
REV. A
–11–
AD9876
Typical AC Characterization Curves for Rx Path
LOG MAG
5dB/REF – 0dB
DELAY
–3.0dB
10ns/REF 0s
72.188ns
9.0MHz
10.8MHz
0
0
1MHz
10MHz
1MHz
100MHz
10MHz
100MHz
TPC 21. Rx LPF Frequency Response, Low fC
Nominal Tuning Targets
TPC 24. Rx LPF Group Delay, Low fC Nominal
Tuning Targets
LOG MAG
DELAY
5dB/REF 0dB
–3.0dB
5ns/REF 0s
34.431ns
22.5MHz
26.5MHz
0
1MHz
10MHz
0
1MHz
100MHz
10MHz
100MHz
TPC 22. Rx LPF Frequency Response, High fC
Nominal Tuning Targets
TPC 25. Rx LPF Group Delay, High fC, Nominal
Tuning Targets
LOG MAG
DELAY
5dB/REF 0dB
–3.0dB
10ns/REF 0s
51.244ns
14.5MHz
14.5MHz
0
0
1MHz
10MHz
1MHz
100MHz
10MHz
100MHz
TPC 26. Rx LPF Group Delay, Low fC, 0 60 and
0 96 Tuning Targets
TPC 23. Rx LPF Frequency Response, Low fC
0 60 and 0 96 Turning Targets
–12–
REV. A
AD9876
Typical AC Characterization Curves for Rx Path (continued)
LOG DELAY
5dB/REF –2dB
33.5MHz
LOG DELAY
–5.1933dB
5ns/REF 0s
29.97ns
29.5MHz
0
COR
AVG
16
1MHz
10MHz
1MHz
100MHz
5dB/REF 0dB
78.8MHz
10MHz
100MHz
TPC 30. Rx LPF Group Delay, High fC, 0 60 and
0 96 Tuning Targets
TPC 27. Rx LPF Frequency Response, High fC,
0 60 and 0 96 Tuning Targets
LOG MAG
0
–3.01dB
700
0
600
COR
AVG
16
ADC INPUT RMS NOISE – V
FILTER ENABLED
500
400
300
200
FILTER BYPASSED
100
0
10kHz
100kHz
–6
1MHz
TPC 28. Rx HPF Frequency Response, fADC = 32 MHz
4
14
GAIN SETTING – dB
24
34
TPC 31. Rx Input Referred Noise vs. Gain
@ fADC = 32 MSPS, fIN = 1 MHz
4000
4000
3800
3800
3600
3600
ADC OUTPUT CODE
ADC OUTPUT CODE
fADC = 50MHz
fADC = 50MHz
3400
3200
3000
fADC = 32MHz
3400
3200
3000
fADC = 32MHz
2800
2800
2600
2600
2400
2400
0
5
10
15
20
25
ADC CLOCK CYCLES
30
35
0
40
10
15
20
25
ADC CLOCK CYCLES
30
35
40
TPC 32. Rx Path Setting, 1/2 Scale Falling Step
with Gain Change
TPC 29. Rx Path Setting, 1/2 Scale Rising Step
with Gain Change
REV. A
5
–13–
AD9876
Typical AC Characterization Curves for Rx Path (Gain = –6 dB, f
11.0
IN
= 5 MHz)
–50
70
10.5
fOSCIN
fOSCIN
65
–55
ENOB
9.5
9.0
fPLLB/2
8.5
MAGNITUDE – dB
MAGNITUDE – dB
10.0
60
fPLLB/2
55
50
–60
fOSCIN
–65
fPLLB/2
–70
8.0
45
–75
7.5
7.0
10
30
20
40
40
10
50
30
20
40
–80
10
50
30
20
fS – MSPS
fS – MHz
TPC 33. Rx Path ENOB vs. fADC
–50
70
10.5
fOSCIN
65
fOSCIN
50
TPC 35. Rx Path THD vs. fADC
TPC 34. Rx Path SNR vs. fADC
11.0
40
fS – MSPS
–55
ENOB
9.5
9.0
fPLLB/2
8.5
MAGNITUDE – dB
MAGNITUDE – dB
10.0
60
55
fPLLB/2
50
fPLLB/2
–60
–65
–70
8.0
fOSCIN
45
–75
7.5
7.0
0
2
4
6
8
40
10 12 14 16 18 20
0
2
4
6
8
–80
10 12 14 16 18 20
0
2
4
6
fIN – MHz
fIN – MHz
11.0
10 12 14 16 18 20
fIN – MHz
TPX 37. Rx Path SNR vs. fIN
TPC 36. Rx Path ENOB vs. fIN
8
TPC 38. Rx Path THD vs. fIN
–50
70
10.5
fPLLB/2
fOSCIN
MAGNITUDE – dB
MAGNITUDE – dB
ENOB
9.5
9.0
–55
65
fOSCIN
10.0
60
fPLLB/2
–60
fPLLB/2
–65
55
8.5
8.0
–6
fOSCIN
0
6
12
18
GAIN – dB
24
30
TPC 39. Rx Path ENOB vs. Gain
36
50
–6
0
6
12
18
GAIN – dB
24
30
TPC 40. Rx Path SNR vs. Gain
–14–
36
–70
–6
0
6
12
18
GAIN – dB
24
30
36
TPC 41. Rx Path THD vs. Gain
REV. A
AD9876
TRANSMIT PATH
The AD9876 transmit path consists of a digital interface port, a
programmable interpolation filter, and a transmit DAC. All
clock signals required by these blocks are generated from the
fOSCIN signal by the PLL-A clock generator. The block diagram
below shows the interconnection between the major functional
components of the transmit path.
AD9876
Tx QUIET
GAIN
Tx [5:0]
Tx SYNC
Tx
DEMUX
12
Kx INTERPOLATION
LPF/BPF
12
TxDAC+
Tx+
CLK-A
fCLK-A
where K is the interpolation factor that can be programmed to be
1, 2, or 4. When the Tx multiplexer is disabled, the frequency of
the Tx Port is:
fCLK − A = fDAC K = L × fOSCIN /K
Note, this will result in a 6-bit data path.
Tx–
INTERPOLATION FILTER
fDAC = L ⴛ fOSCIN
PLL-A
ⴛL
The transmit path expects a new half-word of data at the rate
of fCLK-A. When the Tx multiplexer is enabled, the frequency
of Tx Port is:
fCLK − A = 2 × fDAC K = 2 × L × fOSCIN /K
fOSCIN
CLOCK GEN
OSCIN
XTAL
Figure 1. Transmit Path Block Diagram
DIGITAL INTERFACE PORT
The interpolation filter can be programmed to run at 2× and 4×
upsampling ratios in each of three different modes. The transfer
functions of these six configurations are shown in TPCs 1–6.
The X-axis of each of these figures corresponds to the frequency
normalized to fDAC. These transfer functions show both the
discrete time transfer function of the interpolation filters alone
and with the SIN(x)/x transfer function of the DAC. The
interpolation filter can also be programmed into a passthrough mode if no interpolation filtering is desired.
The Transmit Digital Interface Port has several modes of operation. In its default configuration, the Tx Port accepts six bit
nibbles through the Tx [5:0] and Tx SYNC pins and demultiplexes the data into 12-bit words before passing it to the
interpolation filter. The input data is sampled on the rising edge
of fCLK-A.
The contents of the interpolation filter are not cleared by
hardware or software resets. It is recommended to “flush” the
transmit path with zeros before transmitting data.
Additional programming options for the Tx Port allow: sampling
the input data on the falling edge of fCLK-A, inversion or disabling
of fCLK-A, and reversing the order of the nibbles. Also, the Tx Port
interface can be controlled by the GAIN pin to provide direct
access to the Rx Path Gain Adjust Register. All of these modes
are fully described in the Register Programming Definitions section of this data sheet.
Latency – The number of clock cycles from the time a digital
impulse is written to the DAC until the peak value is output at
the T+ and T– pins.
The data format is twos complement, as shown below:
011 . . 11: Maximum
000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB
The table below contains the following parameters as a function
of the mode that it is programmed.
Flush – The number of clock cycles from the time a digital
impulse is written to the DAC until the output at the Tx+ and
Tx– pins settles to zero.
fLOWER (0.1 dB, 3 dB) – This indicates the lower 0.1 dB or 3 dB
cutoff frequency of the interpolation filter as a fraction of fDAC,
the DAC sampling frequency.
fUPPER (0.1 dB, 3 dB) – This indicates the upper 0.1 dB or 3 dB
cutoff frequency of the interpolation filter as a fraction of fDAC,
the DAC sampling frequency.
Table I. Interpolation Filter Parameters vs. Mode
100 . . 00: Minimum
The data can be translated to a straight binary data format by
simply inverting the most significant bit.
The timing of the interface is fully described in the Transmit
Port Timing section of this data sheet.
PLL-A CLOCK DISTRIBUTION
Figure 1 shows the clock signals used in the transmit path. The
DAC sampling clock, fDAC, is generated by PLL-A. fDAC has a
frequency equal to L × fOSCIN, where fOSCIN is the internal signal
generated either by the crystal oscillator when a crystal is connected between the OSCIN and XTAL pins, or by the clock that
is fed into the OSCIN pin, and L is the multiplier programmed
through the serial port. L can have the values of 1, 2, 4, or 8.
REV. A
Register 7 [7:4] 0 ⴛ 0
Mode
Latency, fDAC
Clock Cycles
Flush, fDAC
Clock Cycles
fLOWER, 0.1 dB
0ⴛ1
0ⴛ4
0ⴛ5
0ⴛ8
0ⴛC
4 × LPF 2 × LPF 4 × BPF 2 × BPF 4 × BPF 4 × BPF
Adj.
Adj.
Lower Upper
86
30
86
3
86
86
128
48
128
48
148
142
0
0
0.398
0.276
fUPPER, 0.1 dB
0.102
0.204
0.602
0.724
fLOWER, 3 dB
0
0
0.381
0.262
fUPPER, 3 dB
0.119
0.238
0.619
0.738
0.148/
0.774
0.226/
0.852
0.131/
0.757
0.243/
0.869
0.274/
0.648
0.352/
0.762
0.257/
0.631
0.369/
0.743
–15–
AD9876
D/A CONVERTER
The AD9876 DAC provides differential output current on the
Tx+ and Tx– pins. The value of the output currents are complementary, meaning that they will always sum to IFS, the full-scale
current of the DAC. For example, when the current from Tx+ is
at full-scale, the current from Tx– is zero. The two currents will
typically drive a resistive load that will convert the output
currents to a voltage. The Tx+ and Tx– output currents are
inherently ground seeking and should each be connected to
matching resistors, RL, that are tied directly to AGND.
The full-scale output current of the DAC is set by the value of
the resistor placed from the FSADJ pin to AGND. The relationship between the resistor, RSET, and the full-scale output current
is governed by the following equation:
I FS = 39.4 RSET
The full-scale current can be set from 2 to 20 mA. Generally,
there is a trade-off between DAC performance and power consumption. The best DAC performance will be realized at an IFS
of 20 mA. However, the value of IFS adds directly to the overall
current consumption of the device.
The single-ended voltage output appearing at the Tx+ and Tx–
nodes are:
VTx + = I Tx + × R L
VTx − = I Tx − × R L
selected, or if the LPF is bypassed. If the wider (approximately
26 MHz) LPF bandwidth is selected, the gain range is –6 dB to
+30 dB. The PGA is comprised of two sections, a continuous
time PGA (CPGA) and a switched capacitor PGA (SPGA). The
CPGA has possible gain settings of 0, 6, 12, 18, 24, and 30. The
SPGA has possible gain settings of –6, –4, –2, 0, +2, +4, and +6
dB. Table V shows how the gain is distributed for each programmed gain setting.
The CPGA input appears at the device Rx+ and Rx– input pins.
The input impedance of this stage is nominally 270 ⍀ differential and is not gain dependent. It is best to ac-couple the input
signal to this stage and let the inputs self bias. This will lower
the offset voltage of the input signal, which is important at higher
gains, since any offset will lower the output compliance range of
the CPGA output. When the inputs are driven by direct coupling,
the dc level should be AVDD/2. However, this could lead to
larger dc offsets and consequently reduce the dynamic range of the
Rx path.
LOW-PASS FILTER
The low-pass filter (LPF) is a programmable, multistage, fourth
order filter comprised of two real poles and a complex pole pair.
The first real pole is implemented within the CPGA. The second
filter stage implements a complex pair of poles. The last real
pole is implemented in a buffer stage that drives the SPGA.
There are two pass-band settings for the LPF. Within each pass
band the filters are tunable over about a ± 30% frequency range.
The formula for the cutoff frequency is:
Note that the full-scale voltage of VTx+ and VTx– should not
exceed the maximum output compliance range of 1.5 V to prevent signal compression. To maintain optimum distortion and
linearity performance, the maximum voltages at VTx+ and VTx–
should not exceed 0.5 V.
fCUTOFF LOW = f ADC × 64 (64 + Target )
fCUTOFF HIGH = f ADC × 158 (64 + Target )
The single-ended full-scale voltage at either output node will be:
V FS = I FS × R L
The differential voltage, VDIFF, appearing across VTx+ and VTx– is:
V DIFF = (TTx + − TTx − ) × R L
where Target is the decimal value programmed as the tuning
target in Register 5.
This filter may also be bypassed by setting Bit 0 of Register 4.
In this case, the bandwidth of the Rx path will decrease with
increasing gain and will be approximately 50 MHz at the highest
gain settings.
and
V DIFF _ FS = I FS × R L
ADC
For optimum performance, a differential output interface is recommended since any common-mode noise or distortion can be
suppressed.
It should be noted that the differential output impedance of the
DAC is 2 × RL and any load connected across the two output
resistors will load down the output voltage accordingly.
RECEIVE PATH DESCRIPTION
The receive path consists of a two-stage PGA, a continuous time,
4-pole LPF, an ADC, a digital HPF, and a digital data multiplexer.
Also working in conjunction with the receive path is an offset
correction circuit and a digital phase-lock loop. Each of these
blocks will be discussed in detail in the following sections.
PROGRAMMABLE GAIN AMPLIFIER
The PGA has a programmable gain range from –6 dB to +36 dB
if the narrower (approximately 12 MHz) LPF bandwidth is
The AD9876’s analog-to-digital converter implements a pipelined multistage architecture to achieve high sample rates while
consuming low power. The ADC distributes the conversion over
several smaller A/D subblocks, refining the conversion with
progressively higher accuracy as it passes the results from stage
to stage. As a consequence of the distributed conversion, ADCs
require a small fraction of the 2N comparators used in a traditional n-bit flash-type A/D. A sample-and-hold function within
each of the stages permits the first stage to operate on a new
input sample while the remaining stages operate on preceding
samples. Each stage of the pipeline, excluding the last, consists
of a low resolution flash A/D connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier amplifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each one of the stages to
facilitate digital correction of flash errors. The last stage simply
consists of a flash A/D.
–16–
REV. A
AD9876
CLOCK AND OSCILLATOR CIRCUITRY
AINP
AINN
A/D
SHA
A/D
GAIN
SHA
D/A
A/D
GAIN
D/A
CORRECTION LOGIC
AD9876
Figure 2. ADC Theory of Operation
The AD9876’s internal oscillator generates all sampling clocks
from a fundamental frequency quartz crystal. Figure 3a shows
how the quartz crystal is connected between OSCIN (Pin 1) and
XTAL (Pin 48) with parallel resonant load capacitors as specified by the crystal manufacturer. The internal oscillator circuitry
can also be overdriven by a TTL-level clock applied to OSCIN
with XTAL left unconnected.
The PLL has a frequency capture range between 10 MHz
and 64 MHz.
The digital data outputs of the ADC are represented in two’s
complement format. They saturate to full scale or zero when the
input signal exceeds the input voltage range.
AD9876
XTAL
XTAL
The twos complement data format is shown below:
OSCIN
011 . . 11: Maximum
Y1
C2
C1
000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB
Figure 3a. Connections for a Fundamental Mode Crystal
100 . . 00: Minimum
VOLTAGE REGULATOR CONTROLLER
The maximum value will be output from the ADC when the
Rx+ input is 1 V or more greater than the Rx– input. The minimum value will be output from the ADC when the Rx– input is
1 V or more greater than the Rx+ input. This results in a fullscale ADC voltage of 2 Vppd.
The data can be translated to straight binary data format by
simply inverting the most significant bit.
The best ADC performance will be achieved when the ADC
clock source is selected from fOSCIN and the OSCIN pin is driven
from a low jitter clock source. The amount of degradation from
jitter on the ADC clock will depend on how quickly the input is
varying at the sampling instance. TPC 36 charts this effect in
the form of ENOB vs. input frequency for the two clocking
scenarios.
The AD9876 contains an on-chip voltage regulator controller
(VRC) for providing a linear 1.3 V supply for low voltage digital
circuitry or other external use. The VRC consists of an op amp
and a resistive voltage divider. As shown in Figure 3b, the resistive divider establishes a voltage of 1.3 V at the inverting input
of the amplifier when DVDD is equal to its nominal voltage of
3.3 V. The feedback loop around the op amp will adjust the gate
voltage such that the voltage at the FB pin, VFB, will be equal to
the voltage at the inverting input of the op amp.
3.3V
DVDD
2R
AD9876
S
The maximum sample rate of the ADC in Full-Precision Mode,
that is outputting 12 bits, is 55 MSPS. TPC 33 shows the ADC
performance in ENOB versus fADC. The maximum sample rate
of the ADC in Half-Precision Mode, that is outputting five bits,
is 64 MSPS. The timing of the interface is fully described in the
Receive Port Timing section of this data sheet.
GATE
1.3R
SI2301
D
FB
VOUT
VFB = 1.3V
C
Figure 3b. Connections for 1.3 V Linear Regulator
DIGITAL HPF
Following the ADC, there is a bypassable digital HPF. The
response is a single-pole IIR HPF. The transfer function is:
(
H (z ) = 1 – 0.99994Z –1
) (1 – 98466Z )
–1
where the sampling period is equal to the ADC clock period.
This results in a 3 dB frequency approximately 1/400th of the
ADC sampling rate. The transfer functions are plotted for
32 MSPS and 50 MSPS in TPC 29 and TPC 32.
The digital HPF introduces a 1 ADC clock cycle latency. If the
HPF function is not desired, the HPF can be bypassed and the
latency will not be incurred.
REV. A
G
The maximum current output from the circuit is largely dependent on the MOSFET device. For the SI2301 shown, 250 mA
can be delivered. The regulated output voltage should have bulk
decoupling and high frequency decoupling capacitors to ground
as required by the load. The regulator circuit will be stable for
capacitive loads between 0.1 µF and 47 µF.
It should be noted that the regulated output voltage, VFB, is
proportional to DVDD. Therefore, the percentage variation in
DVDD will also be seen at the regulated output voltage. The
load regulation is roughly equal to the ON resistance of the
MOSFET device chosen. For the SI2301, this is about 60 mΩ.
–17–
AD9876
AGC TIMING CONSIDERATIONS
When implementing the AGC timing loop, it is important to
consider the delay and settling time of the Rx path in response
to a change in gain. Figure 4 shows the delay the receive signal
experiences through the blocks of the Rx path. Whether the gain
is programmed through the serial port or over the Tx [5:0] pins,
the gain takes effect immediately with the delays shown below.
When gain changes do not involve the CPGA, the new gain will
be evident in samples after seven ADC clock cycles. When the
gain change does involve the CPGA, it takes an additional 45 ns
to 70 ns due to the propagation delays of the buffer, LPF and
PGA. Table V, details the PGA programming map.
GAIN
REGISTER
5ns
DECODE
LOGIC
DIGITAL
HPF
ADC
SHA
BUFFER
LPF
1 CLK
CYCLE
5 CLK
CYCLE
1/2 CLK
CYCLE
10ns
25ns or 50ns
Also, the Tx path can be used in a Reduced Resolution Mode
by setting the Tx Port Multiplexer Bypass Bit (Register 7, Bit
0). In this mode, the Tx data-word becomes six bits and is read
in a single cycle. The clocking modes are the same as described
above, but the level of Tx SYNC is irrelevant.
If Tx SYNC is low for more than one clock cycle, the last transmit data will read continuously until Tx SYNC is brought high
for the second nibble of a new transmit word. This feature can
be used to “flush” the interpolator filters with zeros.
PGA Adjust Timing
In addition to the serial port, the Tx [5:1] pins can be used to
write to the Rx Path Gain Adjust Bits (Register 6, Bits 4:0).
This provides a faster way to update the PGA gain. A high level
on the GAIN pin with Tx SYNC low programs the PGA setting
on either the rising edge or falling edge of CLK-A. The GAIN
pin must be held high, Tx SYNC must be held low, and GAIN
data must be stable for three clock cycles to successfully update
the PGA GAIN value. A low level on the GAIN pin enables data
to be fed to the interpolator and DAC.
tSU
PGA
CLK-A
10ns
Figure 4. AGC Timing
tHD
Tx SYNC
Transmit Port Timing
Tx [5:0]
The AD9876 transmit port consists of a 6-bit databus Tx [5:0],
a clock, and a Tx SYNC signal. Two consecutive nibbles of the
Tx data are multiplexed together to form a 12-bit data-word.
The clock appearing on the CLK-A pin is a buffered version of
the internal Tx data sampling clock. Data from the Tx port is
read on the rising edge of this sampling clock. The Tx SYNC
signal is used to indicate to which word a nibble belongs. The
first nibble of every word is read while Tx SYNC is low, the
second nibble of that same word is read on the following Tx
SYNC high level. The timing is illustrated in the Figure 5.
GAIN
Figure 6. GAIN Programming
Receive Port Timing
The AD9876 receives port consists of a six bit databus Rx [5:0],
a clock, and an Rx SYNC signal. Two consecutive nibbles of the
Rx data are multiplexed together to form a 10-/12-bit data-word.
The Rx data is valid on the rising edge of CLK-A when the
ADC Clock Source PLL-B/2 Bit (Register 3, Bit 6) is set to 0.
The Rx SYNC signal is used to indicate to which word a nibble
belongs. The first nibble of every word is transmitted while Rx
SYNC is low, the second nibble of that same word is transmitted on the following Rx SYNC high level. When Rx SYNC is
low, the sampled nibble is read as the most significant nibble.
When the Rx SYNC is high, the sampled nibble is read as the
least significant nibble. The timing is illustrated in Figure 7.
tSU
CLK-A
tHD
Tx SYNC
Tx [5:0]
Tx 0 LSB
Tx 1 MSB
Tx 1 LSB
Tx 2 MSB
GAIN
Tx 2 LSB Tx 3 MSB
Figure 5. Transmit Timing Diagram AD9876
tHT
The Tx Port is highly configurable and offers the following options.
Negative edge sampling can be chosen by two different methods;
either by setting the Tx Port Negative Edge Sampling Bit (Register 3, Bit 7) or the Invert CLK-A Bit (Register 8, Bit 6). The
main difference between the two methods is that setting Register
3, Bit 7 inverts the internal sampling clock and will affect only
the transmit path, even if CLK-A is used to clock the Rx
data. However, inverting CLK-A would affect both the Rx and
Tx paths if they both use CLK-A.
The first nibble of each word can be read in as the least significant
nibble by setting the Tx LS Nibble First Bit (Register 7, Bit 2).
CLK-A/-B
tVT
Rx SYNC
Rx [5:0]
Rx 0 LSB Rx 1 MSB Rx 1 LSB Rx 2 MSB Rx 2 LSB
Rx 3 MSB
Figure 7. Receive Timing Diagram
The Rx Port is highly configurable and offers the following
options.
Negative edge sampling can be chosen by setting the Invert
CLK-A Bit (Register 8, Bit 6) or the Invert CLK-B Bit (Register
8, Bit 7), depending on the clock selected as the ADC sampling
–18–
REV. A
AD9876
source. Inverting CLK-A would affect the Tx sampling edge as
well as the Rx sampling edge.
The first nibble of each word can be read in as the least significant
nibble by setting the Rx LS Nibble First Bit (Register 8, Bit 2).
Also, the Rx path can be used in a Reduced Resolution Mode
by setting the Rx Port Multiplexer Bypass Bit (Register 8, Bit
0). In this mode, the Rx data-word becomes six bits and is read
in a single cycle. The Clocking Modes are the same as described
above, but the level of Rx SYNC will stay low.
The Rx [5:0] pins can be put into a high impedance state by
setting the Three-State Rx Port Bit (Register 8, Bit 3).
SERIAL INTERFACE FOR REGISTER CONTROL
Bits I4:I0 – A4:A0
These bits determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9876/AD9875.
Serial Interface Port Pin Description
SCLK—Serial Clock
The serial clock pin is used to synchronize data transfers to and
from the AD9876 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
AD9876 is sampled on the rising edge of SCLK. All data read
from the AD9876 is validated on the rising edge of SCLK and is
updated on the falling edge.
The serial port is a 3-wire serial communications port consisting of
a clock (SCLK), chip select (SENABLE), and a bidirectional
data (SDATA) signal. The interface allows read/write access to
all registers that configure the AD9876 internal parameters. Single
or multiple byte transfers are supported as well as MSB first or
LSB first transfer formats.
SENABLE—Serial Interface Enable
General Operation of the Serial Interface
The signal on this line is sampled on the first eight rising edges
of SCLK after SENABLE goes active. Data is then read from or
written to the AD9876 depending on what was read.
Serial communication over the serial interface can be from 1 to
5 bytes in length. The first byte is always the instruction byte.
The instruction byte establishes whether the communication is
going to be a read or write access, the number of data bytes to
be transferred, and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
8th rising edge of SCLK after SENABLE is asserted. Likewise,
the data registers change immediately upon writing to the 8th bit
of each data byte.
The SENABLE pin is active low. It enables the serial communication to the device. SENABLE select should stay low during
the entire communication cycle. All input on the serial port is
ignored when SENABLE is inactive.
SDATA—Serial Data I/O
Figures 8 and 9 show the timing relationships between the three
SPI signals.
SENABLE
tDS
tSCLK
tPWH
SCLK
Instruction Byte
The instruction byte contains the following information as
shown below.
tDS
SDATA
Table II. Instruction Byte Information
MSB
I6
I5
I4
I3
I2
I1
I0
R/W
N1
N0
A4
A3
A2
A1
A0
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 8. Timing Diagram Register Write to AD9876
LSB
I7
tPWL
SENABLE
SCLK
tDV
Bit I7 – R/W
SDATA
This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates read
operation; logic zero indicates a write operation.
Bits I6:I5 – N1:N0
These two bits determine the number of bytes to be transferred
during the data transfer cycle. The bit decodes are shown in the
table below.
Table III. Decode Bits
REV. A
N1:N0
Description
0:0
0:1
1:0
1:1
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
DATA BIT n
DATA BIT n–1
Figure 9. Timing Diagram Register Read from AD9876
MSB/LSB Transfers
The AD9876 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
bit order is controlled by the SPI LSB First Bit (Register 0, Bit
6). The default value is 0, MSB first. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
The AD9876 will automatically decrement the address for each
successive byte required for the multibyte communication cycle.
When the SPI LSB First Bit (Register 0, Bit 6) is set high, the
serial port interprets both instruction and data bytes LSB first.
Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of
–19–
AD9876
the first address to be accessed. The AD9876 will automatically
increment the address for each successive byte required for the
multibyte communication cycle.
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all
registers except Register 0 are set to their default values. Register 0 will remain at the last value sent, with the exception that
the Software Reset Bit will be set to 0.
Figures 10a and 10b show how the serial port words are built
for each of these modes.
INSTRUCTION CYCLE
The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK, a
byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9876 are not simultaneously
updated but occur sequentially. For this reason, it is recommended that single byte transfers be used when changing the
SPI configuration or performing a software reset.
DATA TRANSFER CYCLE
SENABLE
SCLK
SDATA
R/W I6(N) I5(N) I4
I3
I2
I1
D20 D10 D00
I0 D7N D6N
Figure 10a. Serial Register Interface Timing MSB-First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SENABLE
SCLK
SDATA
I0
I1
I2
I3
I4 I5(N) I6(N) R/W D00 D10 D20
D6N D7N
Figure 10b. Serial Register Interface Timing LSB-First
Table IV. Register Layout
Address
(hex)
Bit 7
0
Bit 6
Bit 5
Bit 4
SPI
LSB First
Software
Reset
Bit 3
Bit 2
Bit 1
Bit 0
Default
(hex)
Comments
0 × 00
Read/Write
1
PowerDown
Regulator
PowerDown
PLL-B
PowerDown
PLL-A
PowerDown
DAC
PowerDown
Interpolator
PowerDown
Rx
Reference
PowerDown
ADC and
FPGA
PowerDown
Rx LPF and
CPGA
0 × 00
Read/Write
PWR DN
Pin Low
2
PowerDown
Regulator
PowerDown
PLL-B
PowerDown
PLL-A
PowerDown
DAC
PowerDown
Interpolator
PowerDown
Rx
Reference
PowerDown
ADC and
FPGA
PowerDown
Rx LPF and
CPGA
0 × 9F
Read/Write
PWR DN
Pin High
3
Tx Port
Negative
Edge
Sampling
ADC Clock
Source
PLL-B/2
0 × 02
Read/Write
4
Rx Port
Negative
Edge
Sampling
Rx LPF
Rx Path
Rx Digital Fast ADC
Tuning
DC Offset HPF
Sampling
In Progress Correction Bypass
(Read-Only)
0 × 01
Read/Write
0 × 80
Read/Write
0 × 00
Read/Write
5
PLL-B
(×M) Multiplier
<5:4>
PGA
Gain Set
by Register
7
Interpolation Filter Select
<3:0>
F
Wideband
Rx LPF
PLL-A
(×M) Multiplier
<1:0>
Enable
1-Pole
Rx LPF
Rx LPF
Bypass
Rx LPF fc Adjust <7:0>
6
8
PLL-B
(N) Divider
<3:3>
Invert
CLK-B
Invert
CLK-A
Disable
CLK-B
Rx Path Gain Adjust <4:0>
Disable
CLK-A
Power-Down Tx Port
Interpolator LS Nibble
at
First
Tx QUIET
Pin Low
Tx Port
Demultiplexer
Bypass
0 × 00
Read/Write
Three-State
Rx Port
Rx Port
Multiplexer
Bypass
0 × 00
Read/Write
Rx Port
LS Nibble
First
Die Revision Number <3:0>
–20–
Read- Only
REV. A
AD9876
REGISTER PROGRAMMING DEFINITIONS
REGISTER 0 – RESET/SPI CONFIGURATION
Bit 5: Software Reset
fCLKIN is selected as the ADC sampling clock source and should
be used as the ADC sampling clock whenever possible.
Setting this bit high resets the chip. The PLLs will relock to the
input clock and all registers (except Register 0 × 0, Bit 6) revert to
their default values. Upon completion of the reset, Bit 5 is reset to 0.
Bits 1 and 0 determine the multiplication factor (L) for PLL-A
and the DAC sampling clock frequency, fDAC.
fDAC = L × fCLKIN
The content of the interpolator stages are not cleared by software
or hardware resets. It is recommended to “flush” the transmit
path with zeros before transmitting data.
Bit 6: SPI LSB First
Setting this bit high causes the serial port to send and receive
data least significant bit (LSB) first. The default low state configures the serial port to send and receive data most significant
bit (MSB) first.
REGISTERS 1 AND 2—POWER-DOWN
The combination of the PWR DN pin and Registers 1 and 2
allow for the configuration of two separate pin selectable power
settings. The PWR DN pin selects between two sets of individually
programmed operation modes.
When the PWR DN pin is low, the functional blocks corresponding to the bits set in Register 1 will be powered down.
When the PWR DN pin is high, the functional blocks corresponding to the bits set in Register 2 will be powered down.
Bit 0: Power-Down Receive Filter and CPGA
Setting this bit high powers down and bypasses the Rx LPF and
coarse programmable gain amplifier.
Bit 1: Power-Down ADC and FPGA
Setting this bit high powers down the ADC and fine programmable gain amplifier (FPGA).
Bit 1, 0: PLL-A Multiplier
Bit 1, 0
0, 0: L = 1
0, 1: L = 2
1, 0: L = 4
1, 1: L = 8
Bit 5 to 2: PLL-B Multiplier/Divider
Bits 5 to 2 determine the multiplication factor (M) and division
factor (N) for the PLL-B and the CLK-B frequency. For multiplexed 10-/12-bit data, fCLK-B = fCLKIN × M/N. For nonmultiplexed
6-bit data, fCLK-B = (fCLKIN/2) × M/N. All nine combinations of M
and N values are valid, yielding seven unique M/N ratios.
Bit 5,4
0, 0: M = 3
0, 1: M = 4
1, 0: M = 6
Bit 3,2
0, 0: N = 2
0, 1: N = 4
1, 0: N = 1
Bit 6: ADC Clock Source PLL-B/2
Setting Bit 6 high selects PLL-B/2 as the ADC sampling clock
source. In this mode, the Rx data and CLK-B will run at a rate
of fCLK-B. Rx SYNC will run at fCLK-B/2.
Setting Bit 6 low selects the fCLKIN signal as the ADC sampling
clock source. This mode of operation yields the best ADC
performance if an external crystal is used or a low jitter clock
source drives the OSCIN pin.
Bit 7: Tx Port Negative Edge Sampling
Bit 3: Power-Down Interpolators
Setting Bit 7 high will cause the Tx Port to sample the Tx DATA
and Tx SYNC on the falling edge of CLK-A. By default, the Tx
Port sampling occurs on the rising edge of CLK-A. The timing
is shown in Figure 5.
Setting this bit high powers down the transmit digital interpolators.
It does not clear the content of the data path.
REGISTER 4—RECEIVE FILTER SELECTION
Bit 2: Power-Down Rx Reference
Setting this bit high powers down the ADC reference. This bit
should be set if an external reference is applied.
Bit 4: Power-Down DAC
Setting this bit high powers down the transmit DAC.
Bit 5, Bit 6: Power-Down PLL-A, PLL-B
Setting these bits high powers down the on-chip phase-lock
loops that generated CLK-A and CLK-B, respectively. When
powered down, these clocks are high impedance.
Bit 7: Power-Down Regulator
Setting this bit high powers down the on-chip voltage control regulator.
REGISTER 3—CLOCK SOURCE CONFIGURATION
The AD9876 integrates two independently programmable PLLs
referred to as PLL-A and PLL-B. The outputs of the PLLs are
used to generate all the chips internal and external clock signals
from the fCLKIN signal. All Tx path clock signals are derived
from PLL-A. If fCLKIN is programmed as the ADC sampling
clock source, then the Rx port clocks are also derived from
PLL-A. Otherwise, the ADC sampling clock is PLL-B/2 and the
Rx path clocks are derived from PLL-B.
There is a restriction that the values of L and K both be equal to
4 when fCLKIN is selected as the ADC sampling clock source.
However, the best receive path performance is obtained when
REV. A
The AD9876 receive path has a continuous time 4-pole LPF
and a 1-pole digital HPF. The 4-pole LPF has two selectable
cutoff frequencies. Additionally, the filter can be tuned around
those two cutoff frequencies. These filters can also be bypassed
to different degrees as described below.
The continuous time 4-pole low-pass filter is automatically
calibrated to one of two selectable cutoff frequencies.
The cutoff frequency fCUTOFF is described as a function of the
ADC sampling frequency fADC and can be influenced (± 30%) by
the Rx Filter Tuning Target word in Register 5.
fCUTOFF LOW = f ADC × 64 (64 + Target )
fCUTOFF HIGH = f ADC × 158 (64 + Target )
Bit 0: Rx LPF Bypass
Setting this bit high bypasses the 4-pole LPF. The filter is automatically powered down when this bit is set.
Bit 1: Enable 1-Pole Rx LPF
The AD9876 can be configured with an additional 1-pole ~16 MHz
input filter for applications that require steeper filter roll-off or
want to use the 1-pole filter instead of the 4-pole receive lowpass filter. The 1-pole filter is untrimmed and subject to cutoff
frequency variations of ⫾20%.
–21–
AD9876
Table V. PGA Programming Map
Bit 2: Wideband Rx LPF
This bit selects the nominal cutoff frequency of the 4-pole LPF.
Setting this bit high selects a nominal cutoff frequency of 28.8 MHz.
When the wideband filter is selected, the Rx path gain is limited
to 30 dB.
Bit 3: Fast ADC Sampling
Setting this bit increases the quiescent current in the SVGA
block. This may provide some performance improvement
when the ADC sampling frequency is greater than 50 MSPS
(in 6-Bit Mode).
Bit 4: Rx Digital HPF Bypass
Setting this bit high bypasses the 1-pole digital HPF that follows
the ADC. The digital filter must be bypassed for ADC sampling
above 50 MSPS.
Bit 5: Rx Path DC Offset Correction
Writing a 1 to this bit triggers an immediate receive path offset
correction and reads back zero after the completion of the offset
correction.
Bit 6: Rx LPF Tuning in Progress
This bit indicates when the receive filter calibration is in progress.
The duration of a receive filter calibration is about 500 ms.
Writing to this bit has no effect.
Bit 7: Rx Port Negative Edge Sampling
Setting this bit high disables the automatic background receive
filter calibration. The AD9876 automatically calibrates the
receive filter on reset and every few (~2) seconds thereafter to
compensate for process and temperature variation, power supply, and long term drift. Programming a 1 to this bit disables
this function. Programming a 0 triggers an immediate first calibration and enables the periodic update.
Rx Path
Gain [4:0]
Rx Path
Gain
CPGA
Gain
SPGA
Gain
0 × 00
0 × 01
0 × 02
0 × 03
0 × 04
0 × 05
0 × 06
0 × 07
0 × 08
0 × 09
0 × 0A
0 × 0B
0 × 0C
0 × 0D
0 × 0E
0 × 0F
0 × 10
0 × 11
0 × 12*
0 × 13*
0 × 14*
0 × 15*
–6
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30/30
30/32
30/34
30/36
–6
–6
–6
–6
–6
–6
0
0
0
6
6
6
12
12
12
18
18
18
18/24
18/24
18/24
18/24
0
2
4
6
8
10
6
8
10
6
8
10
6
8
10
6
8
10
12/6
12/8
12/10
12/12
*When the Wideband Rx Filter Bit is set high, the Rx Path Gain is limited to
30 dB. The first of the two values in the chart refers to this mode. The second
number refers to the mode when the lower Rx LPF Cutoff Frequency is chosen, or the Rx LPF Filter is bypassed.
REGISTER 7—TRANSMIT PATH SETTINGS
The AD9876 transmit path has a programmable interpolation
filter that proceeds the transmit DAC. The interpolation filter
can be programmed to operate in seven different modes. Also,
the digital interface can be programmed to operate in several
different modes. These modes are described below.
REGISTER 5—RECEIVE FILTER TUNING TARGET
This register sets the filter tuning target as a function of fOSCIN.
See Register 4 description.
REGISTER 6—Rx PATH GAIN ADJUST
The AD9876 uses a combination of a continuous time PGA
(CPGA) and a switched capacitor PGA (SPGA) for a gain range
of –6 dB to +36 dB with a resolution of 2 dB. The Rx path gain
can be programmed over the serial interface by writing to the
Rx Path Gain Adjust Register or directly using the GAIN and
MSB aligned Tx [5:1] Bits. The register default value is 0 × 00
for the lowest gain setting (–6 dB). The register always reads
back the actual gain setting irrespective of which of the two
programming modes were used.
Bit 0: Transmit Port Demultiplexer Bypass
Setting Bit 0 high bypasses the input data demultiplexer. In this
mode, consecutive nibbles on the Tx [5:0] pins are treated as
individual words to be sent through the Tx path. This creates a
six bit data path. The state of Tx SYNC is ignored in this mode.
Bit 2: Transmit Port Least Significant Nibble First
Setting Bit 2 high reconfigures the AD9876 for a Transmit
Mode that expects least significant nibble before the most
significant nibble.
Bit 3: Power-Down Interpolator at Tx QUIET Pin Low
Table V describes the gains and how they are achieved as a
function of the Rx Path adjust bits.
Bit 5: PGA Gain Set by Register
Setting this bit high will result in the Rx Path Gain being set by
writing to the PGA Gain Control Register. Default is zero which
selects writing the gain through the Tx [5:1] pins in conjunction
with the gain pin.
Setting Bit 3 high enables the Tx QUIET pin to shut off the
DAC output. If the bit is set to 1, then pulling the Tx QUIET
pin low will power down the interpolator filters. In most applications, the interpolator filter will need to be flushed with 0s
before or after being powered down.
–22–
REV. A
AD9876
Bit 4 to Bit 7: Interpolation Filter Select
Bits 4 to 7 define the interpolation filter characteristics and
interpolation rate.
Bits 7:4;
0 × 2; Interpolation Bypass
0 × 0; see TPC 1. 4× Interpolation, LPF
0 × 1; see TPC 2. 2× Interpolation, LPF
0 × 4; see TPC 3. 4× Interpolation, BPF, Adjacent Image
0 × 5; see TPC 4. 2× Interpolation, BPF, Adjacent Image
0 × 8; see TPC 5. 4× Interpolation, BPF, Lower Image
0 × C; see TPC 6. 4× Interpolation, BPF, Upper Image
The interpolation factor has a direct influence on the CLK-A
output frequency. When the transmit input data multiplexer is
enabled (10-/12-Bit Mode):
f CLK − A = 2 × f DAC K
where K is the interpolation factor. When the transmit input data
multiplexer is disabled (5-/6-Bit Mode):
f CLK− A = f DAC K
where K is the interpolation factor.
REGISTER 8—RECEIVER AND CLOCK OUTPUT
SETTINGS
Bit 0: Rx Port Multiplexer Bypass
Setting this bit high bypasses the Rx Port output multiplexer.
This will output only the 6 MSBs of the ADC word. This mode
enables ADC sampling rates above 55 MSPS.
Bit 2: Rx Port LS Nibble First
Reconfigures the AD9876 for a Receive Mode that expects less
significant bits before the most significant bits.
Bit 3: Three-State Rx Port
This bit sets the receive output Rx [5:0] into a high impedance
Three-State Mode. It allows for sharing the bus with other devices.
Bit 4, Bit 5: Disable CLK-A, Disable CLK-B
Setting Bit 4 or Bit 5 stops CLK-A or CLK-B, respectively,
from toggling. The output is held low. Setting Bit 4 or Bit 5
fixes CLK-A or CLK-B to a low output level, respectively.
Bit 6: Invert CLK-A
Setting Bit 6 high inverts the CLK-A output signal.
Bit 7: Invert CLK-B
Setting this bit high inverts the CLK-B output signal. This effectively changes the timing of the Rx [5:0] and Rx SYNC signals
from rising edge triggered to falling edge triggered with respect
to the CLK-B signal.
REGISTER F, DIE REVISION
This register stores the die revision of the chip. It is a ReadOnly Register.
PCB DESIGN CONSIDERATIONS
Although the AD9876 is a mixed-signal device, the part should
be treated as an analog component. The digital circuitry on-chip
has been specially designed to minimize the impact that the
digital switching noise will have on the operation of the analog
REV. A
circuits. Following the power, grounding and layout recommendations in this section will help you get the best performance
from the MxFE.
Component Placement
If the three following guidelines of component placement are
followed, chances for getting the best performance from the
MxFE are greatly increased. First, manage the path of return
currents flowing in the ground plane so that high frequency
switching currents from the digital circuits do not flow on the
ground plane under the MxFE or analog circuits. Second, keep
noisy digital signal paths and sensitive receive signal paths as
short as possible. Third, keep digital (noise generating) and
analog (noise susceptible) circuits as far away from each other
as possible.
In order to best manage the return currents, pure digital circuits
that generate high switching currents should be closest to the
power supply entry. This will keep the highest frequency return
current paths short and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
these circuits should be generously bypassed at each device
which will further reduce the high frequency ground currents.
The MxFE should be placed adjacent to the digital circuits,
such that the ground return currents from the digital sections
will not flow in the ground plane under the MxFE. The analog
circuits should be placed furthest from the power supply.
The AD9876 has several pins that are used to decouple sensitive
internal nodes. These pins are REFIO, REFB, and REFT. The
decoupling capacitors connected to these points should have
low ESR and ESL. These capacitors should be placed as close
to the MxFE as possible and be connected directly to the analog
ground plane.
The resistor connected to the FSADJ pin should also be placed close
to the device and connected directly to the analog ground plane.
Power Planes and Decoupling
The AD9876 evaluation board demonstrates a good power
supply distribution and decoupling strategy. The board has four
layers: two signal layers, one ground plane, and one power plane.
The power plane is split into a 3VDD section used for the 3 V
digital logic circuits, a DVDD section used to supply the digital
supply pins of the AD9876, an AVDD section used to supply
the analog supply pins of the AD9876/AD9875, and a VANLG
section that supplies the higher voltage analog components on
the board. The 3VDD section will typically have the highest
frequency currents on the power plane and should be kept the
furthest from the MxFE and analog sections of the board. The
DVDD portion of the plane brings the current used to power
the digital portion of the MxFE to the device. This should be
treated similarly to the 3VDD power plane and be kept from
going underneath the MxFE or analog components. The MxFE
should largely sit on the AVDD portion of the power plane.
The AVDD and DVDD power planes may be fed from the same
low noise voltage source; however, they should be decoupled
from each other to prevent the noise generated in the DVDD
portion of the MxFE from corrupting the AVDD supply. This
can be done by using ferrite beads between the voltage source and
DVDD and between the source and the AVDD. Both DVDD
and AVDD should have a low ESR, bulk decoupling capacitor
–23–
AD9876
Ground Planes
In general, if the component placing guidelines discussed earlier
can be implemented, it is best to have at least one continuous
ground plane for the entire board. All ground connections should be
made as short as possible. This will result in the lowest impedance
return paths and the quietest ground connections.
If the components cannot be placed in a manner that will keep the
high frequency ground currents from traversing under the MxFE
and analog components, it may be necessary to put current steering
channels into the ground plane to route the high frequency
currents around these sensitive areas. These current steering
channels should be made only when and where necessary.
Signal Routing
The digital Rx and Tx signal paths should be kept as short as
possible. Also, the impedance of these traces should have
a controlled characteristic impedance of about 50 Ω. This will
prevent poor signal integrity and the high currents that can
occur during undershoot or overshoot caused by ringing. If the
signal traces cannot be kept shorter than about 1.5 inches, series
termination resistors (33 Ω to 47 Ω) should be placed close to
all signal sources. It is a good idea to series-terminate all clock
signals at their source, regardless of trace length.
The receive Rx⫹ and Rx⫺ signals are the most sensitive
signals on the entire board. Careful routing of these signals
is essential for good receive path performance. The Rx⫹ and
Rx⫺ signals form a differential pair and should be routed
together as a pair. By keeping the traces adjacent to each other,
noise coupled onto the signals will appear as common mode and
will be largely rejected by the MxFE receive input. Keeping the
driving point impedance of the receive signal low and placing
any low-pass filtering of the signals close to the MxFE will
further reduce the possibility of noise corrupting these signals.
C02599–0–10/02(A)
on the MxFE side of the ferrite as well as a low ESR, ESL
decoupling capacitors on each supply pin (i.e., the AD9876
requires five power supply decoupling caps, one each on Pins 5,
38, 47, 14, and 35). The decoupling caps should be placed as close
to the MxFE supply pins as possible. An example of the proper
decoupling is shown in the AD9876 evaluation board schematic.
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
0.75
0.60
0.45
PIN 1
INDICATOR
9.00 BSC
37
48
36
1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
SEATING
PLANE
SEATING
PLANE
7.00
BSC
TOP VIEW
(PINS DOWN)
7ⴗ
3.5ⴗ
0ⴗ
0.08 MAX
COPLANARITY
VIEW A
25
12
13
0.50
BSC
VIEW A
ROTATED 90ⴗ CCW
24
0.27
0.22
0.17
PRINTED IN U.S.A.
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Revision History
Location
Page
10/02—Data Sheet changed from REV. 0 to REV. A.
Changes to to Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Changes to REGISTER 3—CLOCK SOURCE CONFIGURATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
–24–
REV. A