Radar Receive Path AFE: 6-Channel LNA/PGA/AAF with ADC AD8283 GENERAL DESCRIPTION The AD8283 is designed for low cost, low power, compact size, flexibility, and ease of use. It contains six channels of a low noise preamplifier (LNA) with a programmable gain amplifier (PGA) and an antialiasing filter (AAF) plus one direct-to-ADC channel, all integrated with a single 12-bit analog-to-digital converter (ADC). INA– INB+ INB– INC+ INC– IND+ IND– INE+ INE– INF+ INF– PGA AAF LNA PGA AAF LNA PGA AAF LNA PGA AAF LNA PGA AAF LNA PGA AAF RBIAS VREF DVDD33x DVDD18x MUXA PDWN AVDD33x AVDD18x LNA REFERENCE DSYNC MUX 12-BIT ADC DRV D[0:11] INADC+ INADC– SPI 09795-001 CLK+ CLK– AUX AD8283 SDIO Automotive radar Adaptive cruise control Collision avoidance Blind spot detection Self-parking Electronic bumper INA+ CS APPLICATIONS FUNCTIONAL BLOCK DIAGRAM SCLK 6 channels of LNA, PGA, AAF 1 channel of direct-to-ADC Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) SPI-programmable gain = 16 dB to 34 dB in 6 dB steps Antialiasing filter (AAF) Programmable third-order low-pass elliptic filter (LPF) from 1 MHz to 12 MHz Analog-to-digital converter (ADC) 12 bits of accuracy up to 80 MSPS SNR = 67 dB SFDR = 68 dB Low power, 170 mW per channel at 12 bits/80 MSPS Low noise, 3.5 nV/√Hz maximum of input referred voltage noise Power-down mode 72-lead, 10 mm × 10 mm, LFCSP package Specified from −40°C to +105°C Qualified for automotive applications ZSEL FEATURES Figure 1. is 3.5 nV/√Hz at maximum gain. The channel is optimized for dynamic performance and low power in applications where a small package size is critical. Fabricated in an advanced CMOS process, the AD8283 is available in a 10 mm × 10 mm, RoHS-compliant, 72-lead LFCSP. It is specified over the automotive temperature range of −40°C to +105°C. Each channel features a gain range of 16 dB to 34 dB in 6 dB increments and an ADC with a conversion rate of up to 80 MSPS. The combined input-referred noise voltage of the entire channel Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD8283 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Jitter Considerations....................................................... 17 Applications....................................................................................... 1 SDIO Pin...................................................................................... 17 Functional Block Diagram .............................................................. 1 SCLK Pin ..................................................................................... 17 General Description ......................................................................... 1 CS Pin .......................................................................................... 17 Revision History ............................................................................... 2 RBIAS Pin.................................................................................... 18 Specifications..................................................................................... 3 Voltage Reference ....................................................................... 18 AC Specifications.......................................................................... 3 Power and Ground Recommendations ................................... 18 Digital Specifications ................................................................... 5 Exposed Paddle Thermal Heat Slug Recommendations ...... 18 Switching Specifications .............................................................. 6 Serial Peripheral Interface (SPI) ................................................... 19 Absolute Maximum Ratings............................................................ 7 Hardware Interface..................................................................... 19 ESD Caution.................................................................................. 7 Memory Map .................................................................................. 21 Pin Configuration and Function Descriptions............................. 8 Reading the Memory Map Table.............................................. 21 Typical Performance Characteristics ........................................... 10 Logic Levels................................................................................. 21 Theory of operation ....................................................................... 14 Reserved Locations .................................................................... 21 Radar Receive Path AFE............................................................ 14 Default Values ............................................................................. 21 Channel Overview...................................................................... 15 Application Diagrams .................................................................... 25 ADC ............................................................................................. 16 Outline Dimensions ....................................................................... 27 Clock Input Considerations ...................................................... 16 Ordering Guide .......................................................................... 27 Clock Duty Cycle Considerations ............................................ 17 Automotive Products ................................................................. 27 REVISION HISTORY 4/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8283 SPECIFICATIONS AC SPECIFICATIONS AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 80 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. Table 1. Parameter 1 ANALOG CHANNEL CHARACTERISTICS Gain Gain Range Gain Error Input Voltage Range Input Resistance Input Capacitance Input-Referred Voltage Noise Noise Figure Output Offset AAF Low-Pass Filter Cutoff AAF Low-Pass Filter Cutoff Tolerance AAF Attenuation in Stop Band Group Delay Variation Channel-to-Channel Phase Variation Channel-to-Channel Gain Matching 1 dB Compression Crosstalk POWER SUPPLY AVDD18x AVDD33x DVDD18x DVDD33x IAVDD18 IAVDD33 IDVDD18 IDVDD33 Total Power Dissipation – per channel Power-Down Dissipation Power Supply Rejection Ratio (PSRR) Conditions LNA, PGA, and AAF channel Min AD8283W Typ Max 16/22/28/34 18 −1.25 Channel gain =16 dB Channel gain = 22 dB Channel gain = 28 dB Channel gain = 34 dB 200 Ω input impedance selected 200 kΩ input impedance selected 0.180 160 Max gain at1 MHz Min gain at 1 MHz Max gain, RS = 50 Ω, unterminated Max Gain, RS=RIN = 50 Ω Gain = 16 dB Gain = 34 dB −3 dB, programmable After filter autotune Third order elliptical filter 2× cutoff 3× cutoff Filter set at 2 MHz Frequencies up to −3 dB ¼ of −3 dB frequency Frequencies up to −3 dB 1/4 of −3 dB frequency Relative to output +1.25 0.25 0.125 0.0625 0.03125 0.230 200 22 1.85 −60 −250 −10 −5 −1 −0.5 −0.25 +60 +250 1.0 to 12.0 ±5 30 40 400 ±0.5 ±0.1 9.8 −70 1.8 3.3 1.8 3.3 Full-channel mode Full-channel mode Full-channel mode, no signal, typical supply voltage × maximum supply current; excludes output current 5 1.6 Rev. 0 | Page 3 of 28 dB dB dB V p-p kΩ pF nV/√Hz 6.03 7.1 12.7 1.7 3.1 1.7 3.1 Relative to input 0.280 240 Unit +10 nV/√Hz dB dB LSB LSB MHz % −55 dB dB ns Degrees Degrees dB dB dBm dBc 1.9 3.5 1.9 3.5 190 190 22 2 170 V V V V mA mA mA mA mW +5 +1 +0.5 +0.25 mW mV/V AD8283 Parameter 1 ADC Resolution Max Sample Rate Signal-to-Noise Ratio (SNR) Signal-to-Noise and Distortion (SINAD) SNRFS Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Effective Number of Bits (ENOB) ADC Output Characteristics Maximum Cap Load IDVDD33 Peak Current with Cap Load ADC REFERENCE Output Voltage Error Load Regulation Input Resistance FULL CHANNEL CHARACTERISTICS SNRFS SINAD SFDR Harmonic Distortion Second Harmonic Third Harmonic IM3 Distortion Conditions Min Max 12 80 68.5 66 fIN = 1 MHz 1 10 10.67 Per bit Peak current per bit when driving a 20 pf load; can be programmed via the SPI port if required VREF = 1.024 V At 1.0 mA, VREF = 1.024 V Unit Bits MSPS dB dB 68 Guaranteed no missing codes 20 40 ±25 dB LSB LSB LSB pF mA 2 6 mV mV kΩ FIN = 1 MHz Gain = 16 dB Gain = 22 dB Gain = 28 dB Gain = 34 dB 68 68 68 66 dB dB dB dB FIN = 1 MHz Gain = 16 dB Gain = 22 dB Gain = 28 dB Gain = 34 dB 67 68 67 66 dB dB dB dB FIN = 1 MHz Gain = 16 dB Gain = 22 dB Gain = 28 dB Gain = 34 dB 68 74 74 73 dB dB dB dB −70 −70 −66 −75 −69 dBc dBc dBc dBc dBc 600 200 ns ns LNA, PGA, AAF, and ADC FIN =1 MHz at −10 dBFS, gain = 16 dB FIN =1 MHz at −10 dBFS, gain = 34 dB FIN =1 MHz at −10 dBFS, gain = 16 dB FIN =1 MHz at −10 dBFS, gain = 34 dB FIN1 = 1 MHz, f FIN2 = 1.1 MHz, −1 dBFS, gain = 34 dB Gain Response Time Overdrive Recovery Time 1 AD8283W Typ See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 28 AD8283 DIGITAL SPECIFICATIONS AVDD18x = 1.8 V, AVDD33 = 3.3 V, DVDD18 = 1.8 V, DVDD33 = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 80 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. Table 2. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CS) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) LOGIC OUTPUT (D[11:0], DSYNC) Logic 1 Voltage (IOH = 2 mA) Logic 0 Voltage (IOL = 2 mA) 1 2 3 Temperature Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 0 Full Full 3.0 Full Full 3.0 Typ Max Unit CMOS/LVDS/LVPECL mV p-p V kΩ pF 1.2 20 1.5 3.6 0.3 V V kΩ pF 3.6 0.3 V V kΩ pF DVDD33x + 0.3 0.3 V V kΩ pF 30 0.5 70 0.5 30 2 0.3 V V 0.05 V V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Specified for LVDS and LVPECL only. Specified for 13 SDIO pins sharing the same connection. Rev. 0 | Page 5 of 28 AD8283 SWITCHING SPECIFICATIONS AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 80 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. Table 3. Parameter 1 CLOCK Clock Rate Clock Pulse Width High (tEH) at 80 MSPS Clock Pulse Width Low (tEL) at 80 MSPS Clock Pulse Width High (tEH) at 40 MSPS Clock Pulse Width Low (tEL) at 40 MSPS OUTPUT PARAMETERS Propagation Delay (tPD) at 80 MSPS Rise Time (tR) Fall Time (tF) Data Set-Up Time (tDS) at 80 MSPS Data Hold Time (tDH) at 80 MSPS Data Set-Up Time (tDS) at 40 MSPS Data Hold Time (tDH) at 40 MSPS Pipeline Latency Min Full Full Full Full Full 10 Full Full Full Full Full Full Full Full 1.5 Typ Max Unit 80 MSPS ns ns ns ns 5.0 ns ns ns ns ns ns ns Clock cycles 6.25 6.25 12.5 12.5 9.0 1.5 21.5 1.5 2.5 1.9 1.2 10.0 4.0 22.5 4.0 7 11.0 5.0 23.5 5.0 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. N N –1 INAx CLK– tEL tEH CLK+ tDS tPD D[11:0] N–7 N–6 tDH N–5 N–4 N–3 Figure 2. Timing Definitions for Switching Specifications Rev. 0 | Page 6 of 28 N–2 N–1 N 09795-002 1 Temperature AD8283 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Electrical AVDD18x AVDD33x DVDD18x DVDD33x Analog Inputs INx+, INxAuxiliary Inputs INADC+, INADCDigital Outputs D[11:0], DSYNC, SDIO CLK+, CLK− PDWN, SCLK, CS, AUX, MUXA, ZSEL RBIAS, VREF Environmental Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) With Respect To Rating GND GND GND GND GND −0.3 V to +2.0 V −0.3 V to +3.5 V −0.3 V to +2.0 V −0.3 V to +3.5 V −0.3 V to +3.5 V GND −0.3 V to +2.0 V GND −0.3 V to +3.5 V GND GND −0.3 V to +3.9 V −0.3 V to +3.9 V GND −0.3 V to +2.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +105°C −65°C to +150°C 150°C 300°C Rev. 0 | Page 7 of 28 AD8283 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 NC DVDD33DRV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DVDD33DRV NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD8283 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 NC TEST4 DVDD18CLK CLK+ CLK– DVDD33CLK AVDD33REF VREF RBIAS BAND APOUT ANOUT TEST3 AVDD18ADC AVDD18 INADC+ INADC– NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE SHOULD BE TIED TO ANALOG/DIGITAL GROUND PLANE. 09795-003 NC NC AVDD33B INB– INB+ AVDD33C INC– INC+ AVDD33D IND– IND+ AVDD33E INE– INE+ AVDD33F INF– INF+ NC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC DSYNC PDWN DVDD18 SCLK SDIO CS AUX MUXA ZSEL TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA– INA+ NC Figure 3. Table 5. Pin Function Descriptions Pin No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Name GND NC DSYNC PDWN DVDD18 SCLK SDIO CS AUX MUXA ZSEL TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA− INA+ NC NC NC AVDD33B INB−INB+ AVDD33C INC− INC+ Description Ground. Exposed paddle on the bottom side; should be tied to the analog/digital ground plane. No Connection. Pin can be tied to any potential. Data Out Synchronization. Full Power-Down. Logic high overrides SPI and powers down the part, logic low allows selection through SPI. 1.8 V Digital Supply. Serial Clock. Serial Data Input/Output. Chip Select Bar. Logic high forces to Channel ADC (INADC+/INADC−); AUX has a higher priority than MUXA. Logic high forces to Channel A unless AUX is asserted. Input Impedance Select. Logic high overrides SPI and sets it to 200 kΩ; logic low allows selection through SPI. Pin should not be used; tie to ground. Pin should not be used; tie to ground. 3.3 V Digital Supply, SPI Port. 1.8 V Analog Supply. 3.3 V Analog Supply, Channel A. Negative LNA Analog Input for Channel A. Positive LNA Analog Input for Channel A. No Connect. Pin can be tied to any potential. No Connect. Pin can be tied to any potential. No Connect. Pin can be tied to any potential. 3.3 V Analog Supply, Channel B. Negative LNA Analog Input for Channel B. Positive LNA Analog Input for Channel B. 3.3 V Analog Supply, Channel C. Negative LNA Analog Input for Channel C. Positive LNA Analog Input for Channel C. Rev. 0 | Page 8 of 28 AD8283 Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name AVDD33D IND− IND+ AVDD33E INE− INE+ AVDD33F INF− INF+ NC NC INADC− INADC+ AVDD18 AVDD18ADC TEST3 ANOUT APOUT BAND RBIAS VREF AVDD33REF DVDD33CLK CLKCLK+ DVDD18CLK TEST4 NC NC DVDD33DRV D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NC NC DVDD33DRV NC Description 3.3 V Analog Supply, Channel D. Negative LNA Analog Input for Channel D. Positive LNA Analog Input for Channel D. 3.3 V Analog Supply, Channel E. Negative LNA Analog Input for Channel E. Positive LNA Analog Input for Channel E. 3.3 V Analog Supply, Channel F. Negative LNA Analog Input for Channel F. Positive LNA Analog Input for Channel F. No Connect, Pin can be tied to any potential. No Connect. Pin can be tied to any potential. Negative Analog Input for Alternate Channel F (ADC Only). Positive Analog Input for Alternate Channel F (ADC Only). 1.8 V Analog Supply. 1.8 V Analog Supply, ADC. Pin should not be used; tie to ground. Analog Outputs (Debug Purposes Only). Pin should be floated. Analog Outputs (Debug Purposes Only). Pin should be floated. Band Gap Voltage (Debug Purposes Only). Pin should be floated. External resistor to set the internal ADC core bias current. Voltage Reference Input/Output. 3.3 V Analog Supply, References. 3.3 V Digital Supply, Clock. Clock Input Complement. Clock Input True. 1.8 V Digital Supply, Clock. Pin should not be used; tie to ground. No Connect. Pin can be tied to any potential. No Connect. Pin can be tied to any potential. 3.3 V Digital Supply, Output Driver. ADC Data Out (MSB). ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out. ADC Data Out (LSB). No Connect. Pin should be left open. No Connect. Pin should be left open. 3.3 V Supply, Output Driver. No Connect. Pin can be tied to any potential. Rev. 0 | Page 9 of 28 AD8283 TYPICAL PERFORMANCE CHARACTERISTICS 50 34dB 28dB 22dB 16dB 10 0 –10 –20 –40 0.1 1 10 100 FREQUENCY (MHz) 09795-014 –30 33.50 GAIN ERROR (dB) 0.6 34dB 28dB 22dB 16dB 0.4 0.2 0 –0.2 –0.4 –0.6 –15 10 35 60 85 TEMPERATURE (°C) 09795-038 –0.8 –1.0 –40 33.90 33.98 34.06 34.14 34.22 34.30 34.38 34.46 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25 (dB) 10 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 PERCENTAGE OF DEVICES (%) 9 8 7 6 5 4 3 2 1 16.08 16.16 16.24 16.32 16.4 16.48 16.56 16.64 16.72 16.8 16.88 (dB) 16.96 0 09795-032 PERCENTAGE OF DEVICES (%) 33.82 Figure 8. Channel-to-Channel Gain Matching (Gain = 16 dB) Figure 5. Gain Error vs. Temperature at All Gains 16.00 33.74 Figure 7. Gain Error Histogram (Gain = 34 dB) PERCENTAGE OF DEVICES (%) 0.8 33.66 (LSB) Figure 4. Channel Gain vs. Frequency 1.0 33.58 09795-034 GAIN (dB) 20 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25 (dB) Figure 6. Gain Error Histogram (Gain = 16 dB) Figure 9. Channel-to-Channel Gain Matching (Gain = 34 dB) Rev. 0 | Page 10 of 28 09795-035 30 PERCENTAGE OF DEVICES (%) 40 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 09795-033 VS = 3.3 V, 1.8 V, TA = 25°C, FS = 80 MSPS, RIN =200 kΩ, VREF = 1.0 V. AD8283 12000 70 10000 65 SNR SNR/SINAD (dBFS) 6000 4000 55 50 0 1 2 3 4 5 6 7 CODE 40 16 09795-015 –7 –6 –5 –4 –3 –2 –1 22 20 6000 10 5000 0 GAIN (dB) 7000 4000 3000 –10 –20 2000 –30 1000 –40 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 CODE 34 Figure 13. SNR vs. Gain 12MHz 8MHz 4MHz 2MHz 1MHz –50 0.1 09795-016 NUMBER OF HITS Figure 10. Output Referred Noise Histogram (Gain = 16 dB) 0 28 GAIN (dB) 09795-017 45 2000 0 60 1 10 100 FREQUENCY (Hz) Figure 11. Output Referred Noise Histogram (Gain = 34 dB) 09795-022 NUMBER OF HITS SINAD 8000 Figure 14. Filter Response 15 200 180 160 NOISE (nV/√Hz) 16dB 5 100 28dB 40 34dB 20 1 28dB 80 22dB 10 FREQUENCY (MHz) 16dB 0 0.1 1 FREQUENCY (MHz) 10 Figure 15. Short-Circuit Output-Referred Noise vs. Frequency Figure 12. Short Circuit Input-Referred Noise vs. Frequency Rev. 0 | Page 11 of 28 09795-031 0 0.1 120 60 22dB 09795-030 NOISE (nV/√Hz) 34dB 140 10 AD8283 1000 1.5 1MHz 2MHz 4MHz 8MHz 12MHz 900 800 1.0 AMPLITUDE (V) DELAY (ns) 700 600 500 400 300 200 0.5 0 –0.5 –1.0 1 10 100 FREQUENCY (MHz) –1.5 09795-019 0 0.1 0 0.5 2.0 2.5 3.0 4.0 LEVEL 560mV –50 TRIG HOLDOFF 1.5µs –55 MEAN(C2) 7.177mV µ: 7.1773964m m: 7177m M: 7.177m σ: 0 SDO MEAN(C2) 220mV µ: 220m m: 220m M: 220m σ: 0 3 –65 ANALOG OUTPUT FREQ(C2) 997.8kHz µ: 997.75504k m: 997.8k M: 997.8k σ: 0 2 –80 0 1 2 3 4 5 6 7 INPUT FREQUENCY (MHz) 09795-039 –75 CH2 500mV Ω CH3 1V M1µs 1.25GS/s A CH2 560mV 09795-024 –60 –70 800ps/pt Figure 20. Gain Step Response Figure 17. Harmonic Distortion vs. Frequency 200000 450 180000 400 160000 350 140000 300 120000 250 100000 200 80000 150 60000 100 40000 50 20000 30 25 NOISE FIGURE (dB) 500 20 34dB 50Ω TERMINATED 15 10 34dB UNTERMINATED 0 0.01 0.1 1 10 FREQUENCY (MHz) 0 100 0 0.1 1 FREQUENCY (MHz) Figure 21. Noise Figure vs. Frequency Figure 18. RIN vs. Frequency Rev. 0 | Page 12 of 28 10 09795-042 5 09795-040 IMPEDANCE (Ω) 3.5 Figure 19. Overdrive Recovery SECOND –1dBFS SECOND –10dBFS THIRD –1dBFS THIRD –10dBFS –45 HARMONIC (dBc) 1.5 TIME (µs) Figure 16. Group Delay vs. Frequency –40 1.0 09795-041 100 AD8283 12 11 8 10 PERCENTAGE OF DEVICES (%) 9 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 –60 –52 –44 –36 –28 –20 –12 –4 4 12 20 28 36 44 52 60 –56 –48 –40 –32 –24 –16 –8 0 8 16 24 32 40 48 56 (LSB) 0 –200 –160 –120 –80 –40 0 40 80 120 160 200 –180 –140 –100 –60 –20 20 60 100 140 180 (LSB) Figure 22. Channel Offset Distribution (Gain = 16 dB) Figure 23. Channel Offset Distribution (Gain = 34 dB) Rev. 0 | Page 13 of 28 09795-037 1 0 09795-036 PERCENTAGE OF DEVICES (%) 10 AD8283 THEORY OF OPERATION AAF cutoff characteristics, and ADC sample rate and resolution. RADAR RECEIVE PATH AFE The primary application for the AD8283 is high-speed ramp, frequency modulated, continuous wave radar (HSR-FMCW radar). Figure 25 shows a simplified block diagram of an HSRFMCW radar system. The signal chain requires multiple channels, each including a low noise amplifier (LNA), a programmable gain amplifier (PGA), an antialiasing filter (AAF), and an analog-to-digital converter (ADC). The AD8283 provides all of these key components in a single 10 × 10 LFCSP package. The AD8283 includes a multiplexer (mux) in front of the ADC as a cost saving alternative to having an ADC for each channel. The mux automatically switches between each active channel after each ADC sample. The DSYNC output indicates when Channel A data is at the ADC output, and data for each active channel follows sequentially with each clock cycle. The effective sample rate for each channel is reduced by a factor equal to the number of active channels. The ADC resolution of 12 bits with up to 80 MSPS sampling satisfies the requirements for most HSR-FMCW approaches. The performance of each component is designed to meet the demands of an HSR-FMCW radar system. Some examples of these performance metrics are the LNA noise, PGA gain range, REF. OSCILLATOR VCO CHIRP RAMP GENERATOR LNA PGA AAF LNA PGA AAF 12-BIT ADC MUX LNA PGA DSP AAF 09795-004 PA AD8283 ANTENNA Figure 24. Radar System Overview SDIO SCLK AD8283 SPI INTERFACE MUX CONTROLLER DSYNC 200Ω/ 200kΩ INx– LNA 22dB PGA –6dB, 0dB, 6dB, 12dB AAF MUX THIRD-ORDER ELLIPTICAL FILTER PIPELINE ADC PARALLEL 3.3V CMOS 12-BIT 80MSPS Figure 25. Simplified Block Diagram of a Single Channel Rev. 0 | Page 14 of 28 D11:D0 09795-005 INx+ AD8283 CHANNEL OVERVIEW Each channel contains an LNA, a PGA, and an AAF in the signal path. The LNA input impedance can be either 200 Ω or 200 kΩ. The PGA has selectable gains that result in channel gains ranging from 16 dB to 34 dB. The AAF has a three-pole elliptical response with a selectable cutoff frequency. The mux is synchronized with the ADC and automatically selects the next active channel after the ADC acquires a sample. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion including the LNA, which is designed to be driven from a differential signal source. Low Noise Amplifier (LNA) Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contributions on the following PGA and AAF. The input impedance can be either 200 Ω or 200 kΩ and is selected through the SPI port or by the ZSEL pin. The LNA supports differential output voltages as high as 4.0 V p-p with positive and negative excursions of ±1.0 V from a commonmode voltage of 1.5 V. With the output saturation level fixed, the channel gain sets the maximum input signal before saturation. Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low inputreferred noise voltage of 3.5 nV/√Hz at a channel gain of 34 dB. The use of a fully differential topology and negative feedback minimizes second-order distortion. Differential signaling enables smaller swings at each output, further reducing thirdorder distortion. Recommendation To achieve the best possible noise performance, it is important to match the impedances seen by the positive and negative inputs. Matching the impedances ensures that any commonmode noise is rejected by the signal path. Antialiasing Filter (AAF) The antialiasing filter uses a combination of poles and zeros to create a third-order elliptical filter. An elliptical filter is used to achieve a sharp roll off after the cutoff frequency. The filter uses on-chip tuning to trim the capacitors to set the desired cutoff frequency. This tuning method reduces variations in the cutoff frequency due to standard IC process tolerances of resistors and capacitors. The default −3 dB low-pass filter cutoff is 1/3 or 1/4 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. A cut-off range of 1 MHz to 12 MHz is possible. An example follows: • • • • Four channels selected: A, B, C, and AUX ADC clock: 30 MHz Per channel sample rate = 30/4 = 7.5 MSPS Default tuned cutoff frequency = 7.5/4 = 1.88 MHz Mux and Mux Controller The mux is designed to automatically scan through each active channel. The mux remains on each channel for one clock cycle, then switches to the next active channel. The mux switching is synchronized to the ADC sampling so that the mux switching and channel settling time do not interfere with ADC sampling. As indicated in Table 8, Register Address 0C, Flex Mux Control, Channel A, is usually the first converted input. The one exceptions occurs when Channel AUX is the sole input (see Figure 26 for timing). Channel AUX is always forced to be the last converted input. Unselected codes put the respective channels (LNA, PGA, and Filter) in power-down mode unless Register Address 0C, Bit 6, is set to 1. Figure 26 shows the timing of the clock input and data/DSYNC outputs. The filter that the signal reaches prior to the ADC is used to band limit the signal for antialiasing. Rev. 0 | Page 15 of 28 AD8283 N N+1 INAx CLK– CLK+ D[11:0] XXXX OUTAN – 1 OUTB OUTC OUTD OUTE OUTF OUTB OUTAN tPD DSYNC tDH NOTES 1. FOR ABOVE CONFIGURATION REGISTER ADDRESS 0C SET TO 1010 (CHANNEL A, B, C, D, E AND F ENABLED). 2. DSYNC IS ALWAYS ALIGNED WITH CHANNEL A UNLESS CHANNEL A OR CHANNEL AUX IS THE ONLY CHANNEL SELECTED, IN WHICH CASE DSYNC IS NOT ACTIVE. 3. THERE IS A SEVEN CLOCK CYCLE LATENCY FROM SAMPLING A CHANNEL TO ITS DIGITAL DATA BEING PRESENT ON THE PARALLEL BUS PINS. 09795-006 tDS Figure 26. Data and DSYNC Timing ADC 3.3V The AD8283 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. Figure 27 shows the preferred method for clocking the AD8283. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50MHz, is converted from single ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD8283 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD8283, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. CLK+ ADC AD8283 0.1µF CLK– 09795-007 SCHOTTKY DIODES: HSM2812 0.1µF Figure 27. Transformer-Coupled Differential Clock If a low jitter clock is available, another option is to ac-couple a differential PECL or LVDS signal to the sample clock input pins as shown in and Figure 28 and Figure 29. The AD951x/AD952x family of clock drivers offers excellent jitter performance. 3.3V 50Ω* VFAC3 OUT AD951x/AD952x FAMILY 0.1µF 0.1µF CLK+ CLK 0.1µF 100Ω PECL DRIVER 0.1µF CLK 240Ω *50Ω ADC AD8283 CLK– 240Ω 09795-008 For optimum performance, the AD8283 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or using capacitors. These pins are biased internally and require no additional bias. VFAC3 50Ω 100Ω RESISTOR IS OPTIONAL. Figure 28. Differential PECL Sample Clock 3.3V 50Ω* VFAC3 AD951x/AD952x FAMILY 0.1µF OUT 0.1µF CLK+ CLK 0.1µF LVDS DRIVER 100Ω 0.1µF CLK *50Ω RESISTOR IS OPTIONAL. Figure 29. Differential LVDS Sample Clock Rev. 0 | Page 16 of 28 ADC AD8283 CLK– 09795-009 CLOCK INPUT CONSIDERATIONS 0.1µF OUT MINI-CIRCUITS® ADT1-1WT, 1:1Z 0.1µF XFMR AD8283 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 30). Although the CLK+ input circuit supply is AVDD18, this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible. The AD951x/AD952x family of parts can be used to provide 3.3 V inputs (see Figure 31). In this case, 39 kΩ is not needed. 3.3V AD951x/AD952x FAMILY 0.1µF CLK 50Ω* 1.8V CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK+ ADC AD8283 CLK 0.1µF CLK– 0.1µF 39kΩ 09795-010 VFAC3 OUT *50Ω RESISTOR IS OPTIONAL. Figure 30. Single-Ended 1.8 V CMOS Sample Clock 3.3V 0.1µF CLK 50Ω* 3.3V CMOS DRIVER CLK 0.1µF OPTIONAL 0.1µF 100Ω 0.1µF ADC AD8283 CLK– Figure 31. Single-Ended 3.3 V CMOS Sample Clock In this equation, the RMS aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD8283. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step. The SDIO pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. SCLK PIN CLOCK DUTY CYCLE CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD8283 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD8283. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See Table 8 for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. SNR Degradation = 20 × log 10[1/2 × π × fA × tJ] SDIO PIN CLK+ *50Ω RESISTOR IS OPTIONAL. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs (visit www.analog.com). AD951x/AD952x FAMILY 09795-011 VFAC3 OUT CLOCK JITTER CONSIDERATIONS The SCLK pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. CS PIN The CS pin is required to operate the SPI port interface. It has an internal 70 kΩ pull-up resistor that pulls this pin high and is both 1.8 V and 3.3 V tolerant. RBIAS PIN To set the internal core bias current of the ADC, place a resistor nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using other than the recommended 10.0 kΩ resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1.0% tolerance on this resistor be used to achieve consistent performance. VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD8283. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V Rev. 0 | Page 17 of 28 AD8283 reference to achieve more accuracy. However, this device does not support ADC full-scale ranges below 2.0 V p-p. When applying the decoupling capacitors to the VREF pin, use ceramic low-ESR capacitors. These capacitors should be close to the reference pin and on the same layer of the PCB as the AD8283. The VREF pin should have both a 0.1 μF capacitor and a 1 μF capacitor connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample. POWER AND GROUND RECOMMENDATIONS When connecting power to the AD8283, it is recommended that two separate 1.8 V supplies and two separate 3.3 V supplies be used: one for analog 1.8 V (AVDD18x) and digital 1.8 V (DVDD18x) and one for analog 3.3 V (AVDD33x) and digital 3.3 V (DVDD33x). If only one supply is available for both analog and digital, for example, AVDD18x and DVDD18x, it should be routed to the AVDD18x first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DVDD18x. The same is true for the analog and digital 3.3 V supplies. The user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts, with minimal trace lengths. A single PC board ground plane should be sufficient when using the AD8283. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance can be achieved easily. EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD8283. An exposed continuous copper plane on the PCB should mate to the AD8283 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the device and PCB, partition the continuous copper pad by overlaying a silkscreen or solder mask to divide this into several uniform sections. This ensures several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the AD82833 and PCB. For more detailed information on packaging and for more PCB layout examples, see the AN-772 Application Note. Rev. 0 | Page 18 of 28 AD8283 SERIAL PERIPHERAL INTERFACE (SPI) The AD8283 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., AN-877 Application Note, Interfacing to High Speed ADCs via SPI. There are three pins that define the serial port interface, or SPI. They are the SCLK, SDIO, and CS pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the device’s internal memory map registers. The CS (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 6). Table 6. Serial Port Pins Pin SCLK SDIO CS Function Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles. The falling edge of the CS in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 32 and Table 7. In normal operation, CS is used to signal to the device that SPI commands are to be received and processed. When CS is brought low, the device processes SCLK and SDIO to process instructions. Normally, CS remains low until the communication cycle is complete. However, if connected to a slow device, CS can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CS can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CS is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CS is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CS line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the SDIO Pin and SCLK Pin sections. CS can also be tied low to enable 2-wire mode. When CS is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CS line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CS line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 6 constitute the physical interface between the user’s programming device and the serial port of the AD8283. The SCLK and CS pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. This interface is flexible enough to be controlled by either serial PROMS or PIC microcontrollers. This provides the user with an alternative method, other than a full SPI controller, for programming the device (see the AN-812 Application Note). If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions when the CS is strapped to AVDD during device power-up. See the SDIO Pin and SCLK Pin sections for details on which pinstrappable functions are supported on the SPI pins. Rev. 0 | Page 19 of 28 AD8283 tDS tS tHI tCLK tDH CS tH tLO SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 09795-012 SCLK DON’T CARE Figure 32. Serial Timing Details Table 7. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Minimum Timing (ns) 5 2 40 5 2 16 16 10 tDIS_SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CS and SCLK Hold time between CS and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 32). Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 32) Rev. 0 | Page 20 of 28 AD8283 MEMORY MAP READING THE MEMORY MAP TABLE LOGIC LEVELS Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 and Address 0x01), the device index and transfer registers map (Address 0x04 to Address 0xFF), and the ADC channel functions registers map (Address 0x08 to Address 0x2C). An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address followed by an 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers. RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 8, where an X refers to an undefined feature. Note that all registers except Register 0x00, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 21 of 28 AD8283 Table 8. AD8283 Memory Map Register Addr. (Hex) Register Name Chip Configuration Registers 00 CHIP_PORT_CONFIG 01 Bit 7 (MSB) 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) CHIP_ID Bit 0 (LSB) Default Value Default Notes/ Comments 0 0x18 The nibbles should be mirrored so that LSB- or MSB-first mode is set correct regardless of shift mode. The default is a unique chip ID, specific to the AD8283. This is a read-only register. Chip ID Bits[7:0] (AD8283 = 0xA2, default) Read only Device Index and Transfer Registers 04 DEVICE_INDEX_2 X X X X X X 05 DEVICE_INDEX_1 X X X X FF DEVICE_UPDATE X X X X Data Channel D 1 = on (default) 0 = off X Data Channel C 1 = on (default) 0 = off X Channel Functions Registers 08 GLOBAL_MODES X X X X X X 09 GLOBAL_CLOCK X X X X 0C FLEX_MUX_CONTROL X Powerdown of unused channels 0 = PD (powerdown; default) 1= power-on X X Data Channel E 1 = on (default) 0 = off Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F Internal powerdown mode 00 = chip run (default) 01 = full powerdown 11 = reset X X X Duty cycle stabilizer 1 = on (default) 0 = off Mux input active channels 0000 = A 0001 = Aux 0010 = AB 0011 = A Aux 0100 = ABC 0101 = AB Aux 0110 = ABCD 0111 = ABC Aux 1000 = ABCDE 1001 = ABCD Aux 1010 = ABCDEF 1011 = ABCDE Aux 0x00 Determines the power-down mode (global). 0x01 Turns the internal duty cycle stabilizer on and off (global). 0x00 Sets which mux input channel(s) are in use and whether to power down unused channels. Rev. 0 | Page 22 of 28 Data Channel F 1 = on (default) 0 = off Data Channel B 1 = on (default) 0 = off X 0x0F 0x00 Bits are set to determine which on-chip device receives the next write command. Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. AD8283 Addr. (Hex) 0D Register Name FLEX_TEST_IO 0F FLEX_CHANNEL_INPUT 10 FLEX_OFFSET 11 FLEX_GAIN_1 X X X X 12 FLEX_BIAS_CURRENT X X X X 14 FLEX_OUTPUT_MODE X X X X 15 FLEX_OUTPUT_ADJUST 0= enable Data Bits [11:0] 1= disable Data Bits [11:0] X X X Bit 7 (MSB) Bit 6 User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Bit 5 Reset PN long gen 1 = on 0 = off (default) Bit 4 Reset PN short gen 1 = on 0 = off (default) Bit 0 (LSB) Bit 3 Bit 2 Bit 1 Output test mode—see Table 9 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the OUTPUT_MODE register) X X X X Filter cutoff frequency control 0000 = 1.3 × 1/4 × fSAMPLECH 0001 = 1.2 × 1/4 × fSAMPLECH 0010 = 1.1 × 1/4 × fSAMPLECH 0011 = 1.0 × 1/4 × fSAMPLECH (default) 0100 = 0.9 × 1/4 × fSAMPLECH 0101 = 0.8 × 1/4 × fSAMPLECH 0110 = 0.7 × 1/4 × fSAMPLECH 0111 = N/A 1000 = 1.3 × 1/3 × fSAMPLECH 1001 = 1.2 × 1/3 × fSAMPLECH 1010 = 1.1 × 1/3 × fSAMPLECH 1011 = 1.0 × 1/3 × fSAMPLECH 1100 = 0.9 × 1/3 × fSAMPLECH 1101 = 0.8 × 1/3 × fSAMPLECH 1110 = 0.7 × 1/3 × fSAMPLECH 1111 = N/A X X 6-bit LNA offset adjustment 10 0000 for LNA bias high, mid-high, mid-low (default) 10 0001 for LNA bias low X 010 = 16 dB(default) 011 = 22 dB 100 = 28 dB 101 = 34 dB 1 X LNA bias 00 = high 01 = mid-high (default) 10 = mid-low 11 = low X 1= 0 = offset binary output (default) invert 1 = twos comple(local) ment (global) Output drive current 0000 = low 1111 = high (default) Rev. 0 | Page 23 of 28 Default Value 0x00 Default Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data. (Local, except for PN sequence.) 0x30 Low pass filter cutoff (global). fSAMPLECH = ADC sample rate/ number of active channels. Note that the absolute range is limited to 1 MHz to 12 MHz. 0x20 LNA force offset correction (local). Total LNA + PGA gain adjustment (local) LNA bias current adjustment (global). 0x00 0x09 0x00 Configures the outputs and the format of the data. 0x0F Used to select output drive strength to limit the noise added to the channels by output switching. AD8283 Addr. (Hex) 18 Register Name FLEX_VREF Bit 7 (MSB) X 19 FLEX_USER_PATT1_LSB 1A FLEX_USER_PATT1_ MSB FLEX_USER_PATT2_LSB 1B Bit 0 (LSB) Bit 1 00 = 0.625 V 01 = 0.750 V 10 = 0.875 V 11 = 1.024 V (default) Default Value 0x03 B2 B1 B0 0x00 B11 B10 B9 B8 0x00 B4 B3 B2 B1 B0 0x00 B11 B10 B9 B8 0x00 Bit 6 0= internal reference 1= external reference Bit 5 X Bit 4 X Bit 3 X Bit 2 X B7 B6 B5 B4 B3 B15 B14 B13 B12 B7 B6 B5 1C FLEX_USER_PATT2_ MSB B15 B14 B13 B12 2B FLEX_FILTER X X X 2C CH_IN_IMP X Enable automatic low-pass tuning 1 = on (selfclearing) X X X Default Notes/ Comments Select internal reference (recommended default) or external reference (global); adjust internal reference. User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSBs. User-defined pattern, 2 MSBs. 0x00 X X 0= 200Ω (default) 1= 200kΩ 0x00 Input impedance adjustment (global). Table 9. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard output PN sequence long PN sequence short One-/zero-word toggle User input 1-/0-bit toggle 1× sync One bit high Mixed bit frequency Digital Output Word 1 N/A 1000 0000 0000 1111 1111 1111 0000 0000 0000 1010 1010 1010 N/A N/A 1111 1111 1111 Register 0x19 to Register 0x1A 1010 1010 1010 0000 0011 1111 1000 0000 0000 1010 0011 0011 Rev. 0 | Page 24 of 28 Digital Output Word 2 N/A Same Same Same 0101 0101 0101 N/A N/A 0000 0000 0000 Register 0x1B to Register 0x1C N/A N/A N/A N/A Subject to Data Format Select N/A Yes Yes Yes No Yes Yes No No No No No No AD8283 APPLICATION DIAGRAMS AVDD33REF 0.1µF 3.3V DVDD33SPI 0.1µF 3.3V AVDD33A 0.1µF DVDD33CLK 0.1µF AVDD33B 0.1µF DVDD33DRV 0.1µF AVDD33C 0.1µF DVDD33DRV 0.1µF 1.8V DVDD18 0.1µF 1.8V AVDD18 0.1µF AVDD18 0.1µF DVDD18CLK 0.1µF AVDD18ADC 0.1µF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 AVDD33D 0.1µF 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33E 0.1µF 10kΩ 0.1µF INA+ 0.1µF AD8283 (TOP VIEW) NC TEST4 DVDD18CLK CLK+ CLK– DVDD33CLK AVDD33REF VREF RBIAS BAND APOUT ANOUT TEST3 AVDD18ADC AVDD18 INADC+ INADC– NC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 INA– NC DSYNC PDWN DVDD18 SCLK SDIO CS AUX MUXA ZSEL TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA– INA+ NC INB– 0.1µF 0.1µF INADC+ 0.1µF INADC– 0.1µF INF– 0.1µF INE– 0.1µF IND– INF+ 0.1µF INB+ 0.1µF 0.1µF INC– 54 53 52 51 CLK+ 50 CLK– 49 48 47 46 10kΩ 0.1µF 45 44 1% 0.1µF 43 42 41 40 39 38 37 INE+ 0.1µF INC+ 0.1µF 0.1µF IND+ NOTES 1. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE PART. Figure 33. Differential Inputs Rev. 0 | Page 25 of 28 09795-013 SDIO CS AUX MUXA ZSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NC NC AVDD33B INB– INB+ AVDD33C INC– INC+ AVDD33D IND– IND+ AVDD33E INE– INE+ AVDD33F INF– INF+ NC NC DSYNC PDWN SCLK NC DVDD33DRV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DVDD33DRV NC AVDD33F 0.1µF AD8283 AVDD33REF 0.1µF 3.3V DVDD33SPI 0.1µF 3.3V AVDD33A 0.1µF DVDD33CLK 0.1µF AVDD33B 0.1µF DVDD33DRV 0.1µF AVDD33C 0.1µF DVDD33DRV 0.1µF 1.8V DVDD18 0.1µF 1.8V AVDD18 0.1µF AVDD18 0.1µF DVDD18CLK 0.1µF AVDD18ADC 0.1µF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 AVDD33D 0.1µF 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33E 0.1µF 10kΩ R 0.1µF AD8283 (TOP VIEW) NC TEST4 DVDD18CLK CLK+ CLK– DVDD33CLK AVDD33REF VREF RBIAS BAND APOUT ANOUT TEST3 AVDD18ADC AVDD18 INADC+ INADC– NC 0.1µF 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 INA NC DSYNC PDWN DVDD18 SCLK SDIO CS AUX MUXA ZSEL TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA– INA+ NC INB 0.1µF INC 0.1µF 54 53 52 51 CLK+ 50 CLK– 49 48 47 46 10kΩ 0.1µF 45 44 1% 0.1µF 43 42 41 40 39 38 37 0.1µF 0.1µF INF 0.1µF INE 0.1µF IND NOTES 1. RESISTOR R (INx– INPUTS) SHOULD MATCH THE OUTPUT IMPEDANCE OF THE INPUT DRIVER. 2. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE PART. Figure 34. Single-Ended Inputs Rev. 0 | Page 26 of 28 0.1µF INADC+ INADC– 09795-029 SDIO CS AUX MUXA ZSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NC NC AVDD33B INB– INB+ AVDD33C INC– INC+ AVDD33D IND– IND+ AVDD33E INE– INE+ AVDD33F INF– INF+ NC NC DSYNC PDWN SCLK NC DVDD33DRV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DVDD33DRV NC AVDD33F 0.1µF AD8283 OUTLINE DIMENSIONS 10.00 BSC SQ 0.60 0.42 0.24 0.60 0.42 0.24 55 PIN 1 INDICATOR 72 1 54 PIN 1 INDICATOR 9.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 EXPOSED PAD 37 18 36 19 TOP VIEW 12° MAX 0.05 MAX 0.01 NOM COPLANARITY 0.08 0.20 REF 0.30 0.23 0.18 SEATING PLANE 0.25 MIN 8.50 REF 0.70 0.65 0.60 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 07-26-2010-C 0.90 0.85 0.80 8.60 8.50 SQ 8.40 (BOTTOM VIEW) Figure 35. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-5) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2, 3 AD8283WBCPZ-RL AD8283WBCPZ 1 2 3 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 72-Lead LFCSP_VQ, 13” Tape and Reel 72-Lead LFCSP_VQ, Waffle Pack Package Option CP-72-5 CP-72-5 Z = RoHS Compliant Part. W = Qualilfied for Automotive Applications. Compliant to JEDEC Standard MO-220-VNND-4. AUTOMOTIVE PRODUCTS The AD8283WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. Rev. 0 | Page 27 of 28 AD8283 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09795-0-4/11(0) Rev. 0 | Page 28 of 28