Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23 AD7457 FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for VDD of 2.7 V to 5.25 V Low power: 0.9 mW max at 100 kSPS with VDD = 3 V 3 mW max at 100 kSPS with VDD = 5 V Pseudo differential analog input Wide input bandwidth: 70-dB SINAD at 30 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface—SPI®/QSPI™/ MICROWIRE™/DSP compatible Automatic power-down mode 8-lead SOT-23 package VDD VIN+ 12-BIT SUCCESSIVE APPROXIMATION ADC T/H VIN– VREF SCLK SDATA AD7457 CONTROL LOGIC CS Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation 03157-0-013 APPLICATIONS GND Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7457 is a 12-bit, low power, successive approximation (SAR) analog-to-digital converter that features a pseudo differential analog input. This part operates from a single 2.7 V to 5.25 V power supply and features throughput rates of up to 100 kSPS. 1. Operation with 2.7 V to 5.25 V power supplies. 2. Low power consumption. With a 3 V supply, the AD7457 offers 0.9 mW maximum power consumption for a 100 kSPS throughput rate. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier (T/H) that can handle input frequencies in excess of 1 MHz. The reference voltage for the AD7457 is applied externally to the VREF pin and can range from 100 mV to VDD, depending on what suits the application. 3. Pseudo differential analog input. 4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. Automatic powerdown after conversion allows the average power consumption to be reduced. 5. Variable voltage reference input. 6. No pipeline delay. 7. Accurate control of the sampling instance via the CS input and once-off conversion control. 8. ENOB > 10 bits typically with 500 mV reference. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the device to interface with microprocessors or DSPs. The SAR architecture of this part ensures that there are no pipeline delays. The AD7457 uses advanced design techniques to achieve very low power dissipation. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7457 TABLE OF CONTENTS Specifications..................................................................................... 3 Analog Input ............................................................................... 12 Timing Specifications....................................................................... 5 Analog Input Structure.............................................................. 12 Absolute Maximum Ratings............................................................ 6 Digital Inputs .............................................................................. 13 ESD Caution.................................................................................. 6 Reference Section ....................................................................... 13 Pin Configuration and Functional Descriptions.......................... 7 Serial Interface ............................................................................ 13 Terminology ...................................................................................... 8 Power Consumption .................................................................. 14 Typical Performance Characteristics ............................................. 9 Microprocessor Interfacing....................................................... 14 Theory of Operation ...................................................................... 11 Application Hints ........................................................................... 16 Circuit Information.................................................................... 11 Grounding and Layout .............................................................. 16 Converter Operation.................................................................. 11 Outline Dimensions ....................................................................... 17 ADC Transfer Function............................................................. 11 Ordering Guide .......................................................................... 17 Typical Connection Diagram ................................................... 11 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD7457 SPECIFICATIONS VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal to Noise Ratio (SNR)2 Signal to (Noise + Distortion) (SINAD)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise2 Intermodulation DIstortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay2 Aperture Jitter2 Full-Power Bandwidth2,3 DC ACCURACY Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Offset Error2 Gain Error2 ANALOG INPUT Full-Scale Input Span Absolute Input Voltage VIN+ VIN– 4 DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN6 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance6 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate B Version1 Unit 71 70 −75 −75 dB min dB min dB max dB max −80 −80 5 50 20 2.5 dB typ dB typ ns typ ps typ MHz typ MHz typ Guaranteed no missed codes to 12 bits 12 ±1 ±0.95 ±4.5 ±2 Bits LSB max LSB max LSB max LSB max VIN+ − V IN– VREF V VREF −0.1 to +0.4 −0.1 to +1.5 ±1 30/10 V V V µA max pF typ 2.55 ±1 10/30 V µA max pF typ 2.4 0.8 ±1 10 V min V max µA max pF max VDD = 4.75 V to 5.25 V, ISOURCE = 200 µA VDD = 2.7 V to 3.6 V, ISOURCE = 200 µA ISINK = 200 µA 2.8 2.4 0.4 ±1 10 Straight natural binary V min V min V max µA max pF max 1.6 µs with a 10 MHz SCLK 16 1 100 SCLK cycles µs max kSPS max Test Conditions/Comments fIN = 30 kHz −84 dB typ −86 dB typ fa = 25 kHz; fb = 35 kHz @ −3 dB @ −0.1 dB VDD = 2.7 V to 3.6 V VDD = 4.75 V to 5.25 V When in track/hold ±1% tolerance for specified performance When in track/hold Typically 10 nA, VIN = 0 V or VDD See Serial Interface section Rev. 0 | Page 3 of 20 AD7457 Parameter POWER REQUIREMENTS VDD IDD7,8 During Conversion6 Normal Mode (Static) Normal Mode (Operational) Power-Down Power Dissipation Normal Mode (Operational) Power-Down B Version1 Unit 2.7/5.25 V min/max VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V SCLK on or off VDD = 4.75 V to 5.25 V VDD= 2.7 V to 3.6 V SCLK on or off 1.5 1.2 0.5 0.7 0.33 1 mA max mA max mA typ mA max mA max µA max VDD = 5 V VDD = 3 V VDD = 5 V; SCLK on or off VDD = 3 V; SCLK on or off 3 0.9 5 3 mW max mW max µW max µW max Test Conditions/Comments 1 Temperature ranges as follows: B version: −40°C to +85°C. See Terminology section. 3 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the converter. 4 A dc input is applied to VIN– to provide a pseudo ground for VIN+. 5 The AD7457 is functional with a reference input in the range 100 mV to VDD. 6 Guaranteed by characterization. 7 See Power Consumption section. 8 Measured with a full-scale dc input. 2 Rev. 0 | Page 4 of 20 AD7457 TIMING SPECIFICATIONS1 VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter fSCLK2 tCONVERT t2 t33 t43 t5 t6 t7 t84 tPOWER-UP5 tPOWER-DOWN Limit at TMIN, TMAX 10 10 16 × tSCLK 1.6 10 20 40 0.4 tSCLK 0.4 tSCLK 10 10 35 1 7.4 Unit kHz min MHz max Description tSCLK = 1/fSCLK µs max ns min ns max ns max ns min ns min ns min ns min ns max µs max µs min CS rising edge to SCLK falling edge setup time Delay from CS rising edge until SDATA three-state disabled Data access time after SCLK falling edge SCLK high pulse width SCLK low pulse width SCLK edge to data valid hold time SCLK falling edge to SDATA three-state enabled SCLK falling edge to SDATA three-state enabled Power-up time from full power-down Minimum time spent in power-down 1 The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2 and the Serial Interface section. Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for the output to cross 0.4 V or 2.0 V for VDD = 3 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading. 5 See Power Consumption section. 2 CONVERT START HOLD TRACK TPOWERUP CS SCLK TACQUISTION TACQUISITION THREE-STATE AUTOMATIC POWER DOWN t5 t2 t3 SDATA TRACK TPOWERUP 0 0 t6 t4 0 0 DB11 DB10 t8 t7 DB2 DB1 TPOWERDOWN DB0 4 LEADING ZEROS Figure 2. AD7457 Serial Interface Timing Diagram Rev. 0 | Page 5 of 20 THREE-STATE 03157-0-001 POWER UP AD7457 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +85°C −65°C to +150°C 150°C 211.5°C/W (SOT-23) 91.99°C/W (SOT-23) IOL 1.6mA TO OUTPUT PIN 1.6V CL 25pF 215°C 220°C IOH 200µA 03157-0-012 Parameters VDD to GND VIN+ to GND VIN– to GND Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Input Current to Any Pin except Supplies1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) 1 Transient currents of up to 100 mA do not cause SCR latch-up. Figure 3. Load Circuit for Digital Output Timing Specifications ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 AD7457 VDD 1 SCLK 2 AD7457 8 VREF 7 VIN+ SDATA 3 6 VIN– TOP VIEW CS 4 (Not to Scale) 5 GND 03157-0-002 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Figure 4. 8-Lead SOT-23 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VDD 2 SCLK 3 SDATA 4 CS 5 GND 6 VIN– 7 8 VIN+ VREF Description Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 µF capacitor and a 10 µF tantalum capacitor. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. Serial Data. Logic output. The conversion result from the AD7457 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7457 consists of four leading zeros followed by the 12 bits of conversion data that are provided MSB first. The output coding is straight (natural) binary. Chip Select. This input provides the dual function of powering up the device and initiating a conversion on the AD7457. Analog Ground. Ground reference point for all circuitry on the AD7457. All analog input signals and any external reference signal should be referred to this GND voltage. Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc offset to provide a pseudo ground. Noninverting Analog Input. Reference Input for the AD7457. An external reference in the range 100 mV to VDD must be applied to this input. The specified reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.33 µF. Rev. 0 | Page 7 of 20 AD7457 TERMINOLOGY Signal to (Noise + Distortion) Ratio (SINAD) The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Signal to (Noise + Distortion) = (6.02 N + 1.76 ) dB Aperture Jitter The sample-to-sample variation in the effective point in time at which the actual sample is taken. Therefore, for a 12-bit converter, the SINAD is 74 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7457, it is defined as THD (dB ) = 20 log V22 + V32 + V42 + V52 + V62 Aperture Delay The amount of time from the leading edge of the sampling clock until the ADC actually takes the sample. Full-Power Bandwidth The full-power bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but, for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa − fb), while the third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb). The AD7457 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (000...000 to 000...001) from the ideal (that is, AGND + 1 LSB). Gain Error The deviation of the last code transition (111...110 to 111...111) from the ideal (that is, VREF − 1 LSB), after the offset error has been adjusted out. Track-and-Hold Acquisition Time The minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal. Power Supply Rejection Ratio (PSRR) The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fs. The frequency of this input varies from 1 kHz to 1 MHz. PSRR (dB ) = 10 log (Pf Pfs ) Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output. Rev. 0 | Page 8 of 20 AD7457 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: TA = 25°C, fS = 100 kSPS, fSCLK = 10 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted. 1.0 75 0.8 0.6 DNL ERROR (LSB) SINAD (dB) VDD = 5V VDD = 3V 70 0.4 0.2 0 –0.2 –0.4 65 10 30 20 FREQUENCY (kHz) –0.8 –1.0 0 50 40 03157-0-017 03157-0-014 –0.6 Figure 5. SINAD vs. Analog Input Frequency for VDD = 3 V and 5 V 1024 2048 CODE 3072 4096 Figure 8. Typical DNL for the AD7457 for VDD = 5 V 1.0 0 100mV p-p SINE WAVE ON VDD NO DECOUPLING ON VDD –20 0.8 0.6 INL ERROR (LSB) PSRR (dB) –40 –60 VDD = 3V –80 VDD = 5V 0.4 0.2 0 –0.2 –0.4 –100 –140 0 100 200 300 400 500 600 700 800 SUPPLY RIPPLE FREQUENCY (kHz) 03157-0-018 03157-0-015 –0.6 –120 –0.8 –1.0 0 900 1000 Figure 6. PSRR vs. Supply Ripple Frequency without Supply Decoupling 0 2048 CODE –40 3072 4096 Figure 9. Typical INL for the AD7457 for VDD = 5 V 10000 8192 POINT FFT fSAMPLE = 100kSPS fIN = 30kHz SINAD = 71dB THD = –82dB SFDR =–83dB –20 9949 CODES 9000 8000 7000 6000 –60 5000 –80 4000 3000 –100 2000 03157-0-016 SNR (dB) 1024 –120 –140 0 30 50 FREQUENCY (kHz) 1000 27 CODES 0 2046 100 2047 24 CODES 2048 2049 2050 2051 CODES Figure 7. Dynamic Performance for VDD = 5 V Figure 10. Histogram of 10,000 Conversions of a DC Input Rev. 0 | Page 9 of 20 AD7457 12 4.0 VDD = 3V EFFECTIVE NUMBER OF BITS (LSB) 3.5 CHANGE IN DNL (LSB) 3.0 2.5 2.0 1.5 POSITIVE DNL 1.0 0.5 0 –0.5 VDD = 5V 10 9 8 7 NEGATIVE DNL 6 –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 3.5 VREF (V) Figure 11. Changes in DNL vs. VREF for VDD = 5 V 4 3 2 POSITIVE INL 1 0 NEGATIVE INL –1 –2 0 0.5 1.0 1.5 2.0 2.5 3.0 0.5 1.0 1.5 2.0 VREF (V) 2.5 Figure 13. ENOB vs. VREF for VDD =3V and 5 V 5 CHANGE IN INL (LSB) 11 3.5 VREF (V) Figure 12. Change in INL vs. VREF for VDD = 5 V Rev. 0 | Page 10 of 20 3.0 3.5 AD7457 THEORY OF OPERATION CIRCUIT INFORMATION CAPACITIVE DAC The AD7457 is a 12-bit, low power, single supply, successive approximation analog-to-digital converter (ADC) with a pseudo differential analog input. It operates with a single 2.7 V to 5.25 V power supply and is capable of throughput rates up to 100 kSPS. It requires an external reference to be applied to the VREF pin. The AD7457 has an on-chip differential track-and-hold amplifier, a successive approximation (SAR) ADC, and a serial interface, housed in an 8-lead SOT-23 package. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7457 automatically powers down after conversion, resulting in low power consumption. CS B VIN+ A A B VIN– SW1 SW2 CS VREF CONTROL LOGIC SW3 COMPARATOR CAPACITIVE DAC Figure 15. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding for the AD7457 is straight (natural) binary. The designed code transitions occur at successive LSB values (1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The ideal transfer characteristics of the AD7457 are shown in Figure 16. CONVERTER OPERATION 1LSB = VREF/4096 The AD7457 is a successive approximation ADC based around two capacitive DACs. Figure 14 and Figure 15 show simplified schematics of the ADC in the acquisition phase and the conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 14 (acquisition phase), SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. ADC CODE 111...11 111...10 111...00 011...11 000...10 000...01 000...00 0V 1LSB CAPACITIVE DAC VIN– A A B Figure 16. Ideal Transfer Characteristics CS B VIN+ SW1 SW2 VREF SW3 CS VREF –1LSB ANALOG INPUT TYPICAL CONNECTION DIAGRAM CONTROL LOGIC COMPARATOR CAPACITIVE DAC Figure 14. ADC Acquisition Phase When the ADC starts a conversion (Figure 15), SW3 opens, and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the VIN+ and the VIN– pins must be matched; otherwise the two inputs have different settling times, resulting in errors. Figure 17 shows a typical connection diagram for the AD7457. In this setup, the GND pin is connected to the analog ground plane of the system. The VREF pin is connected to the AD780, a 2.5 V decoupled reference source. The signal source is connected to the VIN+ analog input via a unity gain buffer. A dc voltage is connected to the VIN– pin to provide a pseudo ground for the VIN+ input. The VDD pin should be decoupled to AGND with a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor. The reference pin should be decoupled to AGND with a capacitor of at least 0.33 µF. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit result. Rev. 0 | Page 11 of 20 AD7457 10µF 0.1µF +2.7V TO +5.25V SUPPLY ANALOG INPUT STRUCTURE ANALOG INPUT Figure 19 shows the equivalent circuit of the analog input structure of the AD7457. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV, which causes these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors, C1 in Figure 19, are typically 4 pF and can be attributed primarily to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The capacitors, C2, are the ADC’s sampling capacitors, which typically have a capacitance of 16 pF. The AD7457 has a pseudo differential analog input. The VIN+ input is coupled to the signal source and should have an amplitude of VREF p-p to make use of the full dynamic range of the part. A dc input is applied to the VIN–. The voltage applied to this input provides an offset from ground or a pseudo ground for the VIN+ input. Ensure that (VIN− + VIN+) is less than or equal to VDD to avoid exceeding the maximum ratings of the ADC. The main benefit of pseudo differential inputs is that they separate the analog input signal ground from the ADC’s ground, allowing dc common-mode voltages to be canceled. For ac applications, removing high frequency components from the analog input signal through the use of an RC low pass filter on the relevant analog input pins is recommended. In applications where harmonic distortion and the signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances can significantly affect the ac performance of the ADC, which may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. SERIAL INTERFACE VDD AD7457 VREF P-TO-P VIN+ SCLK µC/µP SDATA CS VIN– GND VREF 0.33µF 2.5V AD780 03157-0-006 DC INPUT VOLTAGE Figure 17. Typical Connection Diagram VDD Because the ADC operates from a single supply, it is necessary to level shift ground-based bipolar signals to comply with the input requirements. An op amp (for example, the AD8021) can be configured to rescale and level shift a ground-based (bipolar) signal, so that it is compatible with the input range of the AD7457. See Figure 18. D C1 +1.25V 0V –1.25V R VIN R1 C2 VDD 2.5V 1.25V 0V D VIN– C1 VIN+ 3R C2 D When a conversion takes place, the pseudo ground corresponds to 0 and the maximum analog input corresponds to 4096. R R1 VIN+ D AD7457 R 0.33µF VIN– VREF EXTERNAL VREF (2.5V) 03157-0-007 Figure 19. Equivalent Analog Input Circuit. Conversion Phase—Switches Open; Track Phase—Switches Closed Figure 18. Op Amp Configuration to Level Shift a Bipolar Input Signal When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 20 shows a graph of the THD versus analog input signal frequency for different source impedances. Rev. 0 | Page 12 of 20 AD7457 –50 errors in the AD7457 transfer function. A capacitor of at least 0.33 µF should be placed on the VREF pin. Suitable reference sources for the AD7457 include the AD780 and the ADR421. Figure 22 shows a typical connection diagram for the VREF pin. TA = 25°C –60 200Ω VDD 100Ω NC 10 VDD 62Ω 10Ω 20 30 INPUT FREQUENCY (kHz) 03157-0-009 –90 AD7457* AD780 –80 40 0.1µF 1 OPSEL 8 NC 7 NC 2.5V 2 VIN 10µF 0.1µF 3 TEMP VOUT 6 4 GND TRIM 5 NC VREF 0.33µF NC = NO CONNECT 50 * ADDITIONAL PINS OMITTED FOR CLARITY 03157-0-011 THD (dB) –70 Figure 20. THD vs. Analog Input Frequency for Various Source Impedances Figure 22. Typical VREF Connection Diagram for VDD = 5 V Figure 21 shows a graph of THD versus analog input frequency for various supply voltages, while sampling at 100 kSPS with an SCLK of 10 MHz. In this case, the source impedance is 10 Ω. –50 TA = 25°C –55 –60 THD (dBs) –70 VDD = 3.6V VDD = 2.7V –80 03157-0-010 VDD = 4.75V –85 –90 10 VDD = 5.25V 20 30 INPUT FREQUENCY (kHz) 40 Figure 2 shows a detailed timing diagram of the serial interface of the AD7457. The serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. The falling edge of CS powers up the AD7457 and also puts the track-and-hold into track. The power-up time is 1 µs minimum and, in this time, the device also acquires the analog input signal. CS must remain low for the duration of power-up. The rising edge of CS initiates the conversion process, puts the track-and-hold into hold mode, and takes the serial data bus out of three-state. The conversion requires 16 SCLK cycles to complete. –65 –75 SERIAL INTERFACE 50 Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages DIGITAL INPUTS The digital inputs applied to the AD7457 are not limited by the maximum ratings that limit the analog inputs. Instead the digital inputs applied, that is, CS and SCLK, can go to 7 V and are not restricted by the VDD + 0.3 V limits as on the analog input. The main advantage of the inputs not being restricted to the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS or SCLK are applied before VDD, there is no risk of latch-up as there would be on the analog inputs, if a signal greater than 0.3 V were applied prior to VDD. REFERENCE SECTION An external source is required to supply the reference to the AD7457. This reference input can range from 100 mV to VDD. The specified reference is 2.50 V for the power supply range 2.70 V to 5.25 V. Errors in the reference source result in gain On the sixteenth SCLK falling edge, after the time t8, the serial data bus goes back into three-state and the device automatically enters full power-down. It remains in power-down until the next falling edge of CS. For specified performance, the throughput rate should not exceed 100 kSPS, which means that there should be no less than 10 µs between consecutive CS falling edges. The conversion result from the AD7457 is provided on the SDATA output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7457 consists of four leading zeros, followed by the 12 bits of conversion data that are provided MSB first. The output coding is straight (natural) binary. Sixteen serial clock cycles are, therefore, required to perform a conversion and to access data from the AD7457. A rising edge of CS provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out on the subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock after CS has gone high provides the second leading zero. The final bit in the data transfer, before the device goes Rev. 0 | Page 13 of 20 AD7457 2.5 into power-down, is valid on the sixteenth falling edge of SCLK, having been clocked out on the previous (fifteenth) falling edge. 2.0 POWER (mW) The conversion time of the device is determined by the serial clock frequency. The faster the SCLK frequency, the shorter the conversion time. Therefore, as the clock frequency used is increased, the ADC is dissipating power for a shorter period of time (during conversion) and it remains in power-down for a longer percentage of the cycle time or throughput rate. This can be seen in Figure 23, which shows typical IDD versus SCLK frequency for VDD of 3 V and 5 V, when operating the device at the maximum throughput of 100 kSPS. 2.5 VDD = 5V 1.0 0.5 VDD = 3V 0 POWER CONSUMPTION The AD7457 automatically enters power-down at the end of each conversion. When in the power-down mode, all analog circuitry is powered down and the current consumption is 1 µA. To achieve the specified power consumption (which is the lowest), there are a few things the user should keep in mind. 1.5 03157-0-024 In applications with a slow SCLK, it is possible to read in data on each SCLK rising edge. In this case, the first falling edge of SCLK after the CS rising edge clocks out the second leading zero and can be read in on the following rising edge. If the first SCLK edge after the CS rising edge is a falling edge, the first leading zero that was clocked out when CS went high is missed, unless it was not read on the first SCLK falling edge. The fifteenth falling edge of SCLK clocks out the last bit of data, which can be read in by the following rising SCLK edge. TA = 25°C 0 20 40 60 THROUGHPUT (kSPS) 80 100 Figure 24. Power vs. Throughput Rate for SCLK = 10 MHz for VDD = 3 V and 5 V MICROPROCESSOR INTERFACING The serial interface of the AD7457 allows the part to be connected to a range of different microprocessors. This section explains how to interface the AD7457 with the ADSP-218x serial interface. AD7457 to ADSP-218x The ADSP-218x family of DSPs can be interfaced directly to the AD7457 without any glue logic. The serial clock for the ADC is provided by the DSP. SDATA from the ADC is connected to the data receive (DR) input of the serial port and CS can be controlled by a flag (FL0). The connection diagram is shown in Figure 25. AD7457* TA = 25°C 2.0 ADSP-21xx* SCLK SCLK SDATA DR0 SPORT0 RFS CS 1.0 *ADDITIONAL PINS OMITTED FOR CLARITY VDD = 5V VDD = 3V SPORT1 Figure 25. AD7457 to ADSP-218x 03157-0-023 0.5 0 0 FL0 03157-0-025 IDD (mA) 1.5 2 4 6 SCLK Frequency (MHz) 8 10 Figure 23. IDD vs. SCLK Frequency for VDD = 3 V and 5 V when Operating at 100 kSPS SPORT0 must be enabled to receive the conversion data and to provide the SCLK, while SPORT1 must be configured for flags, and so on. SPORT0 is configured by setting the bits in its control register as listed in Table 5. Figure 24 shows typical power consumption versus throughput rate for the maximum SCLK frequency of 10 MHz. In this case, the conversion time is the same for all throughputs, because the SCLK frequency is fixed. As the throughput rate decreases, the average power consumption decreases, because the ADC spends more time in power-down. Rev. 0 | Page 14 of 20 AD7457 Table 5. SPORT0 Configuration Bit ISCLK SLEN RFSR Setting 1 1111 0 TFSR IRFS Don’t care 0 ITFS RFSW TFSW INVRFS INVTFS Don’t care 1 Don’t care 0 Don’t care Comment/Description Serial clock generated internally 16 bits of conversion data Receive frame sync required every word Not used RFS is set to be an input and is generated externally Not used Alternate receive framing Not used RFS is active high Not used The flag to generate the CS signal is generated by SPORT1. It is connected to both the ADC and the RFS input of SPORT0 to provide the frame sync signal for the DSP. Rev. 0 | Page 15 of 20 AD7457 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7457 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes, because it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close as possible to the GND pin on the AD7457. Avoid running digital lines under the device, because this couples noise onto the die. The analog ground plane should be allowed to run under the AD7457 to avoid noise coupling. The power supply lines to the AD7457 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feed through the board. A micro strip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with 0.1 µF capacitors to GND. To achieve the best from these decoupling components, place them as close as possible to the device. Rev. 0 | Page 16 of 20 AD7457 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC 1.45 MAX 0.15 MAX 0.38 0.22 0.22 0.08 SEATING PLANE 8° 4° 0° 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178BA Figure 26. 8-Lead Small Outline Transistor Package [SOT-23] (RT-8)—Dimensions shown in millimeters ORDERING GUIDE Model AD7457BRT-R2 AD7457BRT-REEL7 1 Temperature Range –40°C to +85°C –40°C to +85°C Linearity Error (LSB)1 ±1 ±1 Linearity error here refers to integral nonlinearity error. Rev. 0 | Page 17 of 20 Package Description 8-Lead SOT-23 8-Lead SOT-23 Package Option RT-8 RT-8 Branding COD COD AD7457 NOTES Rev. 0 | Page 18 of 20 AD7457 NOTES Rev. 0 | Page 19 of 20 AD7457 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03157–0–10/03(0) Rev. 0 | Page 20 of 20