49% ® PCM1727 PCM 1FPO 727 E Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE DUAL PLL TM FEATURES DESCRIPTION ● ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA ● COMPLETE STEREO DAC: Includes Digital Filter and Output Amp ● DYNAMIC RANGE: 92dB The PCM1727 is a complete low cost stereo audio digital-to-analog converter (DAC) with a dual phaselocked loop (PLL) circuit included. PLL-1 derives a fixed 33.8688MHz (768fS, fS = 44.1kHz) system clock (SCKO-1), and PLL-2 derives both the 384fS (fS = 44.1k/48k/96kHz) system clock (SCKO-2), and the 768fS (fS = 44.1k/48kHz)/384fS (fS = 96kHz) system clock (SCKO-3) from an external 27MHz reference frequency. The DAC contains a 3rd-order ∆Σ modulator, a digital interpolation filter, and an analog output amplifier. The PCM1727 can accept 16-, 20-, or 24-bit input data in either normal or I2S formats. ● MULTIPLE SAMPLING FREQUENCIES: fS = 44.1kHz, 48kHz, 96kHz ● PROGRAMMABLE DUAL PLL CIRCUIT: 27MHz Master Clock Input ● GENERATED SYSTEM CLOCK SCKO1: 33.8688MHz SCK02: 384fS SCK03: 768fS (44.1k/48kHz) 384fS (96kHz) ● NORMAL OR I2S DATA INPUT FORMATS ● SELECTABLE FUNCTIONS: Soft Mute, Analog Output Mode Digital Attenuator (256 Steps) Digital De-emphasis ● +5V SINGLE POWER SUPPLY BCKIN LRCIN DIN Serial Input I/F 8X Oversampling Digital Filter with Function Controller ML The digital filter performs an 8X interpolation function and includes selectable features such as soft mute, digital attenuation and digital de-emphasis. The PCM1727 is ideal for applications which combine compressed audio and video data such as DVD, DVD Audio with CD-DA compatibility, karaoke DSP. Multi-level Delta-Sigma Modulator Low-pass Filter DAC VOUTL CAP Multi-level Delta-Sigma Modulator Low-pass Filter DAC VOUTR MC MD Mode Control I/F ZERO BPZ-Cont. 384fS Open Drain RSTB PLL2 PLL1 SCKO3 SCKO2 SCKO1 OSC MCKO XT1 XT2 Power Supply VCP PGND VCA AGND VDD DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1407A Printed in U.S.A. September, 1997 SPECIFICATIONS All specifications at +25°C, +VCA = +VDD = +VCP = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1727 PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 16 DATA FORMAT Audio Data Interface Format Data Bit Length Audio Data Format Sampling Frequency (fS) PLL PERFORMANCE Master Clock Input Frequency(4) Generated System Clock SCKO-1 SCKO-2 SCKO-3 Output Logic Level VOH (MCKO, SCKO 1 ~ 3) VOL Generated Sysclk Jitter Generated Sysclk Transient(1) Power-Up Time Generated Sysclk Duty Cycle 44.1 26.73 THD+N at –60dB Dynamic Range (EIAJ Method) Signal-to-Noise Ratio(3) (EIAJ Method) Channel Separation DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: ICC + IDD + ICP mA 96 Selectable kHz 27.27 MHz 33.8688 36.8640 36.8640 0.5 ±150 40 15 50 20 30 60 MHz MHz MHz VDC VDC ps ms ms % TTL fs = 44.1kHz fs = 96kHz fs = 44.1kHz fs = 96kHz fs = 44.1kHz fs = 96kHz fs = 44.1kHz fs = 96kHz fs = 44.1kHz 90 90 88 VOUT = VCC/2 at BPZ Full Scale (–0dB) AC Load –89 –87 –31 –29 92 90 94 90 93 –80 dB dB dB dB dB dB dB dB dB ±1.0 ±1.0 ±30 ±3.0 ±2.0 % of FSR % of FSR mV Vp-p VDC kΩ 0.62 x VCA VCA/2 5 DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-emphasis Error INTERNAL ANALOG FILTER –3dB Bandwidth Passband Response 27 16.9344 33.8688 VDD – 0.4 DIGITAL INPUT LOGIC LEVEL DYNAMIC PERFORMANCE(2) THD+N at fS (0dB) Bits Standard/I2S 16/20/24 Selectable MSB First, 2’s Comp 768fS (fS = 44.1k) 384fS 768fS (fS = 44.1k/48k), 384fS (fS = 96k) IOH = 2mA IOL = 4mA Standard Dev fM = 27MHz To Programmed Frequency fM = 27MHz, CL = 15pF UNITS 0.445 0.555 ±0.17 –35 11.125/fS –0.2 +0.55 100 –0.16 f = 20kHz VCC = VDD = VCP fS = 44.1kHz TEMPERATURE RANGE Operation Storage 4.5 –25 –55 5 25 fS fS dB dB sec dB kHz dB 5.5 27 VDC +85 +125 °C °C NOTES: (1) Sysclk transient is the maximum frequency lock time when the PLL frequency is changed. (2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode. (3) SNR is tested at Infinite Zero Detection off. (4) PLL evaluations tested with 1ns maximum jitter on the 27MHz input clock. ® PCM1727 2 PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SSOP XT1 1 24 PIN XT2 NAME I/O 1 XT1 IN DESCRIPTION 2 PGND — PLL Ground 3 VCP — PLL Power Supply (+5V) 27MHz Crystal or External Clock Input PGND 2 23 DGND 4 MCKO OUT VCP 3 22 VDD 5 RSV — 6 SCKO3 OUT MCKO 4 21 SCKO1 7 ML IN Latch Enable Input for Serial Interface Mode(2) RSV 5 20 SCKO2 8 MC IN Bit Clock Input for Serial Interface Mode(2) SCKO3 6 19 LRCIN 9 MD IN Serial Data Input for Serial Interface Mode(2) 10 RSTB IN ML 7 18 DIN Reset; When this pin is low, the DF and modulator are held in reset. 11 8 17 BCKIN VOUTR OUT MC Right Channel, Analog Voltage Output of Audio Signal MD 9 16 ZERO 12 AGND — Analog Ground 13 VCA — Analog Power Supply (+5V) 14 VOUTL OUT RSTB 10 15 CAP VOUTR 11 14 VOUTL AGND 12 13 VCA PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) PCM1727E 24-Pin SSOP 338 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. Buffered Clock Output of Crystal Oscillator Reserve; This pin should be open. System Clock Out 3; This output is 768f S or 384fS. Left Channel, Analog Voltage Output of Audio Signal 15 CAP — 16 ZERO OUT Common Pin of Analog Output Amp 17 BCKIN IN Bit Clock Input for Serial Audio Data(3) 18 DIN IN Serial Audio Data Input(3) 19 LRCIN IN 20 SCKO2 OUT System Clock Out 2; This output is 256fS or 384fS system clock. 21 SCKO1 OUT System Clock Out 1; This output is 33.8688MHz system clock. Zero Data Flag; This pin is low when the input data is continuously zero for more than 65,535 cycles of BCKIN(1). Left and Right Clock (sampling rate–fS)(3) 22 VDD — 23 DGND — Digital Ground 24 XT2 — 27MHz Crystal. Connected to GND at external clock. Digital Power (+5V) Note: (1) Open Drain Output. (2) Schmitt triger input with internal pull-up resistors. (3) Schmitt triger input. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ....................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Input Current (except power supply) ............................................... ±10mA Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C Thermal Resistance, θJA ....................................................................................... +70°C/W The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1727 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = VCP = +5V, fS = 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth is 20kHz. DYNAMIC PERFORMANCE THD+N (0dB) vs TEMPERATURE and VCC = 5V, 384fS THD+N (0dB) vs POWER SUPPLY VOLTAGE TA = 25°C, 384fS –70 –70 –75 fS = 96k THD+N (dB) THD+N (dB) –75 –80 fS = 44.1k –85 –90 –80 –85 fS = 44.1k –90 –95 –95 –25 0 25 50 75 85 4.5 5.0 Temperature (°C) Power Supply Voltage (V) THD+N (0dB) vs SAMPLING RATE (fS) VCC = 5V, TA = 25°C POWER SUPPLY CURRENT vs SAMPLING RATE (fS) VCC = 5V, TA = 25°C 5.5 35 –70 Supply Current (mA) –75 THD+N (dB) fS = 96k –80 –85 –90 –95 44.1k 48k 25 20 15 44.1k 96k 48k 96k Sampling Rate, fS (Hz) Sampling Rate, fS (Hz) ® PCM1727 30 4 TYPICAL PERFORMANCE CURVES DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC PASSBAND RIPPLE CHARACTERISTIC 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –100 –1 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS 0 0.1134fS Frequency (Hz) 5k 10k 15k 20k 25k 0 4999.8375 15k 14999.5125 19999.35 DE-EMPHASIS ERROR (48kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 10k 9999.675 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 0.4535fS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 0.3402fS DE-EMPHASIS ERROR (44.1kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0 –2 –4 –6 –8 –10 –12 0 0.2268fS Frequency (Hz) 20k 25k 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 Frequency (Hz) 5442 10884 16326 21768 Frequency (Hz) ® 5 PCM1727 TYPICAL CONNECTION DIAGRAM Figure 1 illustrates the typical connection diagram for PCM1727 in an DVD Audio application. The 27MHz master video clock (fM) drives XT1 (pin 1) of PCM1727. A programmable system clock is generated by the PCM1727 PLL, with SCKO2 used to drive the MPEG2 decoder’s system clock input. SCKO1 used to drive the CD-DA DSP’s system clock input, SCKO3 used to drive Karaoke DSP’s system clock input. The standard audio signals (data, bit clock, and word clock) are generated in the decoder from PCM1727’s system clock, providing synchronization of audio and video signals. DUAL PLL CIRCUIT PCM1727 has a programmable internal DUAL PLL circuit, as shown in Figure 2. The PLL is designed to accept a 27MHz master clock or crystal oscillator and generate all internal system clocks required to operate the digital filter and ∆Σ modulator, at 384fS. If an external master clock is used, XT2 should be connected to ground. The PLL will directly track any variations in the master clock’s frequency, and jitter on the system clock is specified at 150ps typical. Figure 3 illustrates the timing requirements for the 27MHz master clock. Figure 4 illustrates the system clock connections for an external clock or crystal oscillator. +5V Analog 2 23 PGND DGND 18 DATA MPEG Decoder 17 BCK 19 LRCK 20 SCI 22 VDD 3 VCP VOUTL DIN BCKIN CAP SCKO2 VOUTR ZERO Buffer 21 DSP Karaoke + Post LPF Analog Mute Lch Analog Out Post LPF Analog Mute Rch Analog Out 10µF 11 16 SCKO1 33.8688M Buffer 15 LRCIN Buffer 384fS CD-DA 14 PCM1727 6 DSP SCKO3 768/384fS 27MHz Master Clock 1 27MHz CLK OUT 24 XT1 ML MC XT2 MD RSTB AGND 12 7 STRB 8 SCKO 9 SDO 10 System Controller PIO VCA 13 +5V Analog FIGURE 1. Connection Diagram for External Master Clock in a Typical MPEG2 Application. Frequency Control Internal System Clock PLL2 N Counter Data ROM M Counter Phase Detector and Loop Filter VCO PLL1 M Counter Oscillator N Counter Phase Detector and Loop Filter Counter P VCO 24 1 4 21 6 20 XT2 XT1 MCKO 27MHz SCKO1 33.8688MHz SCKO3 768fs/384fs SCKO2 384fs FIGURE 2. PLL Block Diagram. ® PCM1727 6 1/27MHz IIH (VIH = VDD) : 4mA max IIL (VIL = 0) : 700µA max tCH: 10ns (min) tCL: 15ns (min) tCH XT1 2.0V 0.8V tCL FIGURE 3. XT1 Input Timing. MCKO 27MHz Out MCKO Buffer 27MHz Internal Master Clock C1 X’tal XT1 27MHz Internal Master Clock External Clock XT1 R R C2 XT2 C1, C2 = 10 to 33pF XT2 PCM1727 PCM1727 CRYSTAL RESONATOR CONNECTION EXTERNAL CLOCK INPUT FIGURE 4. System Clock Connection. 1/fS L_ch R_ch LRCIN (pin 19) BCKIN (pin 17) AUDIO DATA WORD = 16-BIT DIN (pin 18) 14 15 16 1 18 19 20 1 2 23 24 3 MSB AUDIO DATA WORD = 24-BIT DIN (pin 18) 3 MSB AUDIO DATA WORD = 20-BIT DIN (pin 18) 2 1 2 3 MSB 14 15 16 1 19 20 1 2 LSB 22 LSB 3 MSB LSB 18 2 3 MSB 23 24 1 2 3 MSB 14 15 16 LSB 18 19 20 LSB 22 23 24 LSB FIGURE 5. “Normal” Data Input Timing. ® 7 PCM1727 1/fS L_ch LRCIN (pin 19) R_ch BCKIN (pin 17) AUDIO DATA WORD = 16-BIT DIN (pin 18) 1 2 MSB AUDIO DATA WORD = 20-BIT DIN (pin 18) 1 2 15 16 1 2 1 2 14 3 MSB LSB 18 3 MSB AUDIO DATA WORD = 24-BIT DIN (pin 18) 14 3 19 20 1 2 LSB 22 3 MSB 1 18 3 2 LSB 2 19 20 1 2 23 24 1 2 LSB MSB 23 24 1 15 16 LSB 22 3 MSB LSB FIGURE 6. “I2S” Data Input Timing. LRCKIN 1.4V tBCH tBCL tLB BCKIN 1.4V tBL tBCY 1.4V DIN tDS tDH BCKIN Pulse Cycle Time : tBCY : 100ns (min) BCKIN Pulse Width High : tBCH : 50ns (min) BCKIN Pulse Width Low : tBCL : 50ns (min) BCKIN Rising Edge to LRCIN Edge : tBL : 30ns (min) LRCIN Edge to BCKIN Rising Edge : tLB : 30ns (min) DIN Set-up Time : tDS : 30ns (min) DIN Hold Time : tDH : 30ns (min) FIGURE 7. Audio Data Input Timing. PCM1727’s internal PLL can be programmed for three different sampling frequencies (LRCIN), as shown in Table I. The internal sampling clocks generated by the various programmed frequencies are shown in Table II. The system clock output frequency for PCM1727 is 100% accurate. Sampling Frequencies-LRCIN (kHz) Standard Sampling Freq 48 96 TABLE I. Sampling Frequencies. Frequency error of generated system clock by programmed PLL is less than ±0.03ppm due to high accuracy PLL construction. Sampling Frequency (LRCIN) To provide MCKO clock and SCKO1, SCKO2, SCKO3 clocks for external circuits, an external buffer may be used to avoid degrading audio performance (as shown in the connection diagram, in Figure 1). SCKO2 System Clock SCKO3 System Clock 44.1kHz Standard 16.9344MHz 33.8688MHz 48kHz Standard 18.4320MHz 36.8640MHz 96kHz Double 36.8640MHz 36.8640MHz TABLE II. Sampling Frequencies vs Internal System Clock (= Output Frequencies of Dual PLL). ® PCM1727 44.1 Double of Standard Sampling Freq 8 MAPPING OF PROGRAM REGISTERS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MODE0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 MODE1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 MODE2 res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUT MODE3 res res res res res A1 A0 IZD SF1 SF0 DSR1 DSR0 res ATC LRP I2S SPECIAL FUNCTIONS PCM1727 includes several special functions, including digital attenuation, digital de-emphasis, soft mute, data format selection and input word resolution. These functions are controlled using a three-wire interface. MD (pin 9) is used for the program data, MC (pin 8) is used to clock in the program data, and ML (pin 7) is used to latch in the program data. Table III lists the selectable special functions. FUNCTION Input Audio Data Format Selection Normal Format I2S Format 16 Bits Lch/Rch = High/Low OFF Soft Mute Control OFF 0dB Lch, Rch Individually Fixed Infinite Zero Detection Circuit Control AL (7:0) LDL A (1:0) Res DAC Attenuation Data for Lch Attenuation Data Load Control for Lch Register Address Reserved, should be “L” Register 1 AR (7:0) LDL A (1:0) Res DAC Attenuation Data for Rch Attenuation Data Load Control for Rch Register Address Reserved, should be “L” Register 2 MUT DEM OPE IW (1:0) PL (3:0) A (1:0) res Left and Right DACs Soft Mute Control De-emphasis Control Left and Right DACs Operation Control Input Audio Data Bit Select Output Mode Select Register Address Reserved, should be “L” Register 3 I2S LRP ATC DSR (1:0) SF (1:0) IZD A (1:0) Res DESCRIPTION Audio Data Format Select Polarity of LRCIN (pin 19) Select Attenuator Control Double Sampling Rate Select Sampling Rate Select Infinite Zero Detection Circuit Control Register Address Reserved, should be “L” TABLE IV. Internal Register Mapping. OFF Operation Enable (OPE) Sampling Rate Selection Standard Sampling Rate—44.1/48kHz Double Sampling Rate—96kHz Sampling Frequency 44.1kHz Group 48kHz Group Register 0 Normal Format De-emphasis Control Attenuation Control Lch, Rch Individually Lch, Rch Common BIT NAME DEFAULT MODE Input Audio Data Bit Selection 16/20/24 Bits Input LRCIN Polarity Selection Lch/Rch = High/Low Lch/Rch = Low/High REGISTER NAME REGISTER 0 (A1 = 0, A0 = 0) Enabled B15 B14 B13 B12 B11 B10 B9 B8 Standard Sampling Rate Analog Output Mode L, R, Mono, Mute B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 44.1kHz Register 0 is used to control left channel attenuation. Bits 0 - 7 (AL0 - AL7) are used to determine the attenuation level. The level of attenuation is given by: Stereo TABLE III. Selectable Functions. ATT = [20 log10 (ATT_DATA/255)] dB PROGRAM REGISTER BIT MAPPING ATTENUATION DATA LOAD CONTROL Bit 8 (LDL) is used to control the loading of attenuation data in B0:B7. When LDL is set to 0, attenuation data will be loaded into AL0:AL7, but it will not affect the attenuation level until LDL is set to 1. LDR in Register 1 has the same function for right channel attenuation. PCM1727’s special functions are controlled using four program registers which are 16 bits long. These registers are all loaded using MD. After the 16 data bits are clocked in, ML is used to latch in the data to the appropriate register. Table IV shows the complete mapping of the four registers and Figure 8 illustrates the serial interface timing. ® 9 PCM1727 Attenuation Level (ATT) can be controlled as following Resistor set AL (R) (7:0). AL (R) (7:0) ATT LEVEL 00h 01h . . . FEh FFh Other Forced to BPZ(1) Disabled Bit 4 (IW1) Bit 3 (IW0) Input Resolution 0 0 1 1 0 1 0 1 16-bit Data Word 20-bit Data Word 24-bit Data Word Reserved B7 B6 B5 B4 B3 B2 B1 B0 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE DATA INPUT DAC OUTPUT SOFTWARE MODE INPUT Zero Forced to BPZ(1) Other Forced to BPZ(1) Enabled Zero Controlled by IZD Enabled Other Normal Enabled Enabled DAC OUTPUT Zero Forced to BPZ(1) Other Normal Zero Zero(2) Other Normal PL2 PL3 Lch OUTPUT Rch OUTPUT NOTE 0 0 0 MUTE MUTE MUTE 0 0 0 1 MUTE R 0 0 1 0 MUTE L 0 0 1 1 MUTE (L + R)/2 0 1 0 0 R MUTE 0 1 0 1 R R 0 1 1 0 R L 0 1 1 1 R (L + R)/2 1 0 0 0 L MUTE 1 0 0 1 L R 1 0 1 0 L L 1 0 1 1 L (L + R)/2 1 1 0 0 (L + R)/2 MUTE 1 1 0 1 (L + R)/2 R 1 1 1 0 (L + R)/2 L 1 1 1 1 (L + R)/2 (L + R)/2 REVERSE STEREO MONO B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 res IZD SF1 SF0 DSR1 DSR0 YES ATC LRP I2S res res res res A1 A0 B5 B4 B3 B2 B1 B0 Register 3 is used to control input data format and polarity, attenuation channel control, system clock frequency, sampling frequency and infinite zero detection. Bits 0 (I2S) and 1 (LRP) are used to control the input data format. A “LOW” on bit 0 sets the format to “Normal” (MSB-first, right-justified Japanese format) and a “HIGH” sets the format to I2S (Philips serial data protocol). Bit 1 (LRP) is used to select the polarity of LRCIN (sample rate clock). When bit 1 is “LOW”, left channel data is assumed TABLE VI. Infinite Zero Detection (IZD) Function. ® PCM1727 PL1 0 REGISTER 3 (A1 = 1, A0 = 1) OPE controls the operation of the DAC: when OPE is “LOW”, the DAC will convert all non-zero input data. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be forced to zero only if IZD is “HIGH”. When OPE is “HIGH”, the output of the DAC will be forced to bipolar zero, irrespective of any input data. DATA INPUT PL0 TABLE VIII. Programmable Output Format. TABLE V. Operation Enable (OPE) Function. IZD = 0 Disabled Bits 5, 6, 7, and 8 (PL0:3) are used to control output format. The output of PCM1727 can be programmed for 16 different states, as shown in Table VIII. Bit 2, (OPE) is used for operational control. Table V illustrates the features controlled by OPE. IZD = 1 Forced to BPZ(1) B7 B6 B5 B4 B3 B2 B1 B0 Register 2 is used to control soft mute, de-emphasis, operation enable, input resolution, and output format. Bit 0 is used for soft mute: a “HIGH” level on bit 0 will cause the output to be muted (this is ramped down in the digital domain, so no “click” is audible). Bit 1 is used to control de-emphasis. A “LOW” level on bit 1 disables de-emphasis, while a “HIGH” level enables de-emphasis. OPE = 0 Enabled Zero Bits 3 (IW0) and 4 (IW1) are used to determine input word resolution. PCM1727 can be set up for input word resolutions of 16, 20, or 24 bits: REGISTER 2 (A1 = 1, A0 = 0) OPE = 1 Controlled by OPE and IZD NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to output amplifier. Register 1 is used to control right channel attenuation. As in Register 1, bits 0 - 7 (AR0 - AR7) control the level of attenuation. res res res res res A1 Enabled Other TABLE VII. Reset (RSTB) Function. A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 B15 B14 B13 B12 B11 B10 B9 B8 Controlled by OPE and IZD RSTB = “LOW” REGISTER 1 (A1 = 0, A0 = 1) res res res res res DAC OUTPUT Zero RSTB = “HIGH” –∞dB (Mute) –48.16dB . . . –0.07dB 0dB B15 B14 B13 B12 B11 B10 B9 B8 DATA INPUT SOFTWARE MODE INPUT 10 when LRCIN is in a “HIGH” phase and right channel data is assumed when LRCIN is in a “LOW” phase. When bit 1 is “HIGH”, the polarity assumption is reversed. Bit 2 (ATC) is used for controlling the attenuator. When bit 2 is “HIGH”, the attenuation data loaded in program Register 0 is used for both left and right channels. When bit 2 is “LOW”, the attenuation data for each register is applied separately to left and right channels. DSR0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 Sampling Frequency 44.1kHz group 48kHz group Reserved Reserved 44.1kHz 48/96kHz Reserved Reserved When IZD is “LOW”, the zero detect circuit is off. Under this condition, no automatic muting will occur if the input is continuously zero. When IZD is “HIGH”, the zero detect feature is enabled. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be immediately forced to a bipolar zero state (VCC/2). The zero detection feature is used to avoid noise which may occur when the input is DC. When the output is forced to bipolar zero, there may be an audible click. PCM1727 allows the zero detect feature to be disabled so the user can implement an external muting circuit. Multiple Normal Double Reserved Reserved SF0 Bit 8 is used to control the infinite zero detection function (IZD). Bits 4 (DSR0) and 5 (DSR1) are used to control multiples of the sampling rate: DSR1 SF1 44.1/48kHz 96kHz Reserved Reserved Bits 6 (SF0) and 7 (SF1) are used to select the sampling frequency: ML (pin 7) MC (pin 8) MD (pin 9) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 FIGURE 8. Three-Wire Serial Interface. tMLH tMLH tMLS 1.4V ML tMCH tMCL tMLL 1.4V MC tMCY LSB MD tMDS 1.4V tMDH MC Pulse Cycle Time MC Pulse Width LOW MC Pulse Width HIGH MD Setup Time MD Hold Time ML Low Level Time ML High Level Time ML Setup Time ML Hold Time tMCY tMCL tMCH tMDS tMDH tMLL tMLH tMLS tMLH 100ns (min) 40ns (min) 40ns (min) 40ns (min) 40ns (min) 40ns + 1SYSCLK (min) 40ns + 1SYSCLK (min) 40ns (min) 40ns (min) SYSCLK: 1/384fS FIGURE 9. Program Register Input Timing. ® 11 PCM1727 APPLICATION CONSIDERATIONS OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1727 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1727: The performance of the internal low pass filter from DC to 24kHz is shown in Figure 10. The higher frequency rolloff of the filter is shown in Figure 11. If the user’s application has the PCM1727 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 12. For some applications, a passive RC filter or 2nd-order filter may be adequate. TD = 11.125 x 1/fS For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs Applications using data from a disc or tape source, such as CD audio, DVD audio, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0 dB dB 0.5 0 –0.5 –1.0 20 100 1k Frequency (Hz) 10k 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 24k 100 1k 10k 100k 1M 10M Frequency (Hz) FIGURE 11. Low Pass Filter Wideband Frequency Response. FIGURE 10. Low Pass Filter Frequency Response. GAIN vs FREQUENCY 6 90 + 10kΩ VSIN 10kΩ 680pF OPA604 10kΩ –14 0 –34 –90 –54 –180 Phase 100pF – –74 –270 –94 –360 100 FIGURE 12. 3rd-Order LPF. ® PCM1727 12 1k 10k Frequency (Hz) 100k 1M Phase (°) 1500pF Gain (dB) Gain Reset +5V power supply for all three power pins. If separate supplies are used without a common connection, the delta between the supplies during ramp-up time must be less than 0.3V. An application circuit to avoid a power-on latch-up condition is shown in Figure 15. PCM1727 has both internal power-on reset circuit and the RSTB pin (pin 10) which accepts an external forced reset by RSTB = LOW. For internal power on reset, initialize (reset) is done automatically at power on VDD >2.2V (typ). During internal reset = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC/2. Figure 13 illustrates the timing of the internal power on reset. PCM1727 accepts an external forced reset when RSTB = L. When RSTB = L, the output of the DAC is invalid and the analog outputs are forced to VCC/2 after internal initialization (1024 system clocks count after RSTB = H.) Figure 14 illustrates the timing of the RSTB reset pin. Digital Power Supply For system applications, the power-up time of the internal PLL circuit to provide a stable system clock output, is approximately 1024 system clocks plus a 15ms transient time. Analog Power Supply VDD DGND POWER SUPPLY CONNECTIONS VCP VCA AGND FIGURE 15. Latch-up Prevention Circuit. PCM1727 has three power supply connections: digital (VDD), analog (VCA), and PLL (VCP). Each connection also has a separate ground return pin. It is acceptable to use a common 2.6V VCC/VDD 2.2V 1.8V Reset Reset Removal Internal Reset 1024 system (SCKO2) clocks SCKO2 Clock FIGURE 13. Internal Power-On Reset Timing. RSTB 50% of VDD tRST(1) Reset Reset Removal Internal Reset 1024 system (SCKO2) clocks SCKO2 Clock NOTE: (1) tRST = 20ns min FIGURE 14. RSTB-Pin Reset Timing. ® 13 PCM1727 BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. Refer to Figure 18 for optimal values of bypass capacitors. Its is also recommended to include a 0.1µF ceramic capacitor in parallel with the 10µF tantalum capacitor. The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 48fS for a 384fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 17. THEORY OF OPERATION The delta-sigma section of PCM1727 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. AC-3 APPLICATION CIRCUIT A typical application for PCM1727 is AC-3 5.1 channel audio decoding and playback. This circuit uses PCM1727 to develop the audio system clock from the 27MHz video clock, with the SCKO2 pin used to drive the AC-3 decoder and two PCM1720 units, the non-PLL version of PCM1723 and PCM1727. A block diagram of the 5-level delta-sigma modulator is shown in Figure 16. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. + + In 8fS 18-Bit + + + Z–1 – + Z–1 – + + + 5-level Quantizer 4 3 Out 48fS (384fS) 2 1 0 FIGURE 16. 5-Level ∆Σ Modulator Block Diagram. 3rd ORDER ∆Σ MODULATOR 20 0 Gain (–dB) –20 –40 –60 –80 –100 –120 –140 –160 0 5 10 15 Frequency (kHz) FIGURE 17. Quantization Noise Spectrum. ® PCM1727 14 20 25 Z–1 (1) +5V Analog 20 14 BCK AC-3 Audio Decoder 16 LRCK 15 DO_0 GNDD 19 VDD VOUTL BCKIN 12 Post Low Pass Filter Analog Mute Left-Channel Front Speaker Post Low Pass Filter Analog Mute Right-Channel Front Speaker LRCIN DIN CAP 13 + DO_1 10µF DO_2 PCM1720 2 SYSCKI 6 5 4 7 VOUTR SCKI 9 MD 10kΩ +5V Analog MC ZERO 8 Mute Control ML TEST RSTB GNDA 17 VCA 10 11 (1) +5V Analog (1) +5V Analog 20 GNDD 14 16 15 19 VDD VOUTL BCKIN 12 MPU 6 SDO 5 SCO STROBE_0 4 RESET 7 Analog Mute Left-Channel Surround Speaker Post Low Pass Filter Analog Mute Left-Channel Surround Speaker LRCIN DIN CAP 13 + 10µF PCM1720 2 Post Low Pass Filter VOUT SCKI 9 MD 10kΩ +5V Analog MC ZERO 8 Mute Control ML RSTB GNDA TEST VCA 10 STROBE_1 17 11 (1) +5V Analog STROBE_2 (1) +5V Analog 23 17 19 18 9 8 7 10 Buffer Buffer Signal Processor Buffer Signal Processor 20 22 21 3 PGND DGND VDD VDP VOUTL BCKIN 6 Post Low Pass Filter Analog Mute Center Channel Post Low Pass Filter Analog Mute Sub-Woofer LRCIN DIN CAP 15 + 10µF MD MC PCM1727 ML VOUT 11 RSTB 10kΩ SCKO2 +5V Analog ZERO 21 14 SCKO1 XT2 SCKO3 GNDA 12 16 Mute Control 24 XT1 1 VCA 27MHz Master Clock Input 13 (1) +5V Analog NOTE: (1) Bypass Capacitor, 1µF ~ 10µF + 0.1µ. FIGURE 18. Connection Diagram for a 6-Channel AC-3 Application. ® 15 PCM1727