Final Electrical Specifications LTC1598 8-Channel, Micropower Sampling 12-Bit Serial I/O A/D Converter U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC ®1598 is an 8-channel, 5V micropower, 12-bit sampling A/D converter. It typically draws only 320µA of supply current when converting and automatically powers down to typically 1nA between conversions. The LTC1598 is available in a 24-pin SSOP package and operates on a 5V supply. The 12-bit, switched-capacitor, successive approximation ADC includes an 8-channel MUX and a sample-and-hold. 12-Bit Resolution Auto Shutdown to 1nA Low Supply Current: 320µA Typ Guaranteed ±3/4LSB Max DNL Single Supply 5V Operation 8-Channel Multiplexer Separate MUX Output and ADC Input Pins MUX and ADC May Be Controlled Separately Sampling Rate: 16.8ksps I/O Compatible with SPI, MICROWIRETM, etc. 24-Pin SSOP Package On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three or four wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. U APPLICATIONS ■ ■ ■ ■ ■ ■ August 1996 Pen Screen Digitizing Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Battery Monitoring Temperature Measurement The circuit can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. U TYPICAL APPLICATION Supply Current vs Sample Rate 24µW, 8-Channel, 12-Bit ADC Samples at 200Hz and Runs Off a 5V Supply 1000 OPTIONAL ADC FILTER 18 MUXOUT ANALOG INPUTS 0V TO 5V RANGE 20 CH0 21 CH1 22 CH2 23 CH3 24 CH4 1 CH5 2 CH6 3 CH7 8 COM 5V 1µF 17 ADCIN 16 15, 19 VREF VCC CS ADC CS MUX 8-CHANNEL MUX + 12-BIT SAMPLING ADC – CLK DIN DOUT NC GND 4, 9 NC 1µF 10 6 SERIAL DATA LINK MICROWIRE AND SPI COMPATABLE SUPPLY CURRENT (µA) 1k TA = 25°C VCC = 5V VREF = 5V fCLK = 320kHz 100 10 5, 14 7 11 12 MPU 1 0.1 13 1 10 SAMPLE FREQUENCY (kHz) 100 1598 TA02 LTC1598 • TA01 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LTC1598 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Notes 1, 2) Supply Voltage (VCC) to GND ................................... 12V Voltage Analog Reference .................... – 0.3V to (VCC + 0.3V) Analog Inputs .......................... – 0.3V to (VCC + 0.3V) Digital Inputs ......................................... – 0.3V to 12V Digital Output .......................... – 0.3V to (VCC + 0.3V) Power Dissipation.............................................. 500mW Operating Temperature Range LTC1598CG ............................................. 0°C to 70°C LTC1598IG ........................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW CH5 1 24 CH4 CH6 2 23 CH3 CH7 3 22 CH2 GND 4 21 CH1 CLK 5 20 CH0 CS MUX 6 19 VCC DIN 7 18 MUX OUT COM 8 17 ADC IN GND 9 16 VREF CS ADC 10 15 VCC DOUT 11 14 CLK NC 12 LTC1598CG LTC1598IG 13 NC G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 110°C/ W Consult factory for Military grade parts. U U U U WW RECOM ENDED OPERATING CONDITIONS PARAMETER Supply Voltage (Note 3) Clock Frequency Total Cycle Time Hold Time, DIN After CLK↑ Setup Time CS↓ Before First CLK↑ (See Operating Sequence) Setup Time, DIN Stable Before CLK↑ CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer CONDITIONS MIN 4.5 (Note 4) 60 150 1 400 1 1 16 44 VCC = 5V fCLK = 320kHz VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V fCLK = 320kHz fCLK = 320kHz W U SYMBOL VCC fCLK tCYC thDI tsuCS tsuDI tWHCLK tWLCLK tWHCS tWLCS U CONVERTER AND MULTIPLEXER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error REF Input Range Analog Input Range MUX Channel Input Leakage Current MUX OUT Leakage Current ADC IN Input Leakage Current 2 CONDITIONS ● (Note 6) ● ● ● ● (Notes 7, 8) (Notes 7, 8) Channel On or Off (Note 9) All Channels Off ● ● ● MIN 12 LTC1598CG TYP MAX TYP MAX 5.5 320 UNITS V kHz µs ns µs ns µs µs µs µs (Note 5) MIN 12 ±3 ± 3/4 ±3 ±8 1.5V to VCC + 0.05V – 0.05V to VCC + 0.05V ±200 ±200 ±1 LTC1598IG TYP MAX ±3 ±1 ±3 ±8 ±200 ±200 ±1 UNITS Bits LSB LSB LSB LSB V V nA nA µA LTC1598 W U DYNAMIC ACCURACY SYMBOL S/(N + D) THD SFDR (Note 5) fSMPL = 16.8kHz PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion (Up to 5th Harmonic) Spurious-Free Dynamic Range Peak Harmonic or Spurious Noise CONDITIONS 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal U DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL VIH VIL IIH IIL VOH PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage VOL IOZ ISOURCE ISINK RREF Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Input Resistance IREF Reference Current ICC Supply Current AC CHARACTERISTICS CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IO = 10µA VCC = 4.75V, IO = 360µA VCC = 4.75V, IO = 1.6mA CS = High VOUT = 0V VOUT = VCC CS = VIH CS = VIL CS = VCC tCYC ≥ 760µs, fCLK ≤ 25kHz tCYC ≥ 60µs, fCLK ≤ 320kHz CS = VCC, CLK = VCC, DIN = VCC tCYC ≥ 760µs, fCLK ≤ 25kHz tCYC ≥ 60µs, fCLK ≤ 320kHz MIN TYP 71 – 78 80 – 80 MAX UNITS dB dB dB dB MIN 2.6 TYP MAX UNITS V V µA µA V V V µA mA mA MΩ kΩ µA µA µA µA µA µA (Note 5) ● 0.8 2.5 – 2.5 ● ● ● ● ● 4.0 2.4 4.64 4.62 0.4 ±3 ● ● – 25 45 5000 55 0.001 90 90 0.001 320 320 ● ● ● ● 2.5 140 ±5 640 (Note 5) SYMBOL tSMPL fSMPL(MAX) PARAMETER Analog Input Sample Time Maximum Sampling Frequency CONDITIONS See Operating Sequence 1 See Operating Sequence 1 tCONV tdDO tdis ten thDO tf tr tON tOFF tOPEN CIN Conversion Time Delay Time, CLK↓ to DOUT Data Valid Delay Time, CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Time Output Data Remains Valid After CLK↓ DOUT Fall Time DOUT Rise Time Enable Turn-On Time Enable Turn-Off Time Break-Before-Make Interval Input Capacitance See Operating Sequence 1 See Test Circuits See Test Circuits See Test Circuits CLOAD = 100pF See Test Circuits See Test Circuits See Operating Sequence 1 See Operating Sequence 2 MIN ● MAX 16.8 ● ● ● ● ● ● ● ● Analog Inputs On-Channel Off-Channel Digital Input TYP 1.5 35 12 250 135 75 230 50 50 260 100 160 20 5 5 600 300 200 150 150 700 300 UNITS CLK Cycles kHz CLK Cycles ns ns ns ns ns ns ns ns ns pF pF pF 3 LTC1598 AC CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: This device is specified at 5V. Consult factory for 3V specified devices. Note 4: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK = 200kHz at 85°C, fCLK ≥ 120kHz at 70°C and fCLK ≥ 1kHz at 25°C. Note 5: VCC = 5V, VREF = 5V and CLK = 320kHz unless otherwise specified. Note 6: Linearity error is specified between the actual end points of the A/D transfer curve. Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above VCC. This spec allows 50mV forward bias of either diode for 4.5V ≤ VCC ≤ 5.5V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range, it will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading. Note 8: Recommended operating condition. Note 9: Channel leakage current is measured after the channel selection. U U U PIN FUNCTIONS CH5 (Pin 1): Analog Multiplexer Input. CH6 (Pin 2): Analog Multiplexer Input. DOUT (Pin 11): Digital Data Output. The A/D conversion result is shifted out of this output. CH7 (Pin 3): Analog Multiplexer Input. NC (Pin 12): No Connection. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. NC (Pin 13): No Connection. CLK (Pin 5): Shift Clock. This clock synchronizes the serial data transfer to both MUX and ADC. It also determines the conversion speed of the ADC. VCC (Pin 15): Power Supply Voltage. This pin provides power to the A/D Converter. It must be bypassed directly to the analog ground plane. CS MUX (Pin 6): MUX Chip Select Input. A logic high on this input allows the MUX to receive a channel address. A logic low enables the selected MUX channel and connects it to the MUX OUT pin for A/D conversion. For normal operation, drive this pin in parallel with CS ADC. VREF (Pin 16): Reference Input. The reference input defines the span of the ADC. DIN (Pin 7): Digital Data Input. The multiplexer address is shifted into this input. MUX OUT (Pin 18): MUX Output. This pin is the output of the multiplexer. Tie to ADC IN for normal operation. COM (Pin 8): Negative Analog Input. This input is the negative analog input to the ADC and must be free of noise with respect to GND. VCC (Pin 19): Power Supply Voltage. This pin should be tied to Pin 15. GND (Pin 9): Analog Ground. GND should be tied directly to an analog ground plane. CS ADC (Pin 10): ADC Chip Select Input. A logic high on this input deselects and powers down the ADC and threestates DOUT. A logic low on this input enables the ADC to sample the selected channel and start the conversion. For normal operation drive this pin in parallel with CS MUX. 4 CLK (Pin 14): Shift Clock. This input should be tied to Pin 5. ADC IN (Pin 17): ADC Input. This input is the positive analog input to the ADC. Connect this pin to MUX OUT for normal operation. CH0 (Pin 20): Analog Multiplexer Input. CH1 (Pin 21): Analog Multiplexer Input. CH2 (Pin 22): Analog Multiplexer Input. CH3 (Pin 23): Analog Multiplexer Input. CH4 (Pin 24): Analog Multiplexer Input. LTC1598 TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf 1.4V VOH DOUT VOL 3k DOUT TEST POINT tr tf 1598 TC02 100pF 1598 TC01 Voltage Waveforms for ten Voltage Waveforms for DOUT Delay Times, tdDO LTC1598 CLK CS ADC VIL tdDO VOH DOUT 1 CLK 2 VOL 1598 TC03 B11 DOUT VOL t en Voltage Waveforms for tdis Load Circuit for tdis and ten VCC tdis WAVEFORM 2, ten DOUT 100pF VIH CS TEST POINT 3k 1598 TC06 DOUT WAVEFORM 1 (SEE NOTE 1) 90% tdis tdis WAVEFORM 1 1598 TC04 DOUT WAVEFORM 2 (SEE NOTE 2) 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1598 TC05 5 LTC1598 U U W U APPLICATIONS INFORMATION INPUT DATA WORD ANALOG CONSIDERATIONS The LTC1598 uses its Chip Select and DIN pins to select one of its eight channels as shown in the operating sequence figures and Table 1. For this discussion we will assume that CS MUX and CS ADC are tied together and will refer to them as simply, CS. When CS is high, the input data on the DIN pin is latched into the 4-bit shift register on the rising edge of the clock. The input data word consists of an “EN” bit and a string of three bits for channel selection. If the “EN” bit is logic high as illustrated in Operating Sequence 1, it enables the selected channel. To ensure correct operation, the CS must be pulled low before the next rising edge of the clock. More than four input bits can be sent to the ADC without problems. The channel will be determined by the last four bits clocked in before CS falls. Once the CS is pulled low, all channels are simultaneously switched off to ensure a break-before-make interval. After a delay of tON, the selected channel is switched on, allowing signal transmission. The selected channel remains on, until the next falling edge of CS. After a delay of tOFF, it terminates the analog signal transmission and switches to the next selected channel. If the “EN” bit is logic low, as illustrated in Operating Sequence 2, it disables all channels. Table 1 shows the various bit combinations for channel selection. Table 1. Logic Table for Channel Selection CHANNEL STATUS EN D2 D1 DO All Off 0 X X X CH0 1 0 0 0 CH1 1 0 0 1 CH2 1 0 1 0 CH3 1 0 1 1 CH4 1 1 0 0 CH5 1 1 0 1 CH6 1 1 1 0 CH7 1 1 1 1 6 Grounding The LTC1598 should be used with an analog ground plane and single-point grounding techniques. To achieve the optimum performance use a printed circuit board. The Ground pins (Pins 4 and 9) should be tied directly to the ground plane with minimum lead length. Bypassing For good performance, the LTC1598 VCC and VREF pins must be free of noise and ripple. Any changes in the VCC and VREF voltages with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with minimum of 0.1µF capacitors and lead lengths as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1598 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. LTC1598 U U W U APPLICATIONS INFORMATION Operating Sequence 1 Example: (CH2, GND) tCYC CS MUX = CS ADC = CS tsuCS CLK EN D1 DIN DON’T CARE D0 D2 NULL BIT HI-Z DOUT B11 B10 B9 B8 tSMPL B7 B6 B5 B4 B3 B2 B1 B0 HI-Z tCONV CH0 TO CH7 tON ADC IN = MUX OUT COM = GND 1598 TD01 Operating Sequence 2 Example: (ALL Channels Off) tCYC CS MUX = CS ADC = CS tsuCS CLK EN D1 DIN DON’T CARE D0 D2 DOUT NULL BIT HI-Z DUMMY CONVERSION HI-Z tCONV CH0 TO CH7 tOFF ADC IN = MUX OUT COM = GND 1598 TD02 7 LTC1598 U TYPICAL APPLICATIONS Microprocessor Interfaces Motorola SPI (MC68HC05) The LTC1598 can interface directly (without external hardware) to most popular microprocessors’ (MPU) synchronous serial formats including MICROWIRETM, SPI and QSPI. If an MPU without a dedicated serial port is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1598. Included here is one serial interface example. The MC68HC05 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSBfirst and in 8-bit increments. The DIN word sent to the data register starts the SPI process. With three 8-bit transfers the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B7 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits B6 through B0 into the MPU. ANDing the second byte with 1FHEX clears the three most significant bits and ANDing the third byte with FEHEX clears the least significant bit. Shifting the data to the right by one bit results in a right justified word. MICROWIRE is a trademark of National Semiconductor Corp. LDA #$52 STA $0A LDA #$FF STA STA STA LDA $04 $05 $06 #$08 STA $50 START BSET 0,$02 LDA $50 STA $0C LOOP1 TST $0B BPL LOOP1 BCLR 0,$02 LDA $0C STA $0C LOOP2 TST $0B BPL LOOP2 LDA $0C STA $0C AND #$IF STA $00 LOOP3 TST $0B BPL LOOP3 LDA $0C AND #$FE STA $01 JMP START 8 MC68HC05 CODE Configuration data for serial peripheral control register (Interrupts disabled, output enabled, master, Norm = 0, Ph = 0, Clk/16) Load configuration data into location $0A (SPCR) Configuration data for I/O ports (all bits are set as outputs) Load configuration data into Port A DDR ($04) Load configuration data into Port B DDR ($05) Load configuration data into Port C DDR ($06) Put DIN word for LTC1598 into Accumulator (CH0 with respect to GND) Load DIN word into memory location $50 Bit 0 Port C ($02) goes high (CS goes high) Load DIN word at $50 into Accumulator Load DIN word into SPI data register ($0C) and start clocking data Test status of SPIF bit in SPI status register ($0B) Loop if not done with transfer to previous instruction Bit 0 Port C ($02) goes low (CS goes low) Load contents of SPI data register into Accumulator Start next SPI cycle Test status of SPIF Loop if not done Load contents of SPI data register into Accumulator Start next SPI cycle Clear 3 MSBs of first DOUT word Load Port A ($00) with MSBs Test status of SPIF Loop if not done Load contents of SPI data register into Accumulator Clear LSB of second DOUT word Load Port B ($01) with LSBs Go back to start and repeat program LTC1598 U TYPICAL APPLICATIONS Data Exchange Between LTC1598 and MC68HC05 CS MUX = CS ADC = CS CLK D2 EN DIN D1 DON'T CARE DO DOUT B11 B10 MPU TRANSMIT WORD 0 MPU RECEIVED WORD ? 0 0 0 EN D2 D1 X D0 X X ? ? X B8 B7 X X X B6 X B5 B4 X X BYTE 2 BYTE 1 ? X B9 ? ? ? ? ? ? 0 B11 B10 B2 B1 B0 B1 X X X X X B1 B0 B1 B2 BYTE 3 B9 B8 B7 B6 BYTE 2 BYTE 1 B3 B5 B4 B2 B3 BYTE 3 1598 TA03 Hardware and Software Interface to Motorola MC68HC05 DOUT FROM LTC1598 STORED IN MC68HC05 RAM MSB #00 0 0 0 B11 B10 B9 B8 B7 CS MUX BYTE 1 CS ADC ANALOG INPUTS LSB #01 B6 B5 B4 B3 B2 B1 B0 0 BYTE 2 LTC1598 C0 MC68HC05 CLK SCK DIN MOSI DOUT MISO 1598 TA04 9 LTC1598 U TYPICAL APPLICATIONS MULTICHANNEL A/D USES A SINGLE ANTIALIASING FILTER This circuit demonstrates how the LTC1598’s independent analog multiplexer can simplify design of a 12-bit data acquisition system. All eight channels are MUXed into a single 1kHz, fourth-order Sallen-Key antialiasing filter, which is designed for single-supply operation. Since the LTC1598’s data converter accepts inputs from ground to the positive supply, rail-to-rail op amps were chosen for the filter to maximize dynamic range. The LT1368 dual railto-rail op amp is designed to operate with 0.1µF load capacitors (C1 and C2). These capacitors provide frequency compensation for the amplifiers and help reduce the amplifier’s output impedance and improve supply rejection at high frequencies. The filter contributes less than 1LSB of error due to offsets and bias currents. The filter’s noise and distortion are less than –72dB for a 100Hz, 2VP-P offset sine input. The combined MUX and A/D errors result in an integral nonlinearity error of ± 3LSB (maximum) and a differential nonlinearity error of ±3/4LSB (maximum). The typical signal-to-noise plus distortion ratio is 71dB, with approximately –78dB of total harmonic distortion. The LTC1598 is programmed through a 4-wire serial interface that is compatable with MICROWIRE, SPI and QSPI. Maximum serial clock speed is 320kHz, which corresponds to a 16.8kHz sampling rate. The complete circuit consumes approximately 800µA from a single 5V supply. Simple Data Acquisition System Takes Advantage of the LTC1598’s MUXOUT/ADCIN Pins-to-Filter Analog Signals Prior to A/D Conversion ANALOG INPUTS 0V TO 5V RANGE 5V 1 2 3 4 5 6 7 8 9 10 11 12 CH5 CH4 CH6 CH3 CH7 CH2 GND CH1 CLK LTC1598 CH0 CS MUX DIN VCC MUXOUT COM ADCIN GND VREF CS ADC VCC DOUT CLK NC NC 24 0.015µF 1µF 23 1/2 LT1368 21 20 7.5k + 22 C2 0.1µF 5V 7.5k 0.03µF – 19 18 1µF 17 7.5k 16 15 7.5k 0.015µF 14 0.03µF 13 + 1/2 LT1368 – C1 0.1µF DATA OUT DATA IN CHIP SELECT CLOCK 10 LTC1598 • TA05 LTC1598 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.318 – 0.328* (8.07 – 8.33) 24 23 22 21 20 19 18 17 16 15 14 13 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.0256 (0.65) BSC 0.010 – 0.015 (0.25 – 0.38) 0.002 – 0.008 (0.05 – 0.21) G24 SSOP 0595 11 LTC1598 U TYPICAL APPLICATION Digitally Linearized Platinum RTD Signal Conditioner 5VOUT +15V LT1027 + 10µF 12k* 500k 400°C TRIM 12.5k* +15V +15V + A1 LT1101 A=10 – 1k* Rplat. + 1k A2 LT1006 – 30.1k** 1µF * TRW-IRC MAR-6 RESISTOR – 0.1% ** 1% FILM RESISTOR Rplat. = 1kΩ AT 0°C – ROSEMOUNT #118MF 3.92M** 500k ZERO°C TRIM CH5 CH4 CH6 CH3 CH7 CH2 GND CH1 CLK LTC1598 CH0 CS MUX VCC MUX OUT DIN COM ADC IN GND VREF VCC CS ADC CLK DOUT NC NC 10µF TANTALUM TO/FROM MC68HC05 LTC1598 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1096/LTC1098 8-Pin SO, Micropower 8-Bit ADC Low Power, Small Size, Low Cost LTC1096L/LTC1098L 8-Pin SO, 2.65V Micropower 8-Bit ADC Low Power, Small Size, Low Cost LTC1196/LTC1198 8-Pin SO, 1Msps 8-Bit ADC Low Power, Small Size, Low Cost LTC1282 3V High Speed Parallel 12-Bit ADC 140ksps, Complete with VREF, CLK, Sample-and-Hold LTC1285/LTC1288 8-Pin SO, 3V, Micropower 1- or 2-Channel, Auto Shutdown LTC1289 Multiplexed 3V, 1A, 12-Bit ADC 8-Channel 12-Bit Serial I/O LTC1594 4-Channel, 5V Micropower 12-Bit ADC Low Power, Small Size, Low Cost LTC1594L 4-Channel, 3V Micropower 12-Bit ADC Low Power, Small Size, Low Cost 12 Linear Technology Corporation LT/GP 0896 5K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1996