LTC1594/LTC1598 4- and 8-Channel, Micropower Sampling 12-Bit Serial I/O A/D Converters U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 12-Bit Resolution Auto Shutdown to 1nA Low Supply Current: 320µA Typ Guaranteed ±3/4LSB Max DNL Single Supply 5V Operation (3V Versions Available: LTC1594L/LTC1598L) Multiplexer: 4-Channel MUX (LTC1594) 8-Channel MUX (LTC1598) Separate MUX Output and ADC Input Pins MUX and ADC May Be Controlled Separately Sampling Rate: 16.8ksps I/O Compatible with QSPI, SPI and MICROWIRETM, etc. Small Package: 16-Pin Narrow SO (LTC1594) 24-Pin SSOP (LTC1598) U APPLICATIONS ■ ■ ■ ■ ■ ■ The LTC ®1594/LTC1598 are micropower, 12-bit sampling A/D converters that feature 4- and 8-channel multiplexers, respectively. They typically draw only 320µA of supply current when converting and automatically power down to a typical supply current of 1nA between conversions. The LTC1594 is available in a 16-pin SO package and the LTC1598 is packaged in a 24-pin SSOP. Both operate on a 5V supply. The 12-bit, switched-capacitor, successive approximation ADCs include a sample-and-hold. On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three or four wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. The circuit can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. Pen Screen Digitizing Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Battery Monitoring Temperature Measurement , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. U TYPICAL APPLICATION 24µW, 4-Channel, 12-Bit ADC Samples at 200Hz and Runs Off a 5V Supply OPTIONAL ADC FILTER Supply Current vs Sample Rate 18 MUXOUT ANALOG INPUTS 0V TO 5V RANGE 20 CH0 21 CH1 22 CH2 23 CH3 24 CH4 1 CH5 2 CH6 3 CH7 8 COM 5V 1µF 17 ADCIN 16 15, 19 VREF VCC CSADC CSMUX 8-CHANNEL MUX + 12-BIT SAMPLING ADC – CLK DIN DOUT NC GND 4, 9 NC 1594/98 TA01 1000 TA = 25°C VCC = 5V VREF = 5V fCLK = 320kHz 1µF 10 6 SERIAL DATA LINK MICROWIRE AND SPI COMPATABLE 5, 14 7 11 MPU SUPPLY CURRENT (µA) 1k 100 10 12 13 1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100 1594/98 TA02 1 LTC1594/LTC1598 U W W W ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) to GND ................................... 12V Voltage Analog Reference .................... – 0.3V to (VCC + 0.3V) Analog Inputs .......................... – 0.3V to (VCC + 0.3V) Digital Inputs ......................................... – 0.3V to 12V Digital Output .......................... – 0.3V to (VCC + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1594CS/LTC1598CG ......................... 0°C to 70°C LTC1594IS/LTC1598IG ..................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U W U PACKAGE/ORDER INFORMATION ORDER PART NUMBER TOP VIEW CH0 1 16 VCC CH1 2 15 MUXOUT CH2 3 14 DIN CH3 4 13 CSMUX LTC1594CS LTC1594IS CH5 1 24 CH4 CH6 2 23 CH3 CH7 3 22 CH2 GND 4 21 CH1 CLK 5 20 CH0 19 VCC CSMUX 6 ADCIN 5 12 CLK DIN 7 18 MUXOUT VREF 6 11 VCC COM 8 17 ADCIN COM 7 10 DOUT GND 9 16 VREF GND 8 9 CSADC S PACKAGE 16-LEAD PLASTIC SO ORDER PART NUMBER TOP VIEW CSADC 10 15 VCC DOUT 11 14 CLK NC 12 TJMAX = 125°C, θJA = 120°C/ W LTC1598CG LTC1598IG 13 NC G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 110°C/ W Consult factory for Military grade parts. U U U U WW RECOM ENDED OPERATING CONDITIONS (Note 5) SYMBOL VCC fCLK tCYC thDI tsuCS tsuDI tWHCLK tWLCLK tWHCS tWLCS 2 PARAMETER Supply Voltage (Note 3) Clock Frequency Total Cycle Time Hold Time, DIN After CLK↑ Setup Time CS↓ Before First CLK↑ (See Operating Sequence) Setup Time, DIN Stable Before CLK↑ CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer CONDITIONS VCC = 5V fCLK = 320kHz VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V fCLK = 320kHz fCLK = 320kHz MIN 4.5 (Note 4) 60 150 1 400 1 1 16 44 TYP MAX 5.5 320 UNITS V kHz µs ns µs ns µs µs µs µs LTC1594/LTC1598 W U U CONVERTER AND MULTIPLEXER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error REF Input Range Analog Input Range MUX Channel Input Leakage Current MUXOUT Leakage Current ADCIN Input Leakage Current CONDITIONS ● (Note 6) ● ● ● (Notes 7, 8) (Notes 7, 8) Off Channel Off Channel (Note 9) W U DYNAMIC ACCURACY SYMBOL S/(N + D) THD SFDR ● ● ● ● LTC1594CS/LTC1598CG LTC1594IS/LTC1598IG MIN TYP MAX MIN TYP MAX 12 12 ±3 ±3 ± 3/4 ±1 ±3 ±3 ±8 ±8 1.5V to VCC + 0.05V – 0.05V to VCC + 0.05V ±200 ±200 ±200 ±200 ±1 ±1 CONDITIONS 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal U DIGITAL AND DC ELECTRICAL CHARACTERISTICS PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage VOL IOZ ISOURCE ISINK RREF Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Input Resistance IREF Reference Current ICC Supply Current UNITS Bits LSB LSB LSB LSB V V nA nA µA (Note 5) fSMPL = 16.8kHz PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion (Up to 5th Harmonic) Spurious-Free Dynamic Range Peak Harmonic or Spurious Noise SYMBOL VIH VIL IIH IIL VOH (Note 5) CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IO = 10µA VCC = 4.75V, IO = 360µA VCC = 4.75V, IO = 1.6mA CS = High VOUT = 0V VOUT = VCC CS = VIH CS = VIL CS = VCC tCYC ≥ 760µs, fCLK ≤ 25kHz tCYC ≥ 60µs, fCLK ≤ 320kHz CS = VCC, CLK = VCC, DIN = VCC tCYC ≥ 760µs, fCLK ≤ 25kHz tCYC ≥ 60µs, fCLK ≤ 320kHz MIN TYP 71 – 78 80 – 80 MAX UNITS dB dB dB dB MIN 2.6 TYP MAX UNITS V V µA µA V V V µA mA mA MΩ kΩ µA µA µA µA µA µA (Note 5) ● 0.8 2.5 – 2.5 ● ● ● ● ● 4.0 2.4 4.64 4.62 0.4 ±3 ● ● ● ● ● ● – 25 45 5000 55 0.001 90 90 0.001 320 320 2.5 140 ±5 640 3 LTC1594/LTC1598 AC CHARACTERISTICS (Note 5) SYMBOL tSMPL fSMPL(MAX) PARAMETER Analog Input Sample Time Maximum Sampling Frequency CONDITIONS See Figure 1 in Applications Information See Figure 1 in Applications Information tCONV tdDO tdis ten thDO tf tr tON tOFF tOPEN CIN Conversion Time Delay Time, CLK↓ to DOUT Data Valid Delay Time, CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Time Output Data Remains Valid After CLK↓ DOUT Fall Time DOUT Rise Time Enable Turn-On Time Enable Turn-Off Time Break-Before-Make Interval Input Capacitance See Figure 1 in Applications Information See Test Circuits See Test Circuits See Test Circuits CLOAD = 100pF See Test Circuits See Test Circuits See Figure 1 in Applications Information See Figure 2 in Applications Information ● MIN 1.5 16.8 ● ● ● ● ● ● ● ● 35 Analog Inputs On-Channel Off-Channel Digital Input The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: These devices are specified at 5V. Consult factory for 3V specified devices (LTC1594L/LTC1598L). Note 4: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK ≥ 160kHz at 85°C, fCLK ≥ 75kHz at 70°C and fCLK ≥ 1kHz at 25°C. Note 5: VCC = 5V, VREF = 5V and CLK = 320kHz unless otherwise specified. CSADC and CSMUX pins are tied together during the test. TYP 12 250 135 75 230 50 50 260 100 160 20 5 5 MAX 600 300 200 150 150 700 300 UNITS CLK Cycles kHz CLK Cycles ns ns ns ns ns ns ns ns ns pF pF pF Note 6: Linearity error is specified between the actual end points of the A/D transfer curve. Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above VCC. This spec allows 50mV forward bias of either diode for 4.5V ≤ VCC ≤ 5.5V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range, it will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading. Note 8: Recommended operating condition. Note 9: Channel leakage current is measured after the channel selection. U W TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Sample Rate Supply Current vs Temperature 400 100 10 TA = 25°C VCC = VREF = 5V fCLK = 320kHz fSMPL = 16.8kHz 94.5 REFERENCE CURRENT (µA) TA = 25°C VCC = 5V VREF = 5V fCLK = 320kHz 350 300 250 1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100 1594/98 G01 4 Reference Current vs Temperature 95.0 450 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 1000 200 – 55 – 35 –15 VCC = VREF = 5V fSMPL = 16.8kHz fCLK = 320kHz 94.0 93.5 93.0 92.5 5 25 45 65 85 105 125 TEMPERATURE (°C) 1594/98 G02 92.0 – 55 – 35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1594/98 G03 LTC1594/LTC1598 U W TYPICAL PERFORMANCE CHARACTERISTICS Change in Offset vs Reference Voltage 1.5 1.0 –1.0 –1.5 – 2.0 VCC = VREF = 5V fCLK = 320kHz fSMPL = 16.8kHz – 2.5 0.5 1.5 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) 4.5 – 3.0 45 5 25 – 55 – 35 – 15 TEMPERATURE (°C) 5.0 CHANGE IN LINEARITY (LSB) – 0.5 2.0 0 1.0 65 –7 –6 –5 –4 –3 TA = 25°C VCC = 5V fCLK = 320kHz 1.0 4.5 0 5.0 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) 9 62 56 8 50 7 44 6 38 5 TA = 25°C VCC = 5V fCLK = 320kHz fSMPL = 16.8kHz 0 1000 5.0 0.6 0.4 0.2 0.0 – 0.2 – 0.4 – 0.6 – 0.8 3 4 2 REFERENCE VOLTAGE (V) 2048 CODE 0 5 S/(N + D) vs Input Level 80 90 80 70 60 50 40 30 20 T = 25°C A 10 VCC = VREF = 5V fSMPL = 16.8kHz 0 1 10 100 INPUT FREQUENCY (kHz) 4096 1594/98 G09 SIGNAL-TO-NOISE PLUS DISTORTION (dB) 10 4.5 0.8 100 SPURIOUS FREE DYNAMIC RANGE (dB) EFFECTIVE NUMBER OF BITS (ENOBs) 74 68 1594/98 G10 1.5 1.0 Spurious Free Dynamic Range vs Frequency 12 11 10 100 INPUT FREQUENCY (kHz) 0 1.0 1594/98 G08 Effective Bits and S/(N + D) vs Input Frequency 1 – 0 .10 –1.0 1 1594/98 G07 2 1 – 0 .15 Differential Nonlinearity vs Code –1 4 3 – 0 .20 1594/98 G06 0.5 –2 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) – 0 .25 85 1.5 ADC NOISE IN LBSs CHANGE IN GAIN (LSB) 2.0 TA = 25°C VCC = 5V fCLK = 320kHz fSMPL = 16.8kHz 1.5 – 0 .30 Peak-to-Peak ADC Noise vs Reference Voltage –10 0 1.0 – 0 .35 1594/98 G05 Change in Gain vs Reference Voltage –8 – 0 .40 – 0 .05 1594/98 G04 –9 TA = 25°C VCC = 5V fCLK = 320kHz fSMPL = 16.8kHz – 0 .45 DIFFERENTIAL NONLINEARITY ERROR (LBS) 2.5 – 0 .50 0 TA = 25°C VCC = 5V fCLK = 320kHz fSMPL = 16.8kHz CHANGE IN OFFSET (LSB) CHANGE IN OFFSET (LSB = 1/4096 VREF) 3.0 Change in Linearity vs Reference Voltage Change in Offset vs Temperature 1000 1594/98 G11 70 60 TA = 25°C VCC = VREF = 5V fIN = 1kHz fSMPL = 16.8kHz 50 40 30 20 10 0 – 40 – 30 –20 –10 INPUT LEVEL (dB) 0 1594/98 G12 5 LTC1594/LTC1598 U W TYPICAL PERFORMANCE CHARACTERISTICS 4096 Point FFT Plot Attenuation vs Input Frequency TA = 25°C VCC = VREF = 5V fIN = 5kHz fCLK = 320kHz fSMPL = 12.5kHz –20 20 –40 MAGNITUDE (dB) 30 40 50 60 70 80 –80 1 100 1000 10 INPUT FREQUENCY (kHz) –120 –120 0 10000 1 2 4 3 5 FREQUENCY (kHz) 6 2 4 3 5 FREQUENCY (kHz) 240 VIN + INPUT 180 COM 120 RSOURCE– 1000 RSOURCE+ VIN 1 SOURCE RESISTANCE (kΩ) 0.1 10 100 0.1 1 10 100 1000 SOURCE RESISTANCE (Ω) 1594/98 G17 1594/98 G16 1000 VCC = VREF = 5V 100 LEAKAGE CURRENT (nA) 160 80 0 5 25 45 – 55 – 35 –15 TEMPERATURE (°C) VCC = 5V VREF = 5V 10 ON CHANNEL 1 OFF CHANNEL 0.1 65 85 1594/98 G19 10000 1594/98 G18 Input Channel Leakage Current vs Temperature Minimum Clock Frequency for 0.1LSB Error vs Temperature 240 + INPUT COM TA = 25°C VCC = VREF = 5V 0 10000 7 1594/98 G15 S & H ACQUISITION TIME (ns) CLOCK FREQUENCY (kHz) –100 6 TA = 25°C VCC = VREF = 5V 60 10 100 1000 RIPPLE FREQUENCY (kHz) 1 10000 300 – 50 CLOCK FREQUENCY (kHz) 0 Sample-and-Hold Acquisition Time vs Source Resistance 360 TA = 25°C VCC = 5V (VRIPPLE = 20mV) VREF = 5V fCLK = 320kHz FEEDTHROUGH (dB) –140 Maximum Clock Frequency vs Source Resistance 0 6 7 1594/98 G14 Power Supply Feedthrough vs Ripple Frequency 320 –80 –100 1594/98 G13 1 – 60 –100 –140 100 TA = 25°C VCC = VREF = 5V f1 = 5kHz f2 = 6kHz – 40 fSMPL = 12.5kHz –20 –60 TA = 25°C VCC = VREF = 5V fSMPL = 16.8kHz 90 0 MAGNITUDE (dB) 10 ATTENUATION (%) Intermodulation Distortion 0 0 0.01 – 60 – 40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1594/98 G20 LTC1594/LTC1598 U U U PIN FUNCTIONS LTC1594 CH0 (Pin 1): Analog Multiplexer Input. CH1 (Pin 2): Analog Multiplexer Input. CH2 (Pin 3): Analog Multiplexer Input. CH3 (Pin 4): Analog Multiplexer Input. ADCIN (Pin 5): ADC Input. This input is the positive analog input to the ADC. Connect this pin to MUXOUT for normal operation. VREF (Pin 6): Reference Input. The reference input defines the span of the ADC. COM (Pin 7): Negative Analog Input. This input is the negative analog input to the ADC and must be free of noise with respect to GND. GND (Pin 8): Analog Ground. GND should be tied directly to an analog ground plane. CSADC (Pin 9): ADC Chip Select Input. A logic high on this input powers down the ADC and three-states DOUT. A logic low on this input enables the ADC to sample the selected channel and start the conversion. For normal operation drive this pin in parallel with CSMUX. DOUT (Pin 10): Digital Data Output. The A/D conversion result is shifted out of this output. VCC (Pin 11): Power Supply Voltage. This pin provides power to the ADC. It must be bypassed directly to the analog ground plane. CLK (Pin 12): Shift Clock. This clock synchronizes the serial data transfer to both MUX and ADC. CSMUX (Pin 13): MUX Chip Select Input. A logic high on this input allows the MUX to receive a channel address. A logic low enables the selected MUX channel and connects it to the MUXOUT pin for A/D conversion. For normal operation, drive this pin in parallel with CSADC. DIN (Pin 14): Digital Data Input. The multiplexer address is shifted into this input. MUXOUT (Pin 15): MUX Output. This pin is the output of the multiplexer. Tie to ADCIN for normal operation. VCC (Pin 16): Power Supply Voltage. This pin should be tied to Pin 11. LTC1598 CH5 (Pin 1): Analog Multiplexer Input. CH6 (Pin 2): Analog Multiplexer Input. CH7 (Pin 3): Analog Multiplexer Input. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CLK (Pin 5): Shift Clock. This clock synchronizes the serial data transfer to both MUX and ADC. It also determines the conversion speed of the ADC. CSMUX (Pin 6): MUX Chip Select Input. A logic high on this input allows the MUX to receive a channel address. A logic low enables the selected MUX channel and connects it to the MUXOUT pin for A/D conversion. For normal operation, drive this pin in parallel with CSADC. DIN (Pin 7): Digital Data Input. The multiplexer address is shifted into this input. COM (Pin 8): Negative Analog Input. This input is the negative analog input to the ADC and must be free of noise with respect to GND. GND (Pin 9): Analog Ground. GND should be tied directly to an analog ground plane. CSADC (Pin 10): ADC Chip Select Input. A logic high on this input deselects and powers down the ADC and threestates DOUT. A logic low on this input enables the ADC to sample the selected channel and start the conversion. For normal operation drive this pin in parallel with CSMUX. DOUT (Pin 11): Digital Data Output. The A/D conversion result is shifted out of this output. NC (Pin 12): No Connection. NC (Pin 13): No Connection. CLK (Pin 14): Shift Clock. This input should be tied to Pin 5. 7 LTC1594/LTC1598 U U U PIN FUNCTIONS VCC (Pin 15): Power Supply Voltage. This pin provides power to the A/D Converter. It must be bypassed directly to the analog ground plane. VCC (Pin 19): Power Supply Voltage. This pin should be tied to Pin 15. VREF (Pin 16): Reference Input. The reference input defines the span of the ADC. CH1 (Pin 21): Analog Multiplexer Input. ADCIN (Pin 17): ADC Input. This input is the positive analog input to the ADC. Connect this pin to MUXOUT for normal operation. CH0 (Pin 20): Analog Multiplexer Input. CH2 (Pin 22): Analog Multiplexer Input. CH3 (Pin 23): Analog Multiplexer Input. CH4 (Pin 24): Analog Multiplexer Input. MUXOUT (Pin 18): MUX Output. This pin is the output of the multiplexer. Tie to ADCIN for normal operation. W BLOCK DIAGRA S LTC1594 15 MUXOUT LTC1598 5 6 ADCIN VREF VCC 3 CH2 MUXOUT CSADC 1 CH0 2 CH1 18 16 CSMUX 4-CHANNEL MUX + 4 CH3 12-BIT SAMPLING ADC CLK DIN – 7 COM DOUT 9 20 CH0 13 21 CH1 12 22 CH2 14 23 CH3 10 24 CH4 LTC1594 8 16 VREF VCC 15, 19 CSADC CSMUX 8-CHANNEL MUX 1 CH5 GND 17 ADCIN + 12-BIT SAMPLING ADC – 2 CH6 CLK DIN DOUT NC 3 CH7 NC 8 COM GND 4, 9 10 6 5, 14 7 11 12 13 LTC1598 1594/98 BD TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf 1.4V VOH DOUT VOL 3k DOUT TEST POINT 100pF 1594/98 TC01 8 tr tf 1594/98 TC02 LTC1594/LTC1598 TEST CIRCUITS Voltage Waveforms for ten Voltage Waveforms for DOUT Delay Times, tdDO LTC1594/LTC1598 CLK CSADC VIL tdDO VOH DOUT 1 CLK 2 VOL 1594/98 TC03 B11 DOUT VOL t en Load Circuit for tdis and ten 1594/98 TC06 Voltage Waveforms for tdis TEST POINT CSADC = CSMUX = CS 3k VCC tdis WAVEFORM 2, ten DOUT 100pF VIH tdis WAVEFORM 1 DOUT WAVEFORM 1 (SEE NOTE 1) 90% tdis 1594/98 TC04 DOUT WAVEFORM 2 (SEE NOTE 2) 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1594/98 TC05 9 LTC1594/LTC1598 U U W U APPLICATIONS INFORMATION OVERVIEW The LTC1594/LTC1598 are micropower, 12-bit sampling A/D converters that feature a 4- and 8-channel multiplexer respectively. They typically draw only 320µA of supply current when sampling at 16.8kHz. Supply current drops linearly as the sample rate is reduced (see Supply Current vs Sample Rate). The ADCs automatically power down when not performing conversions, drawing only leakage current. The LTC1594 is available in a 16-pin narrow SO package and the LTC1598 is packaged in a 24-pin SSOP. Both devices operate on a single supply from 4.5V to 5.5V. The LTC1594/LTC1598 contain a 12-bit, switchedcapacitor ADC, sample-and-hold, serial port and an external reference input pin. In addition, the LTC1594 has a 4-channel multiplexer and the LTC1598 provides an 8-channel multiplexer (see Block Diagram). They can measure signals floating on a DC common mode voltage and can operate with reduced spans to 1.5V. Reducing the spans allow them to achieve 366µV resolution. The LTC1594/LTC1598 provide separate MUX output and ADC input pins to form an ideal MUXOUT/ADCIN loop which economizes signal conditioning. The MUX and ADC of the devices can also be controlled individually through separate chip selects to enhance flexibility. SERIAL INTERFACE For this discussion we will assume that CSMUX and CSADC are tied together and will refer to them as simply CS, unless otherwise specified. The LTC1594/LTC1598 communicate with the microprocessor and other external circuitry via a synchronous, half duplex, 4-wire interface (see Operating Sequences in Figures 1 and 2). tCYC CSMUX = CSADC = CS tsuCS CLK EN D1 DIN DON’T CARE D0 D2 DOUT NULL BIT Hi-Z tSMPL B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z tCONV CH0 TO CH7 tON ADCIN = MUXOUT COM = GND *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY Figure 1. LTC1594/LTC1598 Operating Sequence Example: CH2, GND 10 1594/98 F01 LTC1594/LTC1598 U U W U APPLICATIONS INFORMATION tCYC CSMUX = CSADC = CS tsuCS CLK EN D1 DIN D0N‘T CARE D0 D2 DOUT NULL BIT Hi-Z Hi-Z DUMMY CONVERSION tCONV CH0 TO CH7 tOFF ADCIN = MUXOUT 1594/98 F02 COM = GND Figure 2. LTC1594/LTC1598 Operating Sequence Example: All Channels Off Data Transfer The CLK synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. The LTC1594/LTC1598 first receive input data and then transmit back the A/D conversion results (half duplex). Because of the half duplex operation, DIN and DOUT may be tied together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a rising chip select (CS) signal. After CS rises the input data on the DIN pin is latched into a 4-bit register on the rising edge of the clock. More than four input bits can be sent to the DIN pin without problems, but only the last four bits clocked in before CS falls will be stored into the 4-bit register. This 4-bit input data word will select the channel in the muliplexer (see Input Data Word and Tables 1 and 2). To ensure correct operation the CS must be pulled low before the next rising edge of the clock. Once the CS is pulled low, all channels are simultaneously switched off after a delay of tOFF to ensure a break-before-make interval, tOPEN. After a delay of tON (tOFF + tOPEN), the selected channel is switched on, allowing the ADC in the chip to acquire input signal and start the conversion (see Figures 1 and 2). After 1 null bit, the result of the conversion is output on the DOUT line. The selected channel remains on, until the next falling edge of CS. At the end of the data exchange CS should be brought high. This resets the LTC1594/LTC1598 and initiates the next data exchange. CS DIN1 DIN2 DOUT1 SHIFT MUX ADDRESS IN DOUT2 SHIFT A/D CONVERSION RESULT OUT 1594/98 AI01 tSMPL + 1 NULL BIT Break-Before-Make The LTC1594/LTC1598 provide a break-before-make interval from switching off all the channels simultaneously to switching on the next selected channel once CS is pulled low. In other words, once CS is pulled low, 11 LTC1594/LTC1598 U U W U APPLICATIONS INFORMATION after a delay of tOFF, all the channels are switched off to ensure a break-before-make interval. After this interval, the selected channel is switched on allowing signal transmission. The selected channel remains on until the next falling edge of CS and the process repeats itself with the “EN” bit being logic high. If the “EN” bit is logic low, all the channels are switched off simultaneously after a delay of tOFF from CS being pulled low and all the channels remain off until the next falling edge of CS. Input Data Word When CS is high, the LTC1594/LTC1598 clock data into the DIN inputs on the rising edge of the clock and store the data into a 4-bit register. The input data words are defined as follows: EN D2 D1 D0 Table 2. Logic Table for the LTC1598 Channel Selection CHANNEL STATUS EN D2 D1 DO All Off 0 X X X CH0 1 0 0 0 CH1 1 0 0 1 CH2 1 0 1 0 CH3 1 0 1 1 CH4 1 1 0 0 CH5 1 1 0 1 CH6 1 1 1 0 CH7 1 1 1 1 Transfer Curve The LTC1594/LTC1598 are permanently configured for unipolar only. The input span and code assignment for this conversion type is illustrated below. Transfer Curve CHANNEL SELECTION 1594/98 AI02 “EN” Bit 111111111111 • • • 000000000001 VIN 000000000000 Multiplexer (MUX) Address VREF VREF 4096 VREF–1LSB 1LSB = VREF–2LSB 1LSB 0V The first bit in the 4-bit register is an “EN” bit. If the “EN” bit is a logic high, as illustrated in Figure 1, it enables the selected channel after a delay of tON when the CS is pulled low. If the “EN” bit is logic low, as illustrated in Figure 2, it disables all channels after a delay of tOFF when the CS is pulled low. 111111111110 1594/98 • AI03 The 3 bits of input word following the “EN” bit select the channel in the MUX for the requested conversion. For a given channel selection, the converter will measure the voltage of the selected channel with respect to the voltage on the COM pin. Tables 1 and 2 show the various bit combinations for the LTC1594/LTC1598 channel selection. Table 1. Logic Table for the LTC1594 Channel Selection Output Code OUTPUT CODE INPUT VOLTAGE INPUT VOLTAGE (VREF = 5.000V) 11111111111111 11111111111110 • • • 00000000000001 00000000000000 VREF – 1LSB VREF – 2LSB • • • 1LSB 0V 4.99878V 4.99756V • • • 0.00122V 0V 1594/98 • AI04 CHANNEL STATUS EN D2 D1 DO All Off 0 X X X CH0 1 0 0 0 CH1 1 0 0 1 CH2 1 0 1 0 CH3 1 0 1 1 12 LTC1594/LTC1598 U U W U APPLICATIONS INFORMATION Operation with DIN and DOUT Tied Together Therefore the processor port line must be switched to an input with CS being low to avoid a conflict. The LTC1594/LTC1598 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the microprocessor (MPU). Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as either an input or an output. The LTC1594/ LTC1598 will take control of the data line after CS falling and before the 6th falling CLK while the processor takes control of the data line when CS is high (see Figure 3). Separate Chip Selects for MUX and ADC The LTC1594/LTC1598 provide separate chip selects, CSMUX and CSADC, to control MUX and ADC separately. This feature not only provides the flexibility to select a particular channel once for multiple conversions (see Figure 4) but also maximizes the sample rate up to 20ksps (see Figure 5). tsuCS CS 1 2 EN D2 3 4 5 6 CLK DATA (DIN/DOUT) D1 D0 B11 MPU CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1594/LTC1598 • • • B10 LTC1594/LTC1598 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO MPU PROCESSOR MUST RELEASE DATA LINE AFTER CS FALLING AND BEFORE THE 6TH FALLING CLK LTC1594/LTC1598 TAKES CONTROL OF DATA LINE AFTER CS FALLING AND BEFORE THE 6TH FALLING CLK 1594/98 F03 Figure 3. LTC1594/LTC1598 Operation with DIN and DOUT Tied Together CSMUX CSADC tsuCS tsuCS CLK EN D1 DIN DON’T CARE DOUT DON’T CARE D0 D2 D0 NULL BIT Hi-Z tSMPL B11 B10 B9 B8 B7 B6 tCONV B5 B4 B3 B2 B1 B0 Hi-Z tSMPL NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z tCONV CH0 TO CH7 tON ADCIN = MUXOUT 1594 TD01 COM = GND Figure 4. Select Certain Channel Once for Mulitple Conversions 13 LTC1594/LTC1598 U U W U APPLICATIONS INFORMATION CSADC CSMUX tsuCS tsuCS CLK EN D1 EN DIN B4 B3 B2 B1 D2 NULL BIT B0 B11 B10 B9 B8 tSMPL D1 DON’T CARE D0 D2 DOUT EN D1 DON’T CARE B7 B6 B5 B4 B3 B2 B1 D0 D2 NULL BIT B0 B11 B10 B9 tSMPL tCONV B8 B7 B6 B5 B4 B3 B2 B1 D0 B0 tCONV CH0 TO CH7 tON tON ADCIN = MUXOUT 1594/98 F05 COM = GND Figure 5. Use Separate Chip Selects to Maximize Sample Rate The MUXOUT and ADCIN pins of the LTC1594/LTC1598 form a very flexible external loop that allows Programmable Gain Amplifier (PGA) and/or processing analog input signals prior to conversion. This loop is also a cost effective way to perform the conditioning, because only one circuit is needed instead of one for each channel. In the Typical Applications section, there are a few examples illustrating how to use the MUXOUT/ADCIN loop to form a PGA and to antialias filter several analog inputs. ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 320µA and automatic shutdown between conversions, the LTC1594/LTC1598 achieve extremely low power consumption over a wide range of sample rates (see Figure 6). The auto shutdown allows the supply current to drop with reduced sample rate. Several things must be taken into account to achieve such a low power consumption. 1000 SUPPLY CURRENT (µA) MUXOUT/ADCIN Loop Economizes Signal Conditioning TA = 25°C VCC = 5V VREF = 5V fCLK = 320kHz 100 10 1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100 1594/98 F06 Figure 6. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate leaving the CLK running to clock the input data word into MUX. If the CS, DIN and CLK are not running rail-to-rail, the input logic buffers will draw currents. These currents may be large compared to the typical supply current. To obtain the lowest supply current, run the CS, DIN and CLK pins rail-to-rail. DOUT Loading Shutdown The LTC1594/LTC1598 are equipped with automatic shutdown features. They draw power when the CS pin is low. The bias circuits and comparator of the ADC powers down and the reference input becomes high impedance at the end of each conversion leaving the CLK running to clock out the LSB first data or zeroes (see Figures 1 and 2). When the CS pin is high, the ADC powers down completely 14 Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the DOUT pin can add more than 80mA to the supply current at a 320kHz clock frequency. An extra 80mA or so of current goes into charging and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The (C)(V)(f) currents must be evaluated and the troublesome ones minimized. LTC1594/LTC1598 U U W U APPLICATIONS INFORMATION BOARD LAYOUT CONSIDERATIONS SAMPLE-AND-HOLD Grounding and Bypassing Both the LTC1594/LTC1598 provide a built-in sampleand-hold (S&H) function to acquire signals through the selected channel, assuming the ADCIN and MUXOUT pins are tied together. The S & H of these parts acquire input signals through the selected channel relative to COM input during the tSMPL time (see Figure 7). The LTC1594/LTC1598 are easy to use if some care is taken. They should be used with an analog ground plane and single point grounding techniques. The GND pin should be tied directly to the ground plane. The VCC pin should be bypassed to the ground plane with a 10µF tantalum capacitor with leads as short as possible. If the power supply is clean, the LTC1594/LTC1598 can also operate with smaller 1µF or less surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. Single-Ended Inputs The sample-and-hold of the LTC1594/LTC1598 allows conversion of rapidly varying signals. The input voltage is sampled during the tSMPL time as shown in Figure 7. The sampling interval begins after tON time once the CS is pulled low and continues until the second falling CLK edge after the CS is low (see Figure 7). On this falling CLK SAMPLE tON HOLD “ANALOG” INPUT MUST SETTLE DURING THIS TIME tSMPL CSADC = CSMUX = CS tCONV CLK DIN EN D2 D1 DON‘T CARE D0 DOUT B11 1ST BIT TEST “COM” INPUT MUST SETTLE DURING THIS TIME MUXOUT = ADCIN CH0 TO CH7 COM 1594/98 F07 Figure 7. LTC1594/LTC1598 ADCIN and COM Input Settling Windows 15 LTC1594/LTC1598 U W U U APPLICATIONS INFORMATION edge, the S & H goes into hold mode and the conversion begins. The voltage on the “COM” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the conversion operation may not be performed accurately. The conversion time is 12 CLK cycles. Therefore, a change in the “COM” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “COM” input this error would be: VERROR(MAX) = VPEAK(2π)(f)(“COM”)12/fCLK Where f(“COM”) is the frequency of the “COM” input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. In most cases VERROR will not be significant. For a 60Hz signal on the “COM” input to generate a 1/4LSB error (305µV) with the converter running at CLK = 320kHz, its peak value would have to be 8.425mV. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1594/ LTC1598 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. “Analog” Input Settling The input capacitor of the LTC1594/LTC1598 is switched onto the selected channel input during the tSMPL time (see Figure 7) and samples the input signal within that time. The sample phase is at least 1 1/2 CLK cycles before conversion starts. The voltage on the “analog” input must settle completely within tSMPL. Minimizing RSOURCE+ and C1 will improve the input settling time. If a large “analog” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. During the conversion, the “analog” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “COM” input voltage settles completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE– and C2 will improve settling time. If a large “COM” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 7). Again, the “analog” and “COM” input sampling times can be extended as described above to accommodate slower op amps. Most op amps, including the LT ®1006 and LT1413 single supply op amps, can be made to settle well even with the minimum settling windows of 4.8µs (“analog” input) which occur at the maximum clock rate of 320kHz. Source Resistance The analog inputs of the LTC1594/LTC1598 look like a 20pF capacitor (CIN) in series with a 500Ω resistor (RON) and a 45Ω channel resistance as shown in Figure 8. CIN gets switched between the selected “analog” and “COM” inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time. MUX “ANALOG” R ON RSOURCE + INPUT 45Ω VIN + MUXOUT ADCIN C1 RSOURCE – LTC1594 RON LTC1598 500Ω “COM” INPUT VIN – C2 “COM” Input Settling At the end of the tSMPL, the input capacitor switches to the “COM” input and conversion starts (see Figures 1 and 7). 16 CIN 20pF Figure 8. Analog Input Equivalent Circuit 1594/98 • F08 LTC1594/LTC1598 U W U U APPLICATIONS INFORMATION Input Leakage Current Offset with Reduced VREF Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 200nA (at 85°C) flowing through a source resistance of 1.2k will cause a voltage drop of 240µV or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve Input Channel Leakage Current vs Temperature). The offset of the LTC1594/LTC1598 has a larger effect on the output code when the ADCs are operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Change in Offset vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 122µV which is 0.1LSB with a 5V reference becomes 0.5LSB with a 1V reference and 2.5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “COM” input of the LTC1594/LTC1598. REFERENCE INPUTS The reference input of the LTC1594/LTC1598 is effectively a 50k resistor from the time CS goes low to the end of the conversion. The reference input becomes a high impedance node at any other time (see Figure 9). Since the voltage on the reference input defines the voltage span of the A/D converter, the reference input should be driven by a reference with low ROUT (ex. LT1004, LT1019 and LT1021) or a voltage source with low ROUT. REF+ 1 LTC1594 LTC1598 Noise with Reduced VREF The total input referred noise of the LTC1594/LTC1598 can be reduced to approximately 400µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. ROUT VREF GND 4 1594/98 F09 Figure 9. Reference Input Equivalent Circuit Reduced Reference Operation The effective resolution of the LTC1594/LTC1598 can be increased by reducing the input span of the converters. The LTC1594/LTC1598 exhibit good linearity and gain over a wide range of reference voltages (see typical curves Change in Linearity vs Reference Voltage and Change in Gain vs Reference Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converters. The following factors must be considered when operating at low VREF values: For operation with a 5V reference, the 400µV noise is only 0.33LSB peak-to-peak. In this case, the LTC1594/LTC1598 noise will contribute virtually no uncertainty to the output code. However, for reduced references the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 2.5V reference this same 400µV noise is 0.66LSB peakto-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 1LSB. If the reference is further reduced to 1V, the 400µV noise becomes equal to 1.65LSBs and a stable code may be difficult to achieve. In this case averaging multiple readings may be necessary. This noise data was taken in a very clean setup. Any setup induced noise (noise or ripple on VCC, VREF or VIN) will add to the internal noise. The lower the reference voltage to be used the more critical it becomes to have a clean, noise free setup. 1. Offset 2. Noise 3. Conversion speed (CLK frequency) 17 LTC1594/LTC1598 U W U U APPLICATIONS INFORMATION Conversion Speed with Reduced VREF Effective Number of Bits With reduced reference voltages, the LSB step size is reduced and the LTC1594/LTC1598 internal comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum CLK frequency when low values of VREF are used. The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to S/(N + D) by the equation: The LTC1594/LTC1598 have exceptional sampling capability. Fast Fourier Transform (FFT) test techniques are used to characterize the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 10 shows a typical LTC1594/LTC1598 plot. 0 TA = 25°C VCC = VREF = 5V fIN = 5kHz fCLK = 320kHz fSMPL = 12.5kHz MAGNITUDE (dB) –20 –40 where S/(N + D) is expressed in dB. At the maximum sampling rate of 16.8kHz with a 5V supply, the LTC1594/ LTC1598 maintain above 11 ENOBs at 10kHz input frequency. Above 10kHz the ENOBs gradually decline, as shown in Figure 11, due to increasing second harmonic distortion. The noise floor remains low. EFFECTIVE NUMBER OF BITS (ENOBs) DYNAMIC PERFORMANCE ENOB = [S/(N + D) – 1.76]/6.02 12 11 74 68 10 9 62 56 8 50 7 44 6 38 5 4 3 TA = 25°C VCC = 5V fCLK = 320kHz fSMPL = 16.8kHz 2 1 0 –60 1 –80 10 100 INPUT FREQUENCY (kHz) 1000 1594/98 G10 –100 Figure 11. Effective Bits and S/(N + D) vs Input Frequency –120 –140 0 1 2 4 3 5 FREQUENCY (kHz) 6 7 1594/98 G14 Figure 10. LTC1594/LTC1598 Nonaveraged, 4096 Point FFT Plot Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio (S/N + D) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the ADC’s output. The output is band limited to frequencies above DC and below one half the sampling frequency. Figure 11 shows a typical spectral content with a 16.8kHz sampling rate. 18 Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is defined as: THD = 20log V22 + V32 + V42 + ... + VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through the Nth harmonics. The typical THD LTC1594/LTC1598 U W U U APPLICATIONS INFORMATION specification in the Dynamic Accuracy table includes the 2nd through 5th harmonics. With a 7kHz input signal, the LTC1594/LTC1598 have typical THD of 80dB with VCC = 5V. For input frequencies of 5kHz and 6kHz, the IMD of the LTC1594/LTC1598 is 73dB with a 5V supply. Intermodulation Distortion The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dBs relative to the RMS value of a full-scale input signal. If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while 3rd order IMD terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine waves are equal in magnitudes, the value (in dB) of the 2nd order IMD products can be expressed by the following formula: ( ) Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input. The full-linear bandwidth is the input frequency at which the effective bits rating of the ADC falls to 11 bits. Beyond this frequency, distortion of the sampled input signal increases. The LTC1594/LTC1598 have been designed to optimize input bandwidth, allowing the ADCs to undersample input signals with frequencies above the converters’ Nyquist Frequency. ) amplitude fa ± fb IMD fa ± fb = 20log amplitude at fa ( Peak Harmonic or Spurious Noise U TYPICAL APPLICATIONS N Microprocessor Interfaces Motorola SPI (MC68HC05) The LTC1594/LTC1598 can interface directly (without external hardware) to most popular microprocessors’ (MPU) synchronous serial formats including MICROWIRE, SPI and QSPI. If an MPU without a dedicated serial port is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1594/LTC1598. Included here is one serial interface example. The MC68HC05 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSBfirst and in 8-bit increments. The DIN word sent to the data register starts the SPI process. With three 8-bit transfers the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B7 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits B6 through B0 into the MPU. ANDing the second byte with 1FHEX clears the three most significant bits and ANDing the third byte with FEHEX clears the least significant bit. Shifting the data to the right by one bit results in a right justified word. 19 LTC1594/LTC1598 U TYPICAL APPLICATIONS N MC68HC05 CODE LDA #$52 Configuration data for serial peripheral control register (Interrupts disabled, output enabled, master, Norm = 0, Ph = 0, Clk/16) Load configuration data into location $0A (SPCR) Configuration data for I/O ports (all bits are set as outputs) Load configuration data into Port A DDR ($04) Load configuration data into Port B DDR ($05) Load configuration data into Port C DDR ($06) Put DIN word for LTC1598 into Accumulator (CH0 with respect to GND) Load DIN word into memory location $50 Bit 0 Port C ($02) goes high (CS goes high) Load DIN word at $50 into Accumulator Load DIN word into SPI data register ($0C) and start clocking data Test status of SPIF bit in SPI status register ($0B) STA $0A LDA #$FF STA STA STA LDA $04 $05 $06 #$08 STA $50 START BSET 0,$02 LDA $50 STA $0C LOOP1 TST $0B BPL LOOP1 BCLR 0,$02 LDA $0C STA $0C LOOP2 TST $0B BPL LOOP2 LDA $0C STA $0C AND #$IF STA $00 LOOP3 TST $0B BPL LOOP3 LDA $0C AND #$FE STA $01 JMP START Loop if not done with transfer to previous instruction Bit 0 Port C ($02) goes low (CS goes low) Load contents of SPI data register into Accumulator Start next SPI cycle Test status of SPIF Loop if not done Load contents of SPI data register into Accumulator Start next SPI cycle Clear 3 MSBs of first DOUT word Load Port A ($00) with MSBs Test status of SPIF Loop if not done Load contents of SPI data register into Accumulator Clear LSB of second DOUT word Load Port B ($01) with LSBs Go back to start and repeat program Data Exchange Between LTC1598 and MC68HC05 CSMUX = CSADC = CS CLK EN DIN D2 D1 DO DON‘T CARE DOUT B11 B10 MPU TRANSMIT WORD 0 MPU RECEIVED WORD ? 0 0 0 EN D2 D1 X D0 X X ? ? B8 B7 X X X X B6 X B5 B4 B3 B2 B1 B0 B1 X X X X X X X B1 B0 B1 BYTE 2 BYTE 1 ? X B9 ? ? ? ? ? ? 0 B11 B10 BYTE 3 B9 B8 B7 B6 BYTE 2 BYTE 1 B5 B4 B2 B3 BYTE 3 1594/98 TA03 Hardware and Software Interface to Motorola MC68HC05 DOUT FROM LTC1598 STORED IN MC68HC05 RAM MSB #00 0 0 0 B11 B10 B9 B8 B7 CSMUX BYTE 1 CSADC ANALOG INPUTS LSB #01 B6 B5 B4 B3 B2 B1 B0 0 BYTE 2 LTC1598 C0 MC68HC05 CLK SCK DIN MOSI DOUT MISO 1594/98 TA04 20 B2 LTC1594/LTC1598 U TYPICAL APPLICATIONS N MULTICHANNEL A/D USES A SINGLE ANTIALIASING FILTER than 1LSB of error due to offsets and bias currents. The filter’s noise and distortion are less than –72dB for a 100Hz, 2VP-P offset sine input. This circuit demonstrates how the LTC1598’s independent analog multiplexer can simplify design of a 12-bit data acquisition system. All eight channels are MUXed into a single 1kHz, 4th order Sallen-Key antialiasing filter, which is designed for single supply operation. Since the LTC1598’s data converter accepts inputs from ground to the positive supply, rail-to-rail op amps were chosen for the filter to maximize dynamic range. The LT1368 dual railto-rail op amp is designed to operate with 0.1µF load capacitors (C1 and C2). These capacitors provide frequency compensation for the amplifiers and help reduce the amplifier’s output impedance and improve supply rejection at high frequencies. The filter contributes less The combined MUX and A/D errors result in an integral nonlinearity error of ±3LSB (maximum) and a differential nonlinearity error of ±3/4LSB (maximum). The typical signal-to-noise plus distortion ratio is 71dB, with approximately –78dB of total harmonic distortion. The LTC1598 is programmed through a 4-wire serial interface that is compatable with MICROWIRE, SPI and QSPI. Maximum serial clock speed is 320kHz, which corresponds to a 16.8kHz sampling rate. The complete circuit consumes approximately 800µA from a single 5V supply. Simple Data Acquisition System Takes Advantage of the LTC1598’s MUXOUT/ADCIN Pins-to-Filter Analog Signals Prior to A/D Conversion ANALOG INPUTS 0V TO 5V RANGE 5V 1 2 3 4 5 6 7 8 9 10 11 12 CH5 CH4 CH6 CH3 CH7 CH2 GND CH1 CLK LTC1598 CH0 CSMUX DIN VCC MUXOUT COM ADCIN GND VREF CSADC DOUT NC VCC CLK NC 24 0.015µF 1µF 23 1/2 LT1368 21 20 7.5k + 22 C2 0.1µF 5V 7.5k 0.03µF – 19 18 1µF 17 7.5k 16 15 7.5k 0.015µF 14 0.03µF 13 + 1/2 LT1368 – C1 0.1µF DATA OUT DATA IN CHIP SELECT CLOCK 1594/98 TA05 21 LTC1594/LTC1598 U TYPICAL APPLICATIONS N Using MUXOUT/ADCIN Loop as PGA This figure shows the LTC1598’s MUXOUT/ADCIN loop and an LT1368 being used to create a single channel PGA with eight noninverting gains. Combined with the LTC1391, the system can expand to eight channels and eight gains for each channel. Using the LTC1594, the PGA is reduced to four gains. The output of the LT1368 drives the ADCIN and the resistor ladder. The resistors above the selected MUX channel form the feedback for the LT1368. The loop gain for this amplifier is RS1/RS2 + 1. RS1 is the summation of the resistors above the selected MUX channel and RS2 is the summation of the resistors below the selected MUX channel. If CH0 is selected, the loop gain is 1 since RS1 is 0. Table 1 shows the gain for each MUX channel. The LT1368 dual rail-to-rail op amp is designed to operate with 0.1µF load capacitors. These capacitors provide frequency compensation for the amplifiers, help reduce the amplifiers’ output impedance and improve supply rejection at high frequencies. Because the LT1368’s IB is low, the RON of the selected channel will not affect the loop gain given by the formula above. Using the MUXOUT/ADCIN Loop of the LTC1598 to Form a PGA with Eight Gains in a Noninverting Configuration 5V 1µF LTC1391 1 2 3 4 5 6 7 8 CH0 CH1 CH2 V+ 16 1µF 15 D 14 – V 13 + 12 – CH3 DOUT CH4 DIN CH5 CS CH6 CLK CH7 GND 5V 1/2 LT1368 5V 0.1µF 17 ADCIN 11 10 9 64R 20 CH0 32R 21 CH1 16R 22 CH2 8R 23 CH3 4R 24 CH4 2R 1 CH5 R 2 CH6 R 3 CH7 16 15, 19 VREF VCC CSADC CSMUX 8-CHANNEL MUX + 12-BIT SAMPLING ADC – CLK DOUT DIN LTC1598 18 MUXOUT 8 COM NC GND NC 1µF 10 6 5, 14 µP/µC 11 7 12 13 4, 9 1594/98 TA06 22 LTC1594/LTC1598 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.318 – 0.328* (8.07 – 8.33) 24 23 22 21 20 19 18 17 16 15 14 13 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.0256 (0.65) BSC 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.002 – 0.008 (0.05 – 0.21) 0.010 – 0.015 (0.25 – 0.38) G24 SSOP 0595 S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 8 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 0.406 – 1.270 7 0.050 (1.270) TYP S16 0695 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC1594/LTC1598 U TYPICAL APPLICATION Using the LTC1598 and LTC1391 as an 8-Channel Differential 12-Bit ADC System 5V 18 MUXOUT 20 CH0 21 CH1 22 CH2 23 CH3 24 CH4 1 CH5 2 CH6 16 3 CH7 15 D 14 – V 13 8 5V 1µF LTC1391 CH0 1 2 3 4 5 6 7 CH7 8 CH0 CH1 CH2 V+ CH3 DOUT CH4 DIN CH5 CS CH6 CLK CH7 GND 17 ADCIN 16 15, 19 VREF VCC 1µF 10 CSADC 6 CSMUX 8-CHANNEL MUX COM + 12-BIT SAMPLING ADC – 5, 14 CLK 7 DIN 11 DOUT LTC1598 GND NC NC 12 13 4, 9 12 11 10 9 DIN CLK CS DOUT 1594/98 TA07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1096/LTC1098 8-Pin SO, Micropower 8-Bit ADC Low Power, Small Size, Low Cost LTC1096L/LTC1098L 8-Pin SO, 2.65V Micropower 8-Bit ADC Low Power, Small Size, Low Cost LTC1196/LTC1198 8-Pin SO, 1Msps 8-Bit ADC Low Power, Small Size, Low Cost LTC1282 3V High Speed Parallel 12-Bit ADC 140ksps, Complete with VREF, CLK, Sample-and-Hold LTC1285/LTC1288 8-Pin SO, 3V, Micropower 1- or 2-Channel, Auto Shutdown LTC1286/LTC1298 8-Pin SO, 5V, Micropower 1- or 2-Channel, Auto Shutdown LTC1286 Multiplexed 12-Bit ADC 8-Channel 12-Bit Serial I/O LTC1289 Multiplexed 3V, 1A, 12-Bit ADC 8-Channel 12-Bit Serial I/O LTC1415 5V High Speed Parallel 12-Bit ADC 1.25Msps, Complete with VREF, CLK, Sample-and-Hold LTC1594L 4-Channel, 3V Micropower 12-Bit ADC Low Power, Small Size, Low Cost LTC1598L 8-Channel, 3V Micropower 12-Bit ADC Low Power, Small Size, Low Cost 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 15948f LT/GP 1296 7K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1996