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Engineering Bulletin
In-Circuit Programming of FLASH Memory Using
the Monitor Mode for the MC68HC908SR12
By Timothy J. Airaudi
Applications Engineering, Microcontroller Division
Austin, Texas
Introduction
This engineering bulletin describes how to perform in-circuit
programming (ICP) of the FLASH memory using monitor mode for the
MC68HC908SR12.
Two ICP methods are discussed here:
•
Using the M68ICS08SR in-circuit simulator (ICS) with P&E
Microcomputer Systems software
•
Using P&E Microcomputer Systems software with an external
communications circuit
ICP is a process where user code is programmed into the device’s
FLASH memory after the part has been assembled into the application.
ICP also allows the original users code to be erased and
re-programmed. This method can be used in development,
production/manufacturing, and in a field environment.
P&E is a trademark of P&E Microcomputer Systems, Inc.
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Engineering Bulletin
Using Monitor Mode for FLASH Programming
Motorola’s current solution for ICP is the in-circuit simulators and P&E’s
software.
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The software and ICS allow programming of the parts on the simulator
or in the target circuit via a MON08 ribbon cable. The software also
allows programming of the part, without the ICS, by using an external
communications circuit.
All the programming described here is accomplished by placing the part
into monitor mode. In this mode, erasing and programming are done
through a single-wire interface with the host computer.
The two ways to enter monitor mode are:
•
The ICS provides the entry requirements into standard monitor
mode. These entry requirements must be implemented on the
target board if the ICS is not used.
•
A second way to enter monitor mode, that does not require a high
voltage on the IRQ1 pin, is forced monitor mode. This mode does
not need to meet all the monitor mode entry conditions of the
standard monitor mode, but it does require the part to be blank
(erased).
This engineering bulletin describes how to connect the part,
communicate at different baud rates, place the part into monitor mode,
pass security, and erase and program the part. If the security code is not
known, the contents of the FLASH can’t be read, but the FLASH can be
erased and reprogrammed.
Information on the M68ICS08SR can be found at
http://www.motorola.com/semiconductors, the company’s Web site.
P&E Microcomputer Systems software can be downloaded free from
that company’s Web site.
NOTE:
All of the oscillators used in this engineering bulletin are the 4-pin
“powered” or “canned” type oscillators. Discussing all the different
vendors of crystals, ceramic oscillators, other required external
components, and component layout variables would be too extensive.
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Engineering Bulletin
Using Monitor Mode for FLASH Programming
ICP Using
M68ICS08SR’s
MON08 Interface
Use this procedure for performing ICP using the ICS’s MON08 cable to
the target application.
1. Materials required:
a. PC with P&E’s software installed
b. M68ICS08SR ICS
c.
Adapter/connector to connect the female end of the MON08
cable to the target application
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d. Pin assignment diagram (see Figure 1 and Figure 2)
e. Monitor mode entry requirements (see Table 1)
f.
Crystal oscillator on the target or from an external clock
source with a value from Table 2
g. Target board must have the ability to perform a power-on
reset (POR) not just a reset (required to enter monitor mode).
2. Connections (see Figure 3):
a. 9-pin serial cable from PC to the ICS
b. 5 volts to the ICS
c.
MON08 cable (even pins) from J3 of the ICS to the target
board with these connections:
– MON08 GND to the VSS pin on the part
– MON08 RST to the RST pin on the part
– MON08 IRQ to the IRQ1 pin on the part
– MON08 PTA0 to the PTA0 pin on the part
– MON08 PTA2 to the PTA2 pin on the part
– MON08 PTA1 to the PTA1 pin on the part
– MON08 PTC1 to the PTC1 pin on the part
d. It is assumed that all VDD and VSS pins on the part are already
connected.
3. Operation — Standard monitor mode entry:
a. Launch P&E’s WINIDE in the ICS08SRZ software.
b. Open desired file. (Demo file can be used for testing
purposes.)
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c.
Assemble/Compile the file (see Figure 7).
d. Plug in power to the ICS.
e. Apply power to the target.
f.
Launch the programmer.
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g. From “Target Hardware Type,” select “Class II” (see
Figure 8). If this window does not appear and the window in
Figure 9 appears instead, you should relaunch the
programmer without applying power to the target. You may
want to check the “Show this dialog before attempting to
contact the target 68HC08 board.”
h. From “PC Serial Port Configuration,” select the PC port you
are using and the appropriate baud rate (see Table 2).
i.
From “Target MCU Security Bytes,” select appropriate
security code (blank part = FF).
j.
Select “Contact Target with these Settings…”
k.
Follow the instructions in the “Power Down/Up Dialog”
windows.
l.
Select appropriate algorithm for the part. The high-speed
algorithm will not work at 14.4 and 28.8 kbaud.
m. Double click on “Erase Module” – EM (see Figure 9).
n. Double click on “Program Module” – PM.
o. Record security bytes. This information can be seen by
quitting and then re-entering the programmer. The S19 record
will have the same security bytes as the part just programmed
as long as it is not changed. The security bytes consist of the
information stored in the interrupt vectors, $FFF6–$FFFD.
4. Operation — Forced monitor mode entry:
Forced monitor mode is not supported by this ICS. However,
this mode can be entered by using the procedure found in ICP
Using the External Communications Circuit (No ICS).
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Using Monitor Mode for FLASH Programming
ICP Using
the External
Communications
Circuit (No ICS)
Use this procedure for performing ICP via an external communications
circuit in place of this ICS to the target application.
1. Materials required:
a. PC with P&E software installed
b. Adapter/connector to connect the male end of the 9-pin serial
cable to the target application
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c.
The external communications circuit. Also needed is a 5-volt
power source to power this circuit (see Figure 4, Figure 5,
and Figure 6).
d. Pin assignment diagram (see Figure 1 and Figure 2)
e. Monitor mode entry requirements (see Table 1)
f.
Crystal oscillator on the target or from an external clock
source, with a value from Table 2. If the crystal oscillator in the
target application is not a value listed in Table 2, it may be
possible to “overdrive” the target crystal with an external clock.
An example of this would be overdriving a target’s 32.768-kHz
crystal with a 9.8304-MHz external clock.
g. Target board must have the ability to perform a POR not just
a reset of the part (required to enter monitor mode).
2. Connections (see Figure 4):
a. 9-pin serial cable from PC to the external communications
circuit
b. V+ pin of the RS-232 part to the IRQ1 pin of the part
c.
Communication pin of HC125 to PTA0 of the part
d. Target pin requirements:
– PTA2 of the part to VSS
– PTA1 of the part to VDD via a pullup resistor
– PTC1 of the part to VSS (crystal frequency ÷ 2) or to VDD
via a pullup resistor (crystal frequency ÷ 4). See Table 2.
– RESET has an internal pullup resistor.
e. It is assumed that all VDD and VSS pins on the part are already
connected.
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3. Operation — Standard monitor mode entry:
a. Launch P&E’s WINIDE in the ICS08SRZ software.
b. Open desired file. (Demo file can be used for testing
purposes.)
c.
Assemble/Compile the file (see Figure 7).
d. Apply power to the external communications circuit.
e. Turn on power to the target.
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f.
Launch the programmer.
g. From “Target Hardware Type,” select “Class III” (see
Figure 8).
h. From “PC Serial Port Configuration,” select the PC port in use
and the appropriate baud rate (Table 2).
i.
From “Target MCU Security Bytes,” select appropriate
security code (blank part = FF).
j.
Select “Contact Target with these Settings…”
k.
Follow the instructions in the “Power Cycle Dialog” window.
l.
Select appropriate algorithm for the part. The high-speed
algorithm will not work at 14.4 and 28.8 kbaud.
m. Double click on “Erase Module” – EM (see Figure 9).
n. Double click on “Program Module” – PM.
o. Record security bytes. This information can be seen by
quitting and then re-entering the programmer. The S19 record
will have the same security bytes as the part just programmed
as long as it is not changed. The security bytes consist of the
information stored in the interrupt vectors, $FFF6–$FFFD.
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Using Monitor Mode for FLASH Programming
4. Operation — Forced monitor mode entry:
a. Blank part with oscillator value from Table 2 (divide-by-4
options). See Figure 5. If the crystal oscillator in the target
application is not a value listed in Table 2, it is possible to
“overdrive” the target crystal with an external clock for the
short duration of the programming sequence. An example of
this would be overdriving a target’s 32.768-kHz crystal with a
9.8304-MHz external clock.
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– Remove connection to the IRQ1 pin from V+ of the
external communications circuit.
– No connections to PTA1, PTA2, and PTC1 are necessary
in this mode.
– IRQ has an internal pullup resistor.
– Follow steps in 3. Operation — Standard Monitor Entry.
b. Blank part with a 32.768-kHz oscillator. See Figure 6.
– Connect the IRQ1 pin to VSS.
– Follow steps in 3. Operation — Standard Monitor Entry.
– Note that external components are required on the
CGMXFC pin, as the PLL will be used. Refer to the
MC68HC908SR12 Technical Data, Motorola document
order number MC68HC908SR12/D, for recommended
component values.
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PTC4/ATD9
PTC5/ATD10
PTC6/ATD11
VDDA
VSSA
NC
PTA4/ATD6
PTA3/ATD5
PTA2/ATD4
46
45
44
43
42
41
40
39
38
37 PTA1/ATD3
PTA5/ATD7
36 VREFH
VSSAM
VSS
7
30
OPIN1/ATD0
PTD1/KBI1
8
29
PTB4/T2CH0
IRQ1
9
28
PTB5/T2CH1
PTD2/KBI2
10
27
PTB6/IRQ2
RST
11
26
PTA6/T1CH0
NC: No connection
25 PTD7/KBI7
NC 24
PTB0/SDA0 13
PTD3/KBI3 12
23
31
PTA7/T1CH1
6
22
OSC2
PTC2/PWM2
PTA0/ATD2
21
32
PTC1/PWM1
5
20
OSC1
PC0/PWM0/CD
PTC7/ATD12
19
33
PTD6/KBI6
4
18
VDD
PTD5/KBI5
OPIN2/ATD1
17
34
PTD4/KBI4
3
16
PTD0/KBI0
PTB3/SCL1/RxD
VREFL
15
35
PTB2/SDA1/TxD
2
14
NC
PTB1/SCL0
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PTC3/ATD8 1
47
48 CGMXFC
Engineering Bulletin
Figure 1. 48-Pin LQFP Pin Assignments
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Engineering Bulletin
Using Monitor Mode for FLASH Programming
VDDA
1
42
VSSA
PTC5/ATD10
2
41
PTA4/ATD6
PTC4/ATD9
3
40
PTA3/ATD5
PTA5/ATD7
4
39
PTA2/ATD4
CGMXFC
5
38
PTA1/ATD3
PTC3/ATD8
6
37
VREFH
PTD0/KBI0
7
36
VREFL
VDD
8
35
PTA0/ATD2
OSC1
9
34
VSSAM
OSC2
10
33
OPIN1/ATD0
VSS
11
32
PTB4/T2CH0
PTD1/KBI1
12
31
PTB5/T2CH1
IRQ1
13
30
PTB6/IRQ2
PTD2/KBI2
14
29
PTA6/T1CH0
RST
15
28
PTD7/KBI7
PTD3/KBI3
16
27
PTA7/T1CH1
PTB0/SDA0
17
26
PTC2/PWM2
PTB1/SCL0
18
25
PTC1/PWM1
PTB2/SDA1/TxD
19
24
PC0/PWM0/CD
PTB3/SCL1/RxD
20
23
PTD6/KBI6
PTD4/KBI4
21
22
PTD5/KBI5
Pins Not Available on 42-Pin Package
Internal Connection
OPIN2/ATD1
Unconnected
PTC6/ATD11
Unconnected
PTC7/ATD12
Unconnected
Figure 2. 42-Pin SDIP Pin Assignments
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X
X
X
Blank
“$FFFF”
Blank
“$FFFF”
VDD
or
VTST
VDD
VDD
VTST
VDD
or
VTST
VTST
VDD
GND
VDD
or
GND
VDD
or
GND
X
X
0
X
X
X
X
1
1
X
PTA1
X
X
1
1
1
1
X
(1)
PTA0
X
X
X
X
1
0
X
PTC1
X
X
32.768
kHz
9.8304
MHz
9.8304
MHz
4.9152
MHz
X
External
Clock(2)
—
—
2.4576
MHz
2.4576
MHz
2.4576
MHz
2.4576
MHz
0
Bus
Frequency
NOTES:
1. PTA)=1 if serial communication; PTA) = 0 if parallel communication
2. External clock is derived by a 32.768-kHz crystal or a 4.9152/9.8304-MHz off-chip oscillator.
X
X
0
X
VDD
or
VTST
VTST
X
X
GND
X
PTA2
RST
Address
$FFFE/
$FFFF
OFF
OFF
ON
OFF
OFF
OFF
X
PLL
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
COP
Table 1. Monitor Mode Signal Requirements and Options
IRQ1
r
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—
—
9600
9600
9600
9600
0
Baud
Rate
Enters user
mode
Enters user
mode; will
encounter illegal
address reset
PLL enabled
(BCS set) in
monitor mode
External
frequency
always ÷ by 4
PTA1 and PTA2
voltages only
required if
IRQ1 = VTST;
PTC1
determines
frequency
divider
PTA1 and PTA2
voltages only
required if
IRQ1 = VTST;
PTC1
determines
frequency
divider
No operation
until reset goes
high
Comment
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Using Monitor Mode for FLASH Programming
Table 2. Crystal Frequency vs. Baud Rate
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Divide-by-2 Option (PTC1 to Development Tool or VSS)
Crystal
Frequency (MHz)
Internal Bus
Frequency (MHz)
Baud
Rate
2.4576
1.2288
4800
4.9152
2.4576
9600
7.3728
3.6864
14,400
9.8304
4.9152
19,200
14.7456
7.3728
28,800
Divide-by-4 Option (PTC1 to VDD)
4.9152
1.2288
4800
9.8304
2.4576
9600
14.7456
3.6864
14,400
19.6608
4.9152
19,200
29.4912
7.3728
28,800
PC
RS-232
ICS
2 GND
VSS
4 RST
RST
6 IRQ
IRQ1
8 NC
NC
10 PTA0
PTA0
12 PTA2
PTA2
14
PTA1
PTA1
16
PTC1
PTC1
TARGET
J3
Figure 3. MC68HC908SR12 MON08 Connections
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VDD
IRQ
VDD
RS-232
VTST
PTA0
9600 BAUD
HC125
GND
PTC1 PTA1
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PTA2
OSC1
9.8304 MHz
* OPTIONAL
Figure 4. MC68HC908SR12 Standard Monitor Mode (9.8304 MHz)
VDD
IRQ
VDD
RS-232
VDD
PTA0
9600 BAUD
HC125
GND
OSC1
9.8304 MHz
* OPTIONAL
Figure 5. MC68HC908SR12 Forced Monitor Mode (9.8304 MHz)
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Using Monitor Mode for FLASH Programming
VDD
IRQ
VDD
RS-232
GND
PTA0
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9600 BAUD
HC125
GND
Figure 6. MC68HC908SR12 Forced Monitor Mode (32.768 kHz)
Figure 7. P&E’s WINIDE Window
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Figure 8. P&E’s Target and Security Window
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Using Monitor Mode for FLASH Programming
Figure 9. P&E’s Programmer Window
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Engineering Bulletin
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