MC100EP140 3.3VECL Phase-Frequency Detector The MC100EP140 is a three state phase frequency–detector intended for phase–locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential internal gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to “compare” an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which, when subtracted and integrated, provide an error voltage for control of a VCO. Detector states of operation are shown in the Figure 2 and the State Table. The device is packaged in a small outline, surface mount 8–lead SOIC package. The typical output amplitude of the EP140 is 400 mV, allowing faster switching time and greater bandwidth. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns. More information on Phase Lock Loop operation and application can be found in AND8040. The pinout is shown in Figure 1, the logic diagram in Figure 3, and the typical termination in Figure 5. • • • • • http://onsemi.com MARKING DIAGRAM 8 SO–8 D SUFFIX CASE 751 8 1 KP140 ALYW 1 KP = MC100EP A = Assembly Location L = Wafer Lot Y = Year W = Work Week 500 ps Typical Propagation Delay Maximum Frequency > 2.1 GHz Typical Fully Differential Internally Advanced High Band Output Swing of 400 mV ORDERING INFORMATION Transfer Gain: 1.0 mV/Degree at 1.4 GHz 1.2 mV/Degree at 1.0 GHz Rise and Fall Time: 100 ps Typical Device • • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V Package Shipping MC100EP140D SO–8 98 Units/Rail MC100EP140DR2 SO–8 2500 Units/Reel with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –3.6 V • Open Input Default State Semiconductor Components Industries, LLC, 2002 September, 2002 – Rev. 5 1 Publication Order Number: MC100EP140/D MC100EP140 VCC R FB VEE 8 7 6 5 1 2 3 4 U U D D PIN DESCRIPTION PIN FUNCTION D, D Differential Down Outputs U, U Differential Up Outputs R* ECL Reference Input FB* ECL Feedback Input VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. Figure 1. 8–Lead Pinout (Top View) STATE TABLE R R 1 FB PHASE DETECTOR STATE 2 Pump Down U= L D=H 3 Pump Up U=L D=L FB R L L L L H L H 1–2 H L L L 2 L L L L 2 L L L L 2–3 H L H L 3–2 H H L L 2 L L L L C A U U C U FF A R C Reset D VEE B D Reset FB R B D PUMP UP 2–3–2 A S U L U=H D=L U Reset FB 2–1 FB A R OUTPUT PUMP DOWN 2–1–2 2 Figure 2. Phase Detector Logic Model R INPUT D FF S Reset B D B D Figure 3. Logic Diagram http://onsemi.com 2 D D MC100EP140 ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL–94 V–0 @ 0.125 in Transistor Count 457 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V –6 V VI PECL Mode In Input ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 –6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction–to–Ambient) 0 LFPM 500 LFPM 8 SOIC 8 SOIC 190 130 °C/W °C/W θJC Thermal Resistance (Junction–to–Case) std bd 8 SOIC 41 to 44 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C VI VCC VI VEE 2. Maximum Ratings are those values beyond which device damage may occur. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 55 70 85 60 74 90 63 78 93 mA VOH Output HIGH Voltage (Note 4) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 4) 1755 1880 2005 1755 1880 2005 1755 1880 2005 mV VIH Input HIGH Voltage (Single–Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single–Ended) 1355 1675 1355 1675 1355 1675 mV IIH Input HIGH Current 150 µA IIL Input LOW Current 150 0.5 150 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –0.3 V. 4. All loading with 50 to VCC–2.0 volts. http://onsemi.com 3 MC100EP140 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –3.6 V to –3.0 V (Note 5) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 55 70 85 60 74 90 63 78 93 mA Output HIGH Voltage (Note 6) –1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV VOL Output LOW Voltage (Note 6) –1545 –1420 –1295 –1545 –1420 –1295 –1545 –1420 –1295 mV VIH Input HIGH Voltage (Single–Ended) –1225 –880 –1225 –880 –1225 –880 mV VIL Input LOW Voltage (Single–Ended) –1945 –1625 –1945 –1625 –1945 –1625 mV IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. 6. All loading with 50 to VCC–2.0 volts. AC CHARACTERISTICS VCC = 0 V; VEE = –3.0 V to –3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 7) –40°C Symbol Characteristic fmax Maximum Frequency (See Figure 4 Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential tJITTER Cycle–to–Cycle Jitter (See Figure 4 Fmax/JITTER) VPP Input Voltage Swing tr tf Output Rise/Fall Times (20% – 80%) Min Typ 25°C Max Min >2 R to U, FB to D FB to U, R to D 300 400 Q, Q Typ 85°C Max Min >2 450 600 6002 800 .2 <1 400 800 1200 50 90 180 325 450 Typ >2 475 650 625 850 .2 <1 400 800 1200 60 100 200 350 500 6 500 5 400 4 300 3 ps .2 <1 ps 400 800 1200 mV 70 120 220 ps ÏÏ ÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 2 (JITTER) 100 1 0 0 400 800 1200 1600 FREQUENCY (MHz) Figure 4. Fmax/Jitter http://onsemi.com 4 2000 2400 GHz 650 900 JITTEROUT ps (RMS) VOUTpp (mV) 600 Unit 500 700 7. Measured using a 750 mV VPP pk–pk, 50% duty cycle, clock source. All loading with 50 to VCC–2.0 V. 200 Max MC100EP140 Q D Receiver Device Driver Device Q D 50 50 V TT V TT = V CC – 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices AND8040 – Phase Lock Loop Operation For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 5 MC100EP140 PACKAGE DIMENSIONS SO–8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–07 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 –X– A 8 5 0.25 (0.010) S B 1 M Y M 4 K –Y– G C N X 45 SEATING PLANE –Z– 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X S http://onsemi.com 6 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MC100EP140 Notes http://onsemi.com 7 MC100EP140 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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