MC10EP33
B4 Divider
B
The MC10EP33 is an integrated 4 divider. The differential clock
inputs and the VBB allow a differential, single–ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a 0.01µF capacitor.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power–up, the internal flip–flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
•
•
•
•
•
•
•
•
•
•
•
•
320ps Propagation Delay
3 GHz Typical Toggle Frequency
PECL mode: 3.0V to 5.5V VCC with VEE = 0V
ECL mode: 0V VCC with VEE = –3.0V to –5.5V
Internal Input Resistors: Pulldown on D, D
Q Output will default LOW with inputs open or at VEE
ESD Protection: >4KV HBM, >200V MM
VBB Output
New Differential Input Common Mode Range
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 91 devices
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8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
A
L
Y
W
HEP33
ALYW
= Assembly Location
= Wafer Lot
= Year
= Work Week
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
RESET 1
8
VCC
R
CLK
2
7
CLK, CLK
ECL Clock Inputs
Reset
ECL Asynchronous Reset
Q
B4
CLK
3
6
Q
VBB
4
5
VEE
FUNCTION
VBB
Reference Voltage Output
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative, 0 Supply
TRUTH TABLE
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
ORDERING INFORMATION
Device
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 1
1
Package
Shipping
MC10EP33D
SOIC
98 Units/Rail
MC10EP33DR2
SOIC
2500 Tape & Reel
Publication Order Number:
MC10EP33/D
MC10EP33
MAXIMUM RATINGS*
Value
Unit
VEE
Symbol
Power Supply (VCC = 0V)
Parameter
–6.0 to 0
VDC
VCC
Power Supply (VEE = 0V)
6.0 to 0
VDC
VI
Input Voltage (VCC = 0V, VI not more negative than VEE)
–6.0 to 0
VDC
VI
Input Voltage (VEE = 0V, VI not more positive than VCC)
6.0 to 0
VDC
Iout
Output Current
50
100
mA
IBB
VBB Sink/Source Current{
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
θJA
Thermal Resistance (Junction–to–Ambient)
θJC
Thermal Resistance (Junction–to–Case)
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
Continuous
Surge
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
CLK
tRR
RESET
Q
Figure 2. Timing Diagram
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2
–65 to +150
°C
190
130
°C/W
41 to 44 ± 5%
°C/W
265
°C
MC10EP33
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = –5.5V to –3.0V) (Note 4.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 1.)
18
26
34
18
26
34
18
26
34
mA
VOH
Output HIGH Voltage
(Note 2.)
–1135
–1060
–885
–1070
–945
–820
–1010
–885
–760
mV
VOL
Output LOW Voltage
(Note 2.)
–1935
–1810
–1685
–1870
–1745
–1620
–1810
–1685
–1560
mV
VIH
Input HIGH Voltage
Single Ended
–1210
–885
–1145
–820
–1085
–760
mV
VIL
Input LOW Voltage
Single Ended
–1935
–1610
–1870
–1545
–1810
–1485
mV
VBB
Output Voltage Reference
–1510
–1310
–1445
–1245
–1385
–1185
mV
0.0
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 3.)
IIH
Input HIGH Current
IIL
Input LOW Current
–1410
VEE+2.0
0.0
–1345
VEE+2.0
150
CLK
CLK
0.5
–150
0.0
–1285
VEE+2.0
150
0.5
–150
µA
0.5
–150
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating.
2. All loading with 50 ohms to VCC–2.0 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
4. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.3V, VEE = 0V) (Note 8.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 5.)
18
26
34
18
26
34
18
26
34
mA
VOH
Output HIGH Voltage
(Note 6.)
2165
2240
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage
(Note 6.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage
Single Ended
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage
Single Ended
1365
1690
1430
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
3.3
2.0
3.3
2.0
3.3
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 7.)
IIH
Input HIGH Current
IIL
Input LOW Current
1890
2.0
150
CLK
CLK
0.5
–150
1955
150
0.5
–150
0.5
–150
2015
µA
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
5. VCC = 3.3V, VEE = 0V, all other pins floating.
6. All loading with 50 ohms to VCC–2.0 volts.
7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
8. Input and output parameters vary 1:1 with VCC.
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3
MC10EP33
DC CHARACTERISTICS, PECL (VCC = 5.0V ± 0.5V, VEE = 0V) (Note 12.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 9.)
18
26
34
18
26
34
18
26
34
mA
VOH
Output HIGH Voltage
(Note 10.)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage
(Note 10.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage
Single Ended
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage
Single Ended
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
5.0
2.0
5.0
2.0
5.0
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 11.)
IIH
Input HIGH Current
IIL
Input LOW Current
3590
2.0
3655
150
CLK
CLK
0.5
–150
3715
150
0.5
–150
µA
0.5
–150
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
9. VCC = 5.0V, VEE = 0V, all other pins floating.
10. All loading with 50 ohms to VCC–2.0 volts.
11. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
12. Input and output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VCC = 0V; VEE = –3.0V to –5.5V) or (VCC = 3.0V to 5.5V; VEE = 0V)
–40°C
Min
Typ
fmax
Symbol
Maximum Toggle Frequency
(Note 13.)
Characteristic
2.5
3.0
tPLH,
tPHL
Propagation Delay to
Output Differential
225
200
300
270
tRR
Set/Reset Recovery
300
225
tSKEW
Duty Cycle Skew (Note 14.)
tPW
Minimum Pulse Width
550
480
tJITTER
Cycle–to–Cycle Jitter
VPP
Input Voltage Swing (Diff.)
CLK/Q
RESET/Q
RESET
5.0
25°C
Max
360
360
Min
Typ
2.5
3.0
250
250
320
320
300
225
550
480
20
5.0
TBD
150
800
85°C
Max
380
380
Min
Typ
2.5
3.0
275
275
350
350
300
225
550
480
ps
TBD
ps
20
5.0
TBD
1200
150
800
1200
150
800
Max
Unit
GHz
425
425
ps
ps
20
1200
ps
mV
tr
Output Rise/Fall Times
Q, Q
90
170
200
100
180
250
120
200
280
ps
tf
(20% – 80%)
13. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
14. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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MC10EP33
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–06
ISSUE T
D
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
B
e
X 45 _
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
q
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5
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
MC10EP33
Notes
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MC10EP33
Notes
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7
MC10EP33
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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8
MC10EP33/D