19-0075; Rev. 5; 7/95 Microprocessor Supervisory Circuit ________________________Applications Computers Critical µP Power Monitoring Controllers Intelligent Instruments Portable/Battery-Powered Equipment ____________________________Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Precision 4.65V Voltage Monitoring 200ms Power-OK / Reset Time Delay Independent Watchdog Timer—Preset or Adjustable 1µA Standby Current Power Switching 250mA Output in VCC Mode 25mA Output in Battery-Backup Mode On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 6ns CE Gate Propagation Delay MaxCap or SuperCap Compatible Voltage Monitor for Power-Fail or Low-Battery Warning Backup-Battery Monitor –————– Guaranteed RESET Valid to VCC = 1V ‰ ______________Ordering Information PART TEMP. RANGE VBATT 1 16 WDPO VOUT 2 15 RESET VCC 3 14 WDO GND 4 MAX791 BATT ON 5 0°C to +70°C 16 Plastic DIP MAX791CSE MAX791C/D MAX791EPE 0°C to +70°C 0°C to +70°C -40°C to +85°C 16 Narrow SO Dice* 16 Plastic DIP MAX791ESE MAX791EJE MAX791MJE -40°C to +85°C -40°C to +85°C -55°C to +125°C 16 Narrow SO 16 CERDIP 16 CERDIP * Dice are specified at TA = +25°C. __________Typical Operating Circuit +5V 0.47F* OTHER SYSTEM RESET SOURCES BATT ON SWT VOUT CE IN +12V ADDRESS DECODE PFI MAX791 13 CE IN 9 DIP/SO VBATT CE OUT +12V SUPPLY FAILURE 10 LOWLINE SWT 8 VCC MR 11 WDI PFI 7 CMOS RAM 0.1µF 0.1µF 12 CE OUT PFO 6 PIN-PACKAGE MAX791CPE __________________Pin Configuration TOP VIEW ‰ WDI PFO LOWLINE GND RESET WDO A0–A15 µP I/O NMI RESET INT MR *MaxCap MaxCap is a registered trademark of The Carborundum Corp. SuperCap is a registered trademark of Baknor Industries. ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MAX791 _____________________General Description The MAX791 microprocessor (µP) supervisory circuit reduces the complexity and number of components needed to monitor power-supply and battery-control functions in µP systems. The 50µA supply current makes the MAX791 ideal for use in portable equipment, while the 6ns chip-enable propagation delay and 250mA output capability (25mA in battery-backup mode) make it suitable for larger, higher-performance equipment. The MAX791 comes in 16-pin DIP and narrow SO packages and provides the following functions: –————– 1) µP reset—RESET output is asserted during power-up, power-down, and brownout conditions, and is guaranteed to be in the correct state for VCC down to 1V, even with no battery in the circuit. 2) Manual-reset input. 3) A 1.25V threshold detector provides for power-fail warning and low-battery detection, or monitors a power supply other than +5V. 4) Two-stage power-fail warning—a separate low-line comparator compares V CC to a threshold 150mV above the reset threshold. 5) Backup-battery switchover for CMOS RAM, real-time clocks, µPs, or other low-power logic. 6) Software monitoring of backup-battery voltage. 7) A watchdog-fault output is asserted if the watchdog input has not been toggled within either a preset or an adjustable timeout period. 8) Write protection of CMOS RAM or EEPROM. 9) Pulsed watchdog –——– output, to give advance warning of impending WDO assertion caused by watchdog timeout. MAX791 Microprocessor Supervisory Circuit ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW Narrow SO (derate 8.70mW/°C above +70°C) ............696mW CERDIP (derate 10.00mW/°C above +70°C) ...............800mW Operating Temperature Ranges MAX791C_ _ ......................................................O°C to +70°C MAX791E_ _ ....................................................-40°C to +85°C MAX791MJE ..................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Input Voltage (with respect to GND) VCC .......................................................................-0.3V to +6V VBATT..................................................................-0.3V to + 6V All Other Inputs.....................................-0.3V to (VOUT + 0.3V) Input Current VCC Peak ..........................................................................1.0A VCC Continuous ............................................................250mA VBATT Peak ..................................................................250mA VBATT Continuous ..........................................................25mA GND, BATT ON .............................................................100mA All Other Outputs ............................................................25mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 4.75V to 5.5V, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONDITIONS MIN Operating Voltage Range VCC, VBATT (Note 1) 0 IOUT = 25mA VOUT in Normal Operating Mode VCC = 4.5V IOUT = 250mA VCC = 4.5V VCC - 0.3 MAX791M VCC - 0.40 UNITS 5.5 V VCC - 0.2 VCC - 0.2 V VCC - 0.12 MAX791C/E 0.8 1.2 MAX791M 0.8 1.6 1.2 2.0 VCC = 3V VOUT in Battery-Backup Mode MAX VCC - 0.05 VCC - 0.02 MAX791C/E VCC = 3V, VBATT = 2.8V, IOUT = 100mA VCC-to-VOUT On-Resistance TYP VBATT = 4.5V, IOUT = 20mA VBATT - 0.3 VBATT = 2.8V, IOUT = 10mA VBATT - 0.25 VBATT = 2.0V, IOUT = 5mA VBATT - 0.15 V VBATT = 4.5V 8 15 VBATT = 2.8V 13 25 VBATT = 2.0V 17 30 Supply Current in Normal Operating Mode (Excludes IOUT) VCC > VBATT - 1V 50 150 Supply Current in Battery-Backup Mode (Excludes IOUT) (Note 2) VCC < VBATT - 1.2V, VBATT = 2.8V TA = +25°C VBATT Standby Current (Note 3) VBATT + 0.2V ≤ VCC TA = +25°C -0.1 0.02 TA = TMIN to TMAX -1.0 0.02 VBATT-to-VOUT On-Resistance Battery-Switchover Threshold Ω 0.04 TA = TMIN to TMAX 1 5 Power up VBATT + 0.03 Power down VBATT - 0.03 Ω µA µA µA V Battery-Switchover Hysteresis 60 mV Low-Battery Detector Threshold 2 V 2 _______________________________________________________________________________________ Microprocessor Supervisory Circuit MAX791 ELECTRICAL CHARACTERISTICS (continued) (VCC = 4.75V to 5.5V, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER BATT ON Output Low Voltage BATT ON Output Short-Circuit Current TYP MAX ISINK = 3.2mA CONDITIONS 0.1 0.4 ISINK = 25mA 0.7 1.5 Sink current Source current RESET, LOW-LINE AND WATCHDOG TIMER –————– RESET Threshold Voltage –————– RESET Threshold Hysteresis –———— ——– –————– LOW LINE -to-RESET Threshold Voltage –————– VCC-to-RESET Delay Power down –———— ——– VCC-to-LOW LINE Delay Power down –————– RESET Active Timeout Period Power up Watchdog Timeout Period SWT connected to VOUT Minimum Watchdog Timeout Period 4.7nF capacitor connected from SWT to GND Minimum Watchdog Input Pulse Width –———– WDPO Pulse Width –———– –——– WDPO -to-WDO Delay –————– RESET Output Voltage –————– RESET Output Short-Circuit Current MIN VIL = 0.8V, VIH = 0.75 x VCC 60 mA 15 100 µA 4.50 4.65 4.75 V 15 mV 150 mV 100 µs 80 µs 140 200 280 ms 1.0 1.6 2.25 sec 10 ms 100 ns ms 70 ns MAX791C, ISINK = 50µA, VCC = 1.0V, VCC falling 0.004 0.3 MAX791E/M, ISINK = 50µA, VCC = 1.2V, VCC falling 0.004 0.3 0.1 0.4 7 20 ISINK = 3.2mA, VCC = 4.25V ISINK = 3.2mA, VCC = 4.25V –———— ——– LOW LINE Output Short-Circuit Current Output source current ISOURCE = 1µA, VCC = 5V –——– WDO Output Voltage ISINK = 3.2mA –——– WDO Output Short-Circuit Current Output source current –———– WDPO Output Voltage ISINK = 3.2mA –———– WDPO Output Short-Circuit Current Output source current ISOURCE = 500µA, VCC = 5V ISOURCE = 1mA ns V 3.5 Output source current –———— ——– LOW LINE Output Voltage V 1 1 ISOURCE = 1.6mA, VCC = 5V UNITS 0.4 3.5 15 100 0.4 3.5 3 10 0.4 3.5 7 20 mA V µA V mA V mA _______________________________________________________________________________________ 3 MAX791 Microprocessor Supervisory Circuit ELECTRICAL CHARACTERISTICS (continued) (VCC = 4.75V to 5.5V, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER WDI Threshold Voltage (Note 4) WDI Input Current CONDITIONS VIH MIN TYP VIL WDI = 0V MAX UNITS 0.75 x VCC V 0.8 -50 WDI = VOUT -10 µA 20 50 1.25 1.30 V ±0.01 ±25 nA POWER-FAIL COMPARATOR PFI Input Threshold VCC = 5V 1.20 PFI Leakage Current –——– PFO Output Voltage ISINK = 3.2mA –——– PFO Short-Circuit Current Output sink current –——– PFI-to-PFO Delay VIN = -20mV, VOD = 15mV 15 VIN = 20mV, VOD = 15mV 55 CHIP-ENABLE GATING –—– CE IN Leakage Current –—– –—– CE IN-to-CE OUT Resistance (Note 5) –—– CE OUT Short-Circuit Current (Reset Active) –—– —– CE IN-to-CE OUT Propagation Delay (Note 6) –—– CE OUT Output Voltage High (Reset Active) –————– –—– RESET-to-CE OUT Delay MANUAL RESET INPUT –—– MR Minimum Pulse Width –————– –—– MR -to -RESET Propagation Delay –—– MR Threshold –—– MR Pull-Up Current ISOURCE = 1µA, VCC = 5V Output source current 0.4 V 3.5 60 1 15 mA 100 µA µs Disabled mode ±0.005 ±1 µA Enabled mode 75 150 Ω 0.75 2.0 mA 6 10 ns –—– Disabled mode, CE OUT = 0V 0.1 50Ω source impedance driver, CLOAD = 50pF VCC = 5V, IOUT = -100µA 3.5 VCC = 0V, VBATT = 2.8V, IOUT = 1µA 2.7 Power down 25 VCC = 5V –—– MR = 0V V 15 µs 15 µs 7 µs 1.25 V 23 250 µA Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V. Note 2: The supply current drawn by the MAX791 from the battery (excluding IOUT) typically goes to 10µA when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region. Note 3: "+" = battery-discharging current, "-" = battery-charging current. Note 4: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function. Note 5: The chip-enable resistance is tested with VCC = 4.75V V –C—E– IN = V C—E– OUT = VCC / 2. –—– –—– Note 6: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. 4 _______________________________________________________________________________________ Microprocessor Supervisory Circuit 50 46 42 38 1.5 1 0.5 0 30 60 90 120 150 -60 -30 VBATT-to-VOUT ON-RESISTANCE vs. TEMPERATURE 10 VBATT = 4.5V 60 120 -60 150 0 30 60 90 90 120 150 180 1.50 1.25 1.0 0.9 0.8 0.7 1.00 0.75 0.50 VCC = +5V, VBATT = 0V, NO LOAD ON PFO 0.25 VCC = +5V, VBATT = 0V 0 -60 -30 0 30 60 90 120 -60 150 -30 0 30 60 90 TEMPERATURE (°C) TEMPERATURE (°C) RESET THRESHOLD vs. TEMPERATURE RESET OUTPUT RESISTANCE vs. TEMPERATURE RESET DELAY vs. TEMPERATURE 4.65 4.60 4.55 4.50 4.45 4.40 VBATT = 0V, POWER DOWN 4.35 500 VCC = +5V, VBATT = 2.8V SOURCING CURRENT 300 200 VCC = 0V, VBATT = 2.8V SINKING CURRENT 100 0 30 60 90 TEMPERATURE (°C) 120 150 120 150 210 200 190 180 0 4.30 150 VCC = 0V TO 5V STEP VBATT = 2.8V 220 400 120 230 RESET DELAY (ms) 4.70 600 MAX791-08 MAX791-07 4.80 -30 60 TEMPERATURE (°C) 4.75 -60 30 0 PFI THRESHOLD vs. TEMPERATURE 1.1 150 120 RESET OUTPUT RESISTANCE (Ω) -30 -30 VCC-to-VOUT ON-RESISTANCE vs. TEMPERATURE 0.6 -60 60 TEMPERATURE (°C) VCC = 0V 5 90 PFI THRESHOLD (V) VBATT = 2.8V 30 MAX791-05 MAX791-04 15 0 1.2 VCC-to-VOUT ON-RESISTANCE (Ω) VBATT-to-VOUT ON-RESISTANCE (Ω) VBATT = 2.0V 80 TEMPERATURE (°C) TEMPERATURE (°C) 20 100 MAX791-09 -30 VCC = +4.75V VBATT = 2.8V CE IN = VCC/2 40 0 -60 RESET THRESHOLD (V) 120 MAX791-02 VCC = 0V VBATT = 2.8V NO LOAD MAX791-05 54 2 CE ON-RESISTANCE (Ω) MAX791-01 VCC = +5V VBATT = 2.8V PFI, CE IN = 0V BATTERY SUPPLY CURRENT (µA) VCC SUPPLY CURRENT (µA) 58 CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE BATTERY SUPPLY CURRENT vs. TEMPERATURE (BATTERY-BACKUP MODE) MAX791-03 VCC SUPPLY CURRENT vs. TEMPERATURE (NORMAL OPERATING MODE) 170 -60 -30 0 30 60 90 TEMPERATURE (°C) 120 150 -60 -30 0 30 60 90 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX791 __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE WATCHDOG TIMEOUT vs. TIMING CAPACITOR 12 8 4 0 PROPAGATION DELAY (ns) 200 150 100 50 1 2 3 4 5 VCC to VOUT vs. OUTPUT CURRENT 8 VCC = +5V CE IN = 0V TO 5V DRIVER SOURCE IMPEDENCE = 50Ω 0 SLOPE = 0.8Ω 10 MAX791-14 100 SLOPE = 8Ω 10 VCC = 0V VBATT = 4.5V 1 100 IOUT (mA) 6 150 CLOAD (pF) VCC = 4.5V VBATT = 0V 10 100 1000 VBATT - VOUT (mV) MAX791-13 100 1 50 VBATT to VOUT vs. OUTPUT CURRENT 1000 VCC - VOUT (mV) 12 0 0 10 20 30 40 50 60 70 80 90 100 TIMING CAPACITOR (nF) VCC (V) 16 4 0 0 MAX791-12 VCC = +5V VBATT = 2.8V WATCHDOG TIMEOUT (ms) 16 20 MAX791-11 VBATT = 2.8V, IOUT = 0A CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE 250 MAX791-10 20 IBATT (µA) MAX791 Microprocessor Supervisory Circuit 1000 1 1 10 IOUT (mA) _______________________________________________________________________________________ 100 200 250 300 Microprocessor Supervisory Circuit PIN NAME 1 VBATT FUNCTION 2 VOUT Output Supply Voltage. VOUT connects to VCC when VCC is greater than VBATT and VCC is above the reset threshold. When VCC falls below VBATT and VCC is below the reset threshold, VOUT connects to VBATT. Connect a 0.1µF capacitor from VOUT to GND. Backup-Battery Input. Connect to external battery or capacitor and charging circuit. 3 VCC Input Supply Voltage—+5V input 4 GND Ground. 0V reference for all signals 5 BATT ON 6 –——– PFO 7 PFI 8 SWT Set Watchdog-Timeout Input. Connect this input to VOUT to select the default 1.6sec watchdog timeout period. Connect a capacitor between this input and GND to select another watchdog-timeout period. Watchdog-timeout period = 2.1 x (capacitor value in nF) ms. 9 –—– MR Manual-Reset tied to an external momentary pushbutton switch, or to a logic gate out–————– Input. This input can –be —– –—– put. RESET remains low as long as MR is held low and for 200ms after MR returns high. 10 –———— ——– LOW LINE Battery On Output. Goes high when VOUT switches to VBATT. Goes low when VOUT switches to VCC. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current requirements greater than 250mA. –——– Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry. Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, –——– PFO goes low. Connect PFI to GND or VOUT when not used. –———— ——– LOW LINE Output goes low when VCC falls to 150mV above the reset threshold. The output can be used to generate an NMI if the unregulated supply is inaccessible. Watchdog Input. input. If WDI remains either high or low for longer than the watchdog time–——– WDI is a three-level –——– out period, WDO goes low. WDO remains low until the next transition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between VOUT and GND, which sets it to midsupply when left unconnected. –—– –—– –—– Chip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE IN is –—– –—– low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs first. 11 WDI 12 –—– CE OUT 13 –—– CE IN 14 –——– WDO 15 –————– RESET –————– –————– RESET Output goes low whenever VCC falls below the reset threshold. RESET will remain low for typically 200ms after VCC crosses the reset threshold on power-up. 16 –———– WDPO –———– Output. –Watchdog-Pulse ———– –——– Upon the absence of a transition at WDI, WDPO will pulse low for a minimum of 1ms. WDPO precedes WDO by 70ns. Chip-Enable Input. The input to chip-enable gating circuit. Connect to GND or VOUT if not used. –——– Watchdog Output. WDO goes low if WDI remains either timeout period. –——– –— —– high or low longer than the watchdog –—— – WDO returns –————– high on the next transition at WDI. WDO remains high if WDI is unconnected. WDO is also high when RESET is asserted. _______________________________________________________________________________________ 7 MAX791 ______________________________________________________________Pin Description MAX791 Microprocessor Supervisory Circuit 25µs MIN MR 10 150mV LOWLINE 4.65V 7.5µs TYP 5 VCC RESET BATT ON 3 2 VOUT 1 CE IN 0V CE OUT VBATT 15µs TYP CHIP-ENABLE OUTPUT CONTROL Figure 2. Manual-Reset Timing Diagram 13 12 CE OUT CE IN V OUT MR 9 RESET GENERATION 15 RESET 8 TIMEBASE FOR RESET AND WATCHDOG 16 WDPO 11 WATCHDOG TRANSITION DETECTOR MANUAL RESET MR SWT WDI PFI 7 * WATCHDOG TIMER 14 6 WDO MAX791 * PFO * DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS 1.25V MAX791 4 GND Figure 3. Diode "OR" connections allow multiple reset sources –—– to connect to MR. Figure 1. Block Diagram _______________Detailed Description Manual Reset Input Many µP-based products require manual-reset capability, allowing the operator or test technician to initiate a reset. The Manual Reset Input (MR) can be connected directly to a switch, without an external pull-up resistor or debouncing network. It connects to a 1.25V comparator, and has a pull-up to VOUT as shown in Figure 1. The propagation delay from asserting MR to RESET asserted is 4µs typical. Pulsing MR low for a minimum of 15µs resets all the internal counters, sets the Watchdog Output (WDO) and Watchdog-Pulse Output 8 OTHER RESET SOURCES (WDPO) high, and sets the Set Watchdog-Timeout (SWT) input to VOUT - 0.6V, if it is not already connected to VOUT (for internal timeouts). It also disables the chip-enable function, setting the Chip-Enable Output (CE OUT) to a high state. The RESET output remains active as long as MR is held low, and the reset-timeout period begins after MR returns high (Figure 2). Use this input as either a digital-logic input or a second low-line comparator. Normal TTL/CMOS levels can be wire-OR connected via pull-down diodes (Figure 3), and open-drain/collector outputs can be wire-ORed directly. _______________________________________________________________________________________ Microprocessor Supervisory Circuit MAX791 100ns MIN 1.6sec RESET MAX791 15 TO µP RESET WDI 10k WDPO 70ns WDO –Figure ————– 4. Adding an external pull-down resistor ensures RESET is valid with VCC down to GND. –——– –———– Figure 5. WDI, WDO and WDPO Timing Diagram (VCC mode) RESET Output Watchdog Function The MAX791’s RESET output ensures that the µP powers up in a known state, and prevents code-execution errors during power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources 1.6mA at typically VOUT - 0.5V. When no backup battery is used, RESET output is guaranteed to be valid down to VCC = 1V, and an external 10kΩ pull-down resistor on RESET ensures that RESET will be valid with VCC down to GND (Figure 4). As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the rDS(ON) and the saturation voltage. The 10kΩ pull-down resistor ensures the parallel combination of switch plus resistor is around 10kΩ and the output saturation voltage is below 0.4V while sinking 40µA. When using a 10kΩ external pull-down resistor, the high state for the RESET output with VCC = 4.75V is 4.5V typical. For battery voltages ≥ 2V connected to VBATT, RESET remains valid for VCC from 0V to 5.5V. RESET will be asserted during the following conditions: 1) VCC < 4.65V (typ) 2) MR < 1.25V (typ) 3) RESET remains asserted for 200ms (typ) after VCC rises above 4.65V or after MR has exceeded 1.25V. The MAX791 battery-switchover comparator does not affect RESET assertion. However, RESET is asserted in battery-backup mode since VCC must be below the reset threshold to enter this mode. The watchdog monitors µP activity via the Watchdog Input (WDI). If the µP becomes inactive, WDO and WDPO are asserted. To use the watchdog function, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6sec nominal), WDPO and WDO are asserted, indicating a software fault condition (see Watchdog Output and Watchdog-Pulse Output sections). Watchdog Input A change of state (high to low, low to high, or a minimum 100ns pulse) at WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is 1.6sec. Select alternative timeout periods by connecting an external capacitor from SWT to GND (see Selecting an Alternative Watchdog Timeout section). To disable the watchdog function, leave WDI floating. An internal resistor network (100kΩ equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When VCC is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance. Watchdog Output WDO remains high if there is a transition or pulse at WDI during the watchdog-timeout period. The watchdog function is disabled and WDO is a logic high when VCC is below the reset threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watch- _______________________________________________________________________________________ 9 MAX791 Microprocessor Supervisory Circuit +5V 3 VCC 1 VOUT VBATT 3.6V 2 µP POWER 0.1µF µP MAX791 15 RESET 11 WDI 10 LOWLINE WDPO 16 RESET I/O 9 MR WDO 14 GND 4 *1µF +5V NMI INTERRUPT 1/6 74HC04 5 3 14 VCC CLOCK CD4013 D SET 6 RESET VSS 7 4 Q 1 Q 2 TWO CONSECUTIVE WATCHDOG FAULT INDICATIONS REACTIVATE 4.7k *SETS Q HIGH ON POWER-UP Figure 6. Two consecutive watchdog faults latch the system in reset. dog-timeout period, WDO goes low 70ns after the falling edge of WDPO and remains low until the next transition at WDI (Figure 5). A flip-flop can force the system into a hardware shutdown if there are two successive watchdog faults (Figure 6). WDO has a 2 x TTL output characteristic. Watchdog-Pulse Output As described in the preceding section, WDPO can be used as the clock input to an external D flip-flop. Upon the absence of a watchdog edge or pulse at WDI at the end of a watchdog-timeout period, WDPO will pulse low for 1ms. The falling edge of WDPO precedes WDO by 70ns. Since WDO is high when WDPO goes low, the flip-flop’s Q output remains high as WDO goes low (Figure 5). If the watchdog timer is not reset by a transition at WDI, WDO remains low and WDPO clocks a logic low to the Q output, causing the MAX791 to latch in reset. If the watchdog timer is reset by a transition at WDI, WDO goes high and the flip-flop’s Q output remains high. Thus, a system shutdown is only caused by two successive watchdog faults. The internal pull-up resistors associated with WDO and WDPO connect to VOUT. Therefore, do not connect these outputs directly to CMOS logic that is powered from VCC since, in the absence of VCC (i.e., battery 10 mode), excessive current will flow from WDO or WDPO through the protection diode(s) of the CMOSlogic inputs to ground. Selecting an Alternative Watchdog Timeout Period SWT input controls the watchdog-timeout period. Connecting SWT to VOUT selects the internal 1.6sec watchdog-timeout period. Select an alternative timeout period by connecting a capacitor between SWT and GND. Do not leave SWT floating, and do not connect it to ground. The following formula determines the watchdog-timeout period: Watchdog Timeout Period = 2.1 x (capacitor value in nF) ms This formula is valid for capacitance values between 4.7nF and 100nF (see the Watchdog Timeout vs. Timing Capacitor graph in the Typical Operating Characteristics ). SWT is internally connected to a ±100nA (typ) current source, which charges and discharges the timing capacitor to create the oscillator frequency that sets the watchdog timeout period (see Connecting a Timing Capacitor to SWT in the Applications Information section). ______________________________________________________________________________________ Microprocessor Supervisory Circuit MAX791 +5V VCC RESET THRESHOLD VCC CE IN MAX791 CE OUT 15µs 100µs CE IN CE OUT 100µs CLOAD 50Ω DRIVER RESET GND RESET Figure 7. Reset and Chip-Enable Timing Chip-Enable Signal Gating The MAX791 provides internal gating of chip-enable (CE) signals, to prevent erroneous data from corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The MAX791 uses a series transmission gate from the Chip-Enable Input (CE IN) to CE OUT (Figure 1). The 10ns max CE propagation from CE IN to CE OUT enables the MAX791 to be used with most µPs. Chip-Enable Input CE IN is high impedance (disabled mode) while RESET is asserted. During a power-down sequence were VCC passes 4.65V, CE IN assumes a high-impedance state when the voltage at CE IN goes high or 15µs after reset is asserted, whichever occurs first (Figure 7). During a power-up sequence, CE IN remains high impedance, regardless of CE IN activity, until reset is deasserted following the reset-timeout period. In the high-impedance mode, the leakage currents into this input are ±1µA max over temperature. In the lowimpedance mode, the impedance of CE IN appears as a 75Ω resistor in series with the load at CE OUT. Figure 8. CE Propagation Delay Test Circuit The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CE IN and the capacitive loading on CE OUT (see the Chip-Enable Propagation Delay vs. CE OUT Load Capacitance graph in the Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50% point on CE OUT using a 50Ω driver and 50pF of load capacitance (Figure 8). For minimum propagation delay, minimize the capacitive load at CE OUT and use a low output-impedance driver. Chip-Enable Output In the enabled mode, the impedance of CE OUT is equivalent to 75Ω in series with the source driving CE IN. In the disabled mode, the 75Ω transmission gate is off and CE OUT is actively pulled to VOUT. This source turns off when the transmission gate is enabled. LOWLINE Output The low-line comparator monitors VCC with a typical threshold voltage 150mV above the reset threshold, and has 15mV of hysteresis. LOWLINE typically sinks 3.2mA at 0.1V. For normal operation (VCC above the LOWLINE threshold), LOWLINE is pulled to VOUT. If access to the unregulated supply is unavailable, use LOWLINE to provide a nonmaskable interrupt (NMI) to the µP as VCC begins to fall (Figure 9a). ______________________________________________________________________________________ 11 MAX791 Microprocessor Supervisory Circuit FROM REGULATED SUPPLY 3 V CC VOUT 2 0.1µF 0.1µF µP POWER POWER TO CMOS RAM MAX791 VBATT 1 µP 3.0V 15 RESET LOWLINE 10 11 WDI GND 4 a) VOLTAGE REGULATOR 3 V CC 0.1 µF RESET NMI I/O LINE VOUT 2 0.1µF MAX791 VBATT 1 3.0V 7 15 RESET PFO 6 11 WDI PFI Table 1. Input and Output States in Battery-Backup Mode µP POWER POWER TO CMOS RAM µP RESET NMI I/O LINE GND 4 b) Figure 9. a) If the unregulated supply is inaccessible, LOWLINE generates the NMI for the µP. b) Use PFO to generate the µP NMI if the unregulated supply is inaccessible. Power-Fail Comparator The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the IC. Common uses include monitoring supplies other than 5V (see the Typical Operating Circuit and the Monitoring a Negative Voltage section) and early power-fail detection when the unregulated power is easily accessible (Figure 9b). Power-Fail Input PFI is the input to the power-fail comparator. PFI has a guaranteed input leakage of ±25nA max over temperature. The typical comparator delay is 15µs from VIL to VOL (power failing), and 55µs from VIH to VOH (power being restored). If unused, connect this input to ground. 12 PIN NAME 1 VBATT 2 VOUT VOUT is connected to VBATT through an internal PMOS switch. 3 VCC Battery-switchover comparator monitors VCC for active switchover. 4 GND GND—0V reference for all signals. 5 BATT ON Logic high. The open-circuit output is equal to VOUT. 6 –——– PFO The power-fail comparator remains active in the battery-backup mode for VCC ≥ VBATT –——– - 1.2V typ. Below this voltage, PFO is forced low. 7 PFI The power-fail comparator remains active in the battery-backup mode for VCC ≥ VBATT - 1.2V typ. 8 10 SWT –—– MR –———— ——– LOWLINE 11 WDI 12 –—– CE OUT 13 –—– CE IN High impedance 14 –——– WDO Logic high. The open-circuit output voltage is equal to VOUT. 15 –————– RESET Logic low* 16 –———– WDPO Logic high. The open-circuit output voltage is equal to VOUT. 9 STATUS Supply current is 1µA maximum. SWT is ignored. –—– MR is ignored. Logic low* WDI is ignored, and goes high impedance. Logic high. The open-circuit output voltage is equal to VOUT. * V CC must be below the reset threshold to enter batterybackup mode. Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFI above 1.25V, PFO is actively pulled to V OUT . Connecting PFI through a voltage divider to an unregulated supply allows PFO to generate an NMI as the unregulated power begins to fall (Figure 9b). If the unregulated supply is inaccessible, use LOWLINE to generate the NMI. The LOWLINE threshold is typically 150mV above the reset threshold (see LOWLINE Output section). ______________________________________________________________________________________ Microprocessor Supervisory Circuit MAX791 RESET THRESHOLD VBATT 1 VCC 2 VOUT 200ms TYP RESET 0.1µF VCC CE IN 3 CE OUT MAX791 SECOND CE PULSE ABSENT WHEN VBATT < 2V Figure 10. VCC and VBATT-to-VOUT Switch Figure 11. Backup-Battery Monitor Timing Diagram Battery-Backup Mode Backup-Battery Input The MAX791 requires two conditions to switch to battery-backup mode: 1) VCC must be below the reset threshold; 2) VCC must be below VBATT. Table 1 lists the status of the inputs and outputs in battery-backup mode. The Backup-Battery Input (VBATT) is similar to VCC, except the PMOS switch and parallel diode are much smaller. Accordingly, the on-resistances of the diode and the switch are each approximately 10Ω. Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1µA over temperature and supply voltage. Battery On Output The Battery On (BATT ON) output indicates the status of the internal V CC /battery-switchover comparator, which controls the internal VCC and VBATT switches. For VCC greater that VBATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0.1V saturation voltage. In battery-backup mode, this terminal sources approximately 10µA from VOUT. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications (see Typical Operating Circuit). Input Supply Voltage Output Supply Voltage The Output Supply Voltage (VOUT) is internally connected to the substrate of the IC and supplies all the current to the external system and internal circuitry. All opencircuit outputs will, for example, assume the VOUT voltage in their high states rather than the VCC voltage. At the maximum source current of 250mA, VOUT will typically be 200mV below VCC. Decouple this terminal with a 0.1µF capacitor. The Input Supply Voltage (VCC) should be a regulated +5V. VCC connects to VOUT via a parallel diode and a large PMOS switch. The switch carries the entire current load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than 1Ω each (Figure 10). The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A. ______________________________________________________________________________________ 13 MAX791 Microprocessor Supervisory Circuit Rp* CE RAM 1 +5V CE IN VCC 1N4148 CE VOUT 3 CE OUT CE RAM 2 CE 1 VBATT VOUT 2 CE RAM 3 0.47F CE MAX791 MAX791 CE GND RAM 4 CE GND 4 *MAXIMUM Rp VALUE DEPENDS ON THE NUMBER OF RAMS. MINIMUM Rp VALUE IS 1kΩ ACTIVE-HIGH CE LINES FROM LOGIC Figure 12. SuperCap or MaxCap on VBATT Figure 13. Alternate CE Gating Low-Battery Monitor __________Applications Information The MAX791 low-battery voltage function monitors VBATT. Low-battery detection of 2.0V ±0.15V is monitored only during the reset-timeout period (200ms) that occurs either after a normal power-up sequence or after the MR reset input has been returned to its high state. If the battery voltage is below 2.0V, the second CE pulse is inhibited after reset timeout. If the battery voltage is above 2.0V, all CE pulses are allowed through the CE gate after the reset timeout period. To use this function, after the 200ms reset delay, write 00 (HEX) to a location using the first CE pulse, and write FF (HEX) to the same location using the second CE pulse following RESET going inactive on power-up. The contents of the memory then indicates a good battery (FF) or a low battery (00) (Figure 11). The MAX791 is not short-circuit protected. Shorting VOUT to ground, other than power-up transients such as charging a decoupling capacitor, destroys the device. All open-circuit outputs swing between VOUT and GND rather than VCC and GND. If long leads connect to the chip inputs, ensure that these lines are free from ringing and other conditions that would forward bias the chip’s protection diodes. There are three distinct modes of operation: 1) Normal operating mode with all circuitry powered up. Typical supply current from VCC is 60µA, while only leakage currents flow from the battery. 2) Battery-backup mode where VCC is typically within 0.7V below VBATT. All circuitry is powered up and the supply current from the battery is typically less than 60µA. 3) Battery-backup mode where V CC is less than VBATT by at least 0.7V. VBATT supply current is than 1µA max. 14 ______________________________________________________________________________________ Microprocessor Supervisory Circuit Leakage current through the SuperCap charging diode and MAX791 internal power diode eventually discharges the SuperCap to VCC. Also, if VCC and VBATT start from 0.5V above the reset threshold and power is lost at V CC , the SuperCap on VBATT discharges through VCC until VBATT reaches the reset threshold; the MAX791 then switches to battery-backup mode and the current through VCC goes to zero (Figure 10). +5V R1 VCC PFI C1* R3 Using Separate Power Supplies for VBATT and VCC MAX791 R2 PFO GND TO µP *OPTIONAL +5V PFO If using separate power supplies for VCC and VBATT, VBATT must be less than 0.3V above VCC when VCC is above the reset threshold. As described in the previous section, if VBATT exceeds this limit and power is lost at VCC, current flows continuously from VBATT to VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC switch until the circuit is broken (Figure 10). Alternative Chip-Enable Gating 0V VL VTRIP VH VIN 0V VTRIP = 1.25 R1 + R2 R2 VH = 1.25 / R2 || R3 R1 + R2 || R3 VL - 1.25 + 5 - 1.25 = 1.25 R1 R3 R2 Figure 14. Adding Hysteresis to the Power-Fail Comparator Using SuperCaps or MaxCaps with the MAX791 VBATT has the same operating voltage range as VCC, and the battery-switchover threshold voltages are typically ±30mV centered at VBATT, allowing use of a SuperCap and a simple charging circuit as a backup source (Figure 12). If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC. For example, with a SuperCap connected to VBATT and through a diode to VCC, if VCC quickly changes from 5.4V to 4.9V, the capacitor discharges through V OUT and V CC until VBATT reaches 5.3V typical. Using memory devices with CE and CE inputs allows the MAX791 CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to VOUT, and connect CE OUT to the CE input of each memory device (Figure 13). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated by the MAX791. Adding Hysteresis to the Power-Fail Comparator Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is near the power-fail comparator trip point. Figure 14 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10kΩ to prevent it from loading down the PFO pin. Capacitor C1 adds additional noise rejection. ______________________________________________________________________________________ 15 MAX791 VIN MAX791 Microprocessor Supervisory Circuit R1 PFO PFI MAX791 R2 GND +5V V- MAXIMUM TRANSIENT DURATION (µs) 100 VCC VCC = +5V TA = +25°C 0.1µF CAPACITOR FROM VOUT TO GND 80 MAX791-16 +5V 60 40 20 0 PFO 10 0V VTRIP 5 - 1.25 = 1.25 - VTRIP R1 R2 0V 100 1000 10,000 RESET COMPARATOR OVERDRIVE (mV) (Reset Threshold Voltage - VCC) V- NOTE: VTRIP IS NEGATIVE Figure 15. Monitoring a Negative Voltage Monitoring a Negative Voltage The power-fail comparator can be used to monitor a negative supply voltage using Figure 15’s circuit. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit’s accuracy is affected by the PFI threshold tolerance, the VCC voltage, and resistors R1 and R2. Backup-Battery Replacement The backup battery may be disconnected while VCC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses. Negative-Going VCC Transients While issuing resets to the µP during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration negative-going VCC transients (glitches). It is usually undesirable to reset the µP when VCC experiences only small glitches. Figure 16 shows maximum transient duration vs. reset comparator overdrive, for which reset pulses are not generated. The graph was produced using negativegoing VCC pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset com16 Figure 16. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdrive parator overdrive). The graph shows the maximum pulse width that a negative-going VCC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 40µs or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity. Connecting a Timing Capacitor to SWT SWT is internally connected to a ±100nA current source. When a capacitor is connected from SWT to ground (to select an alternative watchdog timeout period), the current source charges and discharges the timing capacitor to create the oscillator that controls the watchdog timeout period. To prevent timing errors or oscillator start-up problems, minimize external current leakage sources at this pin, and locate the capacitor as close to SWT as possible. The sum of PC board leakage + SWT capacitor leakage must be small compared to ±100nA. ______________________________________________________________________________________ Microprocessor Supervisory Circuit START SET WDI LOW SUBROUTINE OR PROGRAM LOOP, SET WDI HIGH RETURN END Figure 17. Watchdog Flow Diagram Maximum VCC Fall Time The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/µs. A standard rule of thumb for filter capacitance on most regulators is on the order of 100µF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse or 1A / 100µF = 0.01V/µs. The VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time requirement. ______________________________________________________________________________________ 17 MAX791 Watchdog Software Considerations A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than “pulsing” the watchdog input high-low-high or low-high-low. This technique avoids a “stuck” loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 17 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should “hang” in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. MAX791 Microprocessor Supervisory Circuit __________________Chip Topography VOUT VBATT WDPO RESET VCC WDO CE IN 0.11" CE OUT (2.794mm) GND BATT ON PFO WDI PFI SWT MR LOWLINE 0.07" (1.778mm) SUBSTRATE CONNECTED TO VOUT TRANSISTOR COUNT: 729 18 ______________________________________________________________________________________ Microprocessor Supervisory Circuit D E DIM E1 A A1 A2 A3 B B1 C D1 E E1 e eA eB L A3 A A2 L A1 0° - 15° C e B1 eA B eB D1 Plastic DIP PLASTIC DUAL-IN-LINE PACKAGE (0.300 in.) DIM PINS D D D D D D DIM D 0°-8° A 0.101mm 0.004in. e B A1 E C H L SO SMALL OUTLINE PACKAGE (0.150 in.) INCHES MAX MIN 0.200 – – 0.015 0.175 0.125 0.080 0.055 0.022 0.016 0.065 0.045 0.012 0.008 0.080 0.005 0.325 0.300 0.310 0.240 – 0.100 – 0.300 0.400 – 0.150 0.115 A A1 B C E e H L 8 14 16 18 20 24 INCHES MAX MIN 0.069 0.053 0.010 0.004 0.019 0.014 0.010 0.007 0.157 0.150 0.050 0.244 0.228 0.050 0.016 DIM PINS D D D INCHES MIN MAX 0.348 0.390 0.735 0.765 0.745 0.765 0.885 0.915 1.015 1.045 1.14 1.265 8 14 16 MILLIMETERS MIN MAX – 5.08 0.38 – 3.18 4.45 1.40 2.03 0.41 0.56 1.14 1.65 0.20 0.30 0.13 2.03 7.62 8.26 6.10 7.87 2.54 – 7.62 – – 10.16 2.92 3.81 MILLIMETERS MIN MAX 8.84 9.91 18.67 19.43 18.92 19.43 22.48 23.24 25.78 26.54 28.96 32.13 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 3.80 4.00 1.27 5.80 6.20 0.40 1.27 INCHES MILLIMETERS MIN MAX MIN MAX 0.189 0.197 4.80 5.00 0.337 0.344 8.55 8.75 0.386 0.394 9.80 10.00 21-0041A ______________________________________________________________________________________ 19 MAX791 ________________________________________________________Package Information MAX791 Microprocessor Supervisory Circuits ___________________________________________Package Information (continued) DIM E1 E D A 0°-15° Q L L1 e C B1 B S1 S CERDIP CERAMIC DUAL-IN-LINE PACKAGE (0.300 in.) A B B1 C E E1 e L L1 Q S S1 INCHES MIN MAX – 0.200 0.014 0.023 0.038 0.065 0.008 0.015 0.220 0.310 0.290 0.320 0.100 0.125 0.200 0.150 – 0.015 0.070 – 0.098 0.005 – DIM PINS D D D D D D 8 14 16 18 20 24 MILLIMETERS MIN MAX – 5.08 0.36 0.58 0.97 1.65 0.20 0.38 5.59 7.87 7.37 8.13 2.54 3.18 5.08 3.81 – 0.38 1.78 – 2.49 0.13 – INCHES MILLIMETERS MIN MAX MIN MAX – 0.405 – 10.29 – 0.785 – 19.94 – 0.840 – 21.34 – 0.960 – 24.38 – 1.060 – 26.92 – 1.280 – 32.51 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.