LINER LTC691INPBF

LTC690/LTC691
LTC694/LTC695
Microprocessor
Supervisory Circuits
FEATURES
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DESCRIPTION
Guaranteed Reset Assertion at VCC = 1V
1.5mA Maximum Supply Current
Fast (35ns Max) Onboard Gating of RAM Chip
Enable Signals
SO-8 and S16 Packaging
4.65V Precision Voltage Monitor
Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable
Minimum External Component Count
1µA Maximum Standby Current
Voltage Monitor for Power-Fail
or Low-Battery Warning
Thermal Limiting
Performance Specified Over Temperature
Superior Upgrade for MAX690 Family
The LTC®690 family provides complete power supply
monitoring and battery control functions for microprocessor
reset, battery back-up, CMOS RAM write protection, power
failure warning and watchdog timing. A precise internal
voltage reference and comparator circuit monitor the power
supply line. When an out-of-tolerance condition occurs,
the reset outputs are forced to active states and the chip
enable output unconditionally write-protects external
memory. In addition, the RESET output is guaranteed to
remain logic low even with VCC as low as 1V.
The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
APPLICATIONS
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For an early warning of impending power failure, the LTC690
family provides an internal comparator with a user-defined
threshold. An internal watchdog timer is also available, which
forces the reset pins to active states when the watchdog
input is not toggled prior to a preset timeout period.
Critical μP Power Monitoring
Intelligent Instruments
Battery-Powered Computers and Controllers
Automotive Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
RESET Output Voltage
vs Supply Voltage
5
TA = 25°C
EXTERNAL PULL-UP = 10μA
VBATT = 0V
®
VIN
+
10μF
VOUT
ADJ
5V
VCC
+
100μF
0.1μF
VOUT
LTC690/LTC691
LTC694/LTC695
VBATT
3V
POWER TO
μP
0.1μF CMOS RAM POWER
μP
SYSTEM
μP RESET
RESET
51k
PFI
GND
10k
MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
PFO
μP NMI
WDI
I/O LINE
RESET OUTPUT VOLTAGE (V)
LT 1086-5
VIN ≥ 7.5V
4
3
2
1
690 TA01
0.1μF
100Ω
0
0
1
3
4
2
SUPPLY VOLTAGE (V)
5
690 TA02
690fe
1
LTC690/LTC691
LTC694/LTC695
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Terminal Voltage
VCC ..................................................... – 0.3V to 6.0V
VBATT .................................................. –0.3V to 6.0V
All Other Inputs ....................– 0.3V to (VOUT + 0.3V)
Input Current
VCC ................................................................200mA
VBATT ...............................................................50mA
GND.................................................................20mA
VOUT Output Current ...................Short-Circuit Protected
Power Dissipation ...............................................500mW
Operating Temperature Range
LTC690/91/94/95C ............................... 0°C to 70°C
LTC690/91/94/95I ............................– 40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) ................. 300°C
PIN CONFIGURATION
TOP VIEW
VBATT
TOP VIEW
1
VOUT
2
16 RESET
VBATT 1
16 RESET
15 RESET
VOUT 2
15 RESET
VCC 3
14 WDO
GND 4
13 CE IN
VCC
3
14 WDO
GND
4
13 CE IN
BATT ON
LOW⎯LINE
CE OUT
12
5
11 WDI
6
OSC IN
7
10 PFO
OSC SEL
8
9
PFI
12 CE OUT
BATT ON 5
LOW⎯LINE 6
11 WDI
OSC IN 7
10 PFO
9 PFI
OSC SEL 8
SW PACKAGE
16-LEAD WIDE PLASTIC SO
N PACKAGE
16-LEAD PDIP
TJMAX = 110°C, θJA = 130°C/W
TJMAX = 110°C, θJA = 130°C/W CONDITIONS: PCB MOUNT ON
FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE
TOP VIEW
TOP VIEW
VOUT
1
8
VBATT
VOUT
1
8
VBATT
VCC
2
7
RESET
VCC
2
7
RESET
GND
3
6
WDI
GND
3
6
WDI
PFI 4
5
PFO
PFI
4
5
PFO
N8 PACKAGE
8-LEAD PDIP
TJMAX = 110°C, θJA = 130°C/W (N8)
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 110°C, θJA = 180°C/W CONDITIONS; PCB MOUNT ON
FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE
690fe
2
LTC690/LTC691
LTC694/LTC695
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC691CN#PBF
LTC691CN#PBF
LTC691CN
16-Lead PDIP
0°C to 70°C
LTC691IN#PBF
LTC691IN#PBF
LTC691IN
16-Lead PDIP
–40°C to 85°C
LTC695CN#PBF
LTC695CN#PBF
LTC695CN
16-Lead PDIP
0°C to 70°C
LTC695IN#PBF
LTC695IN#PBF
LTC695IN
16-Lead PDIP
–40°C to 85°C
LTC691CSW#PBF
LTC691CSW#PBF
LTC691CSW
16-Lead Wide Plastic SO
0°C to 70°C
LTC691ISW#PBF
LTC691ISW#PBF
LTC691ISW
16-Lead Wide Plastic SO
–40°C to 85°C
LTC695CSW#PBF
LTC695CSW#PBF
LTC695CSW
16-Lead Wide Plastic SO
0°C to 70°C
LTC695ISW#PBF
LTC695ISW#PBF
LTC695ISW
16-Lead Wide Plastic SO
–40°C to 85°C
LTC690CN8#PBF
LTC690CN8#PBF
LTC690CN8
8-Lead PDIP
0°C to 70°C
LTC690IN8#PBF
LTC690IN8#PBF
LTC690IN8
8-Lead PDIP
–40°C to 85°C
LTC694CN8#PBF
LTC694CN8#PBF
LTC694CN8
8-Lead PDIP
0°C to 70°C
LTC694IN8#PBF
LTC694IN8#PBF
LTC694IN8
8-Lead PDIP
–40°C to 85°C
LTC690CS8#PBF
LTC690CS8#PBF
LTC690CS8
8-Lead Plastic SO
0°C to 70°C
LTC690IS8#PBF
LTC690IS8#PBF
LTC690IS8
8-Lead Plastic SO
–40°C to 85°C
LTC694CS8#PBF
LTC694CS8#PBF
LTC694CS8
8-Lead Plastic SO
0°C to 70°C
LTC694IS8#PBF
LTC694IS8#PBF
LTC694IS8
8-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PRODUCT SELECTION GUIDE
PINS
RESET
WATCHDOG
TIMER
BATTERY
BACK-UP
POWER-FAIL
WARNING
LTC690
8
X
X
X
X
LTC691
16
X
X
X
X
LTC694
8
X
X
X
X
LTC695
16
X
X
X
X
LTC699
8
X
X
LTC1232
8
X
X
LTC1235
16
X
X
RAM WRITE
PROTECT
PUSHBUTTON
RESET
CONDITIONAL
BATTERY
BACK-UP
X
X
X
X
X
X
X
X
690fe
3
LTC690/LTC691
LTC694/LTC695
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Operating Voltage Range
VCC
VBATT
4.75
2.00
VOUT Output Voltage
IOUT = 1mA
TYP
MAX
UNITS
5.50
4.25
V
V
Battery Back-Up Switching
l
VCC – 0.05 VCC – 0.005
VCC – 0.10 VCC – 0.005
V
V
IOUT = 50mA
VCC – 0.50 VCC – 0.250
V
VOUT in Battery Back-Up Mode
IOUT = 250μA, VCC < VBATT
VBATT – 0.1 VBATT – 0.2
V
Supply Current (Exclude IOUT)
IOUT = 50mA
Supply Current in Battery Back-Up Mode
VCC = 0V, VBATT = 2.8V
Battery Standby Current (+ = Discharge, – = Charge)
5.5 > VCC > VBATT + 0.2V
Battery Switchover Threshold, VCC – VBATT
Power Up
Power Down
l
0.6
0.6
1.5
2.5
mA
mA
l
0.04
0.04
1
5
μA
μA
+0.02
+0.10
μA
μA
l
–0.1
–0.1
70
50
Battery Switchover Hysteresis
mV
mV
20
BATT ON Output Voltage (Note 4)
ISINK = 3.2mA
BATT ON Output Short-Circuit Current (Note 4)
BATT ON = VOUT Sink Current
mV
0.4
35
BATT ON = 0V Source Current
V
m
0.5
1
25
4.5
4.65
4.75
μA
Reset and Watchdog Timer
l
Reset Voltage Threshold
Reset Threshold Hysteresis
40
Reset Active Time (LTC690/91) (Note 5)
OSC SEL HIGH, VCC = 5V
Reset Active Time (LTC694/95) (Note 5)
OSC SEL HIGH, VCC = 5V
Watchdog Timeout Period, Internal Oscillator
Long Period, VCC = 5V
Short Period, VCC = 5V
Watchdog Timeout Period, External Clock (Note 6)
l
40
35
50
50
60
70
ms
ms
l
160
140
200
200
240
280
ms
ms
l
1.2
1
1.6
1.6
2.00
2.25
sec
sec
l
80
70
100
100
120
140
ms
ms
4097
1025
Clock
Cycles
Long Period
Short Period
4032
960
Reset Active Time PSRR
Watchdog Timeout Period PSRR, Internal OSC
l
Minimum WDI Input Pulse Width
VIL = 0.4V, VIH = 3.5V
RESET Output Voltage at VCC = 1V
ISINK = 10μA, VCC = 1V
RESET and LOW⎯LINE Output Voltage (Note 4)
ISINK = 1.6mA, VCC = 4.25V
ISOURCE = 1μA, VCC = 5V
3.5
ISINK = 1.6mA, VCC = 5V
ISOURCE = 1μA, VCC = 4.25V
3.5
RESET and WDO Output Voltage (Note 4)
V
mV
1
ms/V
1
ms/V
200
ns
4
200
mV
0.4
V
V
0.4
V
V
690fe
4
LTC690/LTC691
LTC694/LTC695
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
RESET, RESET, WDO, LOW⎯LINE
Output Short-Circuit Current (Note 4)
Output Source Current
WDI Input Threshold
Logic Low
Logic high
WDI Input Current
MIN
1
Output Sink Current
TYP
MAX
3
25
25
UNITS
μA
mA
0.8
V
4
–8
50
μA
1.3
1.35
3.5
WDI = VOUT
WDI = 0V
l
l
–50
VCC = 5V
l
1.25
Power-Fail Detector
PFI Input Threshold
PFI Input Threshold PSRR
0.3
PFI Input Current
PFO Output Voltage (Note 4)
PFO Short-Circuit Source Current (Note 4)
±0.01
ISINK = 3.2mA
ISOURCE = 1μA
V
mV/V
±25
nA
0.4
V
3.5
PFI = HIGH, PFO = 0V
1
PFI = LOW, PFO = VOUT
3
25
25
μA
mA
PFI Comparator Response Time (Falling)
ΔVIN = –20mV, VOD = 15mV
2
μs
PFI Comparator Response Time (Rising) (Note 4)
ΔVIN = 20mV, VOD = 15mV
with 10kΩ Pull-Up
40
8
μs
Chip Enable Gating
CE IN Threshold
VIL
VIH
0.8
CE IN Pull-Up Current (Note 7)
CE OUT Output Voltage
3
ISINK = 3.2mA
ISOURCE = 3.0mA
ISOURCE = 1μA, VCC = 0V
CE Propagation Delay
VCC = 5V, CL = 20pF
CE OUT Output Short-Circuit Current
Output Source Current
Output Sink Current
V
2
μA
0.4
V
35
45
ns
VOUT – 1.50
VOUT – 0.05
20
20
l
30
35
mA
Oscillator
OSC IN Input Current (Note 7)
±2
μA
OSC SEL Input Pull-Up Current (Note 7)
5
μA
l
OSC IN Frequency Range
OSC SEL = 0V
OSC IN Frequency with External Capacitor
OSC SEL = 0V, COSC = 47pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range parts or for the LTC692 and
LTC693, consult the factory.
Note 4: The output pins of BATT ON, LOW⎯LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3μA. However, external pullup resistors may be used when higher speed is required.
0
250
4
kHz
kHz
Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms
(50ms typically) while the LTC694 and LTC695 have longer minimum
reset active time of 140ms (200ms typically). The reset active time of
the LTC691 and LTC695 can be adjusted (see Table 2 in Applications
Information section).
Note 6: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer (See Block Diagram).
Variation in the timeout period is caused by phase errors which occur
when the oscillator divides the external clock by 64. The resulting variation
in the timeout period is 64 clocks plus one clock of jitter.
Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pullups which pull to the supply when the input pins are floating.
690fe
5
LTC690/LTC691
LTC694/LTC695
BLOCK DIAGRAM
M2
VBATT
VOUT
M1
VCC
CHARGE
PUMP
–
+
BATT ON
C2
LOW⎯LINE
+
C1
–
CE OUT
1.3V
CE IN
GND
–
PFO
C3
+
PFI
RESET
OSC IN
OSC
OSC SEL
WDI
TRANSITION
DETECTOR
RESET PULSE
GENERATOR
WATCHDOG
TIMER
RESET
WDO
690 BD
PIN FUNCTIONS
VCC: 5V Supply Input. The VCC pin should be bypassed
with a 0.1μF capacitor.
VOUT: Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1μF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5Ω. When VCC is lower than VBATT, VOUT
is internally switched to VBATT. If VOUT and VBATT are not
used, connect VOUT to VCC.
VBATT: Back-Up Battery Input. When VCC falls below VBATT,
auxiliary power, connected to VBATT, is delivered to VOUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, VBATT should be connected to GND.
GND: Ground pin.
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC. The output typically sinks 35mA and can provide
base drive for an external PNP transistor to increase the
output current above the 50mA rating of VOUT. BATT ON
goes high when VOUT is internally switched to VBATT.
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes
low when PFI is below 1.3V. Connect PFI to GND or VOUT
when C3 is not used.
690fe
6
LTC690/LTC691
LTC694/LTC695
PIN FUNCTIONS
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
RESET: Logic Output for μP Reset Control. Whenever
VCC falls below either the reset voltage threshold (4.65V,
typically) or VBATT, RESET goes active low. After VCC returns
to 5V, reset pulse generator forces RESET to remain active
low for a minimum of 35ms for the LTC690 /LTC691 (140ms
for the LTC694/LTC695). When the watchdog timer is
enabled but not serviced prior to a preset timeout period,
reset pulse generator also forces RESET to active low for a
minimum of 35ms for the LTC690/LTC691 (140ms for the
LTC694/5) for every preset timeout period (see Figure 11).
The reset active time is adjustable on the LTC691/LTC695.
An external pushbutton reset can be used in connection with
the RESET output. See Pushbutton Reset in Applications
Information section.
RESET: RESET is an active high logic ouput. It is the
inverse of RESET.
LOWLINE: Logic Output from Comparator C1. LOW⎯LINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (4.65V typically),
LOW⎯LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW⎯LINE returns high (see Figure 1).
LOW⎯LINE goes low when VCC drops below VBATT (see
Table 1).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog timeout
period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
timeout period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW⎯LINE goes
low. The watchdog timer can be disabled by floating WDI
(see Figure 11).
CE IN: Logic input to the Chip⎯Enable gating circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CE OUT: Logic Output on the Chip⎯Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL: Oscillator Selection Input. When OSC SEL is high
or floating, the internal oscillator sets the reset active time
and watchdog timeout period. Forcing OSC SEL low, allows
OSC IN be driven from an external clock signal or external
capacitor be connected between OSC IN and GND.
OSC IN: Oscillator Input. OSC IN can be driven by
an external clock signal or external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this configuration the nominal reset active
time and watchdog timeout period are determined by the
number of clocks or set by the formula (see Applications
Information section). When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 50ms typical for the LTC691 and 200ms typical
for the LTC695. OSC IN selects between the 1.6 seconds
and 100ms typical watchdog timeout periods. In both
cases, the timeout period immediately after a reset is 1.6
seconds typical.
690fe
7
LTC690/LTC691
LTC694/LTC695
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT vs IOUT
2.80
VCC = 5V
VBATT = 2.8V
TA = 25°C
OUTPUT VOLTAGE (V)
4.95
1.308
VCC = 5V
VCC = 0V
VBATT = 2.8V
TA = 25°C
4.90
SLOPE = 5Ω
4.85
1.306
PFI INPUT THRESHOLD (V)
5.00
OUTPUT VOLTAGE (V)
Power Failure Input Threshold
vs Temperature
VOUT vs IOUT
2.78
SLOPE = 125Ω
2.76
2.74
4.80
1.304
1.302
1.300
1.298
1.296
10
0
30
40
20
LOAD CURRENT (mA)
2.72
50
100
0
300
400
200
LOAD CURRENT (μA)
500
690 G01
RESET VOLTAGE THRESHOLD (V)
224
RESET ACTIVE TIME
RESET ACTIVE TIME
4.66
VCC = 5V
56
54
52
50
48
216
208
200
192
50
25
75
0
TEMPERATURE (°C)
100
125
184
–50 –25
50
25
75
0
TEMPERATURE (°C)
690 G04
4
2
1.3V
+
PFO
–
30pF
1
0
1
2
3 4 5
TIME (μs)
4.63
4.62
4.61
4.60
–50 –25
5
VCC = 5V
TA = 25°C
4
3
2
VPFI
1
1.3V
7
8
690 G07
+
PFO
–
30pF
0
100
0
20 40
125
690 G06
6
5
VCC = 5V
TA = 25˚C
4
3
2
5V
1
0
1.315V
VPFI = 20mV STEP
1.295V
6
50
25
75
0
TEMPERATURE (°C)
Power-Fail Comparator Response
Time with Pull-Up Resistor
6
1.315V
VPFI = 20mV STEP
0
PFO OUTPUT VOLTAGE (V)
VCC = 5V
TA = 25°C
5
VPFI
125
4.64
Power-Fail Comparator
Response Time
6
3
100
4.65
690 G05
Power-Fail Comparator
Response Time
1.285V
125
Reset Voltage Threshold
vs Temperature
232
VCC = 5V
1.305V
100
690 G03
Reset Active Time
vs Temperature LTC694-5
58
46
–50 –25
50
25
75
0
TEMPERATURE (°C)
690 G02
Reset Active Time
vs Temperature LTC690-1
PFO OUTPUT VOLTAGE (V)
1.294
–50 –25
PFO OUTPUT VOLTAGE (V)
4.75
690 G08
+
1.3V
–
10k
PFO
30pF
VPFI = 20mV STEP
1.295V
60 80 100 120 140 160 180
TIME (μs)
VPFI
0
2
4
8 10 12 14 16 18
TIME (μs)
6
690 G09
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8
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
Microprocessor Reset
The LTC690 family uses a bandgap voltage reference and a
precision voltage comparator C1 to monitor the 5V supply
input on VCC (see Block Diagram). When VCC falls below
the reset voltage threshold, the RESET output is forced
to active low state. The reset voltage threshold accounts
for a 5% variation on VCC, so the RESET output becomes
active low when VCC falls below 4.75V (4.65V typical).
On power-up, the RESET signal is held active low for a
minimum of 35ms for the LTC690/LTC691 (140ms for the
LTC694/LTC695) after reset voltage threshold is reached to
allow the power supply and microprocessor to stabilize.
The reset active time is adjustable on the LTC691/LTC695.
On power-down, the RESET signal remains active low
even with VCC as low as 1V. This capability helps hold the
microprocessor in stable shutdown condition. Figure 1
shows the timing diagram of the RESET signal.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at VCC pin do
not activate the RESET output. Response time is typically
10μs. To help prevent mistriggering due to transient loads,
VCC pin should be bypassed with a 0.1μF capacitor with
the leads trimmed as short as possible.
The LTC691 and LTC695 have two additional outputs:
RESET and LOW⎯LINE. RESET is an active high output
and is the inverse of RESET. LOW⎯LINE is the output
of the precision voltage comparator C1. When VCC falls
V2
V1
VCC
RESET
t1
below the reset voltage threshold, LOW⎯LINE goes low.
LOW⎯LINE returns high as soon as VCC rises above the
reset voltage threshold.
Battery Switchover
The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. When
VCC rises to 70mV above VBATT, the battery switchover
comparator, C2, connects VOUT to VCC through a charge
pumped NMOS power switch, M1. When VCC falls to 50mV
above VBATT, C2 connects VOUT to VBATT through a PMOS
switch, M2. C2 has typically 20mV of hysteresis to prevent
spurious switching when VCC remains nearly equal to VBATT.
The response time of C2 is approximately 20μs.
During normal operation, the LTC690 family uses a charge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
50mA to VOUT from VCC and has a typical on resistance of
5Ω. The VOUT pin should be bypassed with a capacitor of
0.1μF or greater to ensure stability. Use of a larger bypass
capacitor is advantageous for supplying current to heavy
transient loads.
When operating currents larger than 50mA are required
from VOUT, or a lower dropout (VCC-VOUT voltage differential)
is desired, the LTC691 and LTC695 should be used. These
products provide BATT ON output to drive the base of
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
V1
t1
t1 = RESET ACTIVE TIME
LOW LINE
690 F01
Figure 1. Reset Active Time
690fe
9
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
external PNP transistor (Figure 2). If higher currents
are needed with the LTC690 and LTC694, a high current
Schottky diode can be connected from the VCC pin to the
VOUT pin to supply the extra current.
ANY PNP POWER TRANSISTOR
farad-size double layer capacitors, can be used for short
term memory back-up instead of a battery. The charging
resistor for both capacitors and rechargeable batteries
should be connected to VOUT since this eliminates the
discharge path that exists when the resistor is connected
to VCC (Figure 3).
5
I=
BATT ON
3
2
VOUT
VCC
5V
0.1μF
1
3V
LTC691
LTC695
VOUT – VBATT
R
R
0.1μF
5V
VBATT
GND
4
VCC
0.1μF
690 F02
Figure 2. Using BATT ON to Drive External PNP Transistor
The LTC690 family is protected for safe area operation
with short-circuit limit. Output current is limited to
approximately 200mA. If the device is overloaded for
long period of time, thermal shutdown turns the power
switch off until the device cools down. The threshhold
temperature for thermal shutdown is approximately 155°C
with about 10°C of hysteresis which prevents the device
from oscillating in and out of shutdown.
The PNP switch used in competitive devices was not chosen
for the internal power switch because it injects unwanted
current into the substrate. This current is collected by the
VBATT pin in competitive devices and adds to the charging
current of the battery which can damage lithium batteries.
The LTC690 family uses a charge pumped NMOS power
switch to eliminate unwanted charging current while
achieving low dropout and low supply current. Since no
current goes to the substrate, the current collected by
VBATT pin is strictly junction leakage.
A 125Ω PMOS switch connects the VBATT input to VOUT
in battery back-up mode. The switch is designed for very
low dropout voltage (input-to-output differential). This
feature is advantageous for low current applications such
as battery back-up in CMOS RAM and other low power
CMOS circuitry. The supply current in battery back-up
mode is 1μA maximum.
The operating voltage at the VBATT pin ranges from 2.0V
to 4.25V. High value capacitors, such as electrolytic or
VOUT
LTC690
LTC691
LTC694
LTC695
3V
0.1μF
VBATT
GND
690 F03
Figure 3. Charging External Battery Through VOUT
Replacing the Back-Up Battery
When changing the back-up battery with system power
on, spurious resets can occur while battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge
up the stray capacitance on the VBATT pin. The oscillation
cycle is as follows: When VBATT reaches within 50mV of
VCC, the LTC690 switches to battery back-up. VOUT pulls
VBATT low and the device goes back to normal operation.
The leakage current then charges up the VBATT pin again
and the cycle repeats.
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
from VBATT to GND will hold the pin low while changing
the battery. For example, the battery standby current is
1μA maximum over temperature and the external resistor
required to hold VBATT below VCC is:
R≤
VCC –50mV
1 μA
With VCC = 4.5V, a 4.3M resistor will work. With a 3V
battery, this resistor will draw only 0.7μA from the battery,
which is negligible in most cases.
690fe
10
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond VCC due
to the lead inductance (Figure 4).
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
10Ω
VBATT
4.3M
0.1μF
LTC690
LTC691
LTC694
LTC695
Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
GND
Table 1. Input and Output Status in Battery Back-Up Mode
690 F04
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
VBATT to GND and VOUT to VCC .
SIGNAL
STATUS
VCC
C2 monitors VCC for active switchover.
VOUT
VOUT is connected to VBATT through an internal PMOS switch.
VBATT
The supply current is 1μA maximum.
BATT ON
Logic high. The open-circuit output voltage is equal to VOUT .
PFI
Power failure input is ignored.
PFO
Logic low
Memory Protection
RESET
Logic low
The LTC691 and LTC695 include memory protection
circuitry that ensures the integrity of the data in memory
by preventing write operations when VCC is at invalid level.
Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When VCC is 5V,
CE OUT follows CE IN with a typical propagation delay of
20ns. When VCC falls below the reset voltage threshold
or VBATT, CE OUT is forced high, independent of CE IN. CE
OUT is an alternative signal to drive the CE, CS, or Write
RESET
Logic high. The open-circuit output voltage is equal to VOUT.
VCC
LOW⎯LINE Logic low
V2
V1
WDI
Watchdog input is ignored.
WDO
Logic high. The open-circuit output voltage is equal to VOUT.
CE IN
Chip⎯Enable Input is ignored.
CE OUT
Logic high. The open-circuit output voltage is equal to VOUT.
OSC IN
OSC IN is ignored.
OSC SEL
OSC SEL is ignored.
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CE IN
VOUT = VBATT
CE OUT
VOUT = VBATT
690 F05
Figure 5. Timing Diagram for CE IN and CE OUT
690fe
11
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
5V
0.1μF
VOUT
VCC
LTC691
LTC695
0.1μF
10μF
62512
RAM
CE OUT
VBATT
3V
GND
Power-Fail Warning
VCC
+
CS
20ns PROPAGATION DELAY
CE IN
RESET
GND
FROM DECODER
RESET
TO μP
690 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
VCC
0.1μF
VOUT
VCC
+
62128
RAM
CS1
0.1μF
10μF
LTC690
LTC694
CS
RESET
GND
VBATT
3V
CS2
GND
690 F07
Figure 7. Write Protect for RAM with LTC690 or LTC694
VIN ≥ 7.5V
+
LT1086-5
VIN
VOUT
ADJ
10μF
5V
+
100μF
R3
300k
R1
51k
VCC
0.1μF
R4
10k
LTC690/LTC691
LTC694/LTC695
PFO
PFI
R2
10k
GND
690 F08
TO μP
VIN ≥ 6.5V
VIN VOUT
+
10μF
ADJ
5V
+
10μF
R1
27k
R4
10k
R3
2.7M
R2
8.2k
LTC690/LTC691
LTC694/LTC695
PFO
PFI GND
TO μP
R5
3.3k
Figure 9. Monitoring Regulated DC Supply
with the LTC690’s Power-Fail Comparator
When PFO output is low, R3 sinks current from the summing
junction at the PFI pin.
⎛ R1 R1⎞
VH = 1.3V ⎜ 1+
+ ⎟
⎝ R2 R3 ⎠
⎛ R1 (5V – 1.3V)R1⎞
VL = 1.3V ⎜ 1 +
–
⎟
⎝ R2 1.3V(R3 + R4)⎠
VCC
0.1μF
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
Figure 8. Monitoring Unregulated DC Supply
with the LTC690’s Power-Fail Comparator
LT1086-5
The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microprocessor
to execute shutdown procedure between PFO and RESET
or RESET.
1690 F09
Assuming R4 << R3,VHYSTERESIS = 5V
R1
R3
Example 1: The circuit in Figure 8 demonstrates the use
of the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input VIN is 100mV/ms and the total time to execute a
shutdown procedure is 8ms. Also the noise of VIN is 200mV.
With these assumptions in mind, we can reasonably set
VL = 7.5V which 1.25V greater than the sum of maximum
reset voltage threshold and the dropout voltageof LT1086-5
(4.75V + 1.5V) and VHYSTERESIS = 850mV.
690fe
12
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
VHYSTERESIS = 5V
5V
R1
= 850V
R3
VBATT
R1
1M
R3 ≈ 5.88 R1
PFI
Choose R3 = 300k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.
⎛ 51k (5V – 1.3V)51k⎞
7.5V = 1.3V ⎜ 1+
–
⎟
1.3V(310 k ) ⎠
⎝ R2
R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalculate VL,
⎛ 51k (5V – 1.3V)51k⎞
VL = 1.3V ⎜ 1 +
–
⎟ = 7.32V
1.3V(310k) ⎠
⎝ 10k
⎛ 51k 51k ⎞
VH = 1.3V ⎜ 1 +
+
⎟ = 8.151V
⎝ 10k 300k ⎠
(7.32V – 6.25V)
= 10.7ms
100mV/ms
VHYSTERESIS = 8.151V – 7.32V = 831mV
The 10.7ms allows enough time to execute shutdown
procedure for microprocessor and 831mV of hysteresis
would prevent PFO from going low due to the noise of VIN.
Example 2: The circuit in Figure 9 can be used to measure
the regulated 5V supply to provide early warning of power
failure. Because of variations in the PFI threshold, this
circuit requires adjustment to ensure the PFI comparator
trips before the reset threshold is reached. Adjust R5 such
that the PFO output goes low when the VCC supply reaches
the desired level (e.g., 4.85V).
Monitoring the Status of the Battery
C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
apply a test load to the battery. Since CE OUT is forced high
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.
3V
VCC
LOW-BATTERY SIGNAL
TO μP I/O PIN
PFO
LTC691
LTC695
R2
1M
CE IN
CE OUT
RL
20k
I/O PIN
GND
690 F10
OPTIONAL TEST LOAD
Figure 10. Back-Up Battery Monitor with Optional Test Load
Watchdog Timer
The LTC690 family provides a watchdog timer function
to monitor the activity of the microprocessor. If the
microprocessor does not toggle the Watchdog Input
(WDI) within a seleced timeout period, RESET is forced to
active low for a minimum of 35ms for the LTC690/LTC691
(140ms for the LTC694/LTC695). The reset active time is
adjustable on the LTC691/LTC695. Since many systems
can not service the watchdog timer immediately after
a reset, the LTC691 and LTC695 have longer timeout
period (1.0 second minimum) right after a reset is issued.
The normal timeout period (70ms minimum) becomes
effective following the first transition of WDI after RESET
is inactive. The watchdog timeout period is fixed at 1.0
second minimum on the LTC690 and LTC694. Figure 11
shows the timing diagram of watchdog timeout period and
reset active time. The watchdog timeout period is restarted
as soon as RESET is inactive. When either a high-to-low
or low-to-high transition occurs at the WDI pin prior to
timeout, the watchdog time is reset and begins to time
out again. To ensure the watchdog time does not time
out, either a high-to-low or low-to-high transition on the
WDI pin must occur at or less than the minimum timeout
period. If the input to the WDI pin remains either high or
low, reset pulses will be issued every 1.6 seconds typically.
The watchdog time can be deactivated by floating the WDI
pin. The timer is also disabled when VCC falls below the
reset voltage threshold or VBATT.
690fe
13
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
The LTC691 and LTC695 provide an additional output
(Watchdog Output, WDO) which goes low if the watchdog
timer is allowed to time out and remains low until set high
by the next transition on the WDI pin. WDO is also set high
when VCC falls below the reset voltage threshold or VBATT.
The LTC691 and LTC695 have two additonal pins OSC SEL
and OSC IN, which allow reset active time and watchdog
timeout period to be adjusted per Table 2. Several
configurations are shown in Figure 12.
GND when OSC SEL is forced low. In these configurations,
the nominal reset active time and watchdog timeout
period are determined by the number of clocks or set by
the formula in Table 2. When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 35ms minimum for the LTC691 and 140ms
minimum for the LTC695. OSC IN selectes between the
1 second and 70ms minimum normal watchdog timeout
periods. In both cases, the timeout period immediately
after a reset is at least 1 second.
OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and
VCC = 5V
WDI
t1 = RESET ACTIVE TIME
t2 = NORMAL WATCHDOG TIME-OUT PERIOD
t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY
AFTER A RESET
WDO
t2
t3
RESET
t1
t1
690 F11
Figure 11. Watchdog Timeout Period and Reset Active Time
EXTERNAL OSCILLATOR
EXTERNAL CLOCK
3
5V
VCC
OSC SEL
8
5V
3
VCC
LTC691
LTC695
4
GND
OSC IN
3
VCC
OSC SEL
4
7
8
GND
GND
OSC IN
OSC IN
7
INTERNAL OSCILLATOR
100ms WATCHDOG
FLOATING
OR HIGH
5V
3
VCC
LTC691
LTC695
4
8
LTC691
LTC695
INTERNAL OSCILLATOR
1.6 SECOND WATCHDOG
5V
OSC SEL
OSC SEL
8
FLOATING
OR HIGH
LTC691
LTC695
7
FLOATING
OR HIGH
4
GND
OSC IN
7
690 F12
Figure 12. Oscillator Configurations
690fe
14
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
Table 2. LTC691 and LTC695 Reset Active Time and Watchdog Timeout Selections
WATCHDOG TIME-OUT PERIOD
OSC SEL
OSC IN
NORMAL
(Short Period)
Low
External Clock Input
1024 clks
Low
External Capacitor*
Floating or High
Floating or High
Low
Floating or High
RESET ACTIVE TIME
IMMEDIATELY
AFTER RESET
(Long Period)
LTC691
LTC695
4096 clks
512 clks
2048 clks
1.6 sec
•C
70pF
200ms
•C
70pF
800ms
•C
70pF
1.6 sec
1.6 sec
50ms
50ms
200ms
200ms
100ms
1.6 sec
184,000
*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is fOSC (Hz) =
C (pF )•1025
Pushbutton Reset
The LTC690 family does not provide a logic input for direct
connection to a pushbutton. However, a pushbutton in
series with a 100Ω resistor connected to the RESET output
pin (Figure 13) provides an alternative for manual reset.
Connecting a 0.1μF capacitor to the RESET pin debounces
the pushbutton input.
The 100Ω resistor in series with the pushbutton is required
to prevent the ringing, due to the capacitance and lead
inductance, from pulling the RESET pins of the MPU and
LTC69X below ground.
If a dedicated pushbutton reset input is desired, the LTC1235
is a good choice (Figure 14). It has all the functions of the
LTC695 and provides pushbutton reset as an extra feature.
Its pushbutton is internally debounced and invokes the
normal 200ms reset sequence. This eliminates the need
for the 100Ω resistor and 0.1μF capacitor. It also provides
a more consistent reset pulse.
5V
RESET
RESET
VCC
0.1μF
LTC690/LTC691
LTC694/LTC695
100Ω
MPU
(e.g. 6805)
GND
690 F13
Figure 13. The External Pushbutton Reset
5V
RESET
VCC
LTC1235
RESET
MPU
(e.g. 6805)
PBRST
GND
690 F14
Figure 14. The External Pushbutton Reset with the LTC1235
690fe
15
LTC690/LTC691
LTC694/LTC695
PACKAGE DESCRIPTION
SW Package 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620)
0.291 – 0.299**
(7.391 – 7.595)
0.398 – 0.413*
(10.109 – 10.490)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029 s 45°
(0.254 – 0.737)
15
16
14
12
13
11 10
9
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
0.050
(1.270)
TYP
NOTE 1
0.014 – 0.019
(0.356 – 0.482)
TYP
0.016 – 0.050
(0.406 – 1.270)
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.004 – 0.012
(0.102 – 0.305)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2
1
3
5
4
7
6
8
S16 (WIDE) 0396
N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
0.400*
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.125
(3.175) 0.020
MIN
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
s 45°
(0.254 – 0.508)
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0.004 – 0.010
(0.101 – 0.254)
8
7
6
5
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
0.050
(1.270)
TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
1
3
2
4
N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325 –0.015
(
8.255
+0.889
–0.381
)
0.130 ± 0.005
(3.302 ± 0.127)
0.770*
(19.558)
MAX
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
16
15
14
13
12
11
10
1
2
3
4
5
6
7
9
0.255 ± 0.015*
(6.477 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
8
N16 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
690fe
16
LTC690/LTC691
LTC694/LTC695
REVISION HISTORY
(Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
3/10
Removed “UL Recognized” and UL File Number From Features
1
E
4/10
Remove LTC690MJ8
3
690fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC690/LTC691
LTC694/LTC695
TYPICAL APPLICATION
Capacitor Back-Up with 74HC4016 Switch
5V
VCC
0.1μF
R2
30k
2
74HC4016
7
LTC691
LTC695
13
CE OUT
CE IN
3V
+
100μF
VCC
+
0.1μF
10μF
VBATT
LOW⎯LINE
VBATT
VOUT
VCC
0.1μF
LTC691
LTC695
10 11 12 14
1
5V
VOUT
0.1μF
R1
10k
Write Protect for Additional RAMs
62512
RAM A
CS
20ns PROPAGATION
DELAY
CS⎯A
LOW⎯LINE
GND
GND
0.1μF
LTC690 TA03
CS⎯B
VCC
62128
RAM B
CS⎯1
CS2
VCC
0.1μF
CS⎯C
62128
RAM C
CS⎯1
CS2
OPTIONAL CONNECTION FOR
ADDITIONAL RAMs
690 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1326
Micropower Precision Triple Supply Monitor
4.725V, 3.118V, 1V Thresholds (± 0.75%)
LTC1536
Micropower Triple Supply Monitor for PCI Applications
Meets PCI tFAIL Timing Specifications
690fe
18 Linear Technology Corporation
LT 0410 REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1992