LINER LTC3703

LTC3703
100V Synchronous
Switching Regulator
Controller
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FEATURES
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DESCRIPTIO
High Voltage Operation: Up to 100V
Large 1Ω Gate Drivers
No Current Sense Resistor Required
Step-Up or Step-Down DC/DC Converter
Dual N-Channel MOSFET Synchronous Drive
Excellent Transient Response and DC Line Regulation
Programmable Constant Frequency: 100kHz to
600kHz
±1% Reference Accuracy
Synchronizable up to 600kHz
Selectable Pulse Skip Mode Operation
Low Shutdown Current: 50µA Typ
Programmable Current Limit
Undervoltage Lockout
Programmable Soft-Start
16-Pin Narrow SSOP and 28-Pin SSOP Packages
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APPLICATIO S
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48V Telecom and Base Station Power Supplies
Networking Equipment, Servers
Automotive and Industrial Control
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC®3703 is a synchronous step-down switching
regulator controller that can directly step-down voltages
from up to 100V, making it ideal for telecom and automotive applications. The LTC3703 drives external N-channel
MOSFETs using a constant frequency (up to 600kHz),
voltage mode architecture. The external component count
has been minimized, providing a compact overall solution
footprint.
A precise internal reference provides 1% DC accuracy. A
high bandwidth error amplifier and patented line feed
forward compensation provide very fast line and load
transient response. Strong 1Ω gate drivers allow the
LTC3703 to drive multiple MOSFETs for higher current
applications. The operating frequency is user programmable from 100kHz to 600kHz and can also be synchronized to an external clock for noise-sensitive applications.
Current limit is programmable with an external resistor
and utilizes the voltage drop across the synchronous
MOSFET to eliminate the need for a current sense resistor.
Soft- start is provided by an external capacitor. Pulling the
soft-start pin low shuts down the LTC3703, reducing
supply current to 50µA.
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TYPICAL APPLICATIO
VCC
9.3V TO 15V
+
22µF
25V
VIN
BAS21 15V TO 100V
MODE/SYNC VIN
+
30k
FSET
BOOST
LTC3703
COMP
TG
3300pF
FB
INV
0.1µF
330Ω
95
8µH
SW
VCC
10Ω
DRVCC
Si7456DP
RUN/SS
BG
GND
220µF
25V
×2
+
VIN = 75V
90
85
MBR1100
10µF
113k
1%
VOUT
12V
5A
15k
IMAX
VIN = 25V
VIN = 50V
Si7456DP
0.1µF
15pF
8.06k
1%
100
22µF
×2
EFFICIENCY (%)
22k
Efficiency vs Load Current
BGRTN
80
0
1µF
1500pF
1
3
2
LOAD (A)
4
5
3703 F01b
3703 F01
Figure 1. High Efficiency High Voltage Step-Down Converter
3703f
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LTC3703
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ABSOLUTE
AXI U RATI GS (Note 1)
Supply Voltages
VCC, DRVCC .......................................... –0.3V to 15V
(DRVCC – BGRTN), (BOOST – SW) ...... –0.3V to 15V
BOOST ................................................ –0.3V to 115V
BGRTN ...................................................... –5V to 0V
VIN Voltage ............................................. –0.3V to 100V
SW Voltage ................................................ –1V to 100V
Run/SS Voltage .......................................... –0.3V to 5V
MODE/SYNC, INV Voltages ....................... –0.3V to 15V
fSET, FB, IMAX Voltages ............................... –0.3V to 3V
Peak Output Current <10µs BG,TG ............................ 5A
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Notes 3, 7) ....................... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
MODE/SYNC 1
fSET 2
LTC3703EGN
16 VIN
15 B00ST
COMP 3
14 TG
FB 4
13 SW
IMAX 5
12 VCC
INV 6
RUN/SS 7
GND 8
11 DRVCC
10 BG
9
GN PART
MARKING
BGRTN
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
3703
ORDER PART
NUMBER
TOP VIEW
VIN
1
28 BOOST
NC
2
27 TG
NC
3
26 SW
NC
4
25 NC
NC
5
24 NC
MODE/SYNC
6
23 NC
fSET
7
22 NC
COMP
8
21 VCC
FB
9
20 DRVCC
IMAX 10
19 BG
INV 11
18 NC
NC 12
17 NC
RUN/SS 13
16 NC
GND 14
LTC3703EG
15 BGRTN
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 10V, VMODE/SYNC = VINV = VSW =
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
VCC, DRVCC
VCC, DRVCC Supply Voltage
●
VIN
VIN Pin Voltage
●
ICC
VCC Supply Current
VFB = 0V
RUN/SS = 0V
IDRVCC
DRVCC Supply Current
(Note 5)
RUN/SS = 0V
IBOOST
BOOST Supply Current
(Note 5)
RUN/SS = 0V
●
●
TYP
9.3
MAX
UNITS
15
V
100
V
1.7
50
2.5
mA
µA
0
0
5
5
µA
µA
360
0
500
5
µA
µA
3703f
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LTC3703
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 10V, VMODE/SYNC = VINV = VSW =
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
Feedback Voltage
(Note 4)
MIN
TYP
MAX
UNITS
0.792
0.788
0.800
0.808
0.812
V
V
0.007
0.05
%/V
0.01
0.1
%
0.8
0.87
Main Control Loop
VFB
●
∆VFB, LINE
Feedback Voltage Line Regulation
9V < VCC < 15V (Note 4)
●
∆VFB, LOAD
Feedback Voltage Load Regulation
1V < VCOMP < 2V (Note 4)
●
VMODE/SYNC
MODE/SYNC Threshold
MODE/SYNC Rising
∆VMODE/SYNC
MODE/SYNC Hysteresis
IMODE/SYNC
MODE/SYNC Current
VINV
Invert Threshold
IINV
Invert Current
0 ≤ VINV ≤ 15V
IVIN
VIN Sense Input Current
VIN = 100V
RUN/SS = 0V, VIN = 10V
IMAX
IMAX Source Current
VIMAX = 0V
VOS, IMAX
VIMAX Offset Voltage
|VSW| – VIMAX at IRUN/SS = 0µA
VRUN/SS
Shutdown Threshold
IRUN/SS
RUN/SS Source Current
RUN/SS = 0V
Maximum RUN/SS Sink Current
|VSW| – VIMAX > 100mV
Undervoltage Lockout
VCC Rising
VCC Falling
fOSC
Oscillator Frequency
RSET = 25kΩ
fSYNC
External Sync Frequency Range
tON, MIN
Minimum On-Time
DCMAX
Maximum Duty Cycle
VUV
0.75
20
0 ≤ VMODE/SYNC ≤ 15V
µA
0
1
1.5
2
V
0
1
µA
100
0
140
1
µA
µA
10.5
12
13.5
µA
– 25
10
55
mV
0.7
0.9
1.2
V
2.5
4
5.5
µA
1
●
●
V
mV
9
17
25
µA
8.0
5.7
8.7
6.2
9.3
6.8
V
V
270
300
330
kHz
600
kHz
Oscillator
100
200
f < 200kHz
89
93
1.5
2
1.5
2
ns
96
%
Driver
IBG, PEAK
BG Driver Peak Source Current
RBG, SINK
BG Driver Pull-Down RDS, ON
ITG, PEAK
TG Driver Peak Source Current
RTG, SINK
TG Driver Pull-Down RDS, ON
(Note 8)
AVOL
Op Amp DC Open Loop Gain
(Note 4)
fU
Op Amp Unity Gain Crossover Frequency (Note 6)
IFB
FB Input Current
ICOMP
COMP Sink/Source Current
(Note 8)
1
1
A
1.5
Ω
A
1.5
Ω
Feedback Amplifier
74
0 ≤ VFB ≤ 3V
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: The LTC3703E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3703: TJ = TA + (PD • 100 °C/W) G Package
Note 4: The LTC3703 is tested in a feedback loop that servos VFB to the
reference voltage with the COMP pin forced to a voltage between 1V and 2V.
85
dB
25
MHz
0
±5
±10
1
µA
mA
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(QG • fOSC).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 8: RDS(ON) guaranteed by correlation to wafer level measurement.
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LTC3703
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
TA = 25°C (unless otherwise noted).
Load Transient Response
Efficiency vs Load Current
100
100
IOUT = 5A
95
VOUT
50mV/DIV
95
90
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 15V
IOUT = 0.5A
85
80
VOUT = 12V
f = 300kHz
PULSE SKIP DISABLED
75
70
0
10
20
90
70
IOUT
2A/DIV
80
70
80
VIN = 75V
85
75
30 40 50 60
INPUT VOLTAGE (V)
VIN = 45V
VOUT = 5V
f = 250kHz
PULSE SKIP ENABLED
50µs/DIV
VIN = 50V
VOUT = 12V
1A TO 5A LOAD STEP
3703 G01
3703 G02
VCC Current vs VCC Voltage
VCC Shut-Down Current vs VCC
Voltage
VCC Current vs Temperature
100
4
3.5
90
3.0
3
VCC CURRENT (mA)
2.5
2.0
VFB = 0V
1.5
1.0
80
COMP = 1.5V
VCC CURRENT (µA)
COMP = 1.5V
VCC CURRENT (mA)
3703 G03
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
2
VFB = 0V
1
70
60
50
40
30
20
0.5
10
0
6
8
10
12
VCC VOLTAGE (V)
14
0
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
16
80
0
100
VCC Shut-Down Current vs
Temperature
12
10
VCC VOLTAGE (V)
14
16
3703 G06
Normalized Frequency vs
Temperature
Reference Voltage vs
Temperature
0.803
70
1.20
1.15
60
55
50
45
40
0.802
NORMALIZED FREQUENCY
REFERENCE VOLTAGE (V)
65
VCC CURRENT (µA)
8
3703 G05
3703 G04
0.801
0.800
0.799
1.10
1.05
1.00
0.95
0.90
0.85
35
30
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
6
80
100
3703 G07
0.798
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
3703 G08
0.80
–60 –40 –20
0
20 40 60
TEMPERATURE (°C)
80
100
3703 G09
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LTC3703
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TYPICAL PERFOR A CE CHARACTERISTICS
Driver Peak Source Current vs
Temperature
3.0
3.0
1.2
VCC = 10V
2.8
VCC = 10V
2.4
2.2
2.0
1.8
PEAK SOURCE CURRENT (A)
1.0
2.6
RDS(ON) (Ω)
PEAK SOURCE CURRENT (A)
Driver Peak Source Current vs
Supply Voltage
Driver Pull-Down RDS(ON) vs
Temperature
0.8
0.6
0.4
1.6
1.4
2.5
2.0
1.5
1.0
0.5
0.2
1.2
1.0
–60 –40 –20
0
20 40 60
TEMPERATURE (°C)
80
0
0
–60 –40 –20 0
20 40 60
TEMPERATURE (°C)
100
80
3703 G10
100
RUN/SS Pull-Up Current vs
Temperature
70
1.1
6
DRVCC, BOOST = 10V
60
5
0.7
RUN/SS CURRENT (µA)
RISE
RISE/FALL TIME (ns)
RDS(ON) (Ω)
1.0
50
40
30
FALL
20
0
0.6
7
9 10 11 12 13
8
DRVCC/BOOST VOLTAGE (V)
14
0
15
6000
2000
4000
8000
GATE CAPACITANCE (pF)
3
2
0
–60 –40 –20
10000
RUN/SS Pull-Up Current vs
VCC Voltage
6
25
5
20
Max % DC vs RUN/SS Voltage
90
80
MAX DUTY CYCLE (%)
RUN/SS SINK CURRENT (µA)
2
15
10
5
0
1
–5
0
–10
100
100
IMAX = 0.3V
3
80
1573 G06
RUN/SS Sink Current vs
SW Voltage
4
0 20 40 60
TEMPERATURE (°C)
3703 G14
3703 G13
RUN/SS PULLUP CURRENT (µA)
4
1
10
6
7
8 9 10 11 12 13 14 15
DRVCC/BOOST VOLTAGE (V)
3703 G12
Rise/Fall Time vs Gate
Capacitance
0.8
6
3703 G11
Driver Pull-Down RDS(ON) vs
Supply Voltage
0.9
5
70
60
50
40
30
20
10
0
6
8
10
12
VCC VOLTAGE (V)
14
16
3703 G16
0
0.1
0.5
0.2 0.3 0.4
|SW| VOLTAGE (V)
0.6
0.7
3703 G17
–10
0.5
1.0
2.0
1.5
RUN VOLTAGE (V)
2.5
3.0
3703 G18
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LTC3703
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TYPICAL PERFOR A CE CHARACTERISTICS
IMAX Current vs Temperature
Max % DC vs Frequency and
Temperature
% Duty Cycle vs COMP Voltage
100
13
100
95
12
MAX DUTY CYCLE (%)
DUTY CYCLE (%)
IMAX SOURCE CURRENT (µA)
VIN = 10V
80
60
VIN = 75V
40
VIN = 50V
VIN = 25V
80
100
0.5
0.75
1.00
1.25 1.50
COMP (V)
1.75
Shutdown Threshold vs
Temperature
70
0
100
200 300 400 500
FREQUENCY (kHz)
600
700
3703 G21
tON(MIN) vs Temperature
1.4
160
1.2
140
120
1.0
tON(MIN) (ns)
SHUTDOWN THRESHOLD (V)
2.00
3703 G20
3703 G19
0.8
0.6
0.4
100
80
60
40
0.2
0
–60 –40 –20
25°C
80
75
0
0
20 40 60
TEMPERATURE (°C)
–45°C
85
90°C
20
11
–60 –40 –20
90
20
0
20 40 60
TEMPERATURE (°C)
80
100
3703 G22
0
–60 –40 –20
0
20 40 60
TEMPERATURE (°C)
80
100
3703 G23
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LTC3703
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PI FU CTIO S
(GN16)
MODE/SYNC (Pin 1): Pulse Skip Mode Enable/Sync Pin.
This multifunction pin provides Pulse Skip Mode enable/
disable control and an external clock input for synchronization of the internal oscillator. Pulling this pin below 0.8V
or to an external logic-level synchronization signal disables Pulse Skip Mode operation and forces continuous
operation. Pulling the pin above 0.8V enables Pulse Skip
Mode operation. This pin can also be connected to a
feedback resistor divider from a secondary winding on the
inductor to regulate a second output voltage.
fSET (Pin 2): Frequency Set. A resistor connected to this
pin sets the free running frequency of the internal oscillator. See applications section for resistor value selection
details.
COMP (Pin 3): Loop Compensation. This pin is connected
directly to the output of the internal error amplifier. An RC
network is used at the COMP pin to compensate the
feedback loop for optimal transient response.
FB (Pin 4): Feedback Input. Connect FB through a resistor
divider network to VOUT to set the output voltage. Also
connect the loop compensation network from COMP to
FB.
IMAX (Pin 5): Current Limit Set. The IMAX pin sets the
current limit comparator threshold. If the voltage drop
across the bottom MOSFET exceeds the magnitude of the
voltage at IMAX, the controller goes into current limit. The
IMAX pin has an internal 12µA current source, allowing the
current threshold to be set with a single external resistor
to ground. See the Current Limit Programming section for
more information on choosing RIMAX.
INV (Pin 6): Top/Bottom Gate Invert. Pulling this pin above
2V sets the controller to operate in step-up (boost) mode
with the TG output driving the synchronous MOSFET and
the BG output driving the main switch. Below 1V, the
controller will operate in step-down (buck) mode.
RUN/SS (Pin 7): Run/Soft-Start. Pulling RUN/SS below
0.9V will shut down the LTC3703, turn off both of the
external MOSFET switches and reduce the quiescent supply current to 50µA. A capacitor from RUN/SS to ground
will control the turn-on time and rate of rise of the output
voltage at power-up. An internal 4µA current source pullup at the RUN/SS pin sets the turn-on time at approximately 750ms/µF.
GND (Pin 8): Ground Pin.
BGRTN (Pin 9): Bottom Gate Return. This pin connects to
the source of the pull-down MOSFET in the BG driver and
is normally connected to ground. Connecting a negative
supply to this pin allows the synchronous MOSFET’s gate
to be pulled below ground to help prevent false turn-on
during high dV/dt transitions on the SW node. See the
Applications Information section for more details.
BG (Pin 10): Bottom Gate Drive. The BG pin drives the gate
of the bottom N-channel synchronous switch MOSFET.
This pin swings from BGRTN to DRVCC.
DRVCC (Pin 11): Driver Power Supply Pin. DRVCC provides power to the BG output driver. This pin should be
connected to a voltage high enough to fully turn on the
external MOSFETs, normally 10V to 15V for standard
threshold MOSFETs. DRVCC should be bypassed to BGRTN
with a 10µF, low ESR (X5R or better) ceramic capacitor.
VCC (Pin 12) : Main Supply Pin. All internal circuits except
the output drivers are powered from this pin. VCC should
be connected to a low noise power supply voltage between
9V and 15V and should be bypassed to GND (pin 8) with
at least a 0.1µF capacitor in close proximity to the LTC3703.
SW (Pin 13): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
VIN.
TG (Pin 14): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true floating drive to the top MOSFET.
BOOST (Pin 15): Top Gate Driver Supply. The BOOST pin
supplies power to the floating TG driver. The BOOST pin
should be bypassed to SW with a low ESR (X5R or better)
0.1µF ceramic capacitor. An additional fast recovery
Schottky diode from DRVCC to BOOST will create a complete floating charge-pumped supply at BOOST.
VIN (Pin 16): Input Voltage Sense Pin. This pin is connected to the high voltage input of the regulator and is used
by the internal feedforward compensation circuitry to
improve line regulation. This is not a supply pin.
3703f
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LTC3703
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FU CTIO AL DIAGRA
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RSET
FSET
2
OVERCURRENT
12µA
4µA
IMAX
–
5
RMAX
+
50mV
–
±
+
RUN/SS
±
–
5
CSS
1V
CHIP
SD
+
3.2V
INV
UVSD OTSD
SYNC
DETECT
MODE/SYNC 1
EXT SYNC
VCC
+
OSC
DB
–
FORCED CONTINUOUS
INV
REVERSE
CURRENT
15
COMP
14
3
0.8V
FB
R2
R1
4
+
+ FB
–
÷
% DC
LIMIT
VIN 16
–
PWM
+
13
DRIVE
LOGIC
11
+MIN–
10
+MAX–
9
VCC
(<15V)
0.76V
VIN
BOOST
TG
CB
M1
SW
DRVCC
BG
M2
BGRTN
6 INV
0.84V
12
L1
OVER
TEMP
BANDGAP
VCC
VOUT
8 GND
UVLO
COUT
OT SD
0.8V
REFERENCE
INTERNAL
3.2V VCC
UV SD
GN16
VCC
CVCC
3703 FD
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OPERATIO
(Refer to Functional Diagram)
The LTC3703 is a constant frequency, voltage mode
controller for DC/DC step-down converters. It is designed
to be used in a synchronous switching architecture with
two external N-channel MOSFETs. Its high operating voltage capability allows it to directly step down input voltages
up to 100V without the need for a step-down transformer.
For circuit operation, please refer to the Functional Diagram of the IC and Figure 1. The LTC3703 uses voltage
mode control in which the duty ratio is controlled directly
by the error amplifier output and thus requires no current
sense resistor. The VFB pin receives the output voltage
feedback and is compared to the internal 0.8V reference by
the error amplifier, which outputs an error signal at the
COMP pin. When the load current increases, it causes a
drop in the feedback voltage relative to the reference. The
COMP voltage then rises, increasing the duty ratio until the
3703f
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LTC3703
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OPERATIO
(Refer to Functional Diagram)
output feedback voltage again matches the reference
voltage. In normal operation, the top MOSFET is turned on
when the RS latch is set by the on-chip oscillator and is
turned off when the PWM comparator trips and resets the
latch. The PWM comparator trips at the proper duty ratio
by comparing the error amplifier output (after being “compensated” by the line feedforward multiplier) to a sawtooth
waveform generated by the oscillator. When the top
MOSFET is turned off, the bottom MOSFET is turned on
until the next cycle begins or, if Pulse Skip Mode operation
is enabled, until the inductor current reverses as determined by the reverse current comparator. MAX and MIN
comparators ensure that the output never exceed ±5% of
nominal value by monitoring VFB and forcing the output
back into regulation quickly by either keeping the top
MOSFET off or forcing maximum duty cycle. The operation of its other features—fast transient response, outstanding line regulation, strong gate drivers, short-circuit
protection, and shutdown/soft-start—are described below.
Fast Transient Response
The LTC3703 uses a fast 25MHz op amp as an error
amplifier. This allows the compensation network to be
optimized for better load transient response. The high
bandwidth of the amplifier, along with high switching
frequencies and low value inductors, allow very high loop
crossover frequencies. The 800mV internal reference allows regulated output voltages as low as 800mV without
external level shifting amplifiers.
Line Feedforward Compensation
The LTC3703 achieves outstanding line transient response
using a patented feedforward correction scheme. With
this circuit the duty cycle is adjusted instantaneously to
changes in input voltage, thereby avoiding unacceptable
overshoot or undershoot. It has the added advantage of
making the DC loop gain independent of input voltage.
Figure 2 shows how large transient steps at the input have
little effect on the output voltage.
VOUT
50mV/DIV
VIN
20V/DIV
IL
2A/DIV
20µs/DIV
VOUT = 12V
ILOAD = 1A
25V TO 60V VIN STEP
3703 F02
Figure 2. Line Transient Performance
Strong Gate Drivers
The LTC3703 contains very low impedance drivers capable of supplying amps of current to slew large MOSFET
gates quickly. This minimizes transition losses and allows
paralleling MOSFETs for higher current applications. A
100V floating high side driver drives the top side MOSFET
and a low side driver drives the bottom side MOSFET (see
Figure 3). They can be powered from either a separate DC
supply or a voltage derived from the input or output
voltage (see MOSFET Driver Supplies section). The bottom side driver is supplied directly from the DRVCC pin.
The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during
each off cycle through an external diode from DRVCC when
the top MOSFET turns off. In Pulse Skip Mode operation,
where it is possible that the bottom MOSFET will be off for
an extended period of time, an internal counter guarantees
that the bottom MOSFET is turned on at least once every
10 cycles for 10% of the period to refresh the bootstrap
capacitor. An undervoltage lockout keeps the LTC3703
shut down unless this voltage is above 9V.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-thru.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Miller capacitance, even when the bottom driver is holding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-thru between the top side and bottom side
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(Refer to Functional Diagram)
MOSFETs can occur. To prevent this from occuring, the
bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V supply
is used on BGRTN, the switch node dV/dt could pull the
gate up 2V before the VGS of the bottom MOSFET has more
than 0V across it.
VIN
DRVCC
LTC3703
DRVCC
+
DB
CIN
BOOST
TG
cycle control set to 0%. As CSS continues to charge, the
duty cycle is gradually increased, allowing the output
voltage to rise. This soft-start scheme smoothly ramps the
output voltage to its regulated value, with no overshoot.
The RUN/SS voltage will continue ramping until it reaches
an internal 4V clamp. Then the MIN feedback comparator
is enabled and the LTC3703 is in full operation. When the
RUN/SS is low, the supply current is reduced to 50µA.
VOUT
CB
MT
SW
0V
SHUTDOWN START-UP
L
VOUT
BG
MB
OUTPUT VOLTAGE
IN REGULATION
COUT
BGRTN
0V TO –5V
3V
3703 F03
Figure 3. Floating TG Driver Supply and Negative BG Return
RUN/SS SOFT-STARTS
OUTPUT VOLTAGE AND
INDUCTOR CURRENT
VRUN/SS
1.4V
1V
MINIMUM
DUTY CYCLE
0V
Constant Frequency
The internal oscillator can be programmed with an external resistor connected from fSET to ground to run between
100kHz and 600kHz, thereby optimizing component size,
efficiency, and noise for the specific application. The
internal oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin and can lock to a
frequency in the 100kHz to 600kHz range. When locked to
an external clock, Pulse Skip Mode operation is automatically disabled. Constant frequency operation brings with it
a number of benefits: Inductor and capacitor values can be
chosen for a precise operating frequency and the feedback
loop can be similarly tightly specified. Noise generated by
the circuit will always be at known frequencies.
Subharmonic oscillation and slope compensation, common headaches with constant frequency current mode
switchers, are absent in voltage mode designs like the
LTC3703.
Shutdown/Soft-Start
The main control loop is shut down by pulling RUN/SS pin
low. Releasing RUN/SS allows an internal 4µA current
source to charge the soft-start capacitor CSS. When CSS
reaches 1V, the main control loop is enabled with the duty
CURRENT
LIMIT
MIN COMPARATOR ENABLED
4V
+
NORMAL OPERATION
LTC3703
POWER
ENABLE DOWN MODE
3703 F04
Figure 4. Soft-Start Operation in Start Up and Current Limit
Current Limit
The LTC3703 includes an onboard current limit circuit that
limits the maximum output current to a user-programmed
level. It works by sensing the voltage drop across the
bottom MOSFET and comparing that voltage to a userprogrammed voltage at the IMAX pin. Since the bottom
MOSFET looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current
flowing in it. In a buck converter, the average current in the
inductor is equal to the output current. This current also
flows through the bottom MOSFET during its on-time.
Thus by watching the drain-to-source voltage when the
bottom MOSFET is on, the LTC3703 can monitor the
output current. The LTC3703 senses this voltage and
inverts it to allow it to compare the sensed voltage (which
becomes more negative as peak current increases) with a
positive voltage at the IMAX pin. The IMAX pin includes a
12µA pull-up, enabling the user to set the voltage at IMAX
with a single resistor (RIMAX) to ground. See the Current
Limit Programming section for RIMAX selection.
3703f
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For maximum protection, the LTC3703 current limit consists of a steady-state limit circuit and an instantaneous
limit circuit. The steady-state limit circuit is a gm amplifier
that pulls a current from the RUN/SS pin proportional to
the difference between the SW and IMAX voltages. This
current begins to discharge the capacitor at RUN/SS,
reducing the duty cycle and controlling the output voltage
until the current regulates at the limit. Depending on the
size of the capacitor, it may take many cycles to discharge
the RUN/SS voltage enough to properly regulate the
output current. This is where the instantaneous limit
circuit comes into play. The instantaneous limit circuit is
a cycle-by-cycle comparator which monitors the bottom
MOSFET’s drain voltage and keeps the top MOSFET from
turning on whenever the drain voltage is 50mV above the
programmed max drain voltage. Thus the cycle-by-cycle
comparator will keep the inductor current under control
until the gm amplifier gains control.
cycles to maintain regulation. The frequency drops but
this further improves efficiency by minimizing gate charge
losses. In forced continuous mode, the bottom MOSFET is
always on when the top MOSFET is off, allowing the
inductor current to reverse at low currents. This mode is
less efficient due to resistive losses, but has the advantage
of better transient response at low currents, constant
frequency operation, and the ability to maintain regulation
when sinking current. See Figure 5 for a comparison of the
effect on efficiency at light loads for each mode. The
MODE/SYNC threshold is 0.8V ±7.5%, allowing the MODE/
SYNC to act as a feedback pin for regulating a second
winding. If the feedback voltage drops below 0.8V, the
LTC3703 reverts to continuous operation to maintain
regulation in the secondary supply.
100
The LTC3703 can operate in one of two modes selectable
with the MODE/SYNC pin—Pulse Skip Mode or forced
continuous mode. Pulse Skip Mode is selected when
increased efficiency at light loads is desired. In this mode,
the bottom MOSFET is turned off when inductor current
reverses to minimize the efficiency loss due to reverse
current flow. As the load is decreased (see Figure 6), the
duty cycle is reduced to maintain regulation until its
minimum on-time (~200ns) is reached. When the load
decreases below this point, the LTC3703 begins to skip
PULSE SKIP MODE
EFFICIENCY (%)
Pulse Skip Mode
90
VIN = 25V
80
VIN = 75V
70
60
VIN = 25V
50
VIN = 75V
40
30
20
FORCED CONTINUOUS
PULSE SKIP MODE
10
0
10
100
1000
LOAD (mA)
10000
3703 F05
Figure 5. Efficiency in Pulse Skip/Forced Continuous Modes
FORCED CONTINUOUS
DECREASING
LOAD
CURRENT
3703 F06
Figure 6. Comparison of Inductor Current Waveforms for Pulse Skip Mode and Forced Continuous Operation
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Buck or Boost Mode Operation
The LTC3703 has the capability of operating both as a
step-down (buck) and step-up (boost) controller. In boost
mode, output voltages as high as 80V can be tightly
regulated. With the INV pin grounded, the LTC3703 operates in buck mode with TG driving the main (top side)
switch and BG driving the synchronous (bottom side)
switch. If the INV pin is pulled above 2V, the LTC3703
operates in boost mode with BG driving the main (bottom
side) switch and TG driving the synchronous (top side)
switch. Internal circuit operation is very similar regardless
of the operating mode with the following exceptions: In
boost mode, Pulse Skip Mode operation is always disabled regardless of the level of the MODE/SYNC pin and
the line feedforward compensation is also disabled. The
overcurrent circuitry continues to monitor the load current
by looking at the drain voltage of the main (bottom side)
MOSFET. In boost mode, however, the peak MOSFET
current does not equal the load current but instead
ID = ILOAD/(1 – D). This factor needs to be taken into
account when programming the IMAX voltage.
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Operating Frequency
The choice of operating frequency and inductor value is a
trade off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses and gate charge losses. However, lower frequency operation requires more inductance for a given amount of ripple current, resulting in a
larger inductor size and higher cost. If the ripple current
is allowed to increase, larger output capacitors may be
required to maintain the same output ripple. For converters with high step-down VIN to VOUT ratios, another
consideration is the minimum on-time of the LTC3703
(see the Minimum On-time Considerations section). A
final consideration for operating frequency is that in
noise-sensitive communications systems, it is often desirable to keep the switching noise out of a sensitive
frequency band.
The LTC3703 uses a constant frequency architecture that
can be programmed over a 100kHz to 600kHz range with
a single resistor from the fSET pin to ground, as shown in
Figure 1. The nominal voltage on the fSET pin is 1.2V, and
the current that flows from this pin is used to charge and
discharge an internal oscillator capacitor. The value of
RSET for a given operating frequency can be chosen from
Figure 7 or from the following equation:
RSET (kΩ) =
7100
f(kHz ) – 25
1000
100
RSET (kΩ)
The basic LTC3703 application circuit is shown in
Figure␣ 1. External component selection is determined by
the input voltage and load requirements as explained in the
following sections. After the operating frequency is selected, RSET and L can be chosen. The operating frequency
and the inductor are chosen for a desired amount of ripple
current and also to optimize efficiency and component
size. Next, the power MOSFETs and D1 are selected based
on voltage, load and efficiency requirements. CIN is selected for its ability to handle the large RMS currents in the
converter and COUT is chosen with low enough ESR to
meet the output voltage ripple and transient specifications. Finally, the loop compensation components are
chosen to meet the desired transient specifications.
10
1
0
200
400
600
FREQUENCY (kHz)
800
1000
3703 F07
Figure 7. Timing Resistor (RSET) Value
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The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency in
the range of 100kHz to 600kHz (refer to the MODE/SYNC
Pin section for more details). In this synchronized mode,
Pulse Skip Mode operation is disabled. The clock high
level must exceed 2V for at least 25ns. As shown in
Figure␣ 8, the top MOSFET turn-on will follow the rising
edge of the external clock by a constant delay equal to onetenth of the cycle period.
2V TO 10V
MODE/
SYNC
tMIN = 25ns
0.8T
TG
T
T = 1/fO
D = 40%
ripple current occurs at the highest VIN. To guarantee that
ripple current does not exceed a specified maximum, the
inductor in buck mode should be chosen according to:
L≥

VOUT 
V
1 – OUT 

f ∆IL(MAX)  VIN(MAX) 
The inductor also has an affect on low current operation
when Pulse Skip Mode operation is enabled. The frequency begins to decrease when the output current drops
below the average inductor current at which the LTC3703
is operating at its tON(MIN) in discontinuous mode (see
Figure 6). Lower inductance increases the peak inductor
current that occurs in each minimum on-time pulse and
thus increases the output current at which the frequency
starts decreasing.
0.1T
Power MOSFET Selection
IL
3703 F08
Figure 8. MODE/SYNC Clock Input and Switching
Waveforms for Synchronous Operation
Inductor
The inductor in a typical LTC3703 circuit is chosen for a
specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the
ripple current. The inductor ripple current in the buck
mode is:
∆IL =
VOUT  VOUT 
1–

VIN 
(f)(L) 
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this however, requires a large inductor.
A reasonable starting point is to choose a ripple current
between 20% and 40% of IO(MAX). Note that the largest
The LTC3703 requires at least two external N-channel
power MOSFETs, one for the top (main) switch and one or
more for the bottom (synchronous) switch. The number,
type and “on” resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET will
be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in
applications that have an output voltage that is less than
1/3 of the input voltage. In applications where VIN >> VOUT,
the top MOSFETs’ “on” resistance is normally less important for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switching regulators.
Selection criteria for the power MOSFETs include the “on”
resistance RDS(ON), input capacitance, breakdown voltage
and maximum output current.
The most important parameter in high voltage applications is breakdown voltage BVDSS. Both the top and
bottom MOSFETs will see full input voltage plus any
additional ringing on the switch node across its drain-tosource during its off-time and must be chosen with the
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appropriate breakdown specification. Since many high
voltage MOSFETs have higher threshold voltages (typically, VGS(MIN) ≥ 6V), the LTC3703 is designed to be used
with a 9V to 15V gate drive supply (DRVCC pin).
For maximum efficiency, on-resistance RDS(ON) and input
capacitance should be minimized. Low RDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combination of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 9).
MainSwitchDutyCycle =
SynchronousSwitchDutyCycle =
MILLER EFFECT
a
2
 I

PMAIN = DMAX  MAX  (1 + δ)RDR(ON) +
 1 – DMAX 
 I

1
VOUT 2  MAX  (RDR )(C MILLER )•
 1 – DMAX 
2
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
+V
DS
–
–
3703 F09
Figure 9. Gate Charge Characteristic
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-tosource capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given VDS drain voltage, but can be
adjusted for different VDS voltages by multiplying by the
ratio of the application VDS to the curve specified VDS
values. A way to estimate the CMILLER term is to take the
change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage
specified. CMILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. CRSS
and COS are specified sometimes but definitions of these
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
VIN – VOUT
VIN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VIN
VGS
VOUT
VIN
PSYNC

1
1 
+

(f)
 VCC – VTH(IL) VTH(IL) 

1 
2
=
 (IMAX ) (1 + δ)RDS(0N)
 1 – DMAX 
where δ is the temperature dependency of RDS(ON), RDR is
the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
in drain potential in the particular application. VTH(IL) is the
data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain
current. CMILLER is the calculated capacitance using the
gate charge curve from the MOSFET data sheet and the
technique described above.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 25V, the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 25V, the transition losses
rapidly increase to the point that the use of a higher
RDS(ON) device with lower CMILLER actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, and
typically varies from 0.005/°C to 0.01/°C depending on
the particular MOSFET used.
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Multiple MOSFETs can be used in parallel to lower RDS(ON)
and meet the current and thermal requirements if desired.
The LTC3703 contains large low impedance drivers capable of driving large gate capacitances without significantly slowing transition times. In fact, when driving
MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (5Ω or less) to reduce noise and EMI caused by
the fast transitions.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead time and requiring a reverse recovery period that
could cost as much as 1% to 2% in efficiency. A 1A
Schottky diode is generally a good size for 3A to 5A
regulators. Larger diodes result in additional losses due to
their larger junction capacitance. The diode can be omitted
if the efficiency loss can be tolerated.
Input Capacitor Selection
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT/VIN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
ICIN(RMS)
 V

V
≅ IO(MAX) OUT  IN – 1
VIN  VOUT 
1/ 2
This formula has a maximum at VIN = 2VOUT, where IRMS
= IO(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that the ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
placed in parallel to meet size or height requirements in the
design.
Because tantalum and OS-CON capacitors are not available in voltages above 30V, for regulators with input
supplies above 30V, choice of input capacitor type is
limited to ceramics or aluminum electrolytics. Ceramic
capacitors have the advantage of very low ESR and can
handle high RMS current, however ceramics with high
voltage ratings (>50V) are not available with more than a
few microfarads of capacitance. Furthermore, ceramics
have high voltage coefficients which means that the capacitance values decrease even more when used at the
rated voltage. X5R and X7R type ceramics are recommended for their lower voltage and temperature coefficients. Another consideration when using ceramics is
their high Q which if not properly damped, may result in
excessive voltage stress on the power MOSFETs. Aluminum electrolytics have much higher bulk capacitance,
however, they have higher ESR and lower RMS current
ratings.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low
ESR and RMS current. If the RMS current cannot be
handled by the aluminum capacitors alone, when used
together, the percentage of RMS current that will be
supplied by the aluminum capacitor is reduced to approximately:
% IRMS,ALUM ≈
1
1 + (8fCRESR
)2
• 100%
where RESR is the ESR of the aluminum capacitor and C is
the overall capacitance of the ceramic capacitors. Using an
aluminum electrolytic with a ceramic also helps damp the
high Q of the ceramic, minimizing ringing.
Output Capacitor Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(∆VOUT) is approximately equal to:

1 
∆VOUT ≤ ∆IL  ESR +


8fC OUT 
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Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. ESR also has a significant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of COUT until the feedback loop in the LTC3703 can
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semiconductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electrolytic at a somewhat higher price. An additional ceramic
capacitor in parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special polymer and aluminum electrolytic capacitors are
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Several excellent surge-tested choices
are the AVX TPS and TPSV or the KEMET T510 series.
Aluminum electrolytic capacitors have significantly higher
ESR, but can be used in cost-driven applications providing
that consideration is given to ripple current ratings and
long term reliability. Other capacitor types include
Panasonic SP and Sanyo POSCAPs.
Output Voltage
The LTC3703 output voltage is set by a resistor divider
according to the following formula:
 R1
VOUT = 0.8V 1 + 
 R2
The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of ±1%. Tolerance of the feedback resistors will
add additional error to the output voltage. 0.1% to 1%
resistors are recommended.
MOSFET Driver Supplies (DRVCC and BOOST)
The LTC3703 drivers are supplied from the DRVCC and
BOOST pins (see Figure 3), which have an absolute
maximum voltage of 15V. If the main supply voltage, VIN,
is higher than 15V a separate supply with a voltage
between 9V and 15V must be used to power the drivers. If
a separate supply is not available, one can easily be
generated from the main supply using one of the circuits
shown in Figure␣ 10. If the output voltage is between 10V
and 15V, the output can be used to directly power the
drivers as shown in Figure 10a. If the output is below 10V,
Figure 10b shows an easy way to boost the supply voltage
to a sufficient level. This boost circuit uses the LT1613 in
a ThinSOTTM package and a chip inductor for minimal extra
area (<0.2 in2). Two other possible schemes are an extra
winding on the inductor (Figure 10c) or a capacitive
charge pump (Figure 10d). All the circuits shown in
Figure␣ 10 require a start-up circuit (Q1, D1 and R1) to
provide driver power at initial start-up or following a shortcircuit. The resistor R1 must be sized so that it supplies
sufficient base current and zener bias current at the lowest
expected value of VIN. When using an existing supply, the
supply must be capable of supplying the required gate
driver current which can be estimated from:
IDRVCC = (f)(QG(TOP) + QG(BOTTOM))
This equation for IDRVCC is also useful for properly sizing
the circuit components shown in Figure 10.
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFETs. Capacitor CB is charged through external
diode, DB, from the DRVCC supply when SW is low. When
the top side MOSFET is turned on, the driver places the C B
voltage across the gate-source of the top MOSFET. The
switch node voltage, SW, rises to VIN and the BOOST pin
follows. With the topside MOSFET on, the boost voltage
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D2
ZHCS400
VIN
VIN
+
C10
1µF
16V
1µF
+
CIN
12V
+
VIN
R17
110k
1%
VIN
TG
SW
DRVCC
BG
VIN
LT1613
SHDN
GND
TG
L1
VOUT
10V TO
15V
VCC
SW
COUT
DRVCC
BG
VOUT
L1
<10V
+
+
BGRTN
COUT
BGRTN
3703 F10a
3703 F10b
Figure 10a. VCC Generated from 10V < VOUT < 15V
Figure 10b. VCC Generated from VOUT < 10V
VIN (<40V)
VIN
+
+
1µF
CIN
+
OPTIONAL VCC
CONNECTION
10V < VSEC < 15V
CIN
12V
BAT85
12V
VIN
+
LTC3703
VCC
C9
4.7µF
6.3V
LTC3703
12V
VCC
SW
FB
CIN
LTC3703
R17
1M
1%
L2
10µH
TG1
VSEC
TG
T1
DRVCC
SW
FCB
BG1
GND
BGRTN
R1
0.22µF
VN2222LL
LTC3703
1µF
N
BAT85
VIN
BAT85
VOUT
1
VOUT
VCC
SW
DRVCC
BG
+
COUT
L1
+
COUT
R2
BGRTN
3703 F10c
Figure 10c. Secondary Output Loop and VCC Connection
is above the input supply: VBOOST = VIN + VDRVCC. The
value of the boost capacitor CB needs to be 100 times that
of the total input capacitance of the top side MOSFET(s).
The reverse breakdown of the external diode, DB, must be
greater than VIN(MAX). Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse
current to flow at full reverse voltage. If the reverse
current times reverse voltage exceeds the maximum
3703 F10d
Figure 10d. Capacitive Charge Pump for VCC (VIN < 40V)
allowable power dissipation, the diode may be damaged.
For best results, use an ultrafast recovery silicon diode
such as the BAS21.
An internal undervoltage lockout (UVLO) monitors the
voltage on DRVCC to ensure that the LTC3703 has sufficient gate drive voltage. If the DRVCC voltage falls below
the UVLO threshold, the LTC3703 shuts down and the gate
drive outputs remain low.
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Bottom MOSFET Source Supply (BGRTN)
The bottom gate driver, BG, switches from DRVCC to BGRTN
where BGRTN can be a voltage between ground and –5V.
Why not just keep it simple and always connect BGRTN to
ground? In high voltage switching converters, the switch
node dV/dt can be many volts/ns, which will pull up on the
gate of the bottom MOSFET through its Miller capacitance.
If this Miller current, times the internal gate resistance of
the MOSFET plus the driver resistance, exceeds the threshold of the FET, shoot-through will occur. By using a negative supply on BGRTN, the BG can be pulled below ground
when turning the bottom MOSFET off. This provides a few
extra volts of margin before the gate reaches the turn-on
threshold of the MOSFET. Be aware that the maximum
voltage difference between DRVCC and BGRTN is 15V. If,
for example, VBGRTN = –2V, the maximum voltage on
DRVCC pin is now 13V instead of 15V.
Current Limit Programming
Programming current limit on the LTC3703 is straight
forward. The IMAX pin sets the current limit by setting the
maximum allowable voltage drop across the bottom
MOSFET. The voltage across the MOSFET is set by its onresistance and the current flowing in the inductor, which
is the same as the output current. The LTC3703 current
limit circuit inverts the negative voltage across the MOSFET
before comparing it to the voltage at IMAX, allowing the
current limit to be set with a positive voltage.
To set the current limit, calculate the expected voltage
drop across the bottom MOSFET at the maximum desired
current and maximum junction temperature:
VPROG = (ILIMIT)(RDS(ON))(1 + δ)
where δ is explained in the MOSFET Selection section.
VPROG is then programmed at the IMAX pin using the
internal 12µA pull-up and an external resistor:
RIMAX = VPROG/12µA
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
For best results, use a VPROG voltage between 100mV and
500mV. Values outside of this range may give less accurate current limit. The current limit can also be disabled by
floating the IMAX pin.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
In a typical LTC3703 circuit, the feedback loop consists of
the modulator, the external inductor, the output capacitor
and the feedback amplifier with its compensation network.
All of these components affect loop behavior and must be
accounted for in the loop compensation. The modulator
consists of the internal PWM generator, the output MOSFET
drivers and the external MOSFETs themselves. From a
feedback loop point of view, it looks like a linear voltage
transfer function from COMP to SW and has a gain roughly
equal to the input voltage. It has fairly benign AC behavior
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency.
The external inductor/output capacitor combination makes
a more significant contribution to loop behavior. These
components cause a second order LC roll off at the output,
with the attendant 180° phase shift. This rolloff is what
filters the PWM waveform, resulting in the desired DC
output voltage, but the phase shift complicates the loop
compensation if the gain is still higher than unity at the
pole frequency. Eventually (usually well above the LC pole
frequency), the reactance of the output capacitor will
approach its ESR and the rolloff due to the capacitor
will stop, leaving 6dB/octave and 90° of phase shift
(Figure 11).
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FREQ
–6dB/OCT
–6dB/OCT
–
OUT
RB
–90
PHASE
–6dB/OCT
GAIN
–12dB/OCT
0
C1
R2
R1
FB
GAIN (dB)
GAIN (dB)
GAIN
IN
PHASE (DEG)
PHASE (DEG)
AV
C2
0
FREQ
+
VREF
–90
–180
–180
PHASE
–270
–270
–360
–360
3703 F11
3703 F13
Figure 13. Type 2 Schematic and Transfer Function
So far, the AC response of the loop is pretty well out of the
user’s control. The modulator is a fundamental piece of the
LTC3703 design and the external L and C are usually
chosen based on the regulation and load current requirements without considering the AC loop response. The
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and something less than 360° phase shift at the point that the loop
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 12). This “Type
1” configuration is stable but transient response is less
than exceptional if the LC pole is at a low frequency.
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
for an extended frequency range. LTC3703 circuits using
conventional switching grade electrolytic output capacitors can often get acceptable phase margin with Type 2
compensation.
C1
IN
R1
FB
–6dB/OCT
OUT
VREF
GAIN
–
RB
PHASE (DEG)
GAIN (dB)
Figure 11. Transfer Function of Buck Modulator
0
FREQ
+
–90
–180
PHASE
–270
“Type 3” loops (Figure 14) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC3703
circuits using low ESR tantalum or OS-CON output capacitors need Type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
–360
IN
GAIN (dB)
C3
Figure 12. Type 1 Schematic and Transfer Function
R1
Figure 13 shows an improved “Type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of
phase shift. This allows the loop to remain stable with 90°
more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
R3
FB
R2
C1
–
VREF
–6dB/OCT
GAIN
OUT
RB
PHASE (DEG)
C2
3703 F12
+6dB/OCT
–6dB/OCT
0
FREQ
+
–90
–180
PHASE
–270
–360
3703 F14
Figure 14. Type 3 Schematic and Transfer Function
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Feedback Component Selection
Selecting the R and C values for a typical Type 2 or Type␣ 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable performance with similar power components, but can be way off
if even one major power component is changed significantly. Applications that require optimized transient response will require recalculation of the compensation
values specifically for the circuit in question. The underlying mathematics are complex, but the component values
can be calculated in a straightforward manner if we know
the gain and phase of the modulator at the crossover
frequency.
Modulator gain and phase can be measured directly from
a breadboard or can be simulated if the appropriate
parasitic values are known. Measurement will give more
accurate results, but simulation can often get close enough
to give a working system. To measure the modulator gain
and phase directly, wire up a breadboard with an LTC3703
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
the LTC3703, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple Type 1 loop, with a 10k resistor from
VOUT to FB and a 0.1µF feedback capacitor from COMP to
FB. Choose the bias resistor (RB) as required to set the
desired output voltage. Disconnect RB from ground and
connect it to a signal generator or to the source output of
a network analyzer to inject a test signal into the loop.
Measure the gain and phase from the COMP pin to the
output node at the positive terminal of the output capacitor. Make sure the analyzer’s input is AC coupled so that
the DC voltages present at both the COMP and VOUT nodes
don’t corrupt the measurements or damage the analyzer.
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and generate an AC plot of V(VOUT )/V(COMP) in dB and phase of
VOUT in degrees. Refer to your SPICE manual for details of
how to generate this plot.
*3703 modulator gain/phase
*2003 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other
SPICE simulators
*MOSFETs
rfet mod sw 0.02
;MOSFET rdson
*inductor
lext sw out1 10u
rl out1 out 0.015
;inductor value
;inductor series R
*output cap
cout out out2 540u
resr out2 0 0.01
;capacitor value
;capacitor ESR
*3703 internals
emod mod 0 value = {57*v(comp)}
;3703multiplier
vstim comp 0 0 ac 1 ;ac stimulus
.ac dec 100 1k 1meg
.probe
.end
With the gain/phase plot in hand, a loop crossover frequency can be chosen. Usually the curves look something
like Figure 11. Choose the crossover frequency in the
rising or flat parts of the phase curve, beyond the external
LC poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be -GAIN to make the loop gain at 0dB at this
frequency. Now calculate the needed phase boost, assuming 60° as a target phase margin:
BOOST = – (PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
Finally, choose a convenient resistor value for R1 (10k is
usually a good value). Now calculate the remaining values:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
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TYPE 2 Loop:
 BOOST

K = tan
+ 45°
 2

1
2π • f • G • K • R1
C1 = C 2 K2 − 1
C2 =
(
)
K
2π • f • C1
VREF (R1)
RB =
VOUT − VREF
R2 =
TYPE 3 Loop:
 BOOST

K = tan2 
+ 45°
 4

1
2π • f • G • R1
C1 = C 2 K − 1
C2 =
( )
K
2π • f • C1
R1
R3 =
K −1
1
C3 =
2πf K • R3
VREF (R1)
RB =
VOUT − VREF
R2 =
Boost Converter Design
The following sections discuss the use of the LTC3703 as
a step-up (boost) converter. In boost mode, the LTC3703
can step-up output voltages as high as 80V. These sections discuss only the design steps specific to a boost
converter. For the design steps common to both a buck
and a boost, see the applicable section in the buck mode
section. An example of a boost converter circuit is shown
in the Typical Applications section. To operate the LTC3703
in boost mode, the INV pin should be tied to the VCC
voltage (or a voltage above 2V). Note that in boost mode,
pulse-skip operation and the line feedforward compensation are disabled.
For a boost converter, the duty cycle of the main switch is:
VOUT – VIN
VOUT
For high VOUT to VIN ratios, the maximum VOUT is limited
by the LTC3703’s maximum duty cycle which is typically
93%. The maximum output voltage is therefore:
D=
VOUT (MAX) =
VIN(MIN)
≅ 14VIN(MIN)
1 – DMAX
Boost Converter: Inductor Selection
In a boost converter, the average inductor current equals
the average input current. Thus, the maximum average
inductor current can be calculated from:
IL(MAX) =
IO(MAX)
VO
= IO(MAX) •
1 − DMAX
VIN(MIN)
Similar to a buck converter, choose the ripple current to be
20% to 40% of IL(MAX). The ripple current amplitude then
determines the inductor value as follows:
L=
VIN(MIN)
• DMAX
∆IL • f
The minimum required saturation current for the inductor
is:
IL(SAT) > IL(MAX) + ∆IL/2
Boost Converter: Power MOSFET Selection
For information about choosing power MOSFETs for a
boost converter, see the Power MOSFET Selection section
for the buck converter, since MOSFET selection is similar.
However, note that the power dissipation equations for the
MOSFETs at maximum output current in a boost converter
are:
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2
 I

PMAIN = DMAX  MAX  1 + δ RDS(ON) +
 1 – DMAX 

2 I
1
VOUT  MAX  RDR C MILLER •
2
 1 – DMAX 

1
1 
+

f
 VCC – VTH(IL) VTH(IL) 

2
1 
PSYNC = – 
 IMAX 1 + δ RDS(ON)
 1 – DMAX 
( )
( )(
)
()
( )( )
Boost Converter: Output Capacitor Selection
In boost mode, the output capacitor requirements are
more demanding due to the fact that the current waveform
is pulsed instead of continuous as in a buck converter. The
choice of component(s) is driven by the acceptable ripple
voltage which is affected by the ESR, ESL and bulk
capacitance as shown in Figure 15. The total output ripple
voltage is:

1
ESR 
∆VOUT = IO(MAX) 
+

 f • C OUT 1 – DMAX 
where the first term is due to the bulk capacitance and
second term due to the ESR.
∆VCOUT
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
Figure 15. Output Voltage Ripple
Waveform for a Boost Converter
The choice of output capacitor is driven also by the RMS
ripple current requirement. The RMS ripple current is:
IRMS(COUT ) ≈ IO(MAX) •
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical than
the output capacitor, due to the fact that the inductor is in
series with the input and the input current waveform is
continuous. The input voltage source impedance determines the size of the input capacitor, which is typically in
the range of 10µF to 100µF. A low ESR capacitor is
recommended though not as critical as for the output
capacitor.
The RMS input capacitor ripple current for a boost converter is:
IRMS(CIN) = 0.3 •
VIN(MIN)
• DMAX
L• f
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!
Boost Converter: Current Limit Programming
VOUT
(AC)
∆VESR
discussion in Input Capacitor section for the buck converter). With this combination, the ripple voltage can be
improved significantly. The low ESR ceremic capacitor
will minimize the ESR step, while the electrolytic will
supply the required bulk capacitance.
VO – VIN(MIN)
VIN(MIN)
At lower output voltages (less than 30V), it may be
possible to satisfy both the output ripple voltage and RMS
ripple current requirements with one or more capacitors of
a single capacitor type. However, at output voltages above
30V where capacitors with both low ESR and high bulk
capacitance are hard to find, the best approach is to use a
combination of aluminum and ceramic capacitors (see
The LTC3703 provides current limiting in boost mode by
monitoring the VDS of the main switch during its on-time
and comparing it to the voltage at IMAX. To set the current
limit, calculate the expected voltage drop across the
MOSFET at the maximum desired inductor current and
maximum junction temperature. The maximum inductor
current is a function of both duty cycle and maximum load
current, so the limit must be set for the maximum expected
duty cycle (minimum VIN) in order to ensure that the
current limit does not kick in at loads < IO(MAX):
VPROG =
IO(MAX)
RDS(ON) (1 + δ)
1 – DMAX
 V

=  OUT  IO(MAX) • RDS(ON) (1 + δ)
 VIN(MIN) 
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Once VPROG is determined, RIMAX is chosen as follows:
RIMAX = VPROG/12µA
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where VOUT > VIN.
For hard shorts, the inductor current is limited only by the
input supply capability. Refer to Current Limit Programming for buck mode for further considerations for current
limit programming.
Since significant phase shift begins at frequencies above
the dominant LC pole, choose a crossover frequency no
greater than about half this pole frequency. The gain of the
compensation network should equal –GAIN at this frequency so that the overall loop gain is 0dB here. The
compensation component to achieve this, using a Type 1
amplifier (see Figure 12), is:
G = 10–GAIN/20
C1 = 1/(2π • f • G • R1)
Boost Converter: Feedback Loop/Compensation
Compensating a voltage mode boost converter is unfortunately more difficult than for a buck converter. This is due
to an additional right-half plane (RHP) zero that is present
in the boost converter but not in a buck. The additional
phase lag resulting from the RHP zero is difficult if not
impossible to compensate even with a Type 3 loop, so the
best approach is usually to roll off the loop gain at a lower
frequency than what could be achievable in buck converter.
A typical gain/phase plot of a voltage-mode boost converter is shown in Figure 16. The modulator gain and
phase can be measured as described for a buck converter
or can be estimated as follows:
GAIN (COMP-to-VOUT DC gain) = 20Log(VOUT2/VIN)
Dominant Pole: fP =
1
VIN
•
VOUT 2π LC
GAIN
(dB)
AV
Run/Soft-Start Function
The RUN/SS pin is a multipurpose pin that provide a softstart function and a means to shut down the LTC3703.
Soft-start reduces the input supply’s surge current by
gradually increasing the duty cycle and can also be used
for power supply sequencing.
Pulling RUN/SS below 1V puts the LTC3703 into a low
quiescent current shutdown (IQ ≅ 50µA). This pin can be
driven directly from logic as shown in Figure 17. Releasing
the RUN/SS pin allows an internal 4µA current source to
charge up the soft-start capacitor CSS. When the voltage
on RUN/SS reaches 1V, the LTC3703 begins operating at
its minimum on-time. As the RUN/SS voltage increases
from 1V to 3V, the duty cycle is allowed to increase from
0% to 100%. The duty cycle control minimizes input
supply inrush current and elimates output voltage overshoot at start-up and ensures current limit protection even
with a hard short. The RUN/SS voltage is internally clamped
at 4V.
PHASE
(DEG)
GAIN
RUN/SS
2V/DIV
–12dB/OCT
0
PHASE
0
VOUT
5V/DIV
–90
IL
2A/DIV
–180
3703 F16
Figure 16. Transfer Function of Boost Modulator
VIN = 50V
ILOAD = 2A
CSS = 0.01µF
2ms/DIV
3703 F17
Figure 17. LTC3703 Startup Operation
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If RUN/SS starts at 0V, the delay before starting is approximately:
1V
C SS = (0.25s / µF )C SS
4µA
plus an additional delay, before the output will reach its
regulated value, of:
tDELAY,START =
3V – 1V
C SS = (0.5s / µF )C SS
4µA
The start delay can be reduced by using diode D1 in
Figure 18.
tDELAY,REG ≥
3.3V
OR 5V
RUN/SS
RUN/SS
D1
CSS
CSS
3703 F18
Figure 18. RUN/SS Pin Interfacing
MODE/SYNC Pin (Operating Mode and Secondary
Winding Control)
The MODE/SYNC pin is a dual function pin that can be used
for enabling or disabling Pulse Skip Mode operation and
also as an external clock input for synchronizing the
internal oscillator (see next section). Pulse Skip Mode is
enabled when the MODE/SYNC pin is above 0.8V and is
disabled, i.e. forced continuous, when the pin is below
0.8V.
In addition to providing a logic input to force continuous
operation and external synchronization, the MODE/SYNC
pin provides a means to regulate a flyback winding output
as shown in Figure 10c. The auxiliary output is taken from
a second winding on the core of the inductor, converting
it to a transformer. The auxiliary output voltage is set by
the main output voltage and the turns ratio of the extra
winding to the primary winding as follows:
VSEC ≈ (N + 1)VOUT
Since the secondary winding only draws current when the
synchronous switch is on, load regulation at the auxiliary
output will be relatively good as long as the main output is
running in continuous mode. As the load on the primary
output drops and the LTC3703 switches to Pulse Skip
Mode operation, the auxiliary output may not be able to
maintain regulation, especially if the load on the auxiliary
output remains heavy. To avoid this, the auxiliary output
voltage can be divided down with a conventional feedback
resistor string with the divided auxiliary output voltage fed
back to the MODE/SYNC pin. The MODE/SYNC threshold
is trimmed to 800mV with 20mV of hysteresis, allowing
precise control of the auxiliary voltage and is set as
follows:
 R1
VSEC(MIN) ≈ 0.8V 1 + 
 R2
where R1 and R2 are shown in Figure 10c.
If the LTC3703 is operating in Pulse Skip Mode and the
auxiliary output voltage drops below VSEC(MIN), the MODE/
SYNC pin will trip and the LTC3703 will resume continuous operation regardless of the load on the main output.
Thus, the MODE/SYNC pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary winding. With the loop
in continuous mode (MODE/SYNC < 0.8V), the auxiliary
outputs may nominally be loaded without regard to the
primary output load.
The following table summarizes the possible states available on the MODE/SYNC pin:
Table 1.
MODE/SYNC Pin
Condition
DC Voltage: 0V to 0.75V
Forced Continuous
Current Reversal Enabled
DC Voltage: ≥ 0.87V
Pulse Skip Mode Operation
No Current Reversal
Feedback Resistors
Regulating a Secondary Winding
Ext. Clock: 0V to ≥ 2V
Forced Continuous
No Current Reversal
MODE/SYNC Pin (External Synchronization)
The internal LTC3703 oscillator can be synchronized to an
external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2VP-P. The internal oscillator
locks to the external clock after the second clock transition
is received. When external synchronization is detected,
LTC3703 will operate in forced continuous mode. If an
external clock transition is not detected for three successive periods, the internal oscillator will revert to the
frequency programmed by the RSET resistor. The internal
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oscillator can synchronize to frequencies between 100kHz
and 600kHz, independent of the frequency programmed
by the RSET resistor. However, it is recommended that an
RSET resistor be chosen such that the frequency programmed by the RSET resistor is close to the expected
frequency of the external clock. In this way, the best
converter operation (ripple, component stress, etc) is
achieved if the external clock signal is lost.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC3703 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
V
tON = OUT > tON(MIN)
VIN • f
where tON(MIN) is typically 200ns.
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3703 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency operation is acceptable, the on-time can be increased above
tON(MIN) for the same step-down ratio.
Pin Clearance/Creepage Considerations
The LTC3703 is available in two packages (GN16 and G28)
both with identical functionality. The GN16 package gives
the smallest size solution, however the 0.013” (minimum)
space between pins may not provide sufficient PC board
trace clearance between high and low voltage pins in
higher voltage applications. Where clearance is an issue,
the G28 package should be used. The G28 package has 4
unconnected pins between the all adjacent high voltage
and low voltage pins, providing 5(0.0106”) = 0.053”
clearance which will be sufficient for most applications up
to 100V. For more information, refer to the printed circuit
board design standards described in IPC-2221
(www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703 circuits: 1) LTC3703 VCC current, 2)
MOSFET gate current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. VCC Supply current. The VCC current is the DC supply
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703. Total
supply current is typically about 2.5mA and usually results
in a small (<1%) loss which is proportional to VCC.
2. DRVCC current is MOSFET driver current. This current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge QG moves from DRVCC to
ground. The resulting dQ/dt is a current out of the DRVCC
supply. In continuous mode, IDRVCC = f(QG(TOP) + QG(BOT)),
where QG(TOP) and QG(BOT) are the gate charges of the top
and bottom MOSFETs.
3. I2R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with the
DCR resistance of L to obtain I2R losses. For example, if
each RDS(ON) = 25mΩ and RL = 25mΩ, then total resistance is 50mΩ. This results in losses ranging from 1% to
5% as the output current increases from 1A to 5A for a 5V
output.
4. Transition losses apply only to the topside MOSFET in
buck mode and they become significant when operating at
3703f
25
LTC3703
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APPLICATIO S I FOR ATIO
higher input voltages (typically 20V or greater). Transition
losses can be estimated from the second term of the PMAIN
equation found in the Power MOSFET Selection section.
The transition losses can become very significant at the
high end of the LTC3703 operating voltage range. To
improve efficiency, one may consider lowering the frequency and/or using MOSFETs with lower CRSS at the
expense of higher RDS(ON).
Other losses including CIN and COUT ESR dissipative
losses, Schottky conduction losses during dead-time, and
inductor core losses generally account for less than 2%
total additional loss.
Transient Response
Due to the high gain error amplifier and line feedforward
compensation of the LTC3703, the output accuracy due to
DC variations in input voltage and output load current will
be almost negligible. For the few cycles following a load
transient, however, the output deviation may be larger
while the feedback loop is responding. Consider a typical
48V input to 5V output application circuit, subjected to a
1A to 5A load transient. Initially, the loop is in regulation
and the DC current in the output capacitor is zero. Suddenly, an extra 4A (= 5A-1A) flows out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A) • (RESR) voltage step
at the output; with a typical 0.015Ω output capacitor ESR,
this is a 60mV step at the output.
The feedback loop will respond and will move at the bandwidth allowed by the external compensation network
towards a new duty cycle. If the unity gain crossover frequency is set to 50kHz, the COMP pin will get to 60% of the
way to 90% duty cycle in 3µs. Now the inductor is seeing
43V across itself for a large portion of the cycle and its
current will increase from 1A at a rate set by di/dt = V/L. If
the inductor value is 10µH, the peak di/dt will be 43V/10µH
or 4.3A/µs. Sometime in the next few micro-seconds after
the switch cycle begins, the inductor current will have
risen to the 5A level of the load current and the output
voltage will stop dropping. At this point, the inductor current will rise somewhat above the level of the output current to replenish the charge lost from the output capacitor
during the load transient. With a properly compensated
loop, the entire recovery time will be inside of 10µs.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
choose a low ESR capacitor and/or parallel multiple capacitors at the output. The capacitance value accounts for
the rest of the voltage drop until the inductor current rises.
With most output capacitors, several devices paralleled to
get the ESR down will have so much capacitance that this
drop term is negligible. Ceramic capacitors are an exception; a small ceramic capacitor can have suitably low ESR
with relatively small values of capacitance, making this
second drop term more significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on transient recovery time, the time it takes the LTC3703 to
recover after the output voltage has dropped due to a load
step. Optimizing loop compensation entails maintaining
the highest possible loop bandwidth while ensuring loop
stability. The feedback component selection section describes in detail the techniques used to design an optimized Type 3 feedback loop, appropriate for most LTC3703
systems.
Measurement Techniques
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and generating a suitable transient to test the circuit. Output measurements should be taken with a scope probe directly
across the output capacitor. Proper high frequency probing techniques should be used. In particular, don’t use the
6" ground lead that comes with the probe! Use an adapter
that fits on the tip of the probe and has a short ground clip
to ensure that inductance in the ground path doesn’t cause
a bigger spike than the transient signal being measured.
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
3703f
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LTC3703
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APPLICATIO S I FOR ATIO
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3703 and the transient generator
must be minimized.
Figure 19 shows an example of a simple transient generator. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
to get the desired value. This gives a noninductive resistive
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC3703
circuits. Solder the MOSFET and the resistor(s) as close to
the output of the LTC3703 circuit as possible and set up
the signal generator to pulse at a 100Hz rate with a 5% duty
cycle. This pulses the LTC3703 with 500µs transients10ms
apart, adequate for viewing the entire transient recovery
time for both positive and negative transitions while keeping the load resistor cool.
LTC3703
VOUT
RLOAD
IRFZ44 OR
EQUIVALENT
PULSE
GENERATOR
50Ω
0V TO 10V
100Hz, 5%
DUTY CYCLE
Next, verify that the minimum on-time is not violated. The
minimum on-time occurs at maximum VIN:
tON(MIN) =
VOUT
VIN(MIN) (f)
=
12
= 667ns
72(250kHz)
which is above the LTC3703’s 200ns minimum on-time.
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
72V(max) plus any ringing, choose a 100V MOSFET to
provide a margin of safety. Si7456DP has a 100V BVDSS,
RDS(ON) = 25mΩ(max), δ = 0.009/°C, CMILLER = (19nC –
10nC)/50V = 180pF, VGS(MILLER) = 4.7V, θJA = 20°C/W.
The power dissipation can be estimated at maximum input
voltage, assuming a junction temperature of 100°C (30°C
above an ambient of 70°C):
12
(10)2 [1 + 0.009(100 – 25)](0.025)
72
1
1
 10

+ (72)2   (2)(180pF )• 
+
 (250k)
 2
 10 – 4.7 4.7 
= 0.70W + 0.94 W = 1.64 W
PMAIN =
And double check the assumed TJ in the MOSFET:
TJ = 70°C + (1.64W)(20°C/W) = 103°C
3703 F19
LOCATE CLOSE TO THE OUTPUT
Figure 19. Transient Load Generator
Design Example
As a design example, take a supply with the following
specifications: VIN = 36V to 72V (48V nominal), VOUT =
12V ±5%, IOUT(MAX) = 10A, f=250kHz. First, calculate RSET
to give the 250kHz operating frequency:
RSET = 7100/(250-25) = 31.6k
Next, choose the inductor value for about 40% ripple
current at maximum VIN:
L=
With 10µH inductor, ripple current will vary from 3.2A to
4A (32% to 40%) over the input supply range.
12V
 12 
 1 –  = 10µH
(250kHz)(0.4)(10A)  72
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period in
short circuit) as the top MOSFET, use two Si7456DP
MOSFETs on the bottom:
 72 − 12
PSYNC = 
 (10)2 [1 + 0.009(100 – 25)] •
 72 
 0.025

 = 1.74 W
 2 
TJ = 70°C + (1.74W)(20°C/W) = 105°C
Next, set the current limit resistor. Since IMAX = 10A, the
limit should be set such that the minimum current limit is
>10A. Minimum current limit occurs at maximum RDS(ON).
3703f
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APPLICATIO S I FOR ATIO
Using the above calculation for bottom MOSFET TJ, the
max RDS(ON) = (25mΩ/2) [1 + 0.009 (105-25)] = 21.5mΩ
Therefore, IMAX pin voltage should be set to (10A)(0.0215)
= 0.215V. The RSET resistor can now be chosen to be
0.215V/12µA = 18kΩ.
CIN is chosen for an RMS current rating of about 5A (IMAX/
2) at 85°C. For the output capacitor, two low ESR OSCON
capacitors (18mΩ each) are used to minimize output
voltage changes due to inductor current ripple and load
steps. The ripple voltage will be:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (4A)(0.018Ω/2)
= 36mV
However, a 0A to 10A load step will cause an output
voltage change of up to:
∆VOUT(STEP) = ∆ILOAD(ESR) = (10A)(0.009Ω)
= 90mV
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703. These items are also illustrated graphically in
the layout diagram of Figure 18. For layout of a Boost Mode
Converter, layout is similar with VIN and VOUT swapped.
Check the following in your layout:
1. Keep the signal and power grounds separate. The signal
ground consists of the LTC3703 GND pin, the ground
return of CVCC, and the (–) terminal of VOUT. The power
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRVCC capacitor. Connect the signal
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal of
the output capacitor as close as possible to the (–)
terminals of the input and DRVCC capacitor and away from
the Schottky loop described in (2).
2. The high di/dt loop formed by the top N-channel
MOSFET, the bottom MOSFET and the CIN capacitor
should have short leads and PC trace lengths to minimize
high frequency noise and voltage stress from inductive
ringing.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of CIN, and connect the source of the bottom side
MOSFET directly to the (–) terminal of CIN. This capacitor
provides the AC current to the MOSFETs.
4. Place the ceramic CDRVCC decoupling capacitor immediately next to the IC, between DRVCC and BGRTN. This
capacitor carries the MOSFET drivers’ current peaks.
Likewise the CB capacitor should also be next to the IC
between BOOST and SW.
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG). In
the layout shown in Figure 20, all the small signal components have been placed on one side of the IC and all of the
power components have been placed on the other. This
also helps keep the signal ground and power ground
isolated.
6. A separate decoupling capacitor for the supply, VCC, is
useful with an RC filter between the DRVCC supply and VCC
pin to filter any noise injected by the drivers. Connect this
capacitor close to the IC, between the VCC and GND pins
and keep the ground side of the VCC capacitor (signal
ground) isolated from the ground side of the DRVCC
capacitor (power ground).
7. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC3703 in order to
keep the high impedance FB node short.
3703f
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LTC3703
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APPLICATIO S I FOR ATIO
8. For applications with multiple switching power converters connected to the same input supply, make sure that the
input filter capacitor for the LTC3703 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple, and this could
interfere with the operation of the LTC3703. A few inches
of PC trace or wire (L ≅ 100nH) between CIN of the
LTC3703 and the actual source VIN should be sufficient to
prevent input noise interference problems.
VCC
VIN
DB
1
RSET
RC1
CC1
CC2
RMAX
5
6
7
CC3
8
R1
M1
15
FSET
BOOST
LTC3703
14
3
COMP
TG
CSS
RC2
16
2
4
R2
MODE/SYNC VIN
FB
SW
IMAX
VCC
INV
RUN/SS
GND
DRVCC
BG
BGRTN
+
CIN
CB
13
L1
12
+
RF
11
+
VOUT
COUT
10
CDRVCC
X5R
9
D1
M2
–
CVCC
X5R
3703 F18
Figure 20. LTC3703 Buck Converter Suggested Layout
3703f
29
LTC3703
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TYPICAL APPLICATIO S
36V-72V Input Voltage to 5V/10A Step-Down Converter with Pulse Skip Mode Enabled
VCC
9.3V TO 15V
+
RC1
120k
CC1
8pF
CC2
100pF
1
16
MODE/SYNC VIN
RSET
25k 2
15
FSET
BOOST
LTC3703
3
14
COMP
TG
RMAX 20k
R2
8.06k
1%
RC2
3.2k
CC3
260pF
VIN
DB
36V TO 72V
BAS21
22µF
25V
4
5
6
CSS
0.1µF
R1
42k
1%
7
8
FB
IMAX
INV
RUN/SS
GND
SW
VCC
DRVCC
BG
BGRTN
CIN
22µF
100V
×2
+
M1
Si7456DP
CB
0.1µF
13
L1
4.7µH
12
11
RF
10Ω
COUT
220µF
25V
×2
M2
Si7456DP
10
+
D1
MBR1100
CDRVCC
10µF
9
VOUT
5V
10A
CVCC
1µF
3703 TA01
Single Input Supply 12V/5A Output Step-Down Converter
100Ω
10k
FZT600
*
VIN
15V TO 80V
12V
+
1
RSET 25k
RC1
22k
CC1
15pF
CC2
3300pF
RMAX 20k
R2
8.06k
1%
RC2
330Ω
CC3
1500pF
R1
113k
1%
16
4
5
7
8
DB
BAS21
+
15
FSET
BOOST
LTC3703
3
14
COMP
TG
6
CSS
0.1µF
MODE/SYNC VIN
2
22µF
25V
FB
IMAX
INV
RUN/SS
GND
SW
VCC
DRVCC
BG
BGRTN
CB
0.1µF
13
M1
Si7456DP
CIN
22µF
100V
×2
CMDSH-3
L1
15µH
12
11
RF
10Ω
M2
Si7456DP
10
9
CDRVCC
10µF
COUT
220µF
25V
×2
+
VOUT
12V
5A
D1
MBR1100
CVCC
1µF
*OPTIONAL ZENER PROVIDES UNDERVOLTAGE LOCKOUT ON INPUT SUPPLY, VUVLO ≅ 10 + VZ
3703 TA02
3703f
30
LTC3703
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.053 – .068
(1.351 – 1.727)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
0.42 ±0.03
7.40 – 8.20
(.291 – .323)
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
0.05
(.002)
G28 SSOP 0802
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3703f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3703
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TYPICAL APPLICATIO
5V to 12V/5A Synchronous Boost Converter
VCC
9.3V TO 15V
+
1
RSET 25k
CC1
0.1µF
RMAX 13k
R2
8.06k
1%
R1
113k
1%
DB
CMDSH-3
16
2
15
BOOST
FSET
LTC3703
3
14
TG
COMP
4
5
6
CSS
0.1µF
MODE/SYNC VIN
22µF
25V
7
8
FB
SW
IMAX
VCC
INV
RUN/SS
GND
DRVCC
BG
BGRTN
CB
0.1µF
13
M1
Si7348DP
COUT +
220µF
16V
×2
MBRS140T3
L1
3.3µH
12
11
RF
10Ω
M2
Si7366DP
10
9
VOUT
12V
5A
CIN
100µF
16V
VIN
3V TO 11V
+
CDRVCC
10µF
CVCC
1µF
3703 TA03
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3703f
32
Linear Technology Corporation
LT/TP 1203 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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●
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