19-0094; Rev 7a; 12/96 Microprocessor Supervisory Circuits ________________________Applications ♦ 200ms Power-OK/Reset Timeout Period ♦ 1µA Standby Current, 30µA Operating Current ♦ On-Board Gating of Chip-Enable Signals, 10ns Max Delay ♦ MaxCap™ or SuperCap™ Compatible ♦ Guaranteed RESET Assertion to VCC = +1V ♦ Voltage Monitor for Power-Fail or Low-Battery Warning ♦ Power-Fail Accuracy Guaranteed to ±2% (MAX800L/M) ♦ Available in 16-Pin Narrow SO and Plastic DIP Packages ______________Ordering Information Computers Controllers PART TEMP. RANGE Intelligent Instruments MAX691ACPE 0°C to +70°C 16 Plastic DIP Automotive Systems MAX691ACSE MAX691ACWE MAX691AC/D 0°C to +70°C 0°C to +70°C 0°C to +70°C 16 Narrow SO 16 Wide SO Dice* Critical µP Power Monitoring __________Typical Operating Circuit +8V ____________________________Features 5V REGULATOR 0.1µF 3 VCC 1N4148 1 5 BATT ON VOUT VBATT CE OUT 2 12 CMOS RAM MAX691A 9 MAX693A CE IN 13 PFI MAX800L MAX800M GND WDI 7 NO CONNECTION 8 A0-A15 I/O 11 µP 10 NMI OSC SEL LOW LINE WDO 6 14 *MaxCap ADDRESS DECODE OSC IN PFO RESET SYSTEM STATUS INDICATORS MAX691AEPE -40°C to +85°C 16 Plastic DIP MAX691AESE -40°C to +85°C 16 Narrow SO MAX691AEWE -40°C to +85°C 16 Wide SO MAX691AEJE -40°C to +85°C 16 CERDIP MAX691AMJE -55°C to +125°C 16 CERDIP Ordering Information continued on last page. * Dice are specified at TA = +25 °C, DC parameters only. __________________Pin Configuration 0.47F* 4 PIN-PACKAGE 15 RESET TOP VIEW VBATT 1 16 RESET VOUT 2 15 RESET VCC 3 14 WDO GND 4 BATT ON 5 LOW LINE 6 MAX691A MAX693A MAX800L MAX800M OSC IN 7 13 CE IN 12 CE OUT 11 WDI 10 PFO OSC SEL 8 9 PFI AUDIBLE ALARM DIP/SO SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of The Carborundum Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX691A/MAX693A/MAX800L/MAX800M _______________General Description The MAX691A/MAX693A/MAX800L/MAX800M microprocessor (µP) supervisory circuits are pin-compatible upgrades to the MAX691, MAX693, and MAX695. They improve performance with 30µA supply current, 200ms typ reset active delay on power-up, and 6ns chipenable propagation delay. Features include write protection of CMOS RAM or EEPROM, separate watchdog outputs, backup-battery switchover, and a RESET output that is valid with VCC down to 1V. The MAX691A/ MAX800L have a 4.65V typical reset-threshold voltage, and the MAX693A/MAX800M’s reset threshold is 4.4V typical. The MAX800L/MAX800M guarantee power-fail accuracies to ±2%. MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC .......................................................................-0.3V to +6V VBATT...................................................................-0.3V to +6V All Other Inputs .....................................-0.3V to (VOUT + 0.3V) Input Current VCC Peak...........................................................................1.0A VCC Continuous.............................................................250mA VBATT Peak ..................................................................250mA VBATT Continuous ..........................................................25mA GND, BATT ON .............................................................100mA All Other Outputs ............................................................25mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW Narrow SO (derate 8.70mW/°C above +70°C) ...........696mW Wide SO (derate 9.52mW/°C above +70°C)...............762mW CERDIP (derate 10.00mW/°C above +70°C) ..............800mW Operating Temperature Ranges MAX69_AC_ _/MAX800_C_ _ .............................0°C to +70°C MAX69_AE_ _/MAX800_E_ _ ...........................-40°C to +85°C MAX69_AMJE ................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX691A, MAX800L: VCC = +4.75V to +5.5V, MAX693A, MAX800M: VCC = +4.5V to +5.5V, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONDITIONS MIN Operating Voltage Range, VCC, VBATT (Note 1) 0 IOUT = 25mA VOUT Output TYP VCC = 4.5V IOUT = 250mA VCC-to-VOUT On-Resistance VCC = 4.5V VOUT in Battery-Backup Mode VBATT-to-VOUT On-Resistance 5.5 V VCC - 0.02 VCC - 0.2 VCC - 0.05 VCC - 0.3 MAX69_AE, MAX800_C/E VCC - 0.2 VCC - 0.35 VCC - 0.17 VCC - 0.3V MAX69_AC, MAX800_C 0.8 1.2 MAX69_AE, MAX800_E 0.8 1.4 0.8 1.6 MAX69_A/M VBATT = 4.5V, IOUT = 20mA VBATT = 2.8V, IOUT = 10mA VBATT = 2.0V, IOUT = 5mA VBATT = 4.5V VBATT = 2.8V VBATT = 2.0V VCC > VBATT - 1V Supply Current in Battery-Backup Mode (Excludes IOUT) (Note 2) VCC < VBATT - 1.2V VBATT = 2.8V TA = +25°C VBATT Standby Current (Note 3) VBATT + 0.2V ≤ VCC TA = +25°C TA = TMIN + TMIN Battery Switchover Threshold Power-up Power-down VBATT - 0.3 VBATT - 0.25 VBATT - 0.15 Ω V 15 25 30 Ω 30 100 µA 0.04 1 µA TA = TMIN + TMIN TA = TMIN + TMIN V VCC - 0.40 MAX69_AC/AE, MAX800_C/E Supply Current in Normal Operating Mode (Excludes IOUT) 2 UNITS MAX69_AC MAX69_A/M IOUT = 210mA MAX 5 -0.1 -1.0 0.02 0.02 VBATT + 0.3 VBATT - 0.3 _______________________________________________________________________________________ µA V Microprocessor Supervisory Circuits (MAX691A, MAX800L: VCC = +4.75V to +5.5V, MAX693A, MAX800M: VCC = +4.5V to +5.5V, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONDITIONS MIN Battery Switchover Hysteresis TYP MAX 60 1 100 RESET AND WATCHDOG TIMER MAX691A, MAX800L 4.50 4.65 4.75 MAX693A, MAX800M 4.25 4.40 MAX800L, TA = +25°C, VCC falling 4.55 4.70 MAX800M, TA = +25°C, VCC falling 4.30 4.45 BATT ON Output Short-Circuit Current Reset Threshold Voltage ISINK = 3.2mA ISINK = 25mA Sink current Source current mV 0.1 0.7 60 15 BATT ON Output Low Voltage Reset Threshold Hysteresis VCC to RESET Delay Power-down LOW LINE-to-RESET Delay Reset Active Timeout Period, Power-up Internal Oscillator 140 Reset Active Timeout Period, Power-up External Clock (Note 4) 1.0 70 Watchdog Timeout Period, External Clock (Note 4) Minimum Watchdog Input Pulse Width VIL = 0.8V, VIH = 0.75 x VCC 100 RESET Output Voltage ISINK = 50µA, VCC = 1V, VBATT = 0V, VCC falling ISINK = 3.2mA, VCC = 4.25V ISOURCE = 1.6mA, VCC = 5V LOW LINE Output Voltage ISINK = 3.2mA, VCC = 4.25V ISOURCE = 1µA, VCC = 5V LOW LINE Output Short-Circuit Current Output source current WDO Output Voltage ISINK = 3.2mA ISOURCE = 500µA, VCC = 5V WDO Output Short-Circuit Current Output source current WDI Threshold Voltage (Note 6) WDI Input Current VIH VIL WDI = 0V WDI = VOUT 4.50 V mA µA V 15 mV 80 µs 800 ns 200 280 1.6 100 4096 1024 ms Clock Cycles 2.25 140 sec ms Clock Cycles ns 0.004 0.1 0.3 0.4 V 7 20 mA 3.5 – RESET Output Short-Circuit Output source current Current RESET Output Voltage Low ISINK = 3.2mA (Note 5) 0.4 1.5 2048 Long period Short period Long period Short period Watchdog Timeout Period, Internal Oscillator UNITS 0.1 0.4 V 0.4 3.5 1 15 100 0.4 3.5 3 10 0.75 x VCC 0.8 -50 -10 20 50 V µA V mA V µA _______________________________________________________________________________________ 3 MAX691A/MAX693A/MAX800L/MAX800M ELECTRICAL CHARACTERISTICS (continued) MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits ELECTRICAL CHARACTERISTICS (continued) (MAX691A, MAX800L: VCC = +4.75V to +5.5V, MAX693A, MAX800M: VCC = +4.5V to +5.5V, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX 1.2 1.25 1.3 1.225 1.25 1.275 ±0.01 ±25 UNITS POWER-FAIL COMPARATOR PFI Input Threshold MAX69_AC/AE/AM, VCC = 5V MAX800_C/E, VCC = 5V PFI Leakage Current PFO Output Voltage PFO Output Short-Circuit Current PFI-to-PFO Delay ISINK = 3.2mA ISOURCE = 1µA, VCC = 5V Output source current 0.4 3.5 1 15 VIN = -20mV, VOD = 15mV 25 VIN = 20mV, VOD = 15mV 60 100 V nA V µA µs CHIP-ENABLE GATING CE IN Leakage Current Disable mode ±0.005 ±1 µA CE IN-to-CE OUT Resistance (Note 7) Enable mode 75 150 Ω CE OUT Short-Circuit Current (Reset Active) – Disable mode, CE OUT = 0V 0.75 2.0 mA CE IN-to-CE OUT Propagation Delay (Note 8) 50Ω source impedance driver, CLOAD = 50pF 6 10 ns 0.1 CE OUT Output Voltage High (Reset Active) VCC = 5V, IOUT = -100µA 3.5 VCC = 0V, VBATT = 2.8V, IOUT = 1µA 2.7 RESET-to-CE OUT Delay Power-down V 12 µs INTERNAL OSCILLATOR OSC IN Leakage Current OSC SEL = 0V 0.10 ±5 µA OSC IN Input Pull-Up Current OSC SEL = VOUT or floating, OSC IN = 0V 10 100 µA OSC SEL Input Pull-Up Current OSC SEL = 0V 10 100 µA OSC IN Frequency Range OSC SEL = 0V OSC IN External Oscillator Threshold Voltage VIH OSC IN Frequency with External Capacitor 50 VOUT - 0.3 kHz VOUT - 0.6 VIL 3.65 OSC SEL = 0V, COSC = 47pF 100 2.00 V kHz Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V. Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding IOUT typically goes to 10µA when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region. Note 3: “+” = battery-discharging current, “--” = battery-charging current. Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. Note 5: RESET is an open-drain output and sinks current only. Note 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function. Note 7: The chip-enable resistance is tested with VCC = +4.75V for the MAX691A/MAX800L and VCC = +4.5V for the MAX693A/MAX800M. CE IN = CE OUT = VCC / 2. Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. 4 _______________________________________________________________________________________ Microprocessor Supervisory Circuits 32 30 28 26 -30 0 30 60 90 120 1.5 1 0.5 150 40 -60 -30 0 30 60 90 120 -60 -30 150 90 120 150 180 VCC = 5V, VBATT = 0V 1.25 PFI THRESHOLD (V) 1.1 1.0 0.9 0.8 0 30 60 90 120 150 0.75 0.50 VCC = +5V, VBATT = 0V NO LOAD ON PFO 0 -60 -30 0 30 60 90 120 -60 150 -30 0 30 60 90 TEMPERATURE (°C) RESET THRESHOLD vs. TEMPERATURE RESET OUTPUT RESISTANCE vs. TEMPERATURE RESET DELAY vs. TEMPERATURE 4.55 4.50 4.45 4.40 MAX693A MAX800M 4.30 MAX691A TOC-08 500 VCC = 5V, VBATT = 2.8V SOURCING CURRENT 400 300 200 100 30 60 90 TEMPERATURE (°C) 120 150 220 150 120 150 VCC = 0V TO 5V STEP VBATT = 2.8V 210 200 190 180 VCC = 0V, VBATT = 2.8V SINKING CURRENT 0 0 230 RESET DELAY (ms) MAX691A MAX800L RESET OUTPUT RESISTANCE (Ω) 4.70 600 120 MAX691A TOC-09 TEMPERATURE (°C) MAX691A TOC-07 TEMPERATURE (°C) VBATT = 2.8V -30 1.00 0.25 0.7 0.6 -30 MAX691A TOC-06 1.50 MAX691A TOC-05 VCC-to-VOUT ON-RESISTANCE (Ω) MAX691A TOC-04 1.2 VCC = 0V 5 -60 60 30 PFI THRESHOLD vs. TEMPERATURE VBATT = 4.5V 4.35 0 VCC to VOUT ON-RESISTANCE vs. TEMPERATURE 10 4.60 60 VBATT to VOUT ON-RESISTANCE vs. TEMPERATURE VBATT = 2.8V 4.65 80 TEMPERATURE (°C) 15 4.75 100 TEMPERATURE (°C) VBATT = 2.0V -60 VCC = 4.75V VBATT = 2.8V VCE IN = VCC/2 TEMPERATURE (°C) 20 VBATT-to-VOUT ON-RESISTANCE (Ω) 120 0 -60 RESET THRESHOLD (V) VCC = 5V VBATT = 2.8V NO LOAD CE ON-RESISTANCE (Ω) 34 2 CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE MAX691A TOC-02 VCC = 5V VBATT = 2.8V PFI, CE IN = 0V BATTERY SUPPLY CURRENT (µA) MAX691A TOC-01 VCC SUPPLY CURRENT (µA) 36 BATTERY SUPPLY CURRENT vs. TEMPERATURE (BATTERY-BACKUP MODE) MAX691A TOC-03 VCC SUPPLY CURRENT vs. TEMPERATURE (NORMAL OPERATING MODE) 170 -60 -30 0 30 60 90 TEMPERATURE (°C) 120 150 -60 -30 0 30 60 90 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX691A/MAX693A/MAX800L/MAX800M __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) 8 4 0 1 2 3 4 10 RESET ACTIVE TIMEOUT PERIOD 1 SHORT WATCHDOG TIMEOUT PERIOD 10 100 VCC (V) 1000 VBATT to VOUT (mV) 100 SLOPE = 0.8Ω 8 4 1000 0 VCC = 0V VBATT = 4.5V 10 100 IOUT (mA) 6 1000 150 100 5V VCC RESET THRESHOLD 80µs 100 HI LOW LINE LO SLOPE = 8Ω 10 800ns HI RESET LO HI 12µs LO 1 10 200 250 300 VCC to LOW LINE AND CE OUT DELAY 1 1 50 CLOAD (pF) CE OUT 1 MAX691A TOC-12 12 VBATT to VOUT vs. OUTPUT CURRENT (BATTERY-BACKUP MODE) MAX691A TOC-13 VCC = 4.5V VBATT = 0V 10 16 COSC (pF) VCC to VOUT vs. OUTPUT CURRENT (NORMAL OPERATING MODE) 1000 VCC = 5V CE IN = 0V TO 5V DRIVER SOURCE IMPEDANCE = 50Ω 0 0.1 5 20 MAX691A TOC-15 0 LONG WATCHDOG TIMEOUT PERIOD PROPAGATION DELAY (ns) 12 VCC = 5V VBATT = 2.8V MAX691A TOC-14 IBATT (µA) 16 100 MAX691A TOC-11 VBATT = 2.8V IOUT = 0A CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE WATCHDOG AND RESET TIMEOUT PERIOD vs. OSC IN TIMING CAPACITOR (COSC) WATCHDOG AND RESET TIMEOUT PERIOD (sec) 20 MAX691A TOC-10 BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE VCC to VOUT (mV) MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits 100 IOUT (mA) _______________________________________________________________________________________ Microprocessor Supervisory Circuits PIN NAME FUNCTION 1 VBATT 2 VOUT Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GND. Output Supply Voltage. When VCC is greater than VBATT and above the reset threshold, VOUT connects to VCC. When VCC falls below VBATT and is below the reset threshold, VOUT connects to VBATT. Connect a 0.1µF capacitor from VOUT to GND. Connect VOUT to VCC if no backup battery is used. Input Supply Voltage, 5V input. 3 VCC 4 GND 5 6 7 8 9 10 11 12 13 14 15 16 Ground. 0V reference for all signals. Battery On Output. When VOUT switches to VBATT, BATT ON goes high. When VOUT switches to VCC, BATT ON BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current requirements greater than 250mA. LOW LINE LOW LINE output goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from VOUT to OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast OSC IN and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3). Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and OSC SEL watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1). OSC SEL has a 10µA internal pull-up. Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO PFI goes low. When PFI is not used, connect PFI to GND or VOUT . Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. PFO This is an uncommitted comparator, and has no effect on any other internal circuitry. Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tranWDI sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between VOUT and GND, which sets it to mid-supply when left unconnected. Chip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE IN is CE OUT low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs first. CE IN Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or VOUT. Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset WDO is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. RESET Output goes low whenever VCC falls below the reset threshold. RESET will remain low typically for RESET 200ms after VCC crosses the reset threshold on power-up. RESET RESET is an active-high output. It is open drain, and the inverse of RESET. _______________Detailed Description –————– R E S E T and RESET Outputs The MAX691A/MAX693A/MAX800L/MAX800M’s RESET and RESET outputs ensure that the µP (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors during power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. – When deasserted, RESET sources 1.6mA at typically VOUT - 0.5V. RESET output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to V CC = 1V, and an external 10kΩ pull-down resistor on RESET insures that it will be valid with VCC down to GND (Figure 1). As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the RDS(ON) and the saturation voltage. The 10kΩ pulldown resistor insures the parallel combination of switch plus resistor is around 10kΩ and the output saturation voltage is below 0.4V while sinking 40µA. When using a 10kΩ external pull-down resistor, the high state for RESET output with VCC = 4.75V will be 4.5V typical. For battery voltages ≥ 2V connected to VBATT, RESET and RESET remain valid for VCC from 0V to 5.5V. _______________________________________________________________________________________ 7 MAX691A/MAX693A/MAX800L/MAX800M ______________________________________________________________Pin Description MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits WDI RESET MAX691A MAX693A 15 TO µP RESET WDO 1k t2 RESET t1 t1 t3 t1 = RESET TIMEOUT PERIOD t2 = NORMAL WATCHDOG TIMEOUT PERIOD t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET Figure 1. Adding an external pull-down resistor ensures –————– RESET is valid with VCC down to GND. Figure 2. Watchdog Timeout Period and Reset Active Time RESET and RESET are asserted when VCC falls below the reset threshold (4.65V for the MAX691A/MAX800L, 4.4V for the MAX693A/MAX800M) and remain asserted for 200ms typ after VCC rises above the reset threshold on power-up (Figure 5). The devices’ batteryswitchover comparator does not affect reset assertion. However, both reset outputs are asserted in batterybackup mode since V CC must be below the reset threshold to enter this mode. Watchdog Output The Watchdog Output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout – period. The watchdog function is disabled and WDO is a logic high when VCC is below the reset threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog timeout period, RESET and RESET are asserted for the reset timeout period (200ms typical). WDO goes low and remains low until the next transition at WDI (Figure 2). If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6sec. WDO has a 2 x TTL output characteristic. Watchdog Function The watchdog monitors µP activity via the Watchdog Input (WDI). If the µP becomes inactive, RESET and RESET are asserted. To use the watchdog function, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6sec nominal), WDO, RESET, and RESET are asserted (see RESET and RESET Outputs section, and the Watchdog Output discussion on this page). Watchdog Input A change of state (high to low, low to high, or a minimum 100ns pulse) at the WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is 1.6sec. To disable the watchdog function, leave WDI floating. An internal resistor network (100kΩ equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When VCC is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance. 8 Selecting an Alternative Watchdog and Reset Timeout Period The OSC SEL and OSC IN inputs control the watchdog and reset timeout periods. Floating OSC SEL and OSC IN or tying them both to VOUT selects the nominal 1.6sec watchdog timeout period and 200ms reset timeout period. Connecting OSC IN to GND and floating or connecting OSC SEL to V OUT selects the 100ms normal watchdog timeout delay and 1.6sec delay immediately after reset. The reset timeout delay remains 200ms (Figure 2). Select alternative timeout periods by connecting OSC SEL to GND and connecting a capacitor between OSC IN and GND, or by externally driving OSC IN (Table 1 and Figure 3). OSC IN is internally connected to a ±100nA (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watchdog timeout periods (see Connecting a Timing Capacitor at OSC IN in the Applications Information section). _______________________________________________________________________________________ Microprocessor Supervisory Circuits Watchdog Timeout Period OSC SEL OSC IN Low External Clock Input 1024 clks 4096 clks 2048 clks Low External Capacitor (600/47pF x C)ms (2.4/47pF x C)sec (1200/47pF x C)ms Normal Immediately After Reset Reset Timeout Period Floating Low 100ms 1.6sec 200ms Floating Floating 1.6sec 1.6sec 200ms EXTERNAL OSCILLATOR EXTERNAL CLOCK MAX691A MAX693A MAX800L MAX800M 8 7 8 OSC SEL 7 OSC IN OSC SEL OSC IN 50kHz INTERNAL OSCILLATOR 1.6sec WATCHDOG N.C. N.C. 8 7 OSC SEL OSC IN INTERNAL OSCILLATOR 100ms WATCHDOG N.C. 8 7 OSC SEL OSC IN Figure 3. Oscillator Circuits Chip-Enable Signal Gating The MAX691A/MAX693A/MAX800L/MAX800M provide internal gating of chip-enable (CE) signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. All – these parts use a series transmission gate from CE IN to CE OUT (Figure 4). The 10ns max CE propagation delay from CE IN to CE OUT enables the parts to be used with most µPs. Chip-Enable Input The Chip-Enable Input (CE IN) is high impedance (dis–————– abled mode) while RESET and RESET are asserted. During a power-down sequence where VCC falls below – the reset threshold or a watchdog fault, CE IN assumes – a high-impedance state when the voltage at CE IN goes high or 15µs after reset is asserted, whichever occurs first (Figure 5). During a power-up sequence, CE IN remains high impedance, regardless of CE IN activity, until reset is deasserted following the reset timeout period. In the high-impedance mode, the leakage currents into this terminal are ±1µA max over temperature. In the – low-impedance mode, the impedance of CE IN appears as a 75Ω resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on both the source impedance of the – drive to CE IN and the capacitive loading on the Chip– Enable Output (CE OUT) (see Chip-Enable Propagation Delay vs. CE OUT Load Capacitance in the Typical Operating Characteristics). The CE propagation delay – is production tested from the 50% point of CE IN to the – 50% point of CE OUT using a 50Ω driver and 50pF of load capacitance (Figure 6). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low output-impedance driver. Chip-Enable Output In the enabled mode, the impedance of CE OUT is equivalent to 75Ω in series with the source driving CE IN. In the disabled mode, the 75Ω transmission gate is off and CE OUT is actively pulled to VOUT. This source turns off when the transmission gate is enabled. –——— —— ——– LOW LINE Output LOW LINE is the buffered output of the reset threshold comparator. LOW LINE typically sinks 3.2mA at 0.1V. For normal operation (VCC above the LOW LINE threshold), LOW LINE is pulled to VOUT. Power-Fail Comparator The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the IC. Common uses include low-battery indication (Figure 7), and early power-fail warning (see Typical Operating Circuit). Power-Fail Input Power Fail Input (PFI) is the input to the power-fail comparator. It has a guaranteed input leakage of ±25nA max over temperature. The typical comparator delay is 25µs from VIL to VOL (power failing), and 60µs from VIH to VOH (power being restored). If PFI is not used, connect it to ground. _______________________________________________________________________________________ 9 MAX691A/MAX693A/MAX800L/MAX800M Table 1. Reset Pulse Width and Watchdog Timeout Selections MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits 5 BATT ON 4.65V* VCC 6 3 2 VBATT CE IN 1 13 12 MAX691A MAX693A MAX800L MAX800M OSC SEL WDI PFI RESET GENERATOR 7 15 TIMEBASE FOR RESET AND WATCHDOG 8 WATCHDOG TRANSITION DETECTOR 11 9 WATCHDOG TIMER 14 10 1.25V 4 GND * 4.4V FOR THE MAX693A/MAX800M Figure 4. MAX691A/MAX693A/MAX800L/MAX800M Block Diagram 5.0V VCC RESET 4.0V THRESHOLD 5.0V 0V CE IN 5V 0V CE OUT 15µs 100µs 5V 0V 5V 100µs RESET RESET 0V LOGIC LEVELS SHOWN ARE FROM 0V TO 5V. Figure 5. Reset and Chip-Enable Timing 10 VOUT CHIP-ENABLE OUTPUT CONTROL 16 OSC IN LOW LINE ______________________________________________________________________________________ CE OUT RESET RESET WDO PFO Microprocessor Supervisory Circuits VBATT +5V VCC MAX691A MAX693A MAX800L MAX800M 2.8V 2.0V to 5.5V CE OUT CE IN 50Ω OUTPUT IMPEDANCE VCC VBATT GND CLOAD MAX691A MAX693A MAX800L PFO PFI MAX800M LOW BATT GND Figure 6. CE Propagation Delay Test Circuit Figure 7. Low-Battery Indicator Table 2. Input and Output Status in Battery-Backup Mode Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFI above 1.25V, PFO is actively pulled to VOUT. PIN NAME 1 VBATT 2 VOUT STATUS Supply current is 1µA max. VOUT is connected to VBATT through an internal PMOS switch. 3 VCC Battery switchover comparator monitors VCC for active switchover. 4 GND GND 0V, 0V reference for all signals. 5 BATT ON Logic high. The open-circuit output is equal to VOUT. 6 LOWLINE Logic low* 7 OSC IN 8 OSC SEL 9 PFI The power-fail comparator remains active in the battery-backup mode for VCC ≥ VBATT - 1.2V typ. PFO The power-fail comparator remains active in the battery-backup mode for VCC ≥ VBATT - 1.2V typ. Below this voltage, PFO is forced low. 10 OSC IN is ignored. OSC SEL is ignored. 11 WDI Watchdog is ignored. 12 CE OUT 13 CE IN High impedance 14 WDO Logic high. The open-circuit voltage is equal to VOUT. 15 RESET Logic low* 16 RESET High impedance* Logic high. The open-circuit voltage is equal to VOUT. Battery-Backup Mode Two conditions are required to switch to battery-backup mode: 1) VCC must be below the reset threshold, and 2) VCC must be below VBATT. Table 2 lists the status of the inputs and outputs in battery-backup mode. Battery On Output The Battery On (BATT ON) output indicates the status of the internal V CC /battery-switchover comparator, which controls the internal VCC and VBATT switches. For VCC greater than VBATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0.1V saturation voltage. In battery-backup mode, this terminal sources approximately 10µA from VOUT. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications (see Typical Operating Circuit). Input Supply Voltage The Input Supply Voltage (VCC) should be a regulated 5V. VCC connects to VOUT via a parallel diode and a large PMOS switch. The switch carries the entire current load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than 1Ω each. The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A. * VCC must be below the reset threshold to enter battery-backup mode. ______________________________________________________________________________________ 11 MAX691A/MAX693A/MAX800L/MAX800M +5V MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits Battery-Backup Input The Battery-Backup Input (VBATT) is similar to the VCC input except the PMOS switch and parallel diode are much smaller. Accordingly, the on-resistances of the diode and the switch are each approximately 10Ω. Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1µA over temperature and supply voltage (Figure 8). Output Supply Voltage The Output Supply Voltage (VOUT) pin is internally connected to the substrate of the IC and supplies current to the external system and internal circuitry. All opencircuit outputs will, for example, assume the VOUT voltage in their high states rather than the VCC voltage. At the maximum source current of 250mA, VOUT will typically be 200mV below VCC. Decouple this terminal with a 0.1µF capacitor. __________Applications Information The MAX691A/MAX693A/MAX800L/MAX800M are not short-circuit protected. Shorting VOUT to ground, other than power-up transients such as charging a decoupling capacitor, destroys the device. All open-circuit outputs swing between VOUT and GND rather than VCC and GND. If long leads connect to the chip inputs, insure that these leads are free from ringing and other conditions that would forward bias the chip’s protection diodes. There are three distinct modes of operation: 1) Normal operating mode with all circuitry powered up. Typical supply current from VCC is 35µA while only leakage currents flow from the battery. 2) Battery-backup mode where VCC is typically within 0.7V below VBATT. All circuitry is powered up and the supply current from the battery is typically less than 60µA. 3) Battery-backup mode where V CC is less than VBATT by at least 0.7V. VBATT supply current is 1µA max. Using SuperCap™ or MaxCap™ with the MAX691A/MAX693A/MAX800L/MAX800M VBATT has the same operating voltage range as VCC, and the battery switchover threshold voltages are typically ±30mV centered at VBATT, allowing use of a SuperCap and a simple charging circuit as a backup source (Figure 9). If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC. For example, with a SuperCap connected to VBATT and through a diode to VCC, if VCC quickly changes from 5.4V to 4.9V, the capacitor discharges through VOUT and VCC until VBATT reaches 5.1V typ. Leakage current through the SuperCap charging diode and the internal power diode eventually discharges the SuperCap to VCC. Also, if VCC and VBATT start from 0.1V above the reset threshold and power is lost at VCC, the SuperCap on VBATT discharges through V CC until VBATT reaches the reset threshold; then the battery-backup mode is initiated and the current through VCC goes to zero. +5V 3 VCC 1N4148 VBATT 1 MAX691A MAX693A MAX800L MAX800M VOUT 0.47F* 0.1µF VCC VBATT VOUT MAX691A MAX693A MAX800L MAX800M GND 4 * MaxCap Figure 8. VCC and VBATT to VOUT Switch 12 Figure 9. SuperCap or MaxCap on VBATT ______________________________________________________________________________________ 2 Microprocessor Supervisory Circuits +5V CE CE VOUT CE IN MAX691A/MAX693A/MAX800L/MAX800M VIN Rp* R1 RAM 1 VCC C1* PFI CE OUT CE CE MAX691A MAX693A MAX800L MAX800M MAX691A MAX693A MAX800L MAX800M RAM 2 R3 R2 CE CE GND PFO RAM 3 GND TO µP CE *OPTIONAL 5V RAM 4 PFO CE 0V 0V VL VTRIP VH VIN VTRIP = 1.25 *MAXIMUM Rp VALUE DEPENDS ON THE NUMBER OF RAMS. MINIMUM Rp VALUE IS 1kΩ. ACTIVE-HIGH CE LINES FROM LOGIC Figure 10. Alternate CE Gating VH = 1.25/ R1 VCC PFO PFI Alternate Chip-Enable Gating Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is near the power-fail comparator trip point. Figure 11 shows how to add hysteresis to the power-fail com- VL - 1.25 + 5 - 1.25 = 1.25 R1 R3 R2 +5V If using separate power supplies for VCC and VBATT, VBATT must be less than 0.3V above VCC when VCC is above the reset threshold. As described in the previous section, if VBATT exceeds this limit and power is lost at VCC, current flows continuously from VBATT to VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC switch until the circuit is broken (Figure 8). Adding Hysteresis to the Power-Fail Comparator R2 I I R3 R1 + R2 I I R3 Figure 11. Adding Hysteresis to the Power-Fail Comparator Using Separate Power Supplies for VBATT and VCC Using memory devices with both CE and CE inputs allows the CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to VOUT, and – connect CE OUT to the CE input of each memory device (Figure 10). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated. R1 + R2 R2 MAX691A MAX693A MAX800L MAX800M R2 GND 5V V- PFO 0V VTRIP 5 - 1.25 = 1.25 - VTRIP R1 R2 0V V- NOTE: VTRIP IS NEGATIVE Figure 12. Monitoring a Negative Voltage ______________________________________________________________________________________ 13 100 VCC = 5V TA = +25°C 0.1µF CAPACITOR FROM VOUT TO GND 80 MAX791-16 Backup-Battery Replacement MAXIMUM TRANSIENT DURATION (µs) MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits 60 40 20 0 10 100 1000 10000 RESET COMPARATOR OVERDRIVE, (Reset Threshold Voltage - VCC) (mV) Figure 13. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdrive parator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10kΩ to prevent it from loading down the PFO pin. Capacitor C1 adds noise rejection. Monitoring a Negative Voltage The power-fail comparator can be used to monitor a negative supply voltage using Figure 12’s circuit. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit’s accuracy is affected by the PFI threshold tolerance, the VCC voltage, and resistors R1 and R2. 14 The backup battery may be disconnected while VCC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses. Negative-Going VCC Transients While issuing resets to the µP during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration, negative-going VCC transients (glitches). It is usually undesirable to reset the µP when VCC experiences only small glitches. Figure 13 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not generated. The graph was produced using negativegoing VCC pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width a negative-going VCC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 40µs or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity. Connecting a Timing Capacitor at OSC IN When OSC SEL is connected to ground, OSC IN disconnects from its internal 10µA (typ) pull-up and is internally connected to a ±100nA current source. When a capacitor is connected from OSC IN to ground (to select alternative reset and watchdog timeout periods), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. To prevent timing errors or oscillator start-up problems, minimize external current leakage sources at this pin, and locate the capacitor as close to OSC IN as possible. The sum of PC-board leakage plus OSC capacitor leakage must be small compared to ±100nA. ______________________________________________________________________________________ Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M Maximum VCC Fall Time The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/µs. A standard rule of thumb for filter capacitance on most regulators is on the order of 100µF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse or 1A/100µF = 0.01V/µs. The VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time requirement. START SET WDI LOW Watchdog Software Considerations A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than “pulsing” the watchdog input high-low-high or low-high-low. This technique avoids a “stuck” loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 14 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should “hang” in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. SUBROUTINE OR PROGRAM LOOP SET WDI HIGH RETURN END Figure 14. Watchdog Flow Diagram ______________________________________________________________________________________ 15 _Ordering Information (continued) PART TEMP. RANGE MAX693ACPE 0°C to +70°C 16 Plastic DIP MAX693ACSE MAX693ACWE MAX693AC/D 0°C to +70°C 0°C to +70°C 0°C to +70°C 16 Narrow SO 16 Wide SO Dice* MAX693AEPE MAX693AESE MAX693AEWE MAX693AEJE MAX693AMJE MAX800LCPE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C 0°C to +70°C 16 Plastic SO 16 Narrow SO 16 Wide SO 16 CERDIP 16 CERDIP 16 Plastic DIP MAX800LCSE MAX800LEPE MAX800LESE 0°C to +70°C -40°C to +85°C -40°C to +85°C 16 Narrow SO 16 Plastic DIP 16 Narrow SO MAX800MCPE 0°C to +70°C 16 Plastic DIP MAX800MCSE MAX800MEPE MAX800MESE 0°C to +70°C -40°C to +85°C -40°C to +85°C 16 Narrow SO 16 Plastic DIP 16 Narrow SO ___________________Chip Topography VOUT PIN-PACKAGE * Dice are specified at TA = +25°C, DC parameters only. VBATT RESET RESET VCC WDO CE IN GND CE OUT 0.11" (2.794mm) BATT ON LOW LINE WDI PFI PFO OSC IN OSC SEL 0.07" (1.778mm) TRANSISTOR COUNT: 729 SUBSTRATE CONNECTED TO VOUT ________________________________________________________Package Information SOICN.EPS MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.