AD AD8531AKS

a
FEATURES
Single-Supply Operation: 2.7 Volts to 6 Volts
High Output Current: ⴞ250 mA
Low Supply Current: 750 ␮A/Amplifier
Wide Bandwidth: 3 MHz
Slew Rate: 5 V/␮s
No Phase Reversal
Low Input Currents
Unity Gain Stable
Rail-to-Rail Input and Output
APPLICATIONS
Multimedia Audio
LCD Driver
ASIC Input or Output Amplifier
Headphone Driver
GENERAL DESCRIPTION
The AD8531, AD8532, and AD8534 are single, dual and quad
rail-to-rail input and output single-supply amplifiers featuring
250 mA output drive current. This high output current makes
these amplifiers excellent for driving either resistive or capacitive
loads. AC performance is very good with 3 MHz bandwidth,
5 V/ms slew rate and low distortion. All are guaranteed to operate from a 3 volt single supply as well as a 5 volt supply.
The very low input bias currents enable the AD853x to be used
for integrators, diode amplification and other applications requiring
low input bias current. Supply current is only 750 mA per amplifier
at 5 volts, allowing low current applications to control high
current loads.
Applications include audio amplification for computers, sound
ports, sound cards and set-top boxes. The AD853x family is
very stable and capable of driving heavy capacitive loads, such as
those found in LCDs.
The ability to swing rail-to-rail at the inputs and outputs enables
designers to buffer CMOS DACs, ASICs or other wide output
swing devices in single-supply systems.
The AD8531, AD8532, and AD8534 are specified over the
extended industrial (–40∞C to +85∞C) temperature range. The
AD8531. The AD8532 is available in 8-lead SOIC, MSOP,
TSSOP surface-mount packages. The AD8534 is available in
narrow SO-14 and 14-lead TSSOP surface-mount packages.
All TSSOP, SOT, and SC70 versions are available in tape
and reel only.
Low Cost, 250 mA Output
Single-Supply Amplifiers
AD8531/AD8532/AD8534
PIN CONFIGURATIONS
5-Lead SC70 and SOT-23
(KS and RT Suffixes)
OUT A 1
AD8531
5 V+
Vⴚ 2
4 ⴚIN A
+IN A 3
8-Lead SOIC, TSSOP, and MSOP
(R, RU, and RM Suffixes)
NULL 1
8
NC
–IN A
2
7
V+
+IN A
3
6
OUT A
V–
4
5
NULL
AD8531
8-Lead SOIC, TSSOP, and MSOP
(R, RU, and RM Suffixes)
OUT A
1
–IN A
AD8532
8
V+
2
7
OUT B
+IN A
3
6
–IN B
V–
4
5
+IN B
14-Lead SOIC, and TSSOP
(R, and RU Suffixes)
OUT A
1
14 OUT D
–IN A
2
13 –IN D
+IN A
3
12 +IN D
AD8534
V+
4
+IN B
5
11 V–
–IN B
6
9
–IN C
OUT B
7
8
OUT C
10 +IN C
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD8531/AD8532/AD8534–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
VOS
CM
= 1.5 V, TA = 25ⴗC unless otherwise noted)
Conditions
–40∞C £ TA £ +85∞C
Input Bias Current
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
CMRR
AVO
DVOS/DT
DIB/DT
DIOS/DT
VCM = 0 V to 3 V
RL = 2 kW, VO = 0.5 V to 2.5 V
VOH
IL = 10 mA
–40∞C £ TA £ +85∞C
IL = 10 mA
–40∞C £ TA £ +85∞C
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOL
Output Current
Closed-Loop Output Impedance
IOUT
ZOUT
Min
5
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +85∞C
1
0
38
2.85
2.8
PSRR
ISY
VS = 3 V to 6 V
VO = 0 V
–40∞C £ TA £ +85∞C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
tS
GBP
fo
CS
RL = 2 kW
To 0.01%
NOISE PERFORMANCE
Voltage Noise Density
en
Current Noise Density
in
Unit
25
30
50
60
25
30
3
mV
mV
pA
pA
pA
pA
V
dB
V/mV
mV/∞C
fA/∞C
fA/∞C
2.92
± 250
60
45
Max
45
25
20
50
20
60
f = 1 MHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Typ
55
0.70
100
125
1
1.25
V
V
mV
mV
mA
W
dB
mA
mA
f = 1 kHz, RL = 2 kW
3.5
1.6
2.2
70
65
V/ms
ms
MHz
Degrees
dB
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/÷Hz
nV/÷Hz
pA/÷Hz
Specifications subject to change without notice.
–2–
REV. D
AD8531/AD8532/AD8534
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
VOS
CM
= 2.5 V, TA = 25ⴗC unless otherwise noted)
Conditions
–40∞C £ TA £ +85∞C
Input Bias Current
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
CMRR
AVO
DVOS/DT
DIB/DT
DIOS/DT
VCM = 0 V to 5 V
RL = 2 kW, VO = 0.5 V to 4.5 V
–40∞C £ TA £ +85∞C
VOH
IL = 10 mA
–40∞C £ TA £ +85∞C
IL = 10 mA
–40∞C £ TA £ +85∞C
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOL
Output Current
Closed-Loop Output Impedance
IOUT
ZOUT
–40∞C £ TA £ +85∞C
1
0
38
15
4.9
4.85
VS = 3 V to 6 V
VO = 0 V
–40∞C £ TA £ +85∞C
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWp
tS
GBP
fo
CS
RL = 2 kW
1% Distortion
To 0.01%
NOISE PERFORMANCE
Voltage Noise Density
en
Current Noise Density
in
Unit
25
30
50
60
25
30
5
mV
mV
pA
pA
pA
pA
V
dB
V/mV
mV/∞C
fA/∞C
fA/∞C
4.94
± 250
40
45
Max
47
80
20
50
20
50
f = 1 MHz, AV = 1
PSRR
ISY
Typ
5
–40∞C £ TA £ +85∞C
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
55
0.75
100
125
1.25
1.75
V
V
mV
mV
mA
W
dB
mA
mA
f = 1 kHz, RL = 2 kW
5
350
1.4
3
70
65
V/ms
kHz
ms
MHz
Degrees
dB
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/÷Hz
nV/÷Hz
pA/÷Hz
Specifications subject to change without notice.
REV. D
Min
–3–
AD8531/AD8532/AD8534
ABSOLUTE MAXIMUM RATINGS 1
PACKAGE INFORMATION
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Junction Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; the functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
For supplies less than +6 volts, the differential input voltage is equal to ± VS.
Package Type
␪JA*
␪JC
Unit
5-Lead SC70 (KS)
5-Lead SOT-23 (RT)
8-Lead SOIC (RN)
8-Lead MSOP (RM)
8-Lead TSSOP (RU)
14-Lead SOIC (RN)
14-Lead TSSOP (RU)
376
230
158
210
240
120
240
126
146
43
45
43
36
43
∞C/W
∞C/W
∞C/W
∞C/W
∞C/W
∞C/W
∞C/W
*qJA is specified for the worst case conditions, i.e., qJA is specified for device in socket
for P-DIP packages; qJA is specified for device soldered onto a circuit board for
surface-mount packages.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding Information
AD8531AKS*
AD8531AR
AD8531ART*
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
5-Lead SC70
8-Lead SOIC
5-Lead SOT-23
KS-5
RN-8
RT-5
A7B
AD8532AR
AD8532ARM*
AD8532ARU*
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
8-Lead SOIC
8-Lead MSOP
8-Lead TSSOP
RN-8
RM-8
RU-8
AD8534AR
AD8534ARU*
–40∞C to +85∞C
–40∞C to +85∞C
14-Lead SOIC
14-Lead TSSOP
RN-14
RU-14
A7A
ARA
*Available in reels only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8531/AD8532/AD8534 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
2.5
–VOL
2
+VOH
ⴞVOUT
1.5
1
0.5
0
0
20
40
60
80
100 120
RLOAD – ⍀
140
160
180
200
Figure 1. Output Voltage vs. Load. VS = ± 2.5 V, RL Is Connected to GND (0 V)
–4–
REV. D
Typical Performance Characteristics–AD8531/AD8532/AD8534
TA = 25ⴗC
500
TA = 25ⴗC
400
300
200
400
300
200
100
100
–12 –10 –8 –6 –4 –2 0
2
4
INPUT OFFSET VOLTAGE – mV
–4
–5
–6
–7
–8
–35 –15
5
25 45
65
TEMPERATURE – ⴗC
Figure 3. Input Offset Voltage
Distribution
TA = 25ⴗC
7
6
5
4
3
2
8
7
6
5
4
3
2
1
–35 –15
5
25 45
65
TEMPERATURE – ⴗC
85
3
2
1
0
–1
–35
Figure 6. Input Bias Current vs.
Common-Mode Voltage
–15
5
25 45
65
TEMPERATURE – ⴗC
85
Figure 7. Input Offset Current vs.
Temperature
10000
VS = 2.7V
VS = 5V
VS = 2.7V
TA = 25ⴗC
TA = 25ⴗC
RL = NO LOAD
SINK
10
1
0.1
0.01
0.1
1
10
100
LOAD CURRENT – mA
1000
Figure 8. Output Voltage to Supply
Rail vs. Load Current
TA = 25ⴗC
80
100
SOURCE
SINK
10
60
45
40
90
20
135
0
180
1
0.01
0.01
0.1
1
10
100
LOAD CURRENT – mA
1000
Figure 9. Output Voltage to Supply
Rail vs. Load Current
–5–
1k
10k
100k
1M
10M
FREQUENCY – Hz
100M
Figure 10. Open-Loop Gain and
Phase vs. Frequency
PHASE SHIFT – Degrees
SOURCE
1000
GAIN – dB
100
REV. D
4
0
1
2
3
4
5
COMMON-MODE VOLTAGE – Volts
⌬OUTPUT VOLTAGE – mV
1000
VS = 5V, 3V
VCM = VS/2
–2
Figure 5. Input Bias Current vs.
Temperature
⌬OUTPUT VOLTAGE – mV
5
INPUT OFFSET CURRENT – pA
VCM = VS/2
INPUT BIAS CURRENT – pA
INPUT BIAS CURRENT – pA
8
VS = 5V
85
Figure 4. Input Offset Voltage
vs. Temperature
6
VS = 5V, 3V
VCM = 2.5V
–3
–12 –10 –8 –6 –4 –2 0
2
4
INPUT OFFSET VOLTAGE – mV
Figure 2. Input Offset Voltage
Distribution
VS = 5V
–2
INPUT OFFSET VOLTAGE – mV
VS = 5V
VCM = 2.5V
QUANTITY – Amplifiers
QUANTITY – Amplifiers
500
VS = 2.7V
VCM = 1.35V
AD8531/AD8532/AD8534
5
VS = 5V
RL = NO LOAD
90
20
135
0
180
4
3
2
1
0
100k
1M
10M
FREQUENCY – Hz
100M
Figure 11. Open-Loop Gain & Phase
vs. Frequency
RL = 2k⍀
VIN = 2.5V p-p
1k
10k
100k
1M
FREQUENCY – Hz
OUTPUT SWING – Volts p-p
45
40
OUTPUT SWING – Volts p-p
60
PHASE SHIFT – Degrees
GAIN – dB
80
10k
VS = 5V
TA = 25ⴗC
TA = 25ⴗC
1k
5
VS = 2.7V
RL = 2k⍀
VIN = 4.9V p-p
3
2
1
0
10M
Figure 12. Closed-Loop Output
Voltage Swing vs. Frequency
TA = 25ⴗC
4
1k
10k
100k
1M
FREQUENCY – Hz
10M
Figure 13. Closed-Loop Output
Voltage Swing vs. Frequency
200
VS = 5V
160
TA = 25ⴗC
90
100␮V/div
IMPEDANCE – ⍀
140
120
100
AV = 10
80
60
VS = 5V
AV = 1000
TA = 25ⴗC
FREQUENCY = 1kHz
100
AV = 1
10
0%
10
0%
40
VS = 5V
A V = 1000
TA = 25ⴗC
FREQUENCY = 10kHz
100
90
200␮V/div
180
20
100k
1M
10M
FREQUENCY – Hz
100M
Figure 14. Closed-Loop Output
Impedance vs. Frequency
VS = 5V
TA = 25ⴗC
COMMON-MODE REJECTION – dB
CURRENT NOISE DENSITY – pA/ Hz
1
0.1
0.01
10
MARKER 25.9 ␮V/ Hz
MARKER 41␮V/ Hz
10k
100
1k
10k
FREQUENCY – Hz
100k
Figure 17. Current Noise Density
vs. Frequency
Figure 15. Voltage Noise Density
vs. Frequency
Figure 16. Voltage Noise Density
vs. Frequency
110
140
100
VS = 5V
TA = 25ⴗC
POWER SUPPLY REJECTION – dB
0
1k
90
80
70
60
50
40
1k
10k
100k
1M
FREQUENCY – Hz
10M
Figure 18. Common-Mode Rejection vs. Frequency
–6–
120
100
VS = 2.7V
TA = 25ⴗC
80
60
40
20
PSRR–
PSRR+
0
–20
–40
–60
100
1k
10k
100k
1M
FREQUENCY – Hz
10M
Figure 19. Power Supply Rejection
vs. Frequency
REV. D
AD8531/AD8532/AD8534
PSRR+
40
20
0
–20
–40
–60
100
100k
10k
FREQUENCY – Hz
1k
1M
40
–OS
20
+OS
10
0
10
50
30
SMALL SIGNAL OVERSHOOT – %
SMALL SIGNAL OVERSHOOT – %
40
–OS
+OS
20
10
0
10
100
1000
CAPACITANCE – pF
40
VS = 5V
TA = 25ⴗC
RL = 2k⍀
50
40
–OS
30
+OS
20
10
0
10
10000
100
1000
CAPACITANCE – pF
10000
Figure 22. Small Signal Overshoot
vs. Load Capacitance
0.9
VS = 2.7V
TA = 25ⴗC
RL = 600⍀
30
20
–OS
10
+OS
0
10
10000
Figure 23. Small Signal Overshoot
vs. Load Capacitance
100
1000
CAPACITANCE – pF
Figure 21. Small Signal Overshoot
vs. Load Capacitance
50
VS = 5V
TA = 25ⴗC
RL = 600⍀
TA = 25ⴗC
RL = 2k⍀
30
10M
Figure 20. Power Supply Rejection
vs. Frequency
SMALL SIGNAL OVERSHOOT – %
PSRR–
60
VS = 2.7V
SUPPLY CURRENT/AMPLIFIER – mA
100
80
60
50
VS = 5V
TA = 25ⴗC
120
SMALL SIGNAL OVERSHOOT – %
POWER SUPPLY REJECTION – dB
140
100
1000
CAPACITANCE – pF
0.85
0.8
0.75
VS = 5V
0.7
0.65
0.6
VS = 3V
0.55
0.5
–40
10000
Figure 24. Small Signal Overshoot
vs. Load Capacitance
–20
0
20
40
60
TEMPERATURE – ⴗC
80
Figure 25. Supply Current per
Amplifier vs. Temperature
0.70
TA = 25ⴗC
0.50
0.40
0.30
0.20
0V
VS = ⴞ1.35V
VIN = ⴞ50mV
AV = 1
RL = 2k⍀
CL = 300pF
TA = 25ⴗC
0.10
0.00
0.75 1.00
1.50
2.00
2.50
SUPPLY VOLTAGE – ⴞVolts
3.00
Figure 26. Supply Current per
Amplifier vs. Supply Voltage
REV. D
500 ns/DIV
Figure 27. Small Signal Transient
Response
–7–
20mV/DIV
0.60
20mV/DIV
SUPPLY CURRENT/AMPLIFIER – mA
0.80
0V
VS = ⴞ2.5V
VIN = ⴞ50mV
AV = 1
RL = 2k⍀
CL = 300pF
TA = 25ⴗC
500 ns/DIV
Figure 28. Small Signal Transient
Response
AD8531/AD8532/AD8534
VS = ⴞ2.5V
AV = 1
RL = 2k⍀
TA = 25ⴗC
100
90
VS = ⴞ1.35V
AV = 1
RL = 2k⍀
TA = 25ⴗC
100
90
100
90
10
10
10
0%
0%
0%
500mV
500ns
Figure 29. Large Signal Transient
Response
500mV
10␮s
1V
1V
500ns
Figure 31. No Phase Reversal
Figure 30. Large Signal Transient
Response
V+
APPLICATIONS
THEORY OF OPERATION
50␮A
The AD8531/AD8532/AD8534 is an all-CMOS, high output
current drive, rail-to-rail input/output operational amplifier.
This is the latest entry in Analog Devices’ expanding family of
single-supply devices for the multimedia and telecom marketplaces. Its high output current drive and stability with heavy
capacitive loads makes the AD8531/AD8532/AD8534 an excellent choice as a drive amplifier for LCD panels.
100␮A
20␮A
100␮A
M11
M12
M5
VB2
M1
M3
M4
M8
M2
M15
IN–
OUT
M6
IN+
Figure 32 illustrates a simplified equivalent circuit for the AD8531/
AD8532/AD8534. Like many rail-to-rail input amplifier configurations, it is comprised of two differential pairs, one n-channel
(M1–M2) and one p-channel (M3–M4). These differential pairs
are biased by 50 mA current sources, each with a compliance
limit of approximately 0.5 V from either supply voltage rail. The
differential input voltage is then converted into a pair of differential output currents. These differential output currents are
then combined in a compound folded-cascade second gain
stage (M5–M9). The outputs of the second gain stage at M8
and M9 provide the gate voltage drive to the rail-to-rail output
stage. Additional signal current recombination for the output
stage is achieved through the use of transistors M11–M14.
M16
VB3
M9
M14
20␮A
M7
50␮A
M10
M13
V–
Figure 32. AD8531/AD8532/AD8534 Simplified Equivalent
Circuit
Short-Circuit Protection
As a result of the design of the output stage for maximum load
current capability, the AD8531/AD8532/AD8534 does not have
any internal short-circuit protection circuitry. Direct connection of
the AD8531/AD8532/AD8534’s output to the positive supply
in single-supply applications will destroy the device. In those
applications where some protection is needed, but not at the
expense of reduced output voltage headroom, a low value resistor in series with the output, as shown in Figure 33, can be
used. The resistor, connected within the feedback loop of the
amplifier, will have very little effect on the performance of the
amplifier other than limiting the maximum available output voltage swing. For single 5 V supply applications, resistors less than
20 W are not recommended.
In order to achieve rail-to-rail output swings, the AD8531/
AD8532/AD8534 design employs a complementary commonsource output stage (M15–M16). However, the output voltage
swing is directly dependent on the load current, as the difference
between the output voltage and the supply is determined by the
AD8531/AD8532/AD8534’s output transistors on-channel
resistance (see Figures 8 and 9). The output stage also exhibits
voltage gain by virtue of the use of common-source amplifiers;
as a result, the voltage gain of the output stage (thus, the openloop gain of the device) exhibits a strong dependence to the total
load resistance at the output of the AD8531/AD8532/AD8534.
5V
VIN
AD8532
RX
20⍀
VOUT
Figure 33. Output Short-Circuit Protection
–8–
REV. D
AD8531/AD8532/AD8534
Power Dissipation
Power Calculations for Varying or Unknown Loads
Although the AD8531/AD8532/AD8534 is capable of providing
load currents to 250 mA, the usable output load current drive
capability will be limited to the maximum power dissipation
allowed by the device package used. In any application, the
absolute maximum junction temperature for the AD8531/
AD8532/AD8534 is 150∞C, and should never be exceeded for
the device could suffer premature failure. Accurately measuring
power dissipation of an integrated circuit is not always a
straightforward exercise, so Figure 34 has been provided as a
design aid for either setting a safe output current drive level or
in selecting a heatsink for the package options available on the
AD8531/AD8532/AD8534.
Often, calculating power dissipated by an integrated circuit to
determine if the device is being operated in a safe range is not
as simple as it might seem. In many cases power cannot be
directly measured. This may be the result of irregular output
waveforms or varying loads; indirect methods of measuring
power are required.
1.5
POWER DISSIPATION – Watts
TJ MAX = 150ⴗC
FREE AIR
NO HEATSINK
1
SOIC
␪JA = 158ⴗC/W
SC70
␪JA = 376ⴗC/W
where TJ is junction temperature, and TA is ambient temperature. qJA is the junction to ambient thermal resistance.
TJ = TC + P qJC
P = (TA – TC )/ (qJC – qJA)
25
50
75
85
100
TEMPERATURE – ⴗC
Figure 34. Maximum Power Dissipation vs. Ambient
Temperature
These thermal resistance curves were determined using the
AD8531/AD8532/AD8534 thermal resistance data for each
package and a maximum junction temperature of 150∞C. The
following formula can be used to calculate the internal junction
temperature of the AD8531/AD8532/AD8534 for any application:
TJ = PDISS ¥ qJA + TA
where TJ = junction temperature;
PDISS = power dissipation;
qJA = package thermal resistance,
junction-to-case; and
TA = Ambient temperature of the circuit.
To calculate the power dissipated by the AD8531/AD8532/
AD8534, the following equation can be used:
PDISS = ILOAD ¥ (VS–VOUT)
where ILOAD = is output load current;
VS = is supply voltage; and
VOUT = is output voltage.
The quantity within the parentheses is the maximum voltage
developed across either output transistor. As an additional
design aid in calculating available load current from the
AD8531/AD8532/AD8534, Figure 1 illustrates the AD8531/
AD8532/AD8534 output voltage as a function of load resistance.
REV. D
Given the two equations for calculating junction temperature:
TJ = TA + P qJA
The two equations can be solved for P (power):
TA + P qJA = TC + P qJC
0.5 SOT-23
␪JA = 236ⴗC/W
0
Calculating Power by Measuring Ambient and Case
Temperature
where TC is case temperature and qJA and qJC are given in the
data sheet.
TSSOP
␪JA = 240ⴗC/W
0
There are two methods to calculate power dissipated by an
integrated circuit. The first can be done by measuring the package temperature and the board temperature. The other is to
directly measure the circuit’s supply current.
Once power has been determined it is necessary to go back and
calculate the junction temperature to assure that it has not been
exceeded.
The temperature measurements should be directly on the package and on a spot on the board that is near the package but
definitely not touching it. Measuring the package could be difficult. A very small bimetallic junction glued to the package could
be used or it could be done using an infrared sensing
device if the spot size is small enough.
Calculating Power by Measuring Supply Current
Power can be calculated directly knowing the supply voltage and
current. However, supply current may have a dc component
with a pulse into a capacitive load. This could make rms current
very difficult to calculate. It can be overcome by lifting the supply pin and inserting an rms current meter into the circuit. For
this to work you must be sure all of the current is being delivered by the supply pin you are measuring. This is usually a good
method in a single supply system; however, if the system uses
dual supplies, both supplies may need to be monitored.
Input Overvoltage Protection
As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, the device’s
input overvoltage characteristic must be considered. When an
overvoltage occurs, the amplifier could be damaged depending
on the magnitude of the applied voltage and the magnitude of
the fault current. Although not shown here, when the input
voltage exceeds either supply by more than 0.6 V, pn-junctions
internal to the AD8531/AD8532/AD8534 energize allowing
current to flow from the input to the supplies. As illustrated in
the simplified equivalent input circuit (Figure 32), the AD8531/
AD8532/AD8534 does not have any internal current limiting
resistors, so fault currents can quickly rise to damaging levels.
–9–
AD8531/AD8532/AD8534
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. For the AD8531/AD8532/
AD8534, once the input voltage exceeds the supply by more
than 0.6 V the input current quickly exceeds 5 mA. If this
condition continues to exist, an external series resistor should
be added. The size of the resistor is calculated by dividing the
maximum overvoltage by 5 mA. For example, if the input
voltage could reach 10 V, the external resistor should be (10 V/
5 mA) = 2 kW. This resistance should be placed in series with
either or both inputs if they are exposed to an overvoltage condition. For more information on general overvoltage characteristics of amplifiers refer to the 1993 Seminar Applications Guide,
available from the Analog Devices Literature Center.
5V
RS
5⍀
CS
1␮F
CL
47nF
Figure 36. Snubber Network Compensates for Capacitive
Loads
Output Phase Reversal
Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs
are driven beyond their useful common-mode range. The
AD8531/AD8532/AD8534 is free from reasonable input voltage
range restrictions provided that input voltages no greater than
the supply voltage rails are applied. Although the device’s output will not change phase, large currents can flow through
internal junctions to the supply rails, as was pointed out in the
previous section. Without limit, these fault currents can easily
destroy the amplifier. The technique recommended in the
input overvoltage protection section should therefore be applied
in those applications where the possibility of input voltages
exceeding the supply voltages exists.
The first step is to determine the value of the resistor, RS. A
good starting value is 100 W. This value is reduced until the
small-signal transient response is optimized. Next, CS is determined—10 mF is a good starting point. This value is reduced to
the smallest value for acceptable performance (typically, 1 mF).
For the case of a 47 nF load capacitor on the AD8531/AD8532/
AD8534, the optimal snubber network is a 5 W in series with
1 mF. The benefit is immediately apparent as seen in the scope
photo in Figure 37. The top trace was taken with a 47 nF load
and the bottom trace with the 5 W—1 mF snubber network in
place. The amount of overshoot and ringing is dramatically
reduced. Table I below illustrates a few sample snubber networks
for large load capacitors:
Capacitive Load Drive
The AD8531/AD8532/AD8534 exhibits excellent capacitive
load driving capabilities. It can drive up to 10 nF directly as
shown in Figures 21 through 24. However, even though the
device is stable, a capacitive load does not come without a
penalty in bandwidth. As shown in Figure 35, the bandwidth is
reduced to under 1 MHz for loads greater than 10 nF. A “snubber” network on the output won’t increase the bandwidth, but
it does significantly reduce the amount of overshoot for a given
capacitive load. A snubber consists of a series R-C network
(RS, CS), as shown in Figure 36, connected from the output of
the device to ground. This network operates in parallel with the
load capacitor, CL, to provide phase lag compensation. The actual
value of the resistor and capacitor is best determined empirically.
Table I. Snubber Networks for Large Capacitive Loads
Load Capacitance
(CL)
Snubber Network
(RS, CS)
0.47 nF
4.7 nF
47 nF
300 W, 0.1 mF
30 W, 1 mF
5 W, 1 mF
50mV
100
47nF LOAD
ONLY
SNUBBER
IN CIRCUIT
4
VS = ⴞ2.5V
90
10
0%
50mV
RL = 1k⍀
TA = 25ⴗC
3.5
VOUT
AD8532
VIN
100mV p-p
10␮s
BANDWIDTH – MHz
3
Figure 37. Overshoot and Ringing Is Reduced by Adding
a Snubber Network in Parallel with the 47 nF Load
2.5
2
1.5
1
0.5
0
0.01
0.1
1
CAPACITIVE LOAD – nF
10
100
Figure 35. Unity-Gain Bandwidth vs. Capacitive Load
–10–
REV. D
AD8531/AD8532/AD8534
A High Output Current, Buffered Reference/Regulator
Many applications require stable voltage outputs relatively close
in potential to an unregulated input source. This “low dropout” type of reference/regulator is readily implemented with a
rail-to-rail output op amp, and is particularly useful when using
a higher current device such as the AD8531/AD8532/AD8534.
A typical example is the 3.3 V or 4.5 V reference voltage developed from a 5 V system source. Generating these voltages
requires a three terminal reference, such as the REF196 (3.3 V)
or the REF194 (4.5 V), both which feature low power, with
sourcing outputs of 30 mA or less. Figure 38 shows how such a
reference can be outfitted with an AD8531/AD8532/AD8534
buffer for higher currents and/or voltage levels, plus sink and
source load capability.
VS
5V
U2
AD8531
C1
0.1␮F
VOUT1 =
3.3V @ 100mA
R2
10k⍀ 1%
R1
10k⍀
1%
C3
0.1␮F
VC
ON/OFF
CONTROL
INPUT CMOS HI
(OR OPEN) = ON
LO = OFF
VS
COMMON
R3
(SeeText)
2
3
U1
REF196
4
6
VOUT2 =
3.3V
C2
0.1␮F
C5
100␮F/16V
TANTALUM
R5
0.2⍀
C4
1␮F
To scale VOUT2 to another (higher) output level, the optional
resistor R3 (shown dotted) is added, causing, the new VOUT1 to
become:
Ê R2 ˆ
VOUT 1 =VOUT 2 ¥ Á1+
˜
Ë R3 ¯
The circuit can either be used as shown, as a 5 V to 3.3 V
reference/regulator, or with ON/OFF control. By driving Pin 3
of U1 with a logic control signal as noted, the output is switched
ON/OFF. Note that when ON/OFF control is used, resistor R4
must be used with U1 to speed ON-OFF switching.
A Single-Supply, Balanced Line Driver
The circuit in Figure 39 is a unique line driver circuit topology
used in professional audio applications and has been modified
for automotive and multimedia audio applications. On a single
5 V supply, the line driver exhibits less than 0.7% distortion into
a 600 W load from 20 Hz to 15 kHz (not shown) with an input
signal level of 4 V p-p. In fact, the output drive capability of the
AD8531/AD8532/AD8534 maintains this level for loads as
small as 32 W. For input signals less than 1 V p-p, the THD is
less than 0.1%, regardless of load. The design is a transformerless, balanced transmission system where output common-mode
rejection of noise is of paramount importance. As with the
transformer-based system, either output can be shorted to
ground for unbalanced line driver applications without changing
the circuit gain of 1. Other circuit gains can be set according to
the equation in the diagram. This allows the design to be easily
configured for inverting, noninverting or differential operation.
R4
3.3k⍀
R3
10k⍀
VOUT
COMMON
3
Figure 38. A High Output Current Reference/Regulator
The low dropout performance of this circuit is provided by
stage U2, an AD8531 connected as a follower/buffer for the basic
reference voltage produced by U1. The low voltage saturation
characteristic of the AD8531/AD8532/AD8534 allows up to
100 mA of load current in the illustrated use, as a 5 V to 3.3 V
converter with good dc accuracy. In fact, the dc output voltage
change for a 100 mA load current delta measured less than
1 mV. This corresponds to an equivalent output impedance of
< 0.01 W. In this application, the stable 3.3 V from U1 is applied
to U2 through a noise filter, R1–C1. U2 replicates the U1
voltage within a few millivolts, but at a higher current output at
VOUT1, with the ability to both sink and source output current(s)
—unlike most IC references. R2 and C2 in the feedback path of
U2 provide additional noise filtering.
R2
10k⍀
A2
C1
22␮F
VIN
R7
10k⍀
6
1
A1
A1, A2 = 1/2 AD8532
R3
R2
VO1
5V
2
3
C3
47␮F
12V
R1
10k⍀
GAIN =
1
R6
10k⍀
5V
R10
10k⍀
SET: R7, R10, R11 = R2
7
A1
R11
R12
10k⍀ 10k⍀
6
5
A2
7
R8
100k⍀
5
R9
100k⍀
R14
50⍀
RL
600⍀
C2
1␮F
C4
47␮F
R13
10k⍀
SET: R6, R12, R13 = R3
Figure 39. A Single-Supply, Balanced Line Driver for
Multimedia and Automotive Applications
Transient performance of the reference/regulator for a 100 mA
step change in load current is also quite good and is largely
determined by the R5–C5 output network. With values as
shown, the transient is about 20 mV peak and settles to within
2 mV in less than 10 ms for either polarity. Although room exists
for optimizing the transient response, any changes to the R5–C5
network should be verified by experiment to preclude the possibility of excessive ringing with some capacitor types.
REV. D
R5
50⍀
2
–11–
VO2
AD8531/AD8532/AD8534
A Single-Supply Headphone Amplifier
Because of its speed and large output drive, the AD8531/AD8532/
AD8534 makes an excellent headphone driver, as illustrated in
Figure 40. Its low supply operation and rail-to-rail inputs and
outputs give a maximum signal swing on a single 5 V supply.
To ensure maximum signal swing available to drive the headphone, the amplifier inputs are biased to V+/2, which in this
case is 2.5 V. The 100 kW resistor to the positive supply is
equally split into two 50 kW resistors, with their common point
bypassed by 10 mF to prevent power supply noise from contaminating the audio signal.
In this two-way example, the LO signal is a dc-500 Hz
LP woofer output, and the HI signal is the HP (>500 Hz)
tweeter output. U1B forms an LP section at 500 Hz, while
U1A provides a HP section, covering frequencies ≥500 Hz.
C1
0.01␮F
100k⍀
U1A
3
AD8532
VIN
1
RIN
100k⍀
2
R2
31.6k⍀
CIN
10␮F
4
R5
31.6k⍀
R6
31.6k⍀
R4
49.9⍀
C4
0.02␮F
100k⍀
270␮F
+
C3
0.01␮F
R7
15.8k⍀
VS
DC –
500Hz
LO
100k⍀
6
7
5
U1B
100k⍀
10␮F
VS
0.1␮F
100␮F/25V
TO U1
1␮F/0.1␮F
AD8532
5V
V 5V
V 5V
HI
VS
C2
0.01␮F
The audio signal is then ac-coupled to each input through a
10 mF capacitor. A large value is needed to ensure that the
20 Hz audio information is not blocked. If the input already has
the proper dc bias, the ac coupling and biasing resistors are not
required. A 270 mF capacitor is used at the output to couple the
amplifier to the headphone. This value is much larger than that
used for the input because of the low impedance of the headphones, which can range from 32 W to 600 W. An additional
16 W resistor is used in series with the output capacitor to protect the op amp’s output stage by limiting capacitor discharge
current. When driving a 48 W load, the circuit exhibits less than
0.3% THD+N at output drive levels of 4 V p-p.
500Hz
AND UP
R3
49.9⍀ 270␮F
+
R1
31.6k⍀
COM
50k⍀
10␮F
50k⍀
LEFT
INPUT
1/2
AD8532
16⍀
Figure 41. A Single-Supply, Two-Way Active Crossover
270␮F
LEFT
HEADPHONE
50k⍀
10␮F
100k⍀
V
The crossover example frequency of 500 Hz can be shifted
lower or higher by frequency scaling of either resistors or
capacitors. In configuring the circuit for other frequencies,
complementary LP/HP action must be maintained between
sections, and component values within the sections must be in
the same ratio. Table II provides a design aid to adaptation,
with suggested standard component values for other frequencies.
50k⍀
50k⍀
RIGHT
INPUT
10␮F
1/2
AD8532
Table II. RC Component Selection for Various
Crossover Frequencies
16⍀ 270␮F
RIGHT
HEADPHONE
50k⍀
10␮F
100k⍀
Figure 40. A Single-Supply, Stereo Headphone Driver
A Single-Supply, Two-Way Loudspeaker Crossover Network
Active filters are useful in loudspeaker crossover networks for
reasons of small size, relative freedom from parasitic effects, the
ease of controlling low/high channel drive and the controlled driver
damping provided by a dedicated amplifier. Both Sallen-Key
(SK) and multiple-feedback (MFB) filter architectures are useful in implementing active crossover networks. The circuit
shown in Figure 41 is a single-supply, two-way active crossover
which combines the advantages of both filter topologies. This
active crossover exhibits less than 0.4% THD+N at output levels
of 1.4 V rms using general purpose unity-gain HP/LP stages.
Crossover
Frequency (Hz)
R1/C1 (U1A)1
R5/C3 (U1B)2
100
200
319
500
1k
2k
5k
10 k
160 kW/0.01 mF
80.6 kW/0.01 mF
49.9 kW/0.01 mF
31.6 kW/0.01 mF
16 kW/0.01 mF
8.06 kW/0.01 mF
3.16 kW/0.01 mF
1.6 kW/0.01 mF
NOTES
Applicable for filter a = 2.
1
For Sallen-Key stage U1A: R1 = R2, and C1 = C2, etc.
2
For Multiple Feedback stage U1B: R6 = R5, R7 = R5/2, and
C4 = 2C3.
For additional information on the active filters and active crossover networks, please consult the data sheet for the OP279, a
dual rail-to-rail high-output current operational amplifier.
–12–
REV. D
AD8531/AD8532/AD8534
Direct Access Arrangement for Telephone Line Interface
Figure 42 illustrates a 5 V only transmit/receive telephone line
interface for 600 W transmission systems. It allows full duplex
transmission of signals on a transformer coupled 600 W line in a
differential manner. Amplifier A1 provides gain that can be
adjusted to meet the modem output drive requirements. Both
A1 and A2 are configured to apply the largest possible signal on
a single supply to the transformer. Because of the high output
current drive and low dropout voltage of the AD8531/AD8532/
AD8534s, the largest signal available on a single 5 V supply is
approximately 4.5 V p-p into a 600 W transmission system.
Amplifier A3 is configured as a difference amplifier for two
reasons: (1) It prevents the transmit signal from interfering with
the receive signal and (2) it extracts the receive signal from the
transmission line for amplification by A4. A4’s gain can be
adjusted in the same manner as A1’s to meet the modem’s input
signal requirements. Standard resistor values permit the use of
SIP (Single In-line Package) format resistor arrays.
P1
Tx GAIN
ADJUST
TO TELEPHONE
LINE
1:1
2k⍀
R3
360⍀
1
2
A1
R5
10k⍀
6.2V
ZO
600⍀
R2
9.09k⍀
C1
R1
10k⍀ 0.1␮F
TRANSMIT
TxA
3
6.2V
5V DC
T1
MIDCOM
671-8005
R6
10k⍀
6
7
A2
R7
10k⍀
5
R8
10k⍀
10␮F
R9
10k⍀
R11
10k⍀
A1, A2 = 1/2 AD8532
A3, A4 = 1/2 AD8532
R12
10k⍀
R10
10k⍀
2
3
A3
1
R14
R13
10k⍀ 14.3k⍀
2k⍀
6
5
P2
Rx GAIN
ADJUST
A4
7
RECEIVE
RxA
C2
0.1␮F
Figure 42. A Single-Supply Direct Access Arrangement
for Modems
REV. D
–13–
AD8531/AD8532/AD8534
* AD8531/AD8532/AD8534 SPICE Macro-model
3/96, REV. D
* 5-Volt Version
ARG / ADSC
*
* Copyright 1996 by Analog Devices
*
* Refer to “README.DOC” file for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License
* Statement.
*
* Node assignments
*
noninverting input
*
|
inverting input
*
|
|
positive supply
*
|
|
|
negative supply
*
|
|
|
|
output
*
|
|
|
|
|
.SUBCKT AD8531/AD8532/AD8534_5 1
2
99 50 40
*
* INPUT STAGE
*
M1
3
2
6
50
NIX L=6U W=25U
M2
4
7
6
50
NIX L=6U W=25U
M3
8
2
5
5
PIX L=6U W=25U
M4
9
7
5
5
PIX L=6U W=25U
EOS
7
1
POLY(1) 25
98
5E-3 0.451
IIN1
1
98
5P
IIN2
2
98
5P
IOS
2
1
0.5P
I1
99
5
50U
I2
6
50
50U
R1
99
3
4.833K
R2
99
4
4.833K
R3
8
50
4.833K
R4
9
50
4.833K
D3
5
99
DX
D4
50
6
DX
*
* GAIN STAGE
*
EREF
98
0
POLY(2) 99
0
50
0
0
0.5
+0.5
G1
98
21
POLY(2) 4
3
9
8
0
+145U +145U
RG
21
98
18.078E6
CC
21
40
14P
D1
21
22
DX
D2
23
21
DX
V1
99
22
1.37
V2
23
50
1.37
*
* COMMON MODE GAIN STAGE
*
ECM
24
98
POLY(2) 1
98
2
98
0
0.5
+0.5
R5
24
25
1E6
R6
25
98
10K
C1
24
25
0.75P
*
* OUTPUT STAGE
*
ISY
99
50
450.4U
GSY
99
50
POLY(1) 99
50
-3.334E-4 6.667E-5
EP
99
39
POLY(1) 98
21
0.78925
1
EN
38
50
POLY(1) 21
98
0.78925
1
M15
40
39
99
99
POX L=1.5U
W=1500U
M16
40
38
50
50
NOX L=1.5U
W=1500U
C15
40
39
50P
C16
40
38
50P
.MODEL DX D(RS=1 CJO=0.1P)
.MODEL NIX NMOS(VTO=0.75 KP=205.5U RD=1 RS=1 RG=1 RB=1
+CGSO=4E-9
+CGDO=4E-9 CGBO=16.667E-9 CBS=2.34E-13 CBD=2.34E-13)
.MODEL NOX NMOS(VTO=0.75 KP=195U RD=.5 RS=.5 RG=1 RB=1
+CGSO=66.667E-12
+CGDO=66.667E-12 CGBO=125E-9 CBS=2.34E-13 CBD=2.34E-13)
.MODEL PIX PMOS(VTO=-0.75 KP=205.5U RD=1 RS=1 RG=1 RB=1
+CGSO=4E-9
+CGDO=4E-9 CBDO=16.667E-9 CBS=2.34E-13 CBD=2.34E-13)
.MODEL POX PMOS(VTO=-0.75 KP=195U RD=.5 RS=.5 RG=1 RB=1
+CGSO=66.667E-12
+CGDO=66.667E-12 CGBO=125E-9 CBS=2.34E-13 CBD=2.34E-13)
.ENDS
–14–
REV. D
AD8531/AD8532/AD8534
OUTLINE DIMENSIONS
8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Dimensions shown in millimeters
3.10
3.00
2.90
5.10
5.00
4.90
8
5
14
4.50
4.40 6.40 BSC
4.30
1
8
4.50
4.40
4.30
6.40
BSC
4
1
PIN 1
7
PIN 1
0.65
BSC
0.15
0.05
1.05
1.00
0.80
1.20
MAX
0.30
COPLANARITY 0.19
0.10
8ⴗ
0ⴗ
SEATING 0.20
PLANE
0.09
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING COPLANARITY
PLANE
0.10
0.75
0.60
0.45
8ⴗ
0ⴗ
COMPLIANT TO JEDEC STANDARDS MO-153AA
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
5-Lead Plastic Surface Mount Package [SC70]
(KS-5)
5-Lead Plastic Surface-Mount Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
Dimensions shown in millimeters
2.90 BSC
2.00 BSC
5
4
5
1.25 BSC
2.10 BSC
2
1
2.80 BSC
3
1
PIN 1
0.22
0.08
0.30
0.15
3
0.95 BSC
1.10 MAX
0.10
0.00
2
PIN 1
0.65 BSC
1.00
0.90
0.70
4
1.60 BSC
0.46
0.36
0.26
SEATING
PLANE
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.15 MAX
COMPLIANT TO JEDEC STANDARDS MO-203AA
0.50
0.30
SEATING
PLANE
0.22
0.08
10ⴗ
0ⴗ
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AA
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
8-Lead MSOP Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
5
4.90
BSC
3.00
BSC
1
4.00 (0.1574)
3.80 (0.1497)
4
8
5
1
4
6.20 (0.2440)
5.80 (0.2284)
PIN 1
0.65 BSC
1.27 (0.0500)
BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
0.25 (0.0098)
0.10 (0.0040)
8ⴗ
0ⴗ
0.80
0.40
COPLANARITY
SEATING
0.10
PLANE
SEATING
PLANE
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-187AA
REV. D
1.75 (0.0688)
1.35 (0.0532)
–15–
AD8531/AD8532/AD8534
OUTLINE DIMENSIONS
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-14)
C01099–0–10/02(D)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
14
8
1
7
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
1.27 (0.0500)
BSC
0.51 (0.0201)
0.33 (0.0130)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
ⴛ 45ⴗ
0.25 (0.0098)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.40 (0.0157)
0.19 (0.0075)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
10/02—Data Sheet changed from REV. C to REV. D.
Deleted 8-Lead PDIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted 14-Lead PDIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to Figure 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PRINTED IN U.S.A.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. D