19-2577; Rev 1; 5/03 Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC The MAX3873A is a compact, low-power 2.488Gbps/ 2.67Gbps clock-recovery and data-retiming IC for SDH/SONET applications. The phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output. The MAX3873A meets all SDH/SONET jitter specifications, does not require an external reference clock to aid in frequency acquisition, and provides excellent tolerance to both deterministic and sinusoidal jitter. The MAX3873A provides a PLL loss-of-lock (LOL) output to indicate whether the CDR is in lock. The recovered data and clock outputs are CML with on-chip 50Ω back terminations on each line. The clock output can be powered down if not used. The MAX3873A is implemented in Maxim’s secondgeneration SiGe process and consumes only 260mW at 3.3V supply (output clock disabled, low output swing). The device is available in a 4mm x 4mm 20-pin QFN exposed-pad package and operates from -40°C to +85°C. Features ♦ Fully Integrated Clock Recovery and Data Retiming ♦ Power Dissipation: 260mW with +3.3V Supply ♦ Clock Jitter Generation: 5mUIRMS ♦ Exceeds ANSI, ITU, and Bellcore SDH/SONET Jitter Specifications ♦ Differential Input Range: 50mVP-P to 1.6VP-P ♦ Single +3.3V Power Supply ♦ PLL Fast Track (FASTRACK) Mode Available ♦ Clock Output Can Be Disabled ♦ Input Data Rate: 2.488Gbps or 2.67Gbps ♦ Selectable Output Amplitude ♦ Tolerates 2000 Consecutive Identical Digits ♦ Loss-of-Lock Indicator ♦ Differential CML Data and Clock Outputs ♦ Operating Temperature Range: -40°C to +85°C Ordering Information Applications Switch Matrix Backplanes SDH/SONET Receivers and Regenerators Add/Drop Multiplexers PART TEMP RANGE PINPACKAGE PKG CODE MAX3873AEGP -40°C to +85°C 20 QFN (4mm x 4mm) G2044 Digital Cross-Connects SDH/SONET Test Equipment Pin Configuration GND FIL+ FIL- GND LOL 19 18 17 16 TOP VIEW 20 DWDM Transmission Systems Typical Application Circuit appears at end of data sheet. RATESET 1 15 SDO+ VCC 2 14 SDO- SDI+ 3 13 VCC_BUF SDI- 4 12 SCLKO+ VCC 5 11 SCLKO- 8 9 10 MODE SCLKEN 7 FASTRACK VCC_VCO 6 VCC MAX3873A QFN** **NOTE: THE EXPOSED PAD MUST BE SOLDERED TO THE SUPPLY GROUND. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3873A General Description MAX3873A Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +5.0V Voltage at SDI± .............................. (VCC - 1.0V) to (VCC + 0.5V) CML Output Current at SDO±, SCLKO± ............................22mA Voltage at LOL, FASTRACK, FIL±, SCLKEN MODE, RATESET...................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 20-Lead QFN (derate 20.0mW/°C above +85°C) .....1300mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-50°C to +150°C Processing Temperature..................................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, TA = -40°C to +85°C. Typical values are at 2.488Gbps, VCC = 3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Current (Note 2) SYMBOL ICC TYP MAX MODE = GND, SCLKEN = low CONDITIONS MIN 79 99 MODE = OPEN, SCLKEN = high 112 142 UNITS mA CML INPUT SPECIFICATIONS (SDI+, SDI-) Differential Input Voltage VID Figure 1 Single-Ended Input Voltage VIS Figure 1 Input Common-Mode Voltage Input Termination to VCC DC-coupled, Figure 1 RIN 50 1600 VCC - 0.8 VCC + 0.4 VCC - VID/4 mVP-P V V 40 50 60 MODE = open 640 800 1000 MODE = VCC 400 600 800 MODE = GND 200 400 600 80 100 120 Ω CML OUTPUT SPECIFICATIONS (SDO+, SDO-, SCLKO+, SCLKO-) Differential Output Swing (Note 3) Differential Output Resistance RO Output Common-Mode Voltage (Note 3) MODE = Open VCC - 0.17 MODE = VCC VCC - 0.13 MODE = GND VCC - 0.08 mVP-P Ω V TTL INPUT/OUTPUT SPECIFICATIONS (FASTRACK, LOL, SCLKEN, MODE, RATESET) Input High Voltage VIH Input Low Voltage VIL 2.0 Input Current 2 -30 Output High Voltage VOH IOH = sourcing 40µA Output Low Voltage VOL IOL = sinking 2mA V 0.8 V +30 µA 2.4 _______________________________________________________________________________________ V 0.4 V Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC (VCC = 3.0V to 3.6V, CF = 0.022µF, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, 2.488Gbps, TA = +25°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL Serial Input Data Rate Clock-to-Q Delay tCLK-Q Jitter Peaking JP Jitter Transfer Bandwidth JBW CONDITIONS MIN TYP RATESET = low 2.488 RATESET = high 2.67 Figure 2 (Note 5) -70 MAX UNITS Gbps +70 ps f ≤ 2MHz 0.1 dB RATESET = Low 2.0 MHz f = 70kHz, 0.4UI deterministic jitter on input data 6.9 f = 100kHz, 0.4UI deterministic jitter on input data 2.12 4.5 f = 1MHz, 0.4UI deterministic jitter on input data 0.33 0.6 f = 10MHz, 0.4UI deterministic jitter on input data 0.15 0.3 (Notes 6, 8) UIP-P Sinusoidal Jitter Tolerance f = 70kHz, 0.4UI deterministic jitter on input data 6.9 f = 100kHz, 0.4UI deterministic jitter on input data 2.12 4.5 f = 1MHz, 0.4UI deterministic jitter on input data 0.33 0.6 f = 10MHz, 0.37UI deterministic jitter on input data 0.15 0.3 (Notes 6, 9) (Notes 7, 8) Jitter Generation JGEN (Notes 7, 9) 5 6.8 mUIRMS 45 62 mUIP-P 6 7.65 mUIRMS 40 86 mUIP-P Clock Output Edge Speed 20% to 80% 60 110 ps Data Output Edge Speed 20% to 80% 60 110 ps Tolerated Consecutive Identical Digits 2000 bits 100kHz to 2.5GHz 17 2.5GHz to 4.0GHz 14 Frequency Acquisition Time Figure 4 1 ms LOL Assert Time Figure 4 1.6 µs SDI± Input Return Loss (-20log(S11)) dB _______________________________________________________________________________________ 3 MAX3873A AC ELECTRICAL CHARACTERISTICS MAX3873A Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.0V to 3.6V, CF = 0.022µF, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, 2.488Gbps, TA = +25°C, unless otherwise noted.) (Note 4) Note 1: At TA = -40°C, DC characteristics are guaranteed by design and characterization. Note 2: CML outputs open. Note 3: RL = 50Ω to VCC. Note 4: AC characteristics are guaranteed by design and characterization. Note 5: Relative to the falling edge of SCLKO+. See Figure 2. Note 6: Measured with 223 - 1 PRBS. Note 7: Jitter BW = 12kHz to 20MHz. Note 8: RATESET = low. Note 9: RATESET = high. VCC + 0.4V tCLK 25mV 800mV VCC SCLKO+ VCC - 0.4V (a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL) 25mV tCLK-Q VCC SDO 800mV VCC - 0.4V VCC - 0.8V Figure 2. Definition of Clock-to-Q Delay (b) DC-COUPLED SINGLE-ENDED CML INPUT Figure 1. Definition of Input Voltage Swing SERIAL DATA <2µs 1200 BITS OF 1–0 PATTERN DATA VCO CLOCK PHASE ALIGNED TO INPUT DATA FASTRACK Figure 3. Definition of Phase Acquisition Time INPUT DATA LOL ASSERT TIME FREQUENCY ACQUISITION TIME LOL OUTPUT Figure 4. Definition of LOL Assert Time and Frequency Acquisition Time 4 _______________________________________________________________________________________ Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC RECOVERED CLOCK AND DATA (2.67Gbps, 223 - 1 PATTERN, VIN = 50mVP-P) MAX3873A toc01 MAX3873A toc02 RECOVERED CLOCK AND DATA (2.488Gbps, 223 - 1 PATTERN, VIN = 50mVP-P) 125mV/div 125mV/div 100ps/div 100ps/div RECOVERED CLOCK JITTER (2.488Gbps) JITTER TOLERANCE (2.488Gbps, 223 - 1 PATTERN, VIN = 50mVP-P) MAX3873A toc04 MAX3873A toc03 100 INPUT JITTER (UIp-p) WITH 0.2UI OF PWD WITH 0.4UI OF DETERMINISTIC JITTER 10 1 BELLCORE MASK 223 - 1 PATTERN RMS = 2.0psRMS 0.1 10 100 10ps/div SUPPLY CURRENT vs. TEMPERATURE (SCLKO DISABLED) -1.0 -1.5 BELLCORE MASK -2.0 140 MAX OUTPUT SWING MED OUTPUT SWING 100 80 60 MIN OUTPUT SWING 40 -2.5 -3.0 105 FREQUENCY (Hz) 106 107 160 140 120 MAX OUTPUT SWING MED OUTPUT SWING 100 80 60 MIN OUTPUT SWING 20 0 104 180 40 20 103 MAX3873A toc07 160 120 200 MAX3873A toc06 180 SUPPLY CURRENT (mA) -0.5 TRANSFER (dB) 200 MAX3873A toc05 0 10,000 SUPPLY CURRENT vs. TEMPERATURE (SCLKO ENABLED) SUPPLY CURRENT (mA) JITTER TRANSFER 0.5 1000 JITTER FREQUENCY (kHz) 0 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX3873A Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) BIT-ERROR RATIO vs. INPUT AMPLITUDE PULLIN RANGE (RATESET = 0) 2.8 MAX3873A toc09 2.9 10-3 10-4 BIT ERROR RATIO 2.7 2.6 2.5 2.4 2.3 10-5 10-6 10-7 2.2 10-8 2.1 10-9 2.0 -50 0 50 100 2 3 4 5 JITTER TOLERANCE vs. INPUT DETERMINISTIC JITTER JITTER TOLERANCE vs. PULSE-WIDTH DISTORTION 0.7 fJITTER = 10MHz 0.5 0.4 0.3 0.2 PRBS = 223 - 1 0 1.0 0.9 MAX3873A toc11 MAX3873A toc10 0.8 0.1 1 INPUT VOLTAGE (mVp-p) fJITTER = 1MHz 0.6 0 AMBIENT TEMPERATURE (°C) 1.0 0.9 10-10 SINUSOIDAL JITTER TOLERANCE (UIP-P) FREQUENCY (GHz) 10-2 MAX3873A toc08 3.0 SINUSOIDAL JITTER TOLERANCE (UIP-P) MAX3873A Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC fJITTER = 1MHz PRBS = 223 - 1 0.8 0.7 0.6 0.5 fJITTER = 10MHz 0.4 0.3 0.2 0.1 INPUT DATA FILTERED BY 1870MHz 4TH-ORDER BESSEL FILTER 0 0.05 0.10 0.15 0.20 -40 DETERMINISTIC JITTER (UIP-P) -30 -20 -10 0 10 20 30 40 INPUT PULSE-WIDTH DISTORTION (%) Pin Description PIN NAME 1 RATESET 2, 5, 6 VCC 3.3V Supply Voltage 3 SDI+ Positive Serial Data Input 4 SDI- 7 FASTRACK 8 VCC_VCO 9 6 FUNCTION MODE Input Rate Select. Connect to TTL low for 2.488Gbps data and to TTL high for 2.67Gbps data. Negative Serial Data Input PLL Fast Track Control, TTL Input. When FASTRACK is TTL high, the PLL is switched to a fasttrack mode for fast phase acquisition. When FASTRACK is TTL low, the PLL operates normally. 3.3V VCO Supply Voltage Output Amplitude Mode Select. MODE = open sets the CML output amplitude to high; MODE = high sets the output amplitude to medium; MODE = low sets the output amplitude to low. _______________________________________________________________________________________ Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC PIN NAME FUNCTION 10 SCLKEN Clock Output Enable, TTL Input. When SCLKEN = open or SCLKEN = high, the clock outputs (SCLKO±) are enabled. When SCLKEN = low, the clock outputs are disabled and SCLKO± = VCC. 11 SCLKO- Negative Clock Output, CML. This output can be disabled by setting SCLKEN to low. 12 SCLKO+ Positive Clock Output, CML. This output can be disabled by setting SCLKEN to low. 13 VCC_BUF 3.3V CML Output Buffer Supply Voltage 14 SDO- 15 SDO+ Negative Data Output, CML 16 LOL 17, 20 GND Supply Ground 18 FIL- Negative PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-. 19 FIL+ Positive PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-. EP Exposed Pad Positive Data Output, CML Loss-of-Lock Output, TTL (Active Low). The LOL output indicates a PLL lock failure. Ground. The exposed pad must be soldered to the circuit board ground for proper electrical and thermal operation. Detailed Description The MAX3873A consists of a fully integrated phaselocked loop (PLL), input amplifier, and CML output buffers (Figure 5). The PLL consists of a phase/frequency detector, a loop filter, and a voltage-controlled oscillator (VCO). This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. Input Amplifier The input amplifier provides internal 50Ω line terminations and can accept a differential input amplitude from 50mV P-P to 1600mV P-P . The structure of the input amplifier is shown in Figure 9. Phase Detector The phase detector incorporated in the MAX3873A produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. Frequency Detector VCC GND FIL+ FIL- RATESET SDO+ AMP SDO- MAX3873A MODE SDI+ AMP SDI- PHASE AND FREQUENCY DETECTOR LOOP FILTER VCO I SCLKO+ AMP SCLKO- Q SCLKEN LOL The digital frequency detector (FD) aids frequency acquisition during startup conditions. The frequency difference between the received data and the VCO clock is derived by sampling the VCO outputs on each edge of the data input signal. The FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. Loop Filter and VCO The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor, CF, is required to set the PLL damping ratio. See the Design Procedure section for guidelines on selecting this capacitor. FASTRACK Figure 5. Functional Diagram _______________________________________________________________________________________ 7 MAX3873A Pin Description (continued) The loop filter output controls the on-chip LC VCO running at either 2.488GHz or 2.67GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 2psRMS within a jitter band of 12kHz to 20MHz. Loss-of-Lock Monitor A loss-of-lock (LOL) monitor is incorporated in the MAX3873A to indicate either a loss of frequency lock or the absence of incoming data. Under loss-of-lock conditions, LOL may momentarily assert high due to noise. Design Procedure Setting the Loop Filter The MAX3873A is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (JBW) below 2.0MHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF and can be approximated according to: fz = 1 2π (3000Ω) CF with CF expressed in F. For an overdamped system, the jitter peaking (JP) of a second-order system can be approximated by: fz JP = 20 log 1 + JBW For example, using CF = 2000pF results in jitter peaking of 0.2dB. Reducing CF below 500pF might result in PLL instability. The recommended value is CF = 0.022µF to guarantee a maximum jitter peaking of less than 0.1dB. CF must be a low TC, high-quality capacitor of type X7R or better. FASTRACK Mode The MAX3873A has a PLL fast-track (FASTRACK) mode to decrease locking time in switched data applications. In applications where the input data is switched from one source to another, there is a brief period in which there is no valid data input to the MAX3873A. In the absence of input data, the PLL phase slowly drifts from the ideal position. By enabling FASTRACK during reacquisition, the time required to regain phase alignment is reduced. This is accomplished by increasing the loop bandwidth by approximately 50%. The bandwidth of the MAX3873A is also linearly dependent upon the transition density of the input data. By using a preamble of 1200 bits of a 1–0 pattern during switching, the loop bandwidth is increased by a factor of approximately 2 (Figure 3). Thus, by using a 1–0 pattern preamble and enabling FASTRACK, the PLL bandwidth is increased by a factor of approximately 3, resulting in the fastest possible reacquisition of phase lock. FASTRACK increases the rate at which the MAX3873A acquires the proper phase, assuming that the VCO is already running at the proper frequency. On startup conditions, however, the VCO frequency is significantly different from the input data, and the time required to lock to the incoming data is increased to approximately 1.0ms. HO(j2πf) (dB) H(j2πf) (dB) CF = 2000pF CF = 0.022µF fZ = 2.4kHz CLOSED-LOOP GAIN 0 OPEN-LOOP GAIN MAX3873A Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC CF = 2000pF fZ = 26kHz f (kHz) 1 10 100 Figure 6. Open-Loop Transfer Function 8 1000 -3 CF = 0.022µF f (kHz) 1 10 100 1000 Figure 7. Closed-Loop Transfer Function _______________________________________________________________________________________ Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC The MAX3873A has excellent jitter tolerance. Adding DJ to the input will close the eye opening and result in reduced sinusoidal jitter tolerance. It typically can tolerate more than 0.3UIP-P of 10MHz jitter when measured with a 223 - 1 PRBS data stream with 0.4UI of deterministic jitter (DJ). This gives a total high-frequency jitter tolerance of 0.7UI. Refer to the Jitter Tolerance vs. Pulse-Width Distortion and Jitter Tolerance vs. Deterministic Jitter graphs in the Typical Operating Characteristics section. Input and Output Terminations The MAX3873A’s digital CML outputs (SDO+, SDO-, SCLKO+, SCLKO-) have selectable output amplitude controlled by the MODE input. If the SCLKO outputs are not used, they can be disabled (see the Supply Current vs. Temperature graph in the Typical Operating Characteristics section). The structure of the high-speed digital outputs is shown in Figure 8. The MODE input sets the current in the current source, thereby controlling the output swing. The SCLKEN input sets the current in the SCLKO current source to 0mA, disabling the output. The structure of the CML inputs (SDI±) is shown in Figure 9. Unless the CML input is DC-coupled to a CML output, use AC-coupling with the CML inputs to avoid upsetting the common-mode voltage. Applications Information Consecutive Identical Digits (CID) The MAX3873A has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of less than 10-10. The CID tolerance is tested using a 213 - 1 PRBS, substituting a long run of zeros to simulate the worst case. A CID tolerance of 2000 bits is typical. Exposed-Pad Package The exposed-pad (EP), 20-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3873A and must be soldered to the circuit board for proper thermal and electrical performance. Layout Circuit board layout and design can significantly affect the MAX3873A’s performance. Use good high-frequency design techniques, including minimizing ground inductance and using controlled-impedance transmission lines on the data and clock signals. Place power-supply decoupling as close to the VCC pins as possible. Isolate the input from the output signals to reduce feedthrough. VCC MAX3873A VCC VCC 50Ω 50Ω 50Ω SDI+ OUT+ VCC OUT- 50Ω SDIMODE SCLKO ONLY SCLKEN MAX3873A Figure 8. CML Output Model Figure 9. CML Input Model _______________________________________________________________________________________ 9 MAX3873A Sinusoidal Jitter Tolerance and Input Deterministic Jitter Trade-Offs Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873A Typical Application Circuit SWITCH CARD 2.5Gbps OPTICAL TRANSCEIVER MAX3873A CDR CROSSPOINT SWITCH SDI+ FIL+ FIL- LOL SDI- MAX3873A FASTRACK RATESET 20-PIN QFN MODE SDO+ SDOSCLKO+ SCLKOSCLKEN Chip Information TRANSISTOR COUNT: 2028 PROCESS: SiGe BiCMOS 10 ______________________________________________________________________________________ Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC 12,16,20, 24L QFN.EPS PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM 21-0106 E 1 2 ______________________________________________________________________________________ 11 MAX3873A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3873A Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM 21-0106 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.