19-2247; Rev 0; 10/01 Quad 2.5Gbps Cable Transceiver Features ♦ Quad 2:1 Channel Serialization ♦ Quad 1:2 Channel Deserialization ♦ 3m Link Distance with Low-Cost Copper Cable ♦ Better than 10-16 BER Performance ♦ 10Gbps Aggregate Parallel Interface ♦ System Loopback ♦ 1.25Gbps LVDS Synchronous Interface ♦ 2.5Gbps CML Serial Cable Interface ♦ PLL Lock Detect Signal ♦ Selectable Cable Pre-Emphasis ♦ Fixed Receive Equalization Applications Ordering Information Gigabit Ethernet Cable Backplane Concentration PART System Interconnects Using Low-Cost Copper Cable TEMP. RANGE MAX3780CCQ 0°C to +70°C PIN-PACKAGE 100 TQFP-EP* *Exposed pad System Interconnects Using Parallel Optics Typical Operating Circuit 0.1µF CMOS ASIC 8B/10B CODING 8B/10B DECODING 625MHz 8 TDAT[1:8] ± 1.25Gbps LVDS 625MHz RECEIVER DESKEW 8 CHANNEL IDENTITY TCLK ± TX[1:4] ± MAX3780 CABLE TRANSCEIVER RCLK ± RDAT[1:8] ± +3.3V 2.5Gbps CML 10kΩ LOCK RESET RX[1:4] ± LOOPEN TRIEN EQ1 EQ2 GND REFCLK ± 125MHz REFERENCE CLOCK RXFIL VCC1 VCC2 VCC3 VCC4 VCC6 0.1µF PECL BUFFER 0.1µF 50Ω 50Ω VCC5 TXFIL SUPPLY FILTER NETWORK +3.3V VCC6 - 2V ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3780 General Description The MAX3780 cable transceiver provides a bidirectional interface of four 2.5Gbps channels over low-cost copper cable or external fiber-optic interface. The transmitter section accepts eight channels of input at 1.25Gbps. An integrated 4-bit FIFO allows retiming of the transmit data to a clean local reference clock. The channels are multiplexed (2:1) into four outputs operating at 2.5Gbps. Preemphasis and equalization provide compensation for losses in low-cost cables up to 3m. The receiver recovers the clock and demultiplexes (1:2) the 2.5Gbps channels into eight 1.25Gbps outputs. Fully integrated phase-locked loops and delay-locked loops recover clock and data from the serial data inputs. The transceiver IC is available in a compact 100-pin TQFP package with exposed-ground pad and consumes 2.2W. MAX3780 Quad 2.5Gbps Cable Transceiver ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCCTEMP) ....................................-0.5V to +4.0V Continuous CML Output Current ......................-10mA to +25mA Momentary CML Output Voltage (duration < 1 minute, +25°C).......................0V to (VCC + 0.5V) CML Input Voltage......................................-0.5V to (VCC + 0.5V) LVDS Input and Output Voltage .................-0.5V to (VCC + 0.5V) TTL Input or Output Voltage .......................-0.5V to (VCC + 0.5V) PECL Input Voltage ....................................-0.5V to (VCC + 0.5V) TMPSENS, TXFIL, RXFIL Voltage ...............-0.5V to (VCC + 0.5V) Operating Ambient Temperature Range ................0°C to +70°C Operating Junction Temperature Range ..............0°C to +150°C Storage Ambient Temperature Range...............-55C° to +100°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) PARAMETER MIN TYP MAX 3.0 3.3 3.6 V TA 0 25 70 °C 1.6 2.2 3.3 W ICC 533 665 916 mA TTL Input High Voltage VIH 2.0 TTL Input Low Voltage VIL 0.8 V TTL Input High Current IIH VIH = 2.0V -250 µA IIL VIL = 0V -500 µA 0.4 V Supply Voltage Operating Ambient Temperature SYMBOL VCC CONDITIONS Referenced to GND Power Dissipation Supply Current UNITS TTL INPUTS AND OUTPUTS TTL Input Low Current TTL Output High Voltage VOH Open collector, RLOAD = 10kΩ TTL Output Low Voltage VOL RLOAD = 10kΩ V 2.4 V PECL INPUTS PECL Input High Voltage Referenced to VCC6 -1165 -880 mV PECL Input Low Voltage Referenced to VCC6 -1810 -1475 mV -10 +10 µA 200 800 mVp-p VCC 0.5 VCC + 0.2 V PECL Input Current CML INPUTS (Note 1, Figure 5) Differential Input Voltage Range Total differential signal required to achieve error rate Single-Ended Input Voltage Range Single-ended range of a differential input signal Common-Mode Voltage Inputs open or AC-coupled Input Impedance RIN VCC V Differential 85 100 115 0m channel, EQ1 = 1, EQ2 = 1 400 600 800 Ω CML OUTPUTS (Note 1, Figure 4) Differential Output Voltage (Measured at the End of the Channel) (Note 3) 2 0.5m channel, EQ1 = 1, EQ2 = 1 540 1m channel, EQ1 = 1, EQ2 = 0 500 3m channel, EQ1 = 0, EQ2 = 1 400 _______________________________________________________________________________________ mVp-p Quad 2.5Gbps Cable Transceiver (VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN MAX VCC 0.3 Output Common-Mode Voltage Differential Output Impedance TYP ROUT 85 100 UNITS V 115 Ω LVDS INPUTS Input Voltage Range VI |VGPD| < 925mV 0 2000 mV Differential Input Voltage |VID| |VGPD| < 925mV 150 500 mV Differential Input Impedance RIN 100 115 Ω -80 -200 µA 1.475 V 400 mV 25 mV 1.275 V 25 mV 120 Ω 40 mA Input Common-Mode Current 85 VOS = 1.2V, inputs tied together LVDS OUTPUTS (Note 2) Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance VOH VOL 0.925 |VOD| 250 V ∆|VOD| VOS 1.125 ∆|VOS| ROD Short-Circuit Current Short to supply or ground Impedance When Disabled TRIEN = 0 80 100 5 10 kΩ Note 1: CML differential signal amplitudes are specified as the total signal across the load (V+ - V-). Note 2: LVDS output signal amplitudes are specified according to IEEE 1596.3-1996. Note 3: Differential output voltage is production tested for all EQ1 and EQ2 settings. Typical values are the differential peak-to-peak eye opening at the end of the cable. AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, TA = 0°C to +70°C, REFCLK = 125MHz, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRANSMITTER PARAMETERS TCLK Frequency Transmitter Latency From TDAT to TX 625 MHz 4.5 ns ±0.8 ns LVDS INPUTS Accumulated Phase Error at TCLK Relative to REFCLK _______________________________________________________________________________________ 3 MAX3780 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML differential load = 100Ω ±1%, TA = 0°C to +70°C, REFCLK = 125MHz, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Setup Time tSU Figure 1 100 ps Hold Time tH Figure 1 100 ps CML OUTPUTS Deterministic Jitter (Note 5) 15 25 psp-p Random Jitter Wideband jitter with 01 pattern (Note 7) 22 66 psp-p 140 ps Edge Speed tr, tf 20% to 80%, measured at transmitter output, (EQ1 = 1, EQ2 = 1) RECEIVER PARAMETERS Clock Frequency 625 MHz µs PLL Lock Time After valid data applied 525 Receiver Latency From RX to RDAT 4.3 Jitter Generation (Note 7) 25 ns 66 psp-p +32 ps 50 psp-p LVDS OUTPUTS Clock Duty-Cycle Distortion TPW Variation of 50% crossing from ideal time -32 Measured with K28.5 pattern at RDAT_ outputs Deterministic Jitter Edge Speed tr, tf τCLK-Q Clock-to-Data Delay 15 20% to 80% 160 250 ps Figure 2 268 400 532 ps (Note 6) 220 300 CML INPUTS High-Frequency Jitter Tolerance psp-p Note 4: AC characteristics are guaranteed by design and characterization. Note 5: Deterministic jitter (DJ) and differential output signal measured with K28.5 at TX_ pins. Note 6: High-frequency jitter comprised of 164psp-p of deterministic jitter, 1.6psRMS random jitter, and the remaining as 5MHz sinusoidal jitter. Note 7: Peak-to-peak random jitter is 16.4 ✕ RMS jitter for a jitter probability of 10-16. RCLK τCLK-Q DIFFERENTIAL AMPLITUDE MAX3780 Quad 2.5Gbps Cable Transceiver tH = 100ps 1000mVp-p MAXIMUM INPUT tSU = 100ps 300mV MINIMUM INPUT τCLK-Q RDAT_ Figure 2. Definition of Clock-to-Q Delay CENTER OF RISING OR FALLING CLOCK EDGE Figure 1. LVDS Receiver Input Eye Mask 4 _______________________________________________________________________________________ Quad 2.5Gbps Cable Transceiver 390 370 350 330 310 -10 -20 -30 -15 -20 -25 -40 -35 270 -50 250 75 100 125 -40 1 150 10 JUNCTION TEMPERATURE (°C) TRANSMITTER POWER-SUPPLY REJECTION 1.5 1.0 0.5 1 10,000 0 10 100 0.3 0.2 0.1 1000 100 10 1000 1.0 VCO FREQUENCY DIFFERENCE (ppm) 10 5 0 250 50 100 150 200 250 0 -5 RETURN LOSS (dB) -10 -15 -20 -10 -15 -20 -30 0 200 15 CML OUTPUT RETURN LOSS -25 0.5 150 20 10,000 MAX3780 toc08 -5 RETURN LOSS (dB) 1.5 100 25 VCO FREQUENCY DIFFERENCE (ppm) 0 MAX3780 toc07 2.0 50 30 CML INPUT RETURN LOSS 2.5 0 35 FREQUENCY (kHz) TX TO RX VCO PULLING 3.0 10,000 0 1 POWER-SUPPLY NOISE FREQUENCY (kHz) 3.5 1000 40 0 1 100 RX TO TX VCO PULLING MAX3780 toc05 0.4 10 FREQUENCY (kHz) RECEIVER POWER-SUPPLY REJECTION 0.5 JITTER GENERATION (psp-p/mVp-p) MAX3780 toc04 2.0 1000 100 FREQUENCY (kHz) MAX3780 toc06 50 MAX3780 toc09 25 ADDED DETERMINISTIC JITTER (psp-p) 0 JITTER GENERATION (psp-p/mVp-p) -5 -10 -30 290 ADDED DETERMINISTIC JITTER (psp-p) MAX3708 toc03 0 JITTER TRANSFER (dB) 0 JITTER TRANSFER (dB) 410 5 MAX3708 toc02 430 TMPSENS VOLTAGE (mV) 10 MAX3780 toc01 450 RECEIVER JITTER TRANSFER (RX4 TO RCLK) TRANSMITTER JITTER TRANSFER (REFCLK TO TX_) TMPSENS VOLTAGE VS. TEMPERATURE -25 0 1000 2000 3000 FREQUENCY (MHz) 4000 5000 0 1000 2000 3000 4000 5000 FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX3780 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) RX4 JITTER TOLERANCE VS. INPUT AMPLITUDE INPUT JITTER (UIp-p) INPUT = 210 - 1 PRBS WITH ADDITIONAL 0.4UI OF DETERMINISTIC JITTER 0.25 0.20 0.15 MAX3780 toc12 100 MAX3780 toc11 MAX3780 toc10 0.40 0.35 0.30 EYE DIAGRAM AFTER 3m CABLE UNCOMPENSATED (EQ1 = 1, EQ2 = 1) RX4 JITTER TOLERANCE 0.45 5MHz JITTER TOLERANCE (UIp-p) MAX3780 Quad 2.5Gbps Cable Transceiver INPUT = 80mVp-p 210 - 1 PRBS WITH 0.4UI OF DETERMINISTIC JITTER PATTERN = 27 - 1 PRBS 10 64mV/ div 1 0.10 0.05 0.1 0 10 100 1000 10 1000 100 EYE DIAGRAM AFTER 3m CABLE COMPENSATED (EQ1 = 0, EQ2 = 1) MAX3780 toc13 6 EYE DIAGRAM AFTER 0.5m CABLE (EQ1 = 1, EQ2 = 1) MAX3780 toc15 MAX3780 toc14 PATTERN = 27 - 1 PRBS 64mV/ div 64mV/ div 70ps/div 70ps/div EYE DIAGRAM AFTER 1.0m CABLE (EQ1 = 1, EQ2 = 0) PATTERN = 27 - 1 PRBS 64mV/ div 10,000 JITTER FREQUENCY (kHz) DIFFERENTIAL INPUT AMPLITUDE (mVp-p) PATTERN = 27 - 1 PRBS 70ps/div _______________________________________________________________________________________ 70ps/div Quad 2.5Gbps Cable Transceiver PIN NAME 1, 12, 25, 26, 28, 31, 45, 50, 51, 55, 63, 71, 75, 76, 80, 100 GND Supply Ground 2, 11, 24 VCC1 +3.3V Supply for Receiver, LVDS Data and Clock Outputs, and Digital Receiver Functions 3, 5, 7, 9, 13, 15, 17, 19 RDAT1+ to RDAT8+ Positive Parallel-Data Outputs, LVDS 4, 6, 8, 10, 14, 16, 18, 20 RDAT1- to RDAT8- Negative Parallel-Data Outputs, LVDS 21 RCLK+ Positive 625MHz Recovered Clock, LVDS. Parallel-data outputs are clocked on both the rising and falling edge of the clock. 22 RCLK- Negative 625MHz Recovered Clock, LVDS. Parallel-data outputs are clocked on both the rising and falling edge of the clock. 23 TRIEN Three-State Enable, TTL Input. Setting TRIEN low forces the LVDS outputs into a highimpedance state and the LOCK pin to a logical ‘1’. CML outputs are not affected by TRIEN. Internally pulled high through 15kΩ. 27 LOCK Lock Status Indicator, TTL Output. This output goes high when the transmit PLL, receiver PLL, and receiver DLLs are in lock. Because this output is open-collector TTL, it requires an external 10kΩ pullup resistor to VCC. The LOCK pins from multiple MAX3780s can be connected in parallel to form a single LOCK signal. 29 RXFIL Receiver Loop Filter Connection. Connect a 0.1µF capacitor between RXFIL and VCC2. VCC2 +3.3V Supply for Receiver VCO, Analog Receiver Functions, and External Loop Filter Connection 32, 35, 38, 41, 44 VCC3 +3.3V Supply for CML Inputs 33, 36, 39, 42 RX4- to RX1- Negative Serial Input, CML 34, 37, 40, 43 RX4+ to RX1+ Positive Serial Input, CML 46, 79, 99 VCC6 47 LOOPEN 48 VCCTEMP +3.3V Supply for TMPSENS. Connect to ground to disable the temperature-sensing circuit. 49 TMPSENS Junction Temperature Sensor. Analog output corresponding to the junction temperature of the die. Leave open for normal use. 52 PTPIN 53 EQ2 Transmit Equalizer Control Input #2, TTL. Refer to Table 1 for setting transmitter precompensation. Internally pulled high. 54 EQ1 Transmit Equalizer Control Input #1, TTL. Refer to Table 1 for setting transmitter precompensation. Internally pulled high. 56, 59, 62, 64, 67, 70 VCC4 30 FUNCTION +3.3V Supply for LVDS Inputs, FIFO, Multiplexer, and PECL REFCLK Input Loopback Enable, TTL input. Force low to enable system loopback. Internally pulled high through 15kΩ. Reserved for Maxim Use. Connect to ground for normal operation. +3.3V Supply for CML Outputs _______________________________________________________________________________________ 7 MAX3780 Pin Description Quad 2.5Gbps Cable Transceiver MAX3780 Pin Description (continued) PIN NAME FUNCTION 57, 60, 65, 68 TX4- to TX1- Negative Serial Output, CML 58, 61, 66, 69 TX4+ to TX1+ Positive Serial Output, CML 72 RESET Reset Input, TTL. Connect low for >80ns to reset FIFO and receiver components. Internally pulled high through 15kΩ. 73 TXFIL Transmitter Loop Filter Connection. Connect a 0.1µF capacitor between TXFIL and VCC5. 74 VCC5 +3.3V Supply for Transmitter VCO, Analog Transmitter Functions, and External Loop Filter Connection 77 REFCLK+ Positive Reference Clock Input, PECL 78 REFCLK- Negative Reference Clock Input, PECL 81 TCLK+ Positive Clock Input for Transmitter Input Data, LVDS 82 TCLK- Negative Clock Input for Transmitter Input Data, LVDS 83, 85, 87, 89, 91, 93, 95, 97 TDAT1+ to TDAT8+ Positive Parallel Data Inputs, LVDS 84, 86, 88, 90, 92, 94, 96, 98 TDAT1- to TDAT8- Negative Parallel Data Inputs, LVDS Detailed Description The MAX3780 cable transceiver uses four 2:1 muxes and four 1:2 demuxes to simplify backplane routing. The serial transceiver interface can either be a fiber module or up to 3m of low-cost, twisted-pair copper cable. This bidirectional interface provides low-voltage differential signaling (LVDS) interfaces at the 1.25Gbps parallel inputs and outputs. The serial data inputs and outputs utilize current-mode logic (CML) structures. An integrated PLL recovers the clock from the incoming serial data, as well as retimes the received data. The serial interface uses both precompensation as well as equalization to allow high-speed transmission through up to 3m of copper cable while maintaining a BER < 10-16. The compensation/equalization circuits are optimized for short cables, 0.5m cables, 1m cables, or 3m cables. TTL inputs are provided to select the amount of precompensation. LVDS Inputs and Outputs The MAX3780 parallel interface includes eight differential data inputs at 1.25Gbps, one half-rate differential clock input at 625MHz, eight differential data outputs at 1.25Gbps, and one half-rate differential clock output at 625MHz. All parallel inputs and outputs are LVDS compatible to minimize power dissipation, speed transition time, and improve noise immunity. The LVDS outputs 8 go into a high-impedance state when TRIEN is forced low. This simplifies system checks by allowing vectors to be forced on the LVDS outputs. The LVDS outputs also have short-circuit protection in case of shorts to VCC or GND. PLL Clock Multiplier The PLL clock multiplier uses the 125MHz reference clock to synthesize 1.25GHz and 2.5GHz clocks used to synchronize the transmitter functions. The reference clock is also used to aid frequency acquisition in the receiver. The 125MHz input signal at REFCLK requires a duty cycle between 40% and 60%. To achieve proper jitter performance and BER benchmarks, it is critical to use a high-quality, low-jitter reference clock. See the Reference Clock Requirements table for more information. Bit-Interleaved Multiplexer/Demultiplexer The MAX3780 uses bit interleaving to multiplex the parallel data and bit deinterleaving to demultiplex the serial data. After serial transmission, the channel assignment of the parallel outputs is random for each serial channel. In other words, there is a 50% chance that RDAT1 = TDAT1 and RDAT2 = TDAT2 and a 50% chance that RDAT1 = TDAT2 and RDAT2 = TDAT1. Because the MAX3780 does not perform channel assignment, other circuitry must handle this task. _______________________________________________________________________________________ Quad 2.5Gbps Cable Transceiver MAX3780 TXFIL REFCLK+ REFCLK- TX_LOCK (INTERNAL) 625MHz DDR CLOCK TCLK+ TCLK- REFCLK (INTERNAL) PLL CLOCK MULTIPLIER MAX3780 CABLE TRANSCEIVER 2.5GHz 1.25GHz LVDS INPUTS TDAT1+ TDAT1- D Q FIFO TDAT2+ TDAT2- D Q FIFO TDAT3+ TDAT3- D Q FIFO TDAT4+ TDAT4- D Q FIFO D Q D Q PRECOMP TX1+ TX1- PRECOMP TX2+ TX2CML OUTPUTS TDAT5+ TDAT5- D Q FIFO TDAT6+ TDAT6- D Q FIFO TDAT7+ TDAT7- D Q FIFO TDAT8+ TDAT8- D Q FIFO D Q D Q PRECOMP TX3+ TX3- PRECOMP TX4+ TX4EQ2 RESET EQ1 TRIEN LOOPEN RDAT1+ RDAT1- Q D Q RDAT2+ RDAT2- Q D RDAT3+ RDAT3- Q D Q LVDS OUTPUTS RDAT4+ RDAT4- Q D RDAT5+ RDAT5- Q D RDAT6+ RDAT6- Q D RDAT7+ RDAT7- Q D D D DLL PHASE RECOVERY 0 DLL PHASE RECOVERY 0 DLL PHASE RECOVERY 0 1 1 EQ RX1+ RX1- EQ RX2+ RX2CML INPUTS Q 1 D 1 Q EQ RX3+ RX3- EQ RX4+ RX4- 0 Q RDAT8+ RDAT8- D D 2.5GHz RCLK+ RCLK- DIVIDE BY 2 PLL CLOCK RECOVERY 1.25GHz RXFIL REFCLK K TX_LOCK 1 RX_LOCK TMPSENS VCCTEMP LOCK 0 1 Figure 3. Functional Diagram _______________________________________________________________________________________ 9 MAX3780 Quad 2.5Gbps Cable Transceiver ment, and the DLLs only serve as adjustable delay lines to allow for different channels to have different (static) phase relationships. Table 1. Setting the CML Output Precompensation RECOMMENDED CHANNEL PRECOMPENSATION VALUE EQ1 Extended Range 30% 0 0 3m Cable 20% 0 1 1m Cable 10% 1 0 Off 1 1 0.5m Cable or Fiber Module EQ2 VCC 50Ω 50Ω TX_+ TX_- CML Outputs with Precompensation The serial outputs of the MAX3780 (TX1–TX4) are CML compatible. These outputs offer the best combination of low power dissipation, performance, and external component count. AC-coupling capacitors should always be used to provide immunity to common-mode voltage mismatches. The CML output structure is shown in Figure 4. For more information, refer to the applications note HFAN 01.0 Introduction to LVDS, PECL, and CML. Table 1 gives the amount of compensation for different EQ1 and EQ2 settings. The CML data outputs have adjustable precompensation to compensate for cable and PC board trace losses. The cable and PC board traces have skin-effect and dielectric losses that attenuate high frequencies more than low frequencies. The precompensation FIR filter does the inverse. It attenuates low frequencies and boosts high frequencies. If precompensation is chosen to match the channel attenuation, the data at the end of the cable will be equalized. CML Inputs with Equalization The CML input structure, shown in Figure 5, provides low power dissipation and excellent performance. The CML inputs have integrated 50Ω termination resistors, reducing the external component count required for interfacing. GND Figure 4. Simplified CML Output Structure PLL Clock Recovery The phase-locked loop recovers a synchronous clock signal from the incoming serial data on RX4. This recovered clock is then used to retime all four channels of incoming serial data before demultiplexing. Phase alignment on channels RX1, RX2, and RX3 is achieved by using delay-locked loops. The typical loop bandwidth of the PLL clock recovery circuit is 1.5MHz. Delay-Locked Loop (DLL) Phase Recovery The delay-locked loops in the RX1, RX2, and RX3 receive path are used to phase align the incoming data to the clock generated by the PLL. Because all serial channels originate from the same source and travel down the same cable, it is assumed that the low-frequency jitter on channel 4 is common to all channels. This allows the PLL to maintain frequency/phase align10 The CML inputs of the MAX3780 (RX1–RX4) provide equalization to further compensate for cable losses. The equalization circuit will typically add about 2dB of boost at 2GHz. Lock Detection The LOCK output indicates the state of both the transmitter and receiver PLLs. For lock detect to be asserted high, both the transmitter and receiver internal-lock indicators must be high for 394µs. The internal lock signals go high once frequency lock has been achieved. For LOCK to be asserted low, either the transmitter or receiver internal-lock indicators must be low for a minimum of 1053µs. LOCK is also asserted low when RESET is forced low. LOCK will stay low for a minimum of 394µs. For the lock detector to function properly, there must be data transitions at the RX4 input and a valid reference clock input. Note: The LOCK output is not an accurate indicator of signal presence at the receiver inputs. With no data input, the LOCK output can be high, low, or toggling. ______________________________________________________________________________________ Quad 2.5Gbps Cable Transceiver VCC 2kΩ MAX3780 50Ω 50Ω RX_+ T(°C) ≈ VTEMPSENS (mV) × RX_- 1°C − 273°C mV Applications Information BER Calculation GND Figure 5. CML Input Structure VCC MAX3780 RLOAD = 10kΩ 100Ω LOCK Figure 6. LOCK Output Structure RESET Input Approximately 10ms or longer after power-up, the RESET input should be asserted low. RESET must be held low for a minimum of four reference clock cycles for it to be properly asserted. RESET is used to reset the lock state, FIFO clock logic, and delay-lock loops. Digital transmission systems will always, given enough time, have errors. This is due to the random nature of both voltage noise and timing noise, or jitter. In today’s high performance digital transmission systems, we often try to measure bit error ratios (BERs) of fewer than 1 error every 10,000,000,000 bits (BER<10 -10 ). Measuring such low error rates can prove to be problematic, since even at high data rates, the testing time required to obtain statistically significant results becomes impractical. (For more information, refer to HFTA-05.0 Statistical Confidence Levels for Calculating Error Probability.) The MAX3780 serial interface operates at 2.5Gbps and is designed to operate with a BER better than 10-16 (1 error every 10,000,000,000,000,000 bits). This will give, on average, one error every 46 days on each 2.5Gbps channel. It is practically impossible to directly test such a low BER. For this reason, we turn to mathematics to ensure that this incredible BER is met. The thermal noise in the MAX3780 serial channel is low (<1mVRMS in the CML receiver). The dominant voltage noise in the serial channel is due to crosstalk. The remaining impairments are various types of timing jitter due to clock nonidealities and data-dependant jitter. In this section, all calculations will be done in the time domain (similar to the draft technical report by ANSI T11.2, Project 1230, Fibre Channel—Methodologies for Jitter Specification) where timing jitter is applied directly and voltage noise is converted into an equivalent timing jitter. The equation relating timing jitter to error rate is below: 1UI = ΣDJp−p + α × ΣRJ2RMS ______________________________________________________________________________________ 11 MAX3780 Temperature Sensor To aid in evaluation of thermal performance, a temperature sensor is incorporated into the MAX3780. The temperature sensor may be powered on or off regardless of the state of the rest of the chip. The VCCTEMP pin provides supply voltage for the temperature sensor circuit. The TMPSENS output is designed to output a voltage proportional to the die junction temperature (1mV per Kelvin). The temperature of the die can be estimated as: MAX3780 Quad 2.5Gbps Cable Transceiver Table 2. Summary of Jitter Parameters Contributing to the BER Calculation DETERMINISTIC COMPONENTS PARAMETER TYPICAL (mUIp-p) WORST-CASE (mUIp-p) Reference Clock—Random Reference Clock—Deterministic 5 10 8.75 23.75 Transmitter—Random Transmitter—Oscillator Pulling Transmitter—Supply Noise 2.5 7.5 Transmitter—Output Stage 37.5 62.5 50 112.5 Channel—Cable Losses Channel—Crosstalk Channel—Mismatched Load 28 56 12.5 25 Receiver—VCO Phase Noise Receiver—Input-Referred Noise Receiver—Sampling Offset 187.5 7.5 15 Receiver—Supply Noise 6.25 18.75 345.5 718.5 TYPICAL WORST-CASE ALPHA = 127.8 19.6 ~0 5.7 ✕ 10-23 BER = Deterministic jitter and receiver sampling offset effectively reduce the amount of time that the receiver can sample without error. Errors occur at a rate determined by α: α= 1− ΣDJp−p ΣRJ2RMS An α >16.4 corresponds to a BER < 10-16. Refer to Maxim applications note HFAN-4.0.2 Converting Between RMS and Peak-to-Peak Jitter at a Specified BER. For a discussion of deterministic jitter and random jitter and the characteristics of each, refer to Maxim applications note HFAN-4.0.3 Jitter in Digital Communication Systems, Part 1. Table 2 shows the deterministic and random components used in the BER calculation for the MAX3780. Typical and worst-case numbers are presented. The worst-case estimate represents a BER with greater than 12 TYPICAL (mUIRMS) WORST-CASE (mUIRMS) 0.19 0.38 3.25 10 3.75 10 1.25 2.5 5.12 14.37 387.5 Receiver—Oscillator Pulling TOTALS = RANDOM COMPONENTS 6-sigma margin. Many of the worst-case components are uncorrelated variables that are taken to their individual 6-sigma limits. In summary, the predicted worst-case BER = 10-20. A typical channel will operate error free. All transmitter and channel jitter components are compared to the jitter tolerance of the receiver by translating the components to equivalent phase error in the receiver. Low-frequency jitter components are tracked by the receive PLL, and therefore contribute little to the phase error. High-frequency jitter components (beyond the loop bandwidth of the receiver) are not tracked by the receiver PLL and therefore directly translate to phase error. The phase error transfer function is essentially equivalent to the inverse of the jitter tolerance versus frequency with the high-frequency portion normalized to unity. ______________________________________________________________________________________ Quad 2.5Gbps Cable Transceiver 3) Output Stage Finite bandwidth and pulse-width distortion in the serial transmitter can cause deterministic jitter in the serial data stream. Characterization and simulation results tell us the deterministic jitter is typically 15psp-p (37.5mUIp-p) and 25psp-p (62.5mUIp-p) worst-case. Reference Clock—Deterministic A maximum deterministic jitter of 20psp-p for frequencies greater than 5kHz is stated as a requirement for the reference clock in the Reference Clock Requirements section. Combining the low-pass jitter transfer of the transmitter and the high-pass phase error transfer of the receiver results in a bandpass transfer function. For design margin, it is assumed that this deterministic jitter is within the bandpass frequency range. The typical deterministic component is 2psp-p (5mUIp-p) and the worst-case entry is 4psp-p (10mUIp-p). Channel—Deterministic 1) Cable Losses The frequency-dependent skin-effect and dielectric losses in the cable (and PC board traces) will cause data-dependent jitter (also known as intersymbol interference). Adjustable transmit precompensation and fixed receiver boost is used to reduce the cable-induced jitter. However, there will always be some uncompensated jitter due to the cable and PC board trace losses. Characterization and simulation results tell us the deterministic jitter is typically 20ps p-p (50mUIp-p) and 45ps p-p (112.5mUIp-p) worst-case. Transmitter—Random This is the random jitter that results from the transmitter VCO phase noise and is an AC parameter guaranteed in the AC Electrical Characteristics table. Typical measured numbers are 1.3ps RMS (3.3mUI RMS) and the worst-case specification is 4.0psRMS (10mUIRMS). Transmitter—Deterministic 1) Oscillator Pulling The transmitter and receiver integrated LC oscillators when running at small frequency differences will beat with each other at a rate equivalent to the frequency difference between the oscillators. Typical Operating Characteristic plot RX to TX VCO PULLING shows the typical transmitter jitter versus frequency difference. When referred to the phase error transfer, the deterministic jitter is typically 3.5psp-p (8.75mUIp-p) and 9.5psp-p (23.75mUIp-p) worst-case. 2) Supply Noise Noise on the power supply will modulate the transmit PLL output according to the typical transfer curve shown in the Typical Operating Characteristic plot TRANSMITTER POWER-SUPPLY REJECTION. Combining this transfer function with the phase error transfer of the receiver results in a band-pass characteristic. At the peak of this band pass, the typical transfer is 100fs/mV and the worst-case transfer is 300fs/mV. Making the worst-case assumption that all the supply noise is at this peak with a value of 10mV results in typically 1psp-p (2.5mUIp-p) and worstcase 3psp-p (7.5mUIp-p). 2) Crosstalk The MAX3780 channel requirements allow for crosstalk of up to 5% to be present at the RX inputs. This is a peak-to-peak voltage measurement which refers to 5% of the transmitter amplitude. Characterization and simulation results tell us the deterministic jitter due to crosstalk is typically 11.2psp-p (28mUIp-p) and 22.4psp-p (56mUIp-p) worst-case. 3) Mismatched Load Jitter Incorrect impedances in PC board traces, connectors, cables, and terminations can cause reflections that can, in turn, cause deterministic jitter. These effects are more pronounced on short cables (less attenuation of the reflection) where timing margins are highest. While measurements already account for mistermination effects, we have allocated an additional fixed budget for jitter induced by reflections. Characterization and simulation results tell us the deterministic jitter due to load mismatch is typically 5psp-p (12.5mUIp-p) and 10psp-p (25mUIp-p) worst-case. Receiver—Random 1) VCO Phase Noise This is the random jitter that results from the receiver VCO phase noise and is an AC parameter guaranteed in the AC Electrical Characteristics table. Typical measured numbers are 1.5psRMS (3.75mUIRMS) and the worst-case specification is 4psRMS (10mUIRMS). ______________________________________________________________________________________ 13 MAX3780 Reference Clock—Random A maximum random jitter of 15psRMS for frequencies less than 5kHz is stated as a requirement for the reference clock in the Reference Clock Requirements section. Translating this to the phase error of the receiver gives 75fs RMS (0.19mUI RMS ) typical and 150fs RMS (0.38mUIRMS) worst-case. MAX3780 Quad 2.5Gbps Cable Transceiver 2) Input-Referred Noise All electronic circuits generate random noise. The input-referred noise voltage of the CML RX inputs is < 0.5mVRMS. This will contribute <1psRMS jitter. In the BER calculation, it is assumed the jitter is typically 0.5ps RMS (1.25mUI RMS ) and 1ps RMS (2.5mUIRMS) worst-case. Receiver—Deterministic 1) Sampling Offset The peak-to-peak sampling offset in the receiver is equal to 1UI minus the jitter tolerance minus the random jitter of the receiver. Removal of the random jitter is necessary since receiver VCO Phase Noise in Table 2 accounts for this. For simplicity, the random jitter portion will be assumed to be the typical measured value of 25ps p-p (62.5mUIp-p). Using the numbers from the AC parameter electrical table, the typical sampling offset is calculated to be 187.5mUIp-p and the worst-case is 387.5mUIp-p. 2) Oscillator Pulling The transmitter and receiver integrated LC oscillators, when running at small frequency differences, will beat with each other at a rate equivalent to the frequency difference between the oscillators. Typical Operating Characteristic plot TX to RX VCO PULLING shows the typical receiver jitter versus frequency difference. Typically the receiver oscillator pulling jitter is 3psp-p (7.5mUIp-p) and worst-case is 6psp-p (15.0mUIp-p). 3) Supply Noise terminate these outputs to ground. The parallel data LVDS inputs (TCLK+, TCLK-, TDAT_+, TDAT_-) are internally terminated with 100Ω differential input resistance and therefore do not require external termination. The LVDS inputs must be biased for proper operation. DC-coupling LVDS outputs and inputs together provides sufficient biasing. When interfacing to laboratory test equipment, AC-coupling cannot be used. A signal source with DC offset must be used. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance 50Ω transmission lines to interface with the MAX3780 high-speed inputs and outputs. Place power-supply decoupling as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals. Exposed-Pad (EP) Package The exposed-pad 100-pin TQFP-EP incorporates features that provide a very low thermal resistance path for heat removal from the IC. The pad is electrical ground on the MAX3780 and must be soldered to the circuit board for proper thermal and electrical performance. Noise on the power supply will modulate the receive PLL sampling point according to the typical transfer curve shown in Typical Operating Characteristic plot RECEIVER POWER-SUPPLY REJECTION. Using a typical transfer of 250fs/mV and a worst-case transfer of 750fs/mV with 10mV of supply noise results in 2.5psp-p (6.25mUIp-p) and 7.5psp-p (18.75mUIp-p) respectively. Low-Voltage Differential Signal (LVDS) Inputs/Outputs The MAX3780 has LVDS inputs and outputs for interfacing with high-speed digital circuitry. All LVDS inputs and outputs are compatible with the IEEE-1596.3 LVDS specification. This technology uses 250mV to 400mV differential low-voltage amplitudes to achieve fast transition times, minimize power dissipation, and improve noise immunity. For proper operation, the parallel clock and data LVDS outputs (RCLK+, RCLK-, RDAT_+, RDAT_-) require 100Ω differential DC terminations between the inverting and noninverting outputs. Do not 14 ______________________________________________________________________________________ Quad 2.5Gbps Cable Transceiver PARAMETER SYMBOL Impedance CONDITIONS MIN Differential Through Loss at 1GHz (S12, S21) Wideband Through Loss (S12, S21) Return Loss at 1GHz (S11, S22) Wideband Return Loss (S11, S22) TYP UNITS Ω f = 1GHz, 3m channel 4.0 5.0 f = 1GHz, 1m channel 1.5 2.4 3.2 f = 1GHz, 0.5m channel 1.0 1.7 2.6 6.0 dB See Figures 7–9 -12 dB 5 % MAX UNITS -100 +100 ppm 40 60 % See Figure 10 % of signal at aggressor. Near-end and far-end aggressors driven with 100ps (20% to 80%) edges. End of channel terminated with 100Ω. Channel Crosstalk MAX 100 Reference Clock Requirements PARAMETER SYMBOL CONDITIONS MIN REFCLK Frequency TYP 125 REFCLK Frequency Tolerance REFCLK Duty Cycle f < 5kHz (jitter assumed Gaussian) REFCLK Jitter f > 5kHz (jitter is assumed deterministic, caused by power-supply noise and buffer jitter) MHz 240 psp-p 15 psRMS 20 psp-p UNITS Parallel Fiber Module Requirements PARAMETER Differential Input Impedance SYMBOL CONDITIONS RIN MIN TYP MAX 80 100 120 Ω 300 mVp-p 80 psp-p 800 mVp-p 120 Ω 5 % Transmitter Input Sensitivity Deterministic and random jitter, peak-topeak, (DJ + 16.4 × RJRMS) Total Jitter Generation Receiver Data Output Amplitude Differential Output Impedance Channel-to-Channel Crosstalk Differential ROUT 300 80 100 ______________________________________________________________________________________ 15 MAX3780 Channel Requirements MAX3780 Quad 2.5Gbps Cable Transceiver 0.5m CHANNEL LOSS 1m CHANNEL LOSS 0 0 -1.00 -1.00 -2.00 UPPER MASK -2.00 UPPER MASK -3.00 -4.00 dB NOMINAL -4.00 dB -3.00 NOMINAL -5.00 -6.00 -7.00 -5.00 LOWER MASK -8.00 -6.00 LOWER MASK -7.00 -9.00 -10.00 0 500 1000 1500 2000 2500 3000 3500 4000 500 1000 1500 2000 2500 3000 3500 4000 0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. 0.5m Channel Loss Mask Figure 8. 1.0m Channel Loss Mask 3m CHANNEL LOSS RETURN LOSS MASK 0 -2.00 -4.00 UPPER MASK -8.00 dB dB -6.00 -10.00 NOMINAL -12.00 -14.00 LOWER MASK -16.00 -18.00 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) Figure 9. 3.0m Channel Loss Mask 16 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) Figure 10. Channel Input Return Loss Mask ______________________________________________________________________________________ Quad 2.5Gbps Cable Transceiver GND VCC6 TDAT8- TDAT8+ TDAT7- TDAT7+ TDAT6- TDAT6+ TDAT5- TDAT5+ TDAT4- TDAT4+ TDAT3- TDAT3+ TDAT2- TDAT2+ TDAT1- TDAT1+ TCLK- TCLK+ GND VCC6 REFCLK- REFCLK+ GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TOP VIEW GND 1 75 GND VCC1 2 74 VCC5 RDAT1+ 3 73 TXFIL RDAT1- 4 72 RESET RDAT2+ 5 71 GND RDAT2- 6 70 VCC4 RDAT3+ 7 69 TX1+ RDAT3- 8 68 TX1- RDAT4+ 9 67 VCC4 RDAT4- 10 66 TX2+ VCC1 11 65 TX2- GND 12 64 VCC4 RDAT5+ 13 63 GND RDAT5- 14 62 VCC4 RDAT6+ 15 61 TX3+ RDAT6- 16 60 TX3- RDAT7+ 17 59 VCC4 RDAT7- 18 58 TX4+ RDAT8+ 19 57 TX4- RDAT8- 20 56 VCC4 RCLK+ 21 55 GND RCLK- 22 54 EQ1 TRIEN 23 53 EQ2 VCC1 24 52 PTPIN GND 25 51 GND 48 49 50 VCCTEMP TMPSENS GND VCC3 47 44 RX1+ LOOPEN 43 RX1- 46 42 VCC3 45 41 RX2+ GND 40 VCC6 39 38 RX2- 37 RX4- RX3+ 33 VCC3 VCC3 32 GND 36 31 VCC2 RX3- 30 RXFIL 35 29 34 28 GND RX4+ 27 LOCK VCC3 26 GND MAX3780 CABLE TRANSCEIVER TQFP - EP* *EXPOSED PAD MUST BE CONNECTED TO GROUND Chip Information TRANSISTOR COUNT: 15,270 PROCESS: Bipolar ______________________________________________________________________________________ 17 MAX3780 Pin Configuration Quad 2.5Gbps Cable Transceiver MAX3780 Package Information 18 ______________________________________________________________________________________ Quad 2.5Gbps Cable Transceiver Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3780 Package Information (continued)