ETC AV2636

AVS Technology
AV2636
24-bit 192kHz Stereo Audio DAC
DESCRIPTION
The AV2636 is a high performance, low power
stereo audio digital to analog converter (DAC). It
is designed for high performance audio
applications such as CD player, DVD player,
home theater systems, digital TVs and set top
boxes. Based on the state of the art multi-bit
∆−Σ modulator, it also includes the digital
interpolation filters, digital volume control, digital
de-emphasis and analog low pass filters. It has
no linearity drift due to time and temperature. It
also has high tolerance to clock jitter.
The device has a serial audio interface that
accepts 16/18/20/24 digital data in I2S, Rightjustified or DSP mode. It can work at auto-detect
mode or programmable mode with a two-wire
serial command interface. Audio sample rates
from 8kHz to 192kHz are supported.
FEATURES
•
•
•
•
•
•
•
•
•
•
SNR: 102 dB
THD+N: -90 dB
Input Sample rate: 8kHz – 192kHz
Input data resolution: 16/18/20/24 bits
Digital De-Emphasis for 32k/44.1k/48kHz
Digital Volume Control
Mute Control
Single Power Supply 2.2V – 3.6V
Low Clock Jitter Sensitivity
Small 14-pin SOIC Package
APPLICATIONS
•
•
•
•
DVD/CD Player
Home Theatre Systems
Digital TV and Set-Top Boxes
Electronic Music Instrument
CHIP BLOCK DIAGRAM
SC
SF
SERIAL
AUDIO
INTERFACE
INTERPOLATION
DIGITAL
FILTERS
MULTI-LEVEL
∆−Σ
MODULATOR
SD
DAC
LOW PASS
FILTER
AOUTL
DAC
LOW PASS
FILTER
AOUTR
CONTROL INTERFACE
FMTC
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FMTD
MUTE
MODE
MCK
1-16
VDD
VCM
GND
August 18, 2004
AV2636
Product Datasheet
PIN CONFIGURATION
SF
1
14
MCK
SD
2
13
FMTD
SC
3
12
FMTC
NC
4
11
MODE
VCM
5
10
MUTE
AOUTR
6
9
AOUTL
GND
7
8
VDD
AV2636
PIN DESCRIPTION
Pin Name
SF
SD
Pin
1
2
Type
Digital Input
Digital Input
SC
(NC)
VCM
3
4
5
Digital Input
Analog Output
AOUTR
GND
VDD
AOUTL
MUTE
6
7
8
9
10
Analog Output
Supply
Supply
Analog Output
Digital Input
MODE
11
Digital Input
FMTC
12
Digital Input
FMTD
13
Digital I/O
MCK
14
Digital Input
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Description
Sample rate frame clock input.
Audio data input. It can be 16/18/20/24 bit in 2’s complement
format.
Serial audio data bit clock input.
No Connection
Common mode voltage output. Connect to 10uF cap in parallel with
0.1uF cap.
Right channel analog audio signal output.
Ground supply. Need a solid ground plane.
Power supply. Need a clean power supply.
Left channel analog audio signal output.
Mute control with internal pull down.
High = Mute on.
Low = Mute off.
Chip operation mode selection with internal pull down.
High = Programmable mode.
Low = Auto-detect mode.
Dual functional pin. Its function is controlled by the MODE pin.
Internal pull up.
When MODE = High, FMTC = Serial clock in control interface.
When MODE = Low, FMTC = De-Emphasis: On (high) / Off (low).
Dual functional pin. Its function is controlled by the MODE pin.
Internal pull up. Needs an external 4.7kΩ to VDD.
When MODE = High, FMTD = Serial data in control interface.
When MODE = Low, FMTD = Data input format select:
High = 16-24 bit I2S or 16 bit DSP ‘early’
Low = 16 bit right justified or 16 bit DSP ‘late’
External master clock input. The clock frequency depends on the
audio sample rate.
2-16
August 18, 2004
AV2636
Product Datasheet
ORDERING INFORMATION
PRODUCT
AV2636
PACKAGE
14 pin SOIC
TEMPERATURE RANGE
-25˚C — +85˚C
ELECTROSTATIC DISCHARGE SENSITIVITY
The device of integrated circuits is manufactured on CMOS process. It can be damaged by ESD. AVS
Technology recommends that the device be handled with appropriate ESD precautions. Improper
handling and installation procedures can cause damage to the device.
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are the limiting values of the stress. Operation beyond these limits may cause
permanent damage to the device. Normal operation is not guaranteed at these limits.
Symbol
VDD
Vi
Ai
TA
Tstg
Tj
Tsol
Tvsol
Characteristics
Power supply voltage (Measured to GND)
Digital input voltage range
Digital input forced current
Ambient operating temperature range
Storage temperature range
Junction temperature (Plastic package)
Lead soldering temperature (10 sec., ¼” from pin)
Vapor phase soldering (1 minute)
Min
-0.3
GND – 0.3
-100
-25
-65
-65
Max
+3.6
VDD + 0.3
+100
+125
+150
+150
+240
+220
Units
V
V
mA
˚C
˚C
˚C
˚C
˚C
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
GND
MCK
TA
Characteristics
Power supply voltage
Ground
Master clock frequency
Ambient operating temperature range
AVS Technology, Inc.
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3-16
Min
2.2
-25
Typical
3.3
0
Max
3.6
75
85
Units
V
V
MHz
˚C
August 18, 2004
AV2636
Product Datasheet
ELECTRICAL CHARACTERISTICS
(Test conditions: VDD = 3.3V, GND = 0V, TA = +25˚C, fs = 48kHz, MCK = 256fs unless otherwise stated.
The measurement bandwidth is from 20Hz to 20kHz.)
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
DC Electrical Characteristics
Supply current (VDD = 3.3V)
IDD
10
mA
Supply current (VDD = 2.5V)
IDD
7
mA
Digital I/O Levels (TTL Level)
Digital input high level
VIH
2.0
V
Digital input low level
VIL
0.8
V
Digital output high level (IOH = 2mA)
VOH
VDD–0.2
V
Digital output low level (IOL = 2mA)
VOL
GND+0.2
V
Analog Characteristics
Reference voltage
VCM
VDD/2
V
Full scale analog output level
AOUT
VDD/3.3
Vrms
Minimum resistive load
RL
10
kΩ
Maximum capacitive load
CL
100
pF
Output DC level
VDD/2
V
DAC Analog Output Performance (Test load RL = 10kΩ, CL = 10pF)
VDD = 3.3V SNR
102
dB
THD+N (1kHz, 0dBFs input)
-90
dB
Dynamic Range (1kHz, -60dBFs input)
98
dB
VDD = 2.5V SNR
100
dB
THD+N (1kHz, 0dBFs input)
-90
dB
Dynamic Range (1kHz, -60dBFs input)
96
dB
Channel separation (1kHz)
-95
dB
Interchannel gain mismatch
0.1
dB
Program gain range
-∞
+6
dB
Notes:
1. SNR is measured as the ratio of output level with 1kHz full scale signal, to output level with all zero
signal into the digital input. The measurement is over 20Hz to 20kHz bandwidth with a ‘A-weight’ filter.
2. THD is measured at the output with 1kHz full scale signal into the digital input. The measurement is
over 20Hz to 20kHz bandwidth.
3. Dynamic Range is the ratio of maximum output over minimum output. It is normally measured by
THD+N at the output with an input signal that is 60dB below full scale. The 60dB is then added back
to the THD+N value for the final result.
4. Channel separation is also known as channel cross talk. It is measured by sending a 1kHz full scale
signal into one channel and measuring the output value at the other channel.
5. All measurements are done with a 20kHz low pass filter. Fail to use the filter will result in reduced
performance reading.
6. The VCM pin should be decoupled with a 10uF capacitor in parallel with a 0.1uF capacitor. Smaller
value may result in reduced performance.
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AV2636
Product Datasheet
OPERATING MODE
The AV2636 can operate at two modes. They are auto-detect mode and programmable mode. The
‘MODE’ pin status (High/Low) determines which mode the device will be operated. If MODE = Low (pull to
GND or not connected using internal pull down), the device will be operated at auto-detect mode. If
MODE = High (pull to VDD), the device will be operated at programmable mode. The basic functions of
the two modes are described as follows:
• Auto-detect mode: The relation between sample rate and master clock frequency is auto detected.
De-emphasis and serial interface mode are determined by FMTC and FMTD pins.
• Programmable mode: The device operation will be set by on chip control registers that can be
accessed through a two-wire command interface.
AUDIO DATA SAMPLE RATE AND MASTER CLOCK FREQUENCY
The AV2636 supports various audio data sample rate (fs) from 8kHz to 192kHz. The typical audio sample
rates are 32kHz, 44.1kH, 48kHz, 96kHz and 192kHz. The master clock (MCK) can be of 64fs to 384fs
depending on the operation mode. MCK is an input clock that operates the internal digital filters. Other on
chip clocks are also derived from MCK.
The on-chip master clock detection circuit automatically determines the relationship of master clock
frequency and audio sample rate. The counting error is set to be ±8 master clock cycles. If the error is
larger than the threshold, the DAC output will be shut down and auto muted.
The master clock has to be synchronized with the serial audio data frame signal ‘SF’. SF is also called left
and right data frame signal. The phase difference and clock jitters can be tolerated.
Sample
Rate (fs)
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
192 kHz
64fs
N/A
N/A
N/A
N/A
N/A
12.288
96fs
N/A
N/A
N/A
N/A
N/A
18.432
Master Clock Frequency MCK (MHz)
128fs
192fs
256fs
N/A
N/A
8.192
N/A
N/A
11.2896
N/A
N/A
12.288
11.1896
16.9344
22.5792
12.288
18.432
24.576
24.576
36.864
49.152*
384fs
12.288
16.9344
18.432
33.8688
36.864
73.728*
Note:
* Only available at programmable mode.
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August 18, 2004
AV2636
Product Datasheet
DIGITAL AUDIO DATA INTERFACE
The serial audio data is send to the device through a three-wire interface. The interface consists of three
input pins that are serial clock (SC), serial data (SD) and sync-frame (SF). The sync-frame is also a
left/right channel indicator. Three interface formats are supported.
• I2S mode
• Right justified mode
• DSP mode
All formats send MSB first. The audio data is in 2’s complement format. The mode selection can be either
in auto-detect mode or programmable mode.
The three-wire digital audio data interface timing specification is shown at the following diagram.
SF
tSC
tSFH
tSFS
SC
tSCH
tSCL
SD
tDCS
tDCH
The timing characteristics are shown at the following table.
Symbol
tSC
tSCH
tSCL
tDCS
tDCH
tSFH
tSFS
Description
SC clock cycle time
SC pulse width high
SC pulse width low
SD data setup time relative to SC rising edge
SD data hold time relative to SC rising edge
SF hold time relative to SC rising edge
SF setup time relative to SC rising edge
Min
50
20
20
10
10
10
10
Max
Units
ns
ns
ns
ns
ns
ns
ns
I2S MODE
In I2S mode, the serial interface accepts input data at SD pin and frame input at SF pin. The serial
data is time multiplexed with the frame signal SF indicating left and right channel data. SF is low
during left channel data and high during right channel data. The SF is also a timing signal for the
start of each word of left and right channel.
The MSB of the audio data SD is sampled on the second rising edge of SC following SF transition.
Word lengths of 16/18/20/24 bits are supported.
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August 18, 2004
AV2636
Product Datasheet
1/fs
SF
Left Channel
Right Channel
SC
1 SC
1 SC
SD
n-1 n-2
1
MSB
0
n-1 n-2
LSB
1
MSB
0
LSB
RIGHT JUSTIFIED MODE
In right justified mode, the serial interface accepts input data at SD pin and frame input at SF pin.
The serial data is time multiplexed with the frame signal SF indicating left and right channel data.
SF is high during left channel data and low during right channel data. The SF is also a timing
signal for the end of each word of left and right channel.
The MSB is received first and LSB is aligned with the transition of frame signal SF. Data is
sampled at the rising edge of SC. Word lengths of 16/18/20/24 bits are supported.
1/fs
SF
Left Channel
Right Channel
SC
SD
n-1 n-2
1
MSB
0
LSB
n-1 n-2
MSB
1
0
LSB
DSP MODE
In DSP mode, the serial interface accepts input data at SD pin and frame input at SF pin. Audio
data SD is time multiplexed with left channel first followed by right channel data. Frame sync SF
appears every 1/fs time. Minimum SF pulse high is 1 SC cycle and maximum SF pulse high is 8
SC cycles. Both DSP ‘early’ mode and ‘late’ mode are supported.
The MSB is received first. Data is sampled at the rising edge of SC. Word lengths of 16/18/20/24
bits are supported.
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August 18, 2004
AV2636
Product Datasheet
DSP ‘early’ mode:
1/fs
SF
Max 8 SC cycles
SC
1 SC
Left Channel
SD
n-1 n-2
Right Channel
1
MSB
0 n-1 n-2
1
LSB MSB
0
No Valid Data
LSB
DSP ‘late’ mode:
1/fs
SF
Max 8 SC cycles
SC
Left Channel
SD
n-1 n-2
MSB
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Right Channel
1
0 n-1 n-2
LSB MSB
8-16
1
0
No Valid Data
LSB
August 18, 2004
AV2636
Product Datasheet
SERIAL CONTROL INTERFACE
The AV2636 supports a 2-wire I2C compatible serial control interface. When MODE pin is externally
pulled high, the FMTC and FMTD pins function as SCL and SDA. Where SCL is serial clock input and
SDA is serial data input and output. The internal control registers can be programmed through the
interface.
The chip ID for the AV2636 is a 7-bit hexadecimal number “32hex”. The protocol for write operation
consists of sending 3 bytes of data to the AV2636 at SDA pin. Following each byte is the acknowledge bit
generated by the AV2636. The first byte is the 7-bit chip ID followed by the read/write bit (read is logic
high and write is logic low). The second byte is control register address. The third byte is control register
data. The following diagram shows a “write” sequence and timing of control register address 00H and
data 30H.
START CA6
SDA
0
1
CA0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP
1
0
0
1
1
SCL
Chip ID:
CA[6:0] = 0110010
Register Address: A[7:0] = 00H
Data:
D[7:0] = 30H
Timing specifications
tBF
SDA
tDH_STA
tHIGH
tDH_DA
tDS_DA
tDS_STA
tDS_STO
SCL
STOP
tLOW
START
tf
Symbol
fSC
tDS_STA
tDH_STA
tDS_STO
tLOW
tHIGH
tr
tf
tDS_DA
tDH_DA
tBF
START
Descriptions
SCL clock frequency
START condition SDA setup time
START condition SDA hold time
STOP condition SDA setup time
SCL low pulse time
SCL high pulse time
SCL and SDA rise time
SCL and SDA fall time
Data setup time
Data hold time
Bus free time
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STOP
tr
9-16
Min
Max
100
4.7
4.0
4.0
4.7
4.0
1.0
0.3
250
0
4.7
Units
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
August 18, 2004
AV2636
Product Datasheet
PROGRAMMABLE CONTROL REGISTER ASSIGNMENT
There are 4 programmable control registers in AV2636. Their function and address assignment are
described in the following tables. All the contents of the programmable control registers can be read back
through the serial control interface.
Address
(7-bit hex)
0
1
2
3
Register
CREG0[7:0]
CREG1[7:0]
CREG2[7:0]
CREG3[7:0]
Default Value
(hex)
7F
00
00
00
Function Description
Volume control for both left and right channel
Device control
Serial audio interface mode control
Clock and sample rate settings
Volume Control Register (CREG0[7:0])
Address
7’h00
Bit7
Bit6
Bit5
Default Value
0
1
1
CREG0[7:0]
Bit4
Bit3
VOLUME[7:0]
1
1
Bit2
Bit1
Bit0
1
1
1
Bit2
Bit1
0
0
Bit0
Mute
0
Device Control Register (CREG1[7:0])
Address
7’h01
Default Value
Bit7
StdBy
0
Bit6
DeEmp
0
Bit5
0
CREG1[7:0]
Bit4
Bit3
Reserved
0
0
StdBy: Stand-By Control
0: disable Stand-By (default)
1: enable Stand-By for power saving
(Notes: Mute should be enabled when StdBy is enabled.)
DeEmp: De-emphasis control
0: by-pass de-emphasis filter (default)
1: enable de-emphasis filter
Mute: Software mute control
0: do not mute the left and right channel DACs (default)
1: mute the left and right channel DACs simultaneously
Serial Audio Interface Control Register (CREG2[7:0])
Address
7’h02
Default Value
Bit7
Bit6
Reserved
0
0
Bit5
SFJ
0
CREG2[7:0]
Bit4
Bit3
Bit2
SCJ
SAIM[1:0]
0
0
0
Bit1
Bit0
Format[1:0]
0
0
SFJ: Sync Frame Adjustment
0: do not delay SF signal by 1 SC clock cycle (default)
1: delay SF signal by 1 SC clock cycle
SCJ: Serial Clock Adjustment
0: do not invert SC clock (default)
1: invert SC clock
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AV2636
Product Datasheet
SAIM[1:0]: Serial Audio Interface Mode Control
00: I2S mode
01: DSP ‘early’ mode
10: right justified mode
11: DSP ‘late’ mode
Format[1:0]: Serial Audio Interface Data Resolution
00: 24-bit resolution (default)
01: 20-bit resolution
10: 18-bit resolution
11: 16-bit resolution
Master Clock and Sample Rate Setting Register (CREG3[7:0])
Address
7’h03
Bit7
Default Value
0
Bit6
Bit5
Reserved
0
0
CREG3[7:0]
Bit4
Bit3
0
0
Bit2
Bit1
CKSET[3:0]
0
0
Bit0
0
CKSET[3:0]: The internal operation of AV2636 is affected by the relations between MCK
frequency and input audio sample rate. The correct setting of these 4-bit based on the relations
ensures the correct operation of the device. The following table shows the values of the 4-bit.
CKSET[3:0] For Various Clock and Sample Rate
Sample Rate (kHz)
1X Speed 32/44.1/48
32/44.1/48
2X Speed 88.2/96
88.2/96
88.2/96
88.2/96
4X Speed 192
192
192
192
192
192
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MCK (MHz)
8.192/11.2896/12.288
12.288/16.934/18.432
11.2896/12.288
16.9344/18.432
22.5792/24.576
33.8688/36.864
12.288
18.432
24.576
36.864
49.152
73.728
11-16
256fs
384fs
128fs
192fs
256fs
384fs
64fs
96fs
128fs
192fs
256fs
384fs
0
1
0
1
0
1
0
1
0
1
0
1
CKSET[3:0]
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
August 18, 2004
AV2636
Product Datasheet
DIGITAL FILTER CHARACTERISTICS
The digital interpolation filters have small passband ripples and large stopband attenuations. There are
three types of filters that are implemented for different sample mode (1X/2X/4X) and MCK relations. The
selection of the filters depends on the operation mode of the device, auto-detect mode or programmable
mode.
Programmable mode: filter selection is shown in the following table. 20kHz audio passband is assumed.
Sample Mode
Normal (1X)
Double (2X)
Quad (4X)
Parameter
Passband Ripple
Stopband Attenuation
Passband Ripple
Stopband Attenuation
Passband Ripple
Stopband Attenuation
Condition
F < 0.45fs
F > 0.55fs
F < 0.225fs
F > 0.775fs
F < 0.1125fs
F > 0.8875fs
Min
Max
±0.03
60
±0.03
60
±0.03
53
Unit
dB
dB
dB
dB
dB
dB
Auto-detect mode: filter type is automatically selected based on the detected sample mode and MCK
relations.
The following plots show the digital filter response and closer look of the passband ripple for normal
speed mode (1X), double speed mode (2X) and quad speed (4X).
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AV2636
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Product Datasheet
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August 18, 2004
AV2636
Product Datasheet
DIGITAL DE-EMPHASIS CHARACTERISTIC
The device has a build in digital de-emphasis filter that can be utilized or bypassed in either auto-detect
mode or programmable mode. The characteristic of the filter for 44.1kHz sample frequency is shown as
follows:
Gain (dB)
0 dB
T1=50µs
T1=15µs
-10 dB
F1=3.18kHz
F2=10.61kHz
Frequency
The filter response scales with sample frequency fs and is only applied to 1X sample speed mode.
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August 18, 2004
AV2636
Product Datasheet
RECOMMENDED APPLICATION CONNECTIONS
2.3V – 3.6V
+ 10uF
C2
0.1uF
8
C1
1
2
3
Audio
Data
Processor
VDD
SF
SD
SC
10uF
AOUTR
6
AV2636
10
11
12
13
Hardware
& Software
Control
10uF
AOUTL
MUTE
MODE
FMTC
FMTD
External
Low Pass
Filters for
L/R Channel
VCM
9
5
GND
0.1uF
+ 10uF
C3
C4
7
Notes:
1. Power supply VDD should be a clean analog power that separated from system digital power.
2. C1 and C3 should be placed as close to the AV2636 as possible.
3. Use low ESR capacitors for better performance.
RECOMMENDED EXTERNAL LOW PASS FILTER
1.0nF
2.2kΩ
10kΩ
Vi
+
+Vs
51Ω
Vo
680pF
−
47kΩ
-Vs
10kΩ
10kΩ
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August 18, 2004
AV2636
Product Datasheet
PACKAGE INFORMATION
e
B
14
8
14 PIN SOIC 3.9 mm BODY WIDE
E
1
H
7
D
h x 45˚
A
A1
C
α
SEATING PLANE
Symbols
A
A1
B
C
D
E
e
H
h
L
α
L
Dimensions (mm)
Min
Max
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
8.55
8.75
3.80
4.00
1.27 BSC
5.8
6.2
0.25
0.5
0.40
1.27
0˚
8˚
Dimensions (inches)
Min
Max
0.0532
0.0688
0.0040
0.0098
0.0130
0.0200
0.0075
0.0098
0.3367
0.3444
0.1497
0.1574
0.05 BSC
0.2284
0.2440
0.0099
0.0196
0.0160
0.0500
0˚
8˚
Note:
The package meets JEDEC.95, MS-012. Refer it for further details.
IMPORTANT NOTICE:
AVS Technology, Inc. believes that the information contained in the document is accurate and reliable. However, the information is
provided “AS IS” without any kind of warranty. AVS reserves the right to change the product and the document without prior notice.
Customers are advised to obtain the latest version of the relevant information before placing order. No liability is assumed by AVS
for infringement of any patent, intellectual property, or other rights in the application that use this product and information contained
herein.
AVS Technology, Inc. assumes no liability for any kind of sequential damage due to the use of its product.
AVS Technology, Inc.
www.avstech.com
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August 18, 2004