CS4350
192 kHz Stereo DAC with Integrated PLL
Features
Advanced Multi-bit Delta-Sigma Architecture
Popguard® Technology for Control of Clicks
and Pops
– Hardware Popguard Disable for Fast
Startups
108 dB Dynamic Range
-95 dB THD+N
24-Bit Conversion
Supports All Standard Serial Audio Formats
Supports Audio Sample Rates Up to 192 kHz
Including Time-Division Multiplexed (TDM)
Low-Latency Digital Filtering
+1.5 V to 5.0 V Logic Supplies for Serial Port
Single-Ended or Differential Analog Output
+3.3 V to 5.0 V Control Port Interface
Architecture
Control Port Mode Features
Integrated PLL Locks to Incoming Left-Right
Clock
– Eliminates the Need for External Masterclock Routing
– Reduces Interference and Jitter Sensitivity
– No External Loop Filter Components
Required
Automatic Sample-Rate Range Detection
SPI™ and I²C® Modes
ATAPI Mixing
Mute Control for Individual Channels
Digital Volume Control with Soft Ramp
–
–
–
119 dB Attenuation
1/2 dB Step Size
Zero Crossing Click-Free Transitions
3.3 V to 5.0 V
Reset
PCM
Serial
Interface
LRCK
Level Translator
1.5 V to 5.0 V
Serial Audio Input
Register/
Hardware
Configuration
Recovered MCLK
Multibit ∆Σ
Modulator
DAC
Amp
+
Filter
Left
Channel
Output
Interpolation
Filter with
Volume
Control
Multibit ∆Σ
Modulator
DAC
Amp
+
Filter
Right
Channel
Output
External
Mute
Control
Left and
Right Mute
Controls
RMCK Phase Locked Loop
Advance Product Information
http://www.cirrus.com
Interpolation
Filter with
Volume
Control
RMCK
Hardware or I2C/
SPI Control Data
Level Translator
3.3 V to 5.0 V
Internal Voltage
Reference
and Regulation
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
MARCH '06
DS691A3
CS4350
Description
The CS4350 is a complete stereo digital-to-analog system including PLL-based master clock derivation, digital interpolation, 5th-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, volume control,
channel mixing, and analog filtering. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to
clock jitter, and a minimal set of external components.
The CS4350 supports all standard digital audio interface formats, including TDM.
The CS4350 is available in a 24-pin TSSOP package in both Commercial (-10° to +70°C) and Automotive grades
(-40° to +85°C). The CDB4350 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 39 for complete ordering information.
These features are ideal for cost-sensitive, 2-channel audio systems, including DVD players, A/V receivers, set-top
boxes, digital TVs and VCRs, mini-component systems, and mixing consoles.
2
DS691A3
CS4350
TABLE OF CONTENTS
1. PIN DESCRIPTION.................................................................................................................................. 6
2. CHARACTERISTICS AND SPECIFICATIONS....................................................................................... 8
SPECIFIED OPERATING CONDITIONS .................................................................................................... 8
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8
DAC ANALOG CHARACTERISTICS........................................................................................................... 9
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 11
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE.............................................................. 12
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT.................................................... 13
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT................................................... 14
DIGITAL CHARACTERISTICS .................................................................................................................. 15
POWER AND THERMAL CHARACTERISTICS........................................................................................ 15
3. TYPICAL CONNECTION DIAGRAM .................................................................................................. 16
4. APPLICATIONS .................................................................................................................................... 17
4.1 Sample Rate Range and Oversampling Mode Detect................................................................... 17
4.1.1 Sample Rate Auto-Detect .................................................................................................... 17
4.2 System Clocking ............................................................................................................................ 17
4.2.1 Recovered Master Clock (RMCK)........................................................................................ 17
4.3 Digital Interface Format ................................................................................................................. 18
4.3.1 Time-Division Multiplex (TDM) Mode ................................................................................... 19
4.4 De-Emphasis ................................................................................................................................. 20
4.5 Mute Control .................................................................................................................................. 20
4.6 Recommended Power-Up Sequence ............................................................................................ 20
4.6.1 Stand-Alone Mode ............................................................................................................... 20
4.6.2 Control Port Mode ................................................................................................................ 20
4.7 Popguard® Transient Control ........................................................................................................ 21
4.7.1 Power-Up ............................................................................................................................. 21
4.7.2 Power-Down......................................................................................................................... 21
4.7.3 Discharge Time .................................................................................................................... 21
4.8 Analog Output and Filtering ........................................................................................................... 22
4.9 Grounding and Power Supply Arrangements ................................................................................ 22
4.9.1 Capacitor Placement............................................................................................................ 22
5. STAND-ALONE OPERATION............................................................................................................... 23
5.1 Serial Port Format Selection.......................................................................................................... 23
5.2 De-emphasis Control ..................................................................................................................... 23
5.3 Popguard® Transient Control........................................................................................................ 23
6. CONTROL PORT OPERATION ............................................................................................................ 24
6.1 MAP Auto Increment ..................................................................................................................... 24
6.2 I²C Mode ........................................................................................................................................ 24
6.2.1 I²C Write ............................................................................................................................... 24
6.2.2 I²C Read............................................................................................................................... 24
6.3 SPI Mode ....................................................................................................................................... 25
6.3.1 SPI Write .............................................................................................................................. 25
6.3.2 SPI Read.............................................................................................................................. 26
6.4 Memory Address Pointer (MAP) ................................................................................................... 26
6.4.1 INCR (Auto Map Increment Enable) .................................................................................... 26
6.4.2 MAP (Memory Address Pointer) .......................................................................................... 26
7. REGISTER QUICK REFERENCE ......................................................................................................... 27
8. REGISTER DESCRIPTION ................................................................................................................... 28
8.1 Chip ID - Register 01h ................................................................................................................... 28
8.2 Mode Control - Register 02h ......................................................................................................... 28
8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4 .......................................................................... 28
8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ........................................................................... 28
DS691A3
3
CS4350
8.2.3 Functional Mode (FM[1:0]) Bits 1-0...................................................................................... 29
8.3 Volume Mixing and Inversion Control - Register 03h .................................................................... 29
8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ................................................... 29
8.3.2 Invert Signal Polarity (INVERT_A) Bit 6 ............................................................................... 29
8.3.3 Invert Signal Polarity (INVERT_B) Bit 5 ............................................................................... 29
8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 .................................................... 30
8.4 Mute Control - Register 04h ......................................................................................................... 31
8.4.1 Auto-Mute (AMUTE) Bit 7 .................................................................................................... 31
8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 .......................................................................... 31
8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3................................. 31
8.5 Channel A & B Volume Control - Register 05h & 06h ................................................................... 31
8.6 Ramp and Filter Control - Register 07h ......................................................................................... 32
8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6 ....................................................... 32
8.6.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5 ............................................................. 33
8.6.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4 ........................................... 33
8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2.......................................................................... 33
8.7 Misc. Control - Register 08h .......................................................................................................... 33
8.7.1 Power Down (PDN) Bit 7...................................................................................................... 33
8.7.2 Freeze Controls (FREEZE) Bit 5.......................................................................................... 33
8.7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 34
8.7.4 RMCK control (RMCK_CTR[1:0]) Bits 3:2 ........................................................................... 34
8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1 .................................................................... 34
9. FILTER PLOTS
............................................................................................................................. 35
10. PARAMETER DEFINITIONS............................................................................................................... 37
11. PACKAGE DIMENSIONS ................................................................................................................... 38
THERMAL CHARACTERISTICS ............................................................................................................... 38
12. ORDERING INFORMATION ............................................................................................................... 39
13. REVISION HISTORY .......................................................................................................................... 39
4
DS691A3
CS4350
LIST OF FIGURES
Figure 1. Output Test Load ........................................................................................................................ 10
Figure 2. Maximum Loading....................................................................................................................... 10
Figure 3. Serial Port Timing, Non-TDM Mode............................................................................................ 12
Figure 4. Serial Port Timing, TDM Mode.................................................................................................... 12
Figure 5. Control Port Timing - I²C Format................................................................................................. 13
Figure 6. Control Port Timing - SPI Mode .................................................................................................. 14
Figure 7. Typical Connection Diagram....................................................................................................... 16
Figure 8. Left-Justified up to 24-Bit Data.................................................................................................... 18
Figure 9. I²S, up to 24-Bit Data .................................................................................................................. 18
Figure 10. Right-Justified Data................................................................................................................... 18
Figure 11. TDM Mode Connection Diagram .............................................................................................. 19
Figure 12. TDM Mode Timing .................................................................................................................... 19
Figure 13. De-Emphasis Curve.................................................................................................................. 20
Figure 14. Differential to Single-ended Output Filter.................................................................................. 22
Figure 15. Passive Single-Ended Output Filter .......................................................................................... 22
Figure 16. Control Port Timing, I²C Mode .................................................................................................. 25
Figure 17. Control Port Timing, SPI Mode ................................................................................................. 26
Figure 18. De-Emphasis Curve.................................................................................................................. 28
Figure 19. ATAPI Block Diagram ............................................................................................................... 30
Figure 20. Stopband Rejection (fast), all Modes ........................................................................................ 35
Figure 21. Stopband Rejection (slow), all Modes....................................................................................... 35
Figure 22. Single-Speed (fast) Passband Detail ........................................................................................ 35
Figure 23. Single-Speed (slow) Passband Detail....................................................................................... 35
Figure 24. Double-Speed (fast) Passband Detail....................................................................................... 35
Figure 25. Double-Speed (slow) Passband Detail ..................................................................................... 35
Figure 26. Quad-Speed (fast) Passband Detail ......................................................................................... 36
Figure 27. Quad-Speed (slow) Passband Detail........................................................................................ 36
LIST OF TABLES
Table 1. Pin Descriptions ............................................................................................................................. 7
Table 2. CS4350 Auto-Detect .................................................................................................................... 17
Table 3. Digital Interface Format - Stand-Alone Mode............................................................................... 23
Table 4. Digital Interface Formats .............................................................................................................. 28
Table 5. ATAPI Decode ............................................................................................................................. 30
Table 6. Example Digital Volume Settings ................................................................................................. 32
DS691A3
5
CS4350
1. PIN DESCRIPTION
DIF2(AD1/CDOUT)
1
24
RST
DEM(AD0/CS)
2
23
AOUTB-
DIF0(SDA/CDIN)
3
22
AOUTB+
DIF1(SCL/CCLK)
4
21
BMUTEC
VLC
5
20
VQ
VD_FILT
6
19
GND
GND
7
18
VA
RMCK
8
17
VBIAS
16
AMUTEC
SCLK
9
10
15
AOUTA+
SDIN
11
14
AOUTA-
LRCK
12
13
TSTO
VLS
6
DS691A3
CS4350
Pin Name
#
Pin Description
VLC
5
Control Interface Power (Input) - Positive power for the hardware/software control interface
VD_FILT
6
Regulator Voltage (Output) - Filter connection for internal voltage regulator
GND
7, 19 Ground (Input) - Ground reference
RMCK
8
Recovered Master Clock (Output) - Outputs a master clock derived from LRCK
VLS
9
Serial Audio Interface Power (Input) - Positive power for the serial audio interface
SCLK
10
Serial Clock (Input) - Serial bit-clock for the serial audio interface
SDIN
11
Serial Audio Data Input (Input) - Input for two’s complement serial audio data
LRCK
12
Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line
TSTO
13
Test Output - These pins need to be floating and not connected to any trace or plane.
AOUTA+,AOUTB+,-
14, 15, Differential Analog Outputs (Output) - The full scale differential output level is specified in “DAC Ana22, 23 log Characteristics” on page 9.
AMUTEC
BMUTEC
16, 21 Mute Control (Output) - Control signals for optional mute circuit.
VBIAS
17
Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC
VA
18
Analog Power (Input) - Positive power supply for the analog section
VQ
20
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage
RST
24
Reset (Input) - When pulled low, device will power down and reset all internal registers to their default
settings.
Control Port Definitions
AD1/CDOUT
1
Address Bit 1 / Serial Control Data Out (I/O) - Chip address bit 1 in I²C Mode or data output in SPI
Mode
AD0/CS
2
Address Bit 0 / Chip Select (Input) - Chip address bit 0 in I²C Mode or Chip Select in SPI Mode
SDA/CDIN
3
Serial Control Data In (I/O) - Input/Output for I²C data. Input for SPI data
SCL/CCLK
4
Serial Control Port Clock (Input) - Serial clock for the control port interface
Stand-Alone Definitions
DIF0
DIF1
DIF2
DEM
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial
1, 3, 4 Clock, and Serial Audio Data
2
De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for
44.1 kHz sample rates
Table 1. Pin Descriptions
DS691A3
7
CS4350
2. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical specifications are derived from performance measurements at TA = 25 °C, VA = 3.3 V or 5.0 V)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
VA
4.75
3.14
5.0
3.3
5.25
3.46
V
V
Serial Audio Interface power
VLS
1.35
3.3
5.25
V
Control Interface power
Commercial
Automotive
VLC
3.14
3.3
5.25
V
TA
TA
-10
-40
-
+70
+85
°C
°C
DC Power Supply
Analog power
Specified Temperature Range
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Symbol
Min
Max
Units
Serial Audio Interface power
VA
VLS
-0.3
-0.3
6.0
6.0
V
V
Control Interface power
VLC
-0.3
6.0
V
Iin
VIN-LS
VIN-LC
TA
Tstg
-0.3
-0.3
-55
-65
±10
VLS+ 0.4
VLC+ 0.4
125
150
mA
V
V
°C
°C
Analog power
Input Current, Any Pin Except Supplies
Digital Input Voltage
Serial Audio Interface
Control Interface
Ambient Operating Temperature (power applied)
Storage Temperature
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
8
DS691A3
CS4350
DAC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): input test signal is a 997 Hz sine wave at 0 dBFS; measurement
bandwidth 10 Hz to 20 kHz
Parameter
VA=+5 V
Symbol
Min
Fs = 48, 96, and 192 kHz
Dynamic Range (Note 1)
24-bit
16-bit
A-Weighted
unweighted
A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 1)
24-bit
16-bit
VA=+3.3 V
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
24-bit
Unit
99/102
96/99
-
105/108
102/105
98
95
-
dB
dB
dB
dB
-
-95
-82/-79
-42/-39
-92
-75
-35
-89
-76
-36
-
dB
dB
dB
dB
dB
dB
Single-ended/Differential
97/100
94/97
-
103/106
100/103
98
95
-
dB
dB
dB
dB
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
-
-95
-80/-77
-40/-36
-92
-75
-35
-89
-74
-34
-
dB
dB
dB
dB
dB
dB
(1 kHz)
-
100
-
dB
Interchannel Gain Mismatch
-
0.1
0.25
dB
Gain Drift
-
100
-
ppm/°C
Min
Typ
Max
Unit
Full Scale Output Voltage - Single Ended
2.66
2.8
2.94
Vpp
Full Scale Output Voltage - Differential
5.32
5.6
5.88
Vpp
VQ
-
0.5•VA
-
VDC
IOUTmax
-
10
-
µA
IQmax
-
100
-
µA
RL
-
3
-
kΩ
CL
-
100
-
pF
ZOUT
-
100
-
Ω
16-bit
A-Weighted
unweighted
A-Weighted
unweighted
Max
Single-ended/Differential
Fs = 48, 96, and 192 kHz
Dynamic Range (Note 1)
Typ
Total Harmonic Distortion + Noise (Note 1)
24-bit
16-bit
Interchannel Isolation
DC Accuracy
Note:
1.
One-half LSB of triangular PDF dither is added to data
DAC ANALOG CHARACTERISTICS (CONTINUED)
Analog Output
Parameter
Quiescent Voltage
Max DC Current draw from an AOUT pin
Max Current draw from VQ
Max AC-Load Resistance
Max Load Capacitance
Output Impedance
DS691A3
Symbol
9
CS4350
Note:
2.
RL and CL represent the minimum resistance and maximum capactiance required for the CS4350’s internal op-amp
to remain stable. See Figure 1 and Figure 2 for more details.
CS4350
AOUTx +
3.3 µF
+
Analog
Output
RL
AGND
CL
Capacitive Load -- C L (pF)
125
100
75
25
2.5
3
Figure 1. Output Test Load
10
Safe Operating
Region
50
5
10
15
20
Resistive Load -- RL (kΩ )
Figure 2. Maximum Loading
DS691A3
CS4350
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Amplitude vs. Frequency plots of this data are available in the
“Filter Plots” on page 35
Parameter
Min
Typ
Max
Unit
-0.01 dB corner (Single Speed)
0
-
.454
Fs
-0.1 dB corner (Double Speed)
0
-
.42
Fs
Fast Roll-Off
Passband (Note 3)
-0.2 dB corner (Quad Speed)
0
-
.27
Fs
-3 dB corner (All Speed Modes)
0
-
.499
Fs
-0.01
-
+0.01
dB
Frequency Response 10 Hz to 20 kHz
Single Speed
Double Speed, Quad Speed
-0.02
-
+0.02
dB
0.547
-
-
Fs
102
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
-
9.4/Fs
-
s
Intra-channel Phase Deviation
-
-
±0.56/Fs
s
Inter-channel Phase Deviation
-
-
0
s
StopBand
Stop-Band Attenuation (Note 4)
De-emphasis Error (Note 5)
Fs = 32 kHz
-
-
±0.23
dB
Fs = 44.1 kHz
-
-
±0.14
dB
Fs = 48 kHz
-
-
±0.09
dB
-0.01 dB corner (Single Speed)
0
-
0.417
Fs
-0.1 dB corner (Double Speed)
0
-
.37
Fs
(Relative to 1 kHz)
Slow Roll-Off (Note 6)
Passband (Note 3)
-0.2 dB corner (Quad Speed)
0
-
.27
Fs
-3 dB corner (All Speed Modes)
0
-
.499
Fs
Single Speed
-0.01
-
+0.01
dB
Double Speed, Quad Speed
-0.02
-
+0.02
dB
.583
-
-
Fs
64
-
-
dB
Total Group Delay (Fs = Output Sample Rate)
-
6.5/Fs
-
s
Intra-channel Phase Deviation
-
-
±0.14/Fs
s
Frequency Response 10 Hz to 20 kHz
StopBand
Stop-Band Attenuation (Note 4)
Inter-channel Phase Deviation
De-emphasis Error (Note 5)
(Relative to 1 kHz)
-
-
0
s
Fs = 32 kHz
-
-
±0.23
dB
Fs = 44.1 kHz
-
-
±0.14
dB
Fs = 48 kHz
-
-
±0.09
dB
Notes:
3.
Response is clock dependent.
4.
The Measurement Bandwidth is from stopband to 3 Fs.
5.
De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Stand-Alone
Mode.
6.
Slow Roll-off interpolation filter is only available in Control Port Mode.
DS691A3
11
CS4350
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF)
Parameters
Symbol
Min
Max
Units
7.680
51.2
MHz
45
55
%
Fs
30
54
kHz
Double-Speed Mode
Fs
60
108
kHz
Quad-Speed Mode
Fs
120
216
kHz
40
60
%
-
51.2
MHz
RMCK Output Frequency (Note 7)
RMCK Output Duty Cycle
Input Sample Rate
Single-Speed Mode
LRCK Duty Cycle (Non-TDM Mode)
SCLK Frequency
SCLK High Time
tsckh
8
-
ns
SCLK Low Time
tsckl
8
-
ns
SDIN Setup Time Before SCLK Rising Edge
tds
3
-
ns
SDIN Hold Time After SCLK Rising Edge
tdh
5
-
ns
LRCK Edge to SCLK Rising Edge
tlcks
6
-
ns
SCLK Rising Edge to LRCK Edge
tlckd
5
-
ns
tlrckh
163
SCLK Rising to LRCK Falling Edge
tfsh
5
-
ns
LRCK Rising Edge to SCLK Rising Edge
tfss
5
-
ns
Non-TDM Mode (refer to Figure 3)
TDM Mode (refer to Figure 4)
LRCK High Time
ns
Notes:
7.
RMCK output frequency depends on the input LRCK frequency. See Section 4.1 and Section 4.2 for more details.
tlrckh
LRCK
(input)
LRCK
tlckd
tlcks
tsckh
tsckl
(Input)
tfss
tfsh
tsclkh
tsclkl
SCLK
SCLK
(input)
(Input)
tds
SDIN
(input)
tdh
tds
MSB
MSB-1
Figure 3. Serial Port Timing, Non-TDM Mode
12
SDIN
(Input)
tdh
MSB
MSB-1
Figure 4. Serial Port Timing, TDM Mode
DS691A3
CS4350
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling (Note 8)
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
SDA Setup time to SCL Rising
trc, trc
-
1
µs
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Notes:
8.
Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t
irs
Stop
R e p e ate d
S ta rt
Start
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 5. Control Port Timing - I²C Format
DS691A3
13
CS4350
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling (Note 9)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time (Note 10)
tdh
15
-
ns
Rise Time of CCLK and CDIN (Note 11)
tr2
-
100
ns
Fall Time of CCLK and CDIN (Note 11)
tf2
-
100
ns
Transition Time from CCLK to CDOUT Valid (Note 12)
tr2
-
100
ns
Time from CS rising to CDOUT High-Z
tf2
-
100
ns
Notes:
9.
tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For FSCK < 1 MHz.
12. CDOUT should not be sampled during this time.
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t
dh
Hi-Impedance
CDOUT
t scdov
t scdov
t cscdo
Figure 6. Control Port Timing - SPI Mode
14
DS691A3
CS4350
DIGITAL CHARACTERISTICS
Parameters
High-Level Input Voltage
Symbol
Min
Typ
Max
Units
VLC or VLS = 3.3 V
VIH
VIH
0.7•VL
2.0
-
-
V
V
VLS = 2.5 V
VIH
1.7
-
-
V
VLS = 1.8 V
VLC or VLS = 5.0 V
VIH
0.65•VL
-
-
V
VLC or VLS = 3.3 V
VIL
VIL
-
-
0.35•VL
0.8
V
V
VLS = 2.5 V
VIL
-
-
0.7
V
VLS = 1.8 V
VIL
-
-
0.35•VL
V
Iin
8
-
±10
-
µA
pF
V
VLC or VLS = 5.0 V
High-Level Input Voltage
Input Leakage Current
Input Capacitance
High Level Output Voltage (RMCK) IO = 2 mA (VLS ≥ 3.0V)
VOH
VLS-1.0
Low Level Output Voltage (RMCK) IO = -2 mA (VLS ≥ 3.0V)
VOL
-
-
0.4
V
VOH
VOL
-
2
VA
0
10
-
pF
mA
V
V
RMCK Output Load Drive
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
VA= 5.0 V
VA= 3.3 V
VLS = VLC =5.0 V (Note 14)
IA
IA
ILS
-
14
11
0.1
18
14
1
mA
mA
mA
VLS = VLC =3.3 V (Note 14)
ILS
-
0.1
1
mA
VLS = VLC = 5.0 V (Note 15)
ILC
-
6
9
mA
VLS = VLC = 3.3 V (Note 15)
ILC
-
4
7
mA
Ipd
-
100
-
µA
-
100
50
140
75
mW
mW
-
1
1
60
60
-
mW
mW
dB
dB
Power Supply Current - Normal Operation (Note 13)
Power Supply Current - Power-Down State (Note 16)
VA, VLS, VLC
Power Dissipation - Normal Operation (Note 13)
VA = VLC= VLS = 5.0 V
VA = VLC= VLS = 3.3 V
Power Dissipation - Power-Down State (Note 16)
VA = VLC= VLS = 5.0 V
VA = VLC= VLS = 3.3 V
Power Supply Rejection Ratio (Note 17)
(1 kHz)
(60 Hz)
PSRR
PSRR
Notes:
13. Current consumption increases with increasing Fs within the range of a speed mode. Typ and Max values are
based on highest FS within a speed mode. Variance between speed modes is small.
14. ILS measured with no external loading on pin 7 (RMCK).
15. ILC measured with no external loading on pin 2 (SDA).
16. Power-down mode is defined as RES pin = Low with all clock and data lines held static.
17. Valid with the recommended capacitor values on VFILT, VQ, and VBIAS as shown in the typical connection diagram in Figure 7.
DS691A3
15
CS4350
3. TYPICAL CONNECTION DIAGRAM
+3.3 V or +5 V
+
0.1 µF
10 µF
18
VLS
+
10 µF
VA
*Optional for PopGuard
Disable
VBIAS+ 17
*47 kΩ
8
Digital
Audio
Source
RMCK
12 LRCK
VD_FILT
6
10 SCLK
0.1 µF +
10 µF
11 SDIN
+1.5 V to +5 V
9
VLS
AMUTEC 16
0.1 µF
AOUTA+ 15
CS4350
+3.3 V to +5 V
5
AOUTA- 14
Differential or Singleended Output Filter
AOUTA
Differential or Singleended Output Filter
AOUTB
VLC
0.1 µF
BMUTEC 21
24 RST
µ C/
Mode
Configuration
4 DIF1(SCL/CCLK)
AOUTB+ 22
3 DIF0(SDA/CDIN)
AOUTB- 23
2 DEM(AD0/CS)
1 DIF2(AD1/CDOUT)
TS
T
GN
D
G
ND
O
VQ 20
13
7
19
+ 3.3 µF
N.C.
Figure 7. Typical Connection Diagram
16
DS691A3
CS4350
4. APPLICATIONS
4.1
Sample Rate Range and Oversampling Mode Detect
The device operates in one of three oversampling modes based on the input sample rate. In Control Port
Mode, the allowed sample rate range in each mode will depend on how the FM[1:0] bits are configured. In
Stand-Alone Mode, the sample rate range will be according to Table 2.
4.1.1
Sample Rate Auto-Detect
The Auto-Detect feature is enabled by default. In this state, the CS4350 will auto-detect the correct mode
when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges shown in
Table 2. Sample rates outside the specified range for each mode are not supported when Auto-Detect is
enabled.
Input Sample Rate (Fs)
Mode
30 kHz - 54 kHz
60 kHz - 108 kHz
120 kHz - 216 kHz
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Table 2. CS4350 Auto-Detect
In Control Port Mode, the Auto-Detect feature can be disabled by the format bits in the control port
register 02h. In this state, the CS4350 will not auto-detect the correct mode based on the input sample
rate (Fs). The operational mode must then be set manually according to one of the ranges referred to in
Section 8.2.3. Sample rates outside the specified range for each mode are not supported. In Stand-Alone
Mode it is not possible to disable auto-detect of sample rates.
4.2
System Clocking
The device requires external generation of the left/right (LRCK) and serial (SCLK) clocks. The left/right clock
frequency is equal to the input sample rate (Fs).
Refer to Section 4.3 for the required SCLK-to-LRCK timing associated with the selected digital interface format, and “Switching Specifications - Serial Audio Interface” on page 12 for the maximum allowed clock frequencies.
4.2.1
Recovered Master Clock (RMCK)
The CS4350 generates a high-frequency master clock (RMCK) which it derives from the LRCK input,
available on the RMCK pin. In Stand-Alone Mode, the frequency of RMCK is equal to 256 x LRCK in Single-Speed and Double-Speed Mode; and 128 x LRCK in Quad-Speed Mode. In Control-Port Mode, the
frequency of the RMCK signal can be selected through register 08h (see Section 8.7 on page 33 for more
details).
DS691A3
17
CS4350
4.3
Digital Interface Format
The device will accept audio samples in 1 of 8 digital interface formats, as shown in Table 3 on page 23 for
Stand-Alone Mode and Table 4 on page 28 for Control Port Mode.
The desired serial audio interface format is selected via the DIF[2:0] bits in Control Port Mode (see
Section 8.2.1), or the DIF[2:0] pins in Stand-Alone Mode (see Section 5.1). For illustrations of the required
relationship between LRCK, SCLK and SDIN, see Figures 8-10. For all formats, SDIN is valid on the rising
edge of SCLK.
For more information about serial audio formats, refer to the Cirrus Logic Application Note AN282,
The 2-Channel Serial Audio Interface: A Tutorial, available at www.cirrus.com.
LRCK
Left Channel
Right Channel
SCLK
SDIN
MSB
-1
-2
-3
-4
+5
-5
+4
+3
+2
+1
MSB
LSB
-1
-2
-3
+5
-4
+4
+3
+2
+1
LSB
Figure 8. Left-Justified up to 24-Bit Data
Right Channel
Left Channel
LRCK
SCLK
SDIN
MSB
-1
-2
-3
-4
+5
-5
+4
+3
+2
+1
LSB
MSB
-1
-2
-3
+5
-4
+4
+3
+2
+1
LSB
Figure 9. I²S, up to 24-Bit Data
LRCK
Right Channel
Left Channel
SCLK
SDIN
LSB
MSB
-1
-2
-3
-4
-5
+7
+6
+5
+4
+3
+2
+1 LSB
MSB
-1
-2
-3
-4
-5
+7
+6
+5
+4
+3
+2
+1 LSB
Figure 10. Right-Justified Data
18
DS691A3
CS4350
4.3.1
Time-Division Multiplex (TDM) Mode
Four TDM interface modes are available that allow the CS4350 to input stereo PCM data in one of 4 time
“slots”. Figure 11 shows the serial port connections necessary to input 8-channel TDM data into four
CS4350 devices, and the corresponding DIF[2:0] pin or register-bit settings required for each CS4350.
Figure 12 shows the TDM data format for each of the four CS4350 devices shown in Figure 11.
.
LRCK
CS43501
CS43502
CS43503
CS43504
DIF[2:0] = 100
DIF[2:0] = 101
DIF[2:0] = 110
DIF[2:0] = 111
LRCK
ILRCK
LRCK
LRCK
SCLK
ISCLK
SCLK
SCLK
SDIN
SDIN
SDIN
SDIN
SCLK TDM_OUT
TDM Source
Figure 11. TDM Mode Connection Diagram
256 clks
LRCK
SCLK
SDIN1
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
Slot 1, ch A
Slot 1, ch B
Slot 2, ch A
Slot 2, ch B
Slot 3, ch A
Slot 3, ch B
Slot 4, ch A
Slot 4, ch B
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Data
MSB
LSB
zero
Figure 12. TDM Mode Timing
DS691A3
19
CS4350
4.4
De-Emphasis
The device includes on-chip digital de-emphasis. Figure 13 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 13. De-Emphasis Curve
Note:
4.5
De-emphasis is only available in Single-Speed Mode.
Mute Control
The mute control pins (AMUTEC and BMUTEC) go active during power-up initialization, reset, muting (see
Section 8.4.3), and loss of LRCK. These pins are intended to be used as control for external mute circuits
to prevent the clicks and pops that can occur in any single-ended single-supply system.
Use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle-channel noise and signal-to-noise ratios which are only limited by the external mute circuit.
4.6
4.6.1
Recommended Power-Up Sequence
Stand-Alone Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are fixed to the appropriate frequencies, as discussed in Section 4.2. In this state, the control
port registers are reset to their default settings, VQ will remain low, and VBIAS will be connected to
VA.
2. Bring RST high. The device will remain in a low power state with VQ low for approximately 512 LRCK
cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in
Quad-Speed Mode).
3. The device will then initiate the power up sequence which lasts approximately 50 µs when the
Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of
power-up timing.
4.6.2
Control Port Mode
1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate
frequency, as discussed in Section 4.2. In this state, the control port is reset to its default settings, VQ
will remain low, and VBIAS will be connected to VA.
20
DS691A3
CS4350
2. Bring RST high. The device will remain in a low-power state with VQ low.
3. Perform a control port write to a valid register prior to the completion of approximately 512 LRCK
cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in
Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs when
the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of
power-up timing.
4.7
Popguard® Transient Control
The CS4350 uses a novel technique to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated
inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the
appropriate DC-blocking capacitors.
4.7.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.
Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins.
This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing audible power-up transients.
4.7.2
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready
for the next power-on.
4.7.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
DS691A3
21
CS4350
4.8
Analog Output and Filtering
The Cirrus Application Note titled Design Notes for a 2-Pole Filter with Differential Input, available as AN48
at www.cirrus.com, discusses the second-order Butterworth filter and differential-to-single-ended converter
that was implemented on the CS4350 evaluation board, CDB4350. Figure 14 illustrates this
implementation. If only single-ended outputs from the CS4350 are required, the passive output filter shown
in Figure 15 can be used.
5600 pF
CS4350
4.02 kΩ
1000 pF
C0G
4.64 kΩ
AOUTx AOUTx +
1.62 kΩ
392 Ω
221 Ω
C0G
-
C0G
562 Ω
+
Analog
Output
47 kΩ
2700 pF
.015 µF
AGND
22 µF
C0G
1.37 kΩ
22 µF
Figure 14. Differential to Single-ended Output Filter
CS4350
AOUTx +
3.3 µF
+
560 Ω
10 kΩ
Analog
Output
2200 pF
AGND
Figure 15. Passive Single-Ended Output Filter
4.9
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4350 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 7 shows the recommended power arrangements, with VA, VLC, and VLS connected to clean supplies. The use of split analog and digital ground
planes is not reccomended. However, if planes are split between digital ground and analog ground the GND
pins of the CS4350 should be connected to the analog ground plane.
All signals, especially clocks, should be kept away from the VBIAS, VFILT, and VQ pins in order to avoid
unwanted coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.
Note:
All decoupling capacitors should be referenced to analog ground.
The CDB4350 evaluation board demonstrates the optimum layout and power supply arrangements.
22
DS691A3
CS4350
5. STAND-ALONE OPERATION
5.1
Serial Port Format Selection
The desired serial audio format is selected with the DIF2, DIF1 and DIF0 pins. For an explanation of the
required relationship between the LRCK, SCLK and SDIN, see Figures 8-10. For all formats, SDIN is valid
on the rising edge of SCLK. TDM Mode requires the selection of which stereo pair time “slot” is used to output data as shown in Table 3 and Figure 12.
DIF2
DIF1
DIF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DESCRIPTION
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
TDM slot 0
TDM slot 1
TDM slot 2
TDM slot 3
FORMAT
FIGURE
0
1
2
3
4
5
6
7
9
8
10
10
12
12
12
12
Table 3. Digital Interface Format - Stand-Alone Mode
5.2
De-emphasis Control
When pulled to VLC, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM
pin turns off the de-emphasis filter.
5.3
Popguard® Transient Control
In Stand-Alone Mode, Popguard is enabled by default. Popguard can be defeated in Stand-Alone Mode by
placing a 47 kΩ resistor between RMCK and VLS.
DS691A3
23
CS4350
6. CONTROL PORT OPERATION
The control port is used to load all the internal register settings (see ”Register Description” on page 28). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential
interference problems, the control port pins should remain static if no operation is required.
The control port can operate in I²C or SPI mode.
6.1
MAP Auto Increment
The device has a MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for consecutive writes or reads. If INCR is
set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of consecutive registers.
6.2
I²C Mode
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see Figure 16 for the clock to data relationship). There is no CS pin. AD1 and AD0
enable the user to alter the chip address (10010[AD1][AD0][R/W]) and should be tied to VLC or GND as
required before powering up the device. SPI Mode will be selected if the device ever detects a high to low
transition on the AD0/CS pin after power-up.
6.2.1
I²C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in ”Switching Characteristics - Control Port - I²C Format” on page 13.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be
10010. The sixth and seventh bit must match the settings of the AD1 and AD0 pins respectively, and
the eighth must be 0 (the eighth bit of the address byte is the R/W bit).
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by
the MAP.
4. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are
written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other
registers are desired, initiate a STOP condition to the bus.
6.2.2
I²C Read
To read from the device, follow the procedure below while adhering to the control port switching specifications in ”Switching Characteristics - Control Port - I²C Format” on page 13.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be
10010. The sixth and seventh bits must match the setting of the AD1 and AD0 pins, respectively, and
the eighth must be 1. The eighth bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the
24
DS691A3
CS4350
MAP or the default address (see Section 6.4.2) if an I²C read is the first operation performed on the
device.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read;
then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C
Write instructions, followed by step 1 of the I²C Read section. If no further reads from other registers
are desired, initiate a STOP condition to the bus.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS
1 0 0 1 0 AD1 AD0 R/W
SDA
MAP BYTE
INC 6
ACK
5
4
3
DATA +1
DATA
2
1
0
7
6
1
ACK
0
7
6
1
DATA +n
0
7
6
1
ACK
0
ACK
STOP
START
Figure 16. Control Port Timing, I²C Mode
6.3
SPI Mode
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 17 for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select
signal and is used to control SPI writes to the control port. When the device detects a high-to-low transition
on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in
on the rising edge of CCLK.
6.3.1
SPI Write
To write to the device, follow the procedure below while adhering to the control port switching specifications in ”Switching Characteristics - Control Port - SPI Format” on page 14.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011110 (R/W = 0).
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are
written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are
desired, bring CS high
DS691A3
25
CS4350
6.3.2
SPI Read
To read from the device, follow the procedure below while adhering to the values specified in ”Switching
Characteristics - Control Port - SPI Format” on page 14.
1.
Bring CS low.
2. The address byte on the CDIN pin must then be 10011111 (R/W = 1).
3. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the
SPI write operation.
4. If the INCR bit (see Section 6.1) is set to 1, keep CS low and continue providing clocks on CCLK to
read from multiple consecutive registers. Bring CS high when reading is complete.
5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further reads from other registers are
desired, bring CS high.
CS
CCLK
C H IP
ADDRESS
CDIN
MAP
1001111
C H IP
ADDRESS
DATA
LSB
MSB
R/W
b y te 1
1001111
R/W
b y te n
High Impedance
CDOUT
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 17. Control Port Timing, SPI Mode
6.4
Memory Address Pointer (MAP)
7
INCR
0
6.4.1
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled
1 - Enabled
6.4.2
MAP (Memory Address Pointer)
Default = ‘0000’
26
DS691A3
CS4350
7. REGISTER QUICK REFERENCE
Addr
Function
1h
Chip ID
2h
Mode Control
3h
Volume, Mixing,
and Inversion
Control
default
default
default
4h
Mute Control
default
5h
Channel A Volume
Control
6h
Channel B Volume
Control
7h
Ramp and Filter
Control
default
default
default
8h
Misc. Control
default
DS691A3
7
6
5
4
3
2
1
0
PART4
PART3
PART2
PART1
PART0
REV2
REV1
REV0
1
1
1
1
0
-
-
-
Reserved
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
0
0
0
0
0
0
0
0
VOLB=A
INVERTA
INVERTB
Reserved
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
0
0
0
1
0
0
1
AMUTE
Reserved
MUTEC
A=B
MUTE_A
MUTE_B
Reserved
Reserved
Reserved
1
0
0
0
0
0
0
1
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
SZC1
SZC0
RMP_UP
RMP_DN
Reserved
FILT_SEL
Reserved
Reserved
1
0
1
1
0
0
0
1
PDN
Reserved
FREEZE
POPG_EN
RMCK_
CTRL1
RMCK_
CTRL0
0
0
0
1
0
0
R_
R_
SELECT1 SELECT0
0
0
27
CS4350
8. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
8.1
Chip ID - Register 01h
7
PART4
1
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
0
2
REV2
-
1
REV1
-
0
REV0
-
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11110b and the remaining Bits
(2 through 0) are for the chip revision (Rev. A0 = 000)
8.2
Mode Control - Register 02h
7
Reserved
0
8.2.1
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
FM1
0
0
FM0
0
Digital Interface Format (DIF[2:0]) Bits 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 8-10.
DIF2
DIF1
DIF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
TDM slot 0
TDM slot 1
TDM slot 2
TDM slot 3
Format
Figure
0 (Default)
1
2
3
4
5
6
7
8
9
10
10
12
12
12
12
Table 4. Digital Interface Formats
8.2.2
De-Emphasis Control (DEM[1:0]) Bits 3-2
Default = 0
00 - No De-emphasis
01 - 44.1 kHz De-emphasis
10 - 48 kHz De-emphasis
11 - 32 kHz De-emphasis
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
Function:
Selects the appropriate digital filter to maintain the standard
15 µs/50 µs digital de-emphasis filter response at 32, 44.1
or 48 kHz sample rates. (See Figure 18)
Note:
Mode
28
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 18. De-Emphasis Curve
De-emphasis is only available in Single-Speed
DS691A3
CS4350
8.2.3
Functional Mode (FM[1:0]) Bits 1-0
Default = 00
00 - Auto speed mode detect
01 - Single-Speed Mode (30 to 54 kHz sample rates)
10 - Double-Speed Mode (50 to 108 kHz sample rates)
11 - Quad-Speed Mode (100 to 216 kHz sample rates)
Function:
Selects the required range of input sample rates or auto speed mode.
8.3
Volume Mixing and Inversion Control - Register 03h
7
VOLB=A
0
8.3.1
6
INVERT_A
0
5
INVERT_B
0
4
Reserved
0
3
ATAPI3
1
2
ATAPI2
0
1
ATAPI1
0
0
ATAPI0
1
Channel A Volume = Channel B Volume (VOLB=A) Bit 7
Function:
When set to 0 (default), the AOUTA and AOUTB volume levels are independently controlled by the A and
the B Channel Volume Control Bytes.
When set to 1, the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and
Volume Control Bytes, and the B Channel Bytes are ignored.
8.3.2
Invert Signal Polarity (INVERT_A) Bit 6
Function:
When set to 1, this bit inverts the signal polarity of channel A.
When set to 0 (default), this function is disabled.
8.3.3
Invert Signal Polarity (INVERT_B) Bit 5
Function:
When set to 1, this bit inverts the signal polarity of channel B.
When set to 0 (default), this function is disabled.
DS691A3
29
CS4350
8.3.4
ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0
Default = 1001 - AOUTA=aL, AOUTB=bR (Stereo)
Function:
The CS4350 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 5 and Figure 19 for additional information.
A Channel
Volume
Control
Left Channel
Audio Data
Σ
MUTE
AoutA
MUTE
AoutB
Σ
B Channel
Volume
Control
Right Channel
Audio Data
Figure 19. ATAPI Block Diagram
ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0
AOUTA
AOUTB
0
0
0
0
MUTE
MUTE
0
0
0
1
MUTE
bR
0
0
1
0
MUTE
bL
0
0
1
1
MUTE
b[(L+R)/2]
0
1
0
0
aR
MUTE
0
1
0
1
aR
bR
0
1
1
0
aR
bL
0
1
1
1
aR
b[(L+R)/2]
1
0
0
0
aL
MUTE
1
0
0
1
aL
bR
1
0
1
0
aL
bL
1
0
1
1
aL
b[(L+R)/2]
1
1
0
0
a[(L+R)/2]
MUTE
1
1
0
1
a[(L+R)/2]
bR
1
1
1
0
a[(L+R)/2]
bL
1
1
1
1
a[(L+R)/2]
b[(L+R)/2]
Table 5. ATAPI Decode
30
DS691A3
CS4350
8.4
Mute Control - Register 04h
7
AMUTE
1
8.4.1
6
Reserved
0
5
MUTEC A=B
0
4
MUTE_A
0
3
MUTE_B
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
Auto-Mute (AMUTE) Bit 7
Function:
When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be
retained and the Mute Control pin will go active during the mute period.
When set to 0, this function is disabled
8.4.2
AMUTEC = BMUTEC (MUTEC A=B) Bit 5
Function:
When set to 0 (default) the AMUTEC and BMUTEC pins operate independently.
When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an
AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only
when the requirements for both AMUTEC and BMUTEC are valid.
8.4.3
Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3
Function:
When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will
be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross
bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any
ramping due to the soft and zero cross function.
When set to 0 (default), this function is disabled.
8.5
Channel A & B Volume Control - Register 05h & 06h
7
VOL7
0
6
VOL6
0
5
VOL5
0
4
VOL4
0
3
VOL3
0
2
VOL2
0
1
VOL1
0
0
VOL0
0
Digital Volume Control (VOL[7:0]) Bits 7-0
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments
from 0 to -127.5 dB. Volume settings are decoded as shown in Table 6. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. The actual
attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12.
DS691A3
31
CS4350
Binary Code
Decimal Value
Volume Setting
00000000
00000001
00000110
11111111
0
1
6
255
0 dB
-0.5 dB
-3.0 dB
-127.5 dB
Table 6. Example Digital Volume Settings
8.6
Ramp and Filter Control - Register 07h
7
SZC1
1
8.6.1
6
SZC0
0
5
RMP_UP
1
4
RMP_DN
1
3
Reserved
0
2
FILT_SEL
0
1
Reserved
0
0
Reserved
1
Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6
Default = 10
SZC1 SZC0
Description
0
0
Immediate Change
0
1
Zero Cross
1
0
Soft Ramp
1
1
Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp PCM
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp and Zero Cross
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
32
DS691A3
CS4350
8.6.2
Soft Volume Ramp-Up after Error (RMP_UP) Bit 5
Function:
When set to 1 (default), an un-mute will be performed after executing a filter mode change, after LRCK is
lost, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by
the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Note:
8.6.3
For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4
Function:
When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is
affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control
register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Note:
8.6.4
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
Interpolation Filter Select (FILT_SEL) Bit 2
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the ”Combined Interpolation & On-Chip Analog Filter Response” on page 11, and response plots can be found in Figures 22 through 27.
8.7
Misc. Control - Register 08h
7
PDN
0
8.7.1
6
Reserved
0
5
FREEZE
0
4
POPG_EN
1
3
2
1
RMCK_CTRL1 RMCK_CTRL0 R_SELECT1
0
0
0
0
R_SELECT0
0
Power Down (PDN) Bit 7
Function:
When set to 1 the entire device will enter a low-power state and the contents of the control registers will
be retained. The power-down bit defaults to ‘0’ on power-up.
8.7.2
Freeze Controls (FREEZE) Bit 5
Function:
When set to 1, this function allows modifications to be made to the registers without the changes taking
effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect
simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
When set to 0 (default), register changes take effect immediately.
DS691A3
33
CS4350
8.7.3
Popguard Enable (POPG_EN) Bit 4
Function:
When set to 1, (default) the Device will initiate a ramping function as outlined in Section 4.7 on page 21.
When set to 0, the outputs will step to VQ upon release of PDN.
8.7.4
RMCK control (RMCK_CTR[1:0]) Bits 3:2
Default = 00
RMCK_CTR1
RMCK_CTR0
Mode
0
0
256x LRCK for 48 kHz and 96 kHz, 128x @ 192kHz
0
1
512x @ 48kHz, 256x @ 96 kHz, 128x @ 192kHz
1
0
Manual control (see RMCK_RATIO)
1
1
RMCK off
Function: These bits set the function of the RMCK pin with respect to the LRCK.
8.7.5
RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1
Default = 00
Function: To select the RMCK-to-LRCK ratio.
R_SELECT1
R_SELECT0
RMCK/LRCK Ratio
0
0
512
0
1
256
1
0
128
1
1
64
Note:
RMCK_CTR must be set to 10 to enable this function. Please note the maximum RMCK output
frequency as specified in the ”Switching Specifications - Serial Audio Interface” on page 12.
34
DS691A3
CS4350
9. FILTER PLOTS
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
0.02
0.02
0.015
0.015
0.01
0.01
0.005
0.005
Amplitude (dB)
Figure 21. Stopband Rejection (slow), all Modes
Amplitude (dB)
Figure 20. Stopband Rejection (fast), all Modes
0
0
0.005
0.005
0.01
0.01
0.015
0.015
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0.02
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
−0.1
−0.2
−0.2
−0.3
−0.3
−0.4
−0.4
−0.5
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 24. Double-Speed (fast) Passband Detail
DS691A3
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
−0.1
−0.5
0.05
Figure 23. Single-Speed (slow) Passband Detail
Amplitude (dB)
Amplitude (dB)
Figure 22. Single-Speed (fast) Passband Detail
0
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 25. Double-Speed (slow) Passband Detail
35
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
Amplitude (dB)
Amplitude (dB)
CS4350
0
−0.1
−0.1
−0.2
−0.2
−0.3
−0.3
−0.4
−0.4
−0.5
0
0.05
0.1
0.15
0.2
Frequency (normalized to Fs)
0.25
Figure 26. Quad-Speed (fast) Passband Detail
36
0
0.3
−0.5
0
0.05
0.1
0.15
0.2
Frequency (normalized to Fs)
0.25
0.3
Figure 27. Quad-Speed (slow) Passband Detail
DS691A3
CS4350
10.PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Intra-Channel Phase Deviation
The deviation from linear phase within a given channel.
Inter-Channel Phase Deviation
The difference in phase between channels.
DS691A3
37
CS4350
11.PACKAGE DIMENSIONS
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
b2
e
A1
SIDE VIEW
END VIEW
L
SEATING
PLANE
1 2 3
TOP VIEW
DIM
MIN
INCHES
NOM
A
A1
A2
b
D
E
E1
e
L
µ
-0.002
0.03346
0.00748
0.303
0.248
0.169
-0.020
0°
-0.004
0.0354
0.0096
0.307
0.2519
0.1732
0.026 BSC
0.024
4°
MAX
0.043
0.006
0.037
0.012
0.311
0.256
0.177
-0.028
8°
MIN
MILLIMETERS
NOM
NOTE
MAX
-0.05
0.85
0.19
7.70
6.30
4.30
-0.50
0°
--0.90
0.245
7.80
6.40
4.40
0.65 BSC
0.60
4°
1.10
0.15
0.95
0.30
7.90
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
1. D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2.
3.
Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in
excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more
than 0.07 mm at least material condition.
These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
Parameters
Package Thermal Resistance
38
Single-Layer PCB
Multi-Layer PCB
Symbol
Min
Typ
Max
Units
θJA
-
70
105
-
°C/Watt
DS691A3
CS4350
12.ORDERING INFORMATION
Product
Description
Package Pb-Free
Grade
Temp Range
Commercial -10° to +70°C
CS4350
192 kHz Stereo DAC
with Integrated PLL
24-TSSOP
YES
Automotive -40° to +85°C
CDB4350
Evaluation Board for CS4350
-
-
Container
Order#
Rail
CS4350-CZZ
Tape and Reel
CS4350-CZZR
Rail
CS4350-DZZ
Tape and Reel
CS4350-DZZR
-
CDB4350
-
13.REVISION HISTORY
Release
Changes
A1
Advance Datasheet
A2
-Changed description of TSTO pin in “Pin Description” on page 7 and “Typical Connection Diagram” on page 16.
-Corrected Full-Scale Voltage in “DAC Analog Characteristics (Continued)” on page 9
-Changed base address in “I²C Mode” on page 24 and “SPI Mode” on page 25.
A3
Corrected typographical error in chip address shown in Section 6.2 on page 24.
Corrected typographical error in value stated for the upper five bits in Section 6.2.1 on page 24.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus")
believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS"
without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,
including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use
of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of
Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such
as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor
SPI is a trademark of Motorola, Inc.
DS691A3
39