DD-03282 ARINC 429 TRANSCEIVER FEATURES DESCRIPTION The DD-03282 device is a two-channel receiver, one-channel transmitter in accordance with the “ARINC Specification 429 Digital Information Transfer System, Mark 33” (ARINC 429). This device can be used in conjunction with the DD-03182 Line Driver chip. consists of a transmitter circuit, two identical but independent receiver circuits, and a programmable control register to select operating options. The two receiver circuits operate identically. Each contains a line receiver which provides a direct electrical interface to an ARINC 429 data bus. The DD-03282 provides an interface between a standard avionics type serial digital data bus and 16-bit-wide digital data buses. The interface circuit The Transceiver transmits TTL information on DO(A)/DO(B) output pins. The signal format is compatible with DDCs ARINC-429 line driver chip DD-03182. • Two Receivers & One Transmitter • Parity Status & Generation of Receive and Transmit Words • Wraparound Self Test • Low Power CMOS Control Register Receive Decoder ARINC 429 → Receive 1 → Receive Decoder Self-test data ARINC 429 → Receive 0 → ARINC 429 • Transmit ← (to external driver) 16 Bits DATA BUS CONTROL • STATUS CLOCK Transmit Encoder 32 Bits TX FIFO 8 words FIGURE 1. DD-03282 BLOCK DIAGRAM © 1994, 1999 Data Device Corporation TABLE 1. DD-03282 SPECIFICATION ELECTRICAL DESCRIPTION (MAXIMUM RATINGS) Supply Voltage (VCC) - 0.5V to + 7.0V DC Input Voltage (VIN) (except pinsDI1+2(A + B)) -1.5V to VCC + 1.5V Voltage at Pins DI1(A,B) and DI2(A,B) -29V to + 29V Clamp Diode Current ± 20 mA DC Output Current, per pin ± 25 mA DCV or GND current, per pin ± 50 mA Storage Temperature -65°C to +150°C -55°C to +125°C Operating Temperature 1MCK Clock Frequency 1.16 MHz TABLE 2. DD-03282 SPECIFICATION DC ELECTRICAL CHARACTERISTICS SYM PARAMETER MIN TYP MAX UNITS TEST CONDITIONS ARINC LINE INPUTS VIH Logic 1 Input Voltage 6.5 10 13 V VDIFF PIN 2-3, 4-5 VIL Logic 0 Input Voltage -6.5 -10 -13 V VDIFF PIN 2-3, 4-5 -2.5 0 +2.5 V VDIFF PIN 2-3, 4-5 ±5 V VNUL Null Input Voltage VCM Common Mode Voltage RI Differential Input Impedance 12 Kohm RH RG Input Impedance to VCC Input Impedance to GND 12 12 Kohm Kohm CI Differential Input Capacitance 20 pF CH Input Capacitance to VCC 20 pF CG Input Capacitance to GND 20 pF 0.8 V ALL OTHER INPUTS (including bidirectional) VIL Max. Low Level Input Voltage VIH Min. High Level Input Voltage IIN Max. Input Current ±10 µA CIN Input Capacitance 15 pF 2.0 V VIN = GND to VCC ALL OUTPUTS (including bidirectional) VOH Min. High Level Output Voltage VCC -0.1 2.7 VOL Max. Low Level Voltage ICC Supply Current VCC Supply Voltage 4.5 2 V V |IOUT| = 20µA |IOUT| = 6mA 0.1 0.4 V V |IOUT| = 20µA |IOUT| = 6mA 5.0 10 mA 5.0 5.5 VDC 1MCK = 1MHz TABLE 3. DD-03282 SPECIFICATION AC ELECTRICAL CHARACTERISTICS DATA RATE 100 kb/s SYMBOL PARAMETER DATA RATE 12.5 kb/s MIN MAX MIN MAX 40 60 10 40 60 10 UNITS CKDC TCRF 1MCK Duty Cycle 1MCK Rise/Fall Time TMR Master Reset Pulse Width TDR Transmitter Data Rate (1MCK = 1 MHz) 99 101 12.4 12.6 kbps RDR Receiver Data Rate (1MCK = 1 MHz) 95 105 9.0 14.5 kbps 200 % ns 200 ns GENERAL DESCRIPTION Two receiver circuits each operate identically. Each contains a line receiver which provides a direct electrical interface to an ARINC-429 data bus. Incoming data is shifted into a 32-bit shift register and latched into a data buffer if a valid word is received. The control register allows the user to select the various options. These include: ARINC 429, as defined and described in ARINC Specification 429 Digital Information Transfer System, Mark 33, has been in use since 1977. It is the foundation for digital communications in modern civil aircraft. Certification issues have driven 429 to be defined as a simplex bus (one transmitter, multiple receivers) for point-to-point communications using 32-bit words with odd parity and 12-14.5 kHz (Lo Speed) or 100 kHz (Hi Speed) operation. Word length (32 or 25 bits). Transmitter Bit 32 (parity or data). The DD-03282 provides an interface between a standard avionics type serial digital data bus and most typical 16-bit-wide microcomputer data buses. The avionics buses supported by this device include: Transmitter parity (even or odd). Wraparound self test. Source/Destination code filtering of received data. ARINC 429 Transmitter data rate (Hi Speed or Lo Speed). ARINC 571 Receiver data rate (Hi Speed or Lo Speed). ARINC 575 The Transceiver fully supports the ARINC 429 data rates and receiver electrical characteristics over temperature (-55°C to +125°C for “DC” package, -55°C to +85°C for “PP” and “GP” packages) and voltages (4.5 VDC to 5.5 VDC). It interfaces with TTL, CMOS, or NMOS support circuitry using a standard 5 volt Vcc supply. The interface circuit consists of a transmitter circuit, two identical, but independent receiver circuits, and a user-programmable control register for use in selecting operating options. The transmitter circuit contains an 8 word x 32 bit buffer and control logic which allows the user to write a block of data into the transmitter. Once the user enables the transmitter, the data block is automatically sent without further attention. 3 PIN DESCRIPTIONS (Refer to FIGURE 2 ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Vcc DI1(A) DI1(B) DI2(A) DI2(B) DR1 DR2 SEL OE1 OE2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 N / C 6 D I 2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DD-03282DC TOP VIEW CERDIP D I 2 D I 1 D I 1 B A B A V C C 5 4 3 2 1 DBCEN MR TXCK 1MCK N/C N/C LDCW ENTX DO(B) DO(A) TXR LD2 LD1 D0 D1 D2 D3 D4 D5 GND D B C E N M R T X C K I M C K 44 43 42 41 40 N/C 7 39 N/C 8 38 N/C DR2 9 37 LDCW 36 ENTX DD-03282PP TOP VIEW OE2 12 34 DO(A) PLCC D14 14 31 LD1 D12 16 30 D0 29 D1 D11 17 18 19 20 21 22 23 24 25 26 27 28 N / C G N D D 5 D 4 D 3 D 1 0 D 9 D 8 D 7 D I 2 D I 2 D I 1 D I 1 B A B A D 6 V C C D B C E N 44 43 42 41 40 39 38 N / C M R T X C K I M C K 37 36 35 34 N / C N/C 1 33 N/C 2 32 N/C DR2 3 31 LDCW OE2 6 D15 7 D14 8 D13 9 Data In 1, LO (input, ARINC 429 compatible). ARINC 429 “B” data input to receiver 1. DI2(A) Data In 2, HI (input, ARINC 429 compatible). ARINC 429 “A” data input to receiver 2. DI2(B) Data In 2, LO (input, ARINC 429 compatible). ARINC 429 “B” data input to receiver 2. DR1 Data ready, Receiver 1 (output, active Low). A logic 0 indicates valid data available in receiver 1 DR2 Data ready, Receiver 2 (output, active Low). A logic 0 indicates valid data available in receiver 2 SEL Receiver data select (input). Selects receiver word 1 or 2 to be read on to the data bus. Logic 0 selects receiver word 1 OE1 Receiver 1 data enable (input, active Low). Logic 0 enables selected data from receiver 1 on to data bus. OE2 Receiver 2 data enable (input, active Low). Logic 0 enables selected data from receiver 2 on to data bus. LD1 Load Tx word 1 (input, active Low). Logic 0 pulse loads word 1 into the transmitter memory from data bus. LD2 Load Tx word 2 (input, active Low). Logic 0 pulse loads word 2 into the transmitter memory from data bus. TXR Transmitter ready (output, active High). Logic 1 indicates the transmitter memory is empty and ready to accept new data. Reset to logic 1. DO(A) Transmitter data, HI (output. active High, return to zero). Logic 1 indicates transmitter data bit is a 1. The signal returns to zero for second half of bit time. DO(B) Transmitter data. LO (output, active High, return to zero). Logic 1 indicates transmitter data bit is a 0. The signal returns to zero for second half of bit time. ENTX Enable Transmitter, (input, active High). Logic 1 enables transmitter to send data from transmitter memory. This must be Logic 0 while writing data into transmitter memory. LDCW Load control register, (input, active Low). Logic 0 pulse loads control register from the data bus. NC No connect. 1MCK External clock, (input, TTL compatible). Master clock used by both the receivers and transmitter. The 1MHZ rate is a X10 clock for the HI data rate (100 kbps), and an X80 clock for the LO data rate (12.5 kbps) TXCK Transmitter clock (output). Delivers a clock frequency equal to the transmit data rate. The clock is always enabled and in phase with the data. The clock is a logic 1 during the first half of the data bit time. MR Master Reset (input, active Low pulse). Logic 0 resets transmitter memory, bit counters, word counter, gap timers, DRn, and TXR. Used on power up and system reset. This does not affect the control register. D 2 DR1 5 DI1(B) 32 LD2 D13 15 4 Data In 1, HI (input, ARINC 429 compatible). ARINC 429 “A” data input to receiver 1. 33 TXR D15 13 SEL DI1(A) 35 DO(B) OE1 11 OE1 5 VDC power input. DO-D15 16-Bit Data Bus (bidirectional, Tri-state). Bidirectional data bus for reading data from either of the receivers, or for writing data into the transmitter memory or control register. N / C DR1 SEL 10 Vcc 30 ENTX DD-03282GP 29 DO(B) TOP VIEW 28 DO(A) 27 TXR PQFP 26 LD2 25 LD1 24 D0 D12 10 23 D1 D11 11 12 13 14 15 16 17 18 19 20 21 22 N / C G N D D 5 D 4 D 3 D 1 0 D 9 D 8 D 7 D 6 D 2 FIGURE 2. DD-03282 PIN-OUTS 4 X1,Y1 TABLE 4. CONTROL REGISTER FORMAT BIT DESCRIPTION 15 (MSB) WLSEL 14 RCYSEL 13 TXSEL 12 PARCK 11 Y2 10 X2 09 SDEN2 08 Y1 07 X1 06 SDEN1 05 SLFTST 04 PAREN 03 NOT USED 02 NOT USED 01 NOT USED 00 NOT USED SDEN2 X2,Y2 PARCK TXSEL RCVSEL DBCEN Data bit control enable (input, active Low with internal pull up to Vcc). Logic 0 enables the transmitter parity bit control function as defined by control register bit 4, PAREN. Logic 1 forces transmitter parity bit insertion regardless of PAREN value. Pin is normally left open or tied to GND. WLSEL FUNCTIONAL DESCRIPTION S/D Compare Code RX1 (Bit 7, Bit 8). If the Receiver 1 S/D code check is enabled (SDENB1 = 1), then incoming receiver data S/D fields will be compared to Xl,Yl. If they match, the word will be accepted by Receiver 1; if not, it will be ignored. X1 (Bit 7) is compared to serial data bit 9, Y1 (Bit 8) is compared to serial data bit 10. S/D Code Check Enable RX2 (Bit 9). Logic 1 enables the Source/Destination Decoder for Receiver 2. S/D Compare Code RX2 (Bit 10, Bit 11). If the Receiver 2 S/D code check is enabled (SDENB2 = 1), then incoming receiver data S/D fields will be compared to X2,Y2. If they match, the word will be accepted by Receiver 2; if not, it will be ignored. X2 (Bit 10) is compared to serial data bit 9, Y2 (Bit 11) is compared to serial data bit 10. Parity Check Enable (Bit 12). Logic 1 inverts the transmitter parity bit. Logic 0 selects normal odd parity; logic 1 selects even parity. Transmitter Data Rate Select (Bit 13). Logic 0 sets the transmitter to the HI data rate. HI rate is equal to the clock rate divided by 10 (100 kbps for 1 MHz clock). Logic 1 sets the transmitter to the LO data rate. LO rate is equal to the clock rate divided by 80 (12.5 kbps for 1 MHz clock). Receiver Data Rate Select (Bit 14). Logic 0 sets both receivers to accept the HI data rate. The nominal HI data rate is the input clock divided by 10 (100 kbps for 1 MHz clock). Logic 1 sets both receivers to accept the LO data rate. The nominal LO data rate is the input clock divided by 80 (12.5 kbps for 1 MHz clock). Word Length Select (Bit 15). Logic 0 sets the transmitter and receivers to a 32-bit word format. Logic 1 sets them to a 25-bit word format. NOT USED When writing to the control register, the four "not used" bits are "don't care" bits. These four bits will not be used on the chip. CONTROL REGISTER: The DD-03282 supports a variety of options. These options are selected by data written into the control register. Data is written into the control register from the data bus when the LDCW signal is pulsed to a logic 0. NOTES: The twelve control bits are defined below and shown above in TABLE 4. The test mode should always conclude with ten nulls. This step prevents both receivers from accepting any invalid data stream. NAME For the first word it is recommended that SDENBn, Xn and Yn be changed within 20 bit times after DRn goes low and after the bit stream has been read, or within 30-bit times after a master reset has been removed. TXSEL should only be changed during the time that TXR is high or Master Reset is low. RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both Receiver 1 and Receiver 2 should be ignored. If the control word (which includes WLSEL) is set during Master Reset, the Receiver/Transmitter operation will be correct. If the control word is changed other than during Master Reset, then TXR must be TRUE to ensure correct operation of the transmitter, and the first data stream received, in each receiver, should be ignored. DESCRIPTION PAREN SLFTST SDEN1 Transmitter Parity Enable (Bit 4). Enables parity bit insertion into transmitter data bit 32. Parity is always inserted if DBCEN (Pin 40) is open or HI. If DBCEN is LO, Logic 0 on PAREN inserts data on bit 32, and Logic 1 on PAREN inserts parity on bit 32. Self Test Enable (Bit 5). Logic 0 enables a wrap– around test mode which internally connects the transmitter outputs to both receiver inputs, bypassing the receiver front end. The test data is inverted before going into Receiver 2, so its data is the complement of that received by Receiver 1. The transmitter output is active during test mode. S/D Code Check Enable RX1 (Bit 6). Logic 1 enables the Source/Destination Decoder for Receiver 1. 5 DATA FORMAT DATA ACCESS: To access the receiver data, the user sets the receiver data select line (SEL) to a logic 0 and pulses the output enable (OEn) line with a logic 0. This causes Data Word 1 to be placed on the data bus. To obtain Data Word 2, the user sets the SEL line to a logic 1 and pulses OEn with another Low. When both Word 1 and Word 2 have been read, Data Ready (DRn) will be reset. This reset is triggered by the leading edge of the final OEn. The ARINC serial data is shuffled and formatted into two 16-bit words (WORD 1 and WORD 2) used by the bidirectional data bus interface. FIGURE 3 describes the mapping between the 32-bit ARINC serial data and the two data words. FIGURE 4 describes the mapping for the 25-bit serial word as used when control register bit WLSEL is set to logic 1. If a new data word is received before the previous data has been read from the receiver buffer (as indicated by the DR signal flip flop), the receiver buffer will not be overwritten by the new data. RECEIVER OPERATION Since the two receivers are functionally identical, only one will be discussed in detail. Each receiver consists of the following circuits: DATA ERROR CONDITIONS: If the receiver input data word string is broken before the entire data word is received, the receiver will reset and ignore the partially received data word. LINE RECEIVER: The Line Receiver functions as a voltage level translator. It transforms the ±10 volt differential ARINC data signals into 5 volt internal logic levels. The line receiver is protected against shorts to ±29 volts and provides common mode voltage rejection. The outputs of the Line Receiver are one of two inputs to the Self-Test Data Selector. The other input to the Data Selector is the self-test signal from the transmitter section. The self-test signals are inverted going into Receiver 2. The data selector is controlled by Control Register bit 05 (SLFTST). If the receiver input data word string is not properly framed with at least 1 null bit before the word and 1 null bit after the word, the receiver will reset and ignore the improperly framed data word. TRANSMITTER OPERATION The transmitter section consists of an 8 word x 32 bit FIFO, parity generator, transmitter word-gap timer, and TTL output circuit. INCOMING DATA: The incoming data (either self test or ARINC) is triple sampled by the word gap timer to generate a data clock. The start of each bit is first detected and then verified two receive-clock cycles later. The receive clock is 1 MHz for HI speed and 125 kHz for LO speed operation and is generated by the Receiver/Transmitter timing circuit. The receive clock is ten times the normal data rate to ensure no data ambiguity. FIFO BUFFER: The 8 x 32 buffer memory allows the user to load up to eight words into the transmitter, enable it, and then ignore it while the transmitter sends the data. Data is loaded into the buffer by pulsing LD1 to load the first 16 bits (WORD 1) from the data bus and pulsing LD2 to load WORD 2. LD1 must always precede LD2 for each 32-bit word. The transmitter must always be disabled while loading the buffer (ENTX = logic 0). DATA CLOCK: The derived data clock then shifts the data down a 32 bit long Data Shift register. The data word length is selectable for either 25 bits or 32 bits long by the Control Register bit "WLSEL." As soon as the data word is completely received, an internal signal is generated by the word-gap timer circuit to enable loading data into the 32-bit Rx buffer latch. If the buffer is full and new data is inadvertently strobed with LD1 and LD2, the last 32-bit word in the buffer will be overwritten. Data will remain in the buffer until ENTX goes to a logic 1, which will cause data to be shifted out serially. S/D DECODER: The Source/Destination decoder compares the user set code (X and Y) with bits 9 and 10 of the data word. (The decoder can be enabled and disabled by the "SDENB" bit of the control register). If the two codes are matched, a signal is generated to latch in the received data into the receiver buffer. Otherwise, the data word is ignored and not latched into the buffer. If the data is latched, the Data Ready output signal is set to a logic 0 to indicate to the user that a valid data word has been received and is ready to be read. The buffer data is transmitted until the last word in the buffer is shifted out. At this time a transmitter ready signal (TXR) is set to a logic 1 indicating that the buffer is empty and ready to receive up to eight more data words. Writing into the buffer memory is disabled when ENTX is set to logic 1. READY SIGNAL: The transmitter ready signal (TXR) is set to logic 0 with the first occurrence of a LD2 pulse to indicate that the buffer is not empty. PARITY: The parity of the incoming message is checked when it is received. A logic 0 in bit 8 of word 1 indicates the received word has an odd number of 1's (no error). Logic 1 indicates the received word has an even number of 1's (error condition). OUTPUT REGISTER: The output register can shift out a word of 32 or 25 bits as controlled by control register bit "WLSEL." TX WORD GAP: The TX word gap timer circuit inserts a 4-bit timer gap between words. This gives a minimum requirement of a 36-bit time (or 29-bit time in the 25-bit mode) for each word transmission. The 4-bit time gap is also automatically maintained when a new block of data is loaded into the buffer, which may take less than interword gap time. 6 ARINC SERIAL DATA FORMAT ON BUS (BIT 1 IS TRANSMITTED FIRST) FUNCTION P S A I R G I T SSM N Y BIT 32 31 30 29 M S B DATA 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BIT 15 14 13 12 11 10 9 FUNCTION L S/D S OR B DATA L S B M S S I B G N 8 7 6 5 4 3 2 1 0 M S B LABEL 8 7 6 15 14 13 12 11 10 9 8 7 M L S S/D P S B OR SSM A B R DATA DATA DATA I/O WORD 2 FORMAT 5 6 4 5 3 4 2 3 1 2 1 0 L S B LABEL I/O WORD 1 FORMAT FIGURE 3. MAPPING OF SERIAL DATA TO/FROM WORD 1 AND WORD 2 — 32-BIT FORMAT 25 BIT SERIAL DATA FORMAT ON BUS (BIT 1 IS TRANSMITTED FIRST) FUNCTION P A R I T Y BIT 25 BIT 15 14 13 12 11 10 9 FUNCTION M S S I B G N M S B L S B DATA L S B M S B LABEL S/D 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DATA 0 L S B 8 7 15 14 13 12 11 10 9 Not Used 6 8 5 7 M P S A B R 4 6 3 5 2 4 1 3 LABEL I/O WORD 2 FORMAT I/O WORD 1 FORMAT FIGURE 4. MAPPING OF SERIAL DATA TO/FROM WORD 1 AND WORD 2 — 25-BIT FORMAT 7 2 1 0 L S B SELF-TEST OPERATION PARITY GENERATOR: The parity generator calculates either odd or even parity as specified by control register bit "PARCK." Odd parity is normally used; even parity is available to test the receive parity check circuit. Bit 8 of word one is replaced with a parity bit during serial transmission if parity is selected by the control register bit "PAREN" and the DBCEN pin. Otherwise, bit 8 is passed through as data. By clearing the control register bit (SLFTST) self-test option, the user may perform a functional test of the Transceiver. The user can write data into the transmitter and it will be internally wrapped around into both receivers. The user can then verify reception and integrity of the data. (Self-test data input to channel 2 is inverted.) The ARINC 429 line receiver interface and the external line drivers are not tested. TRANSMITTER OUTPUT: The transmitter outputs TTL compatible signals: DO(A) and DO(B). DO(A) and DO(B) are the transmitter data in two rail, return-to-zero format. DO(A) indicates a logic 1 data bit by going to a 1 for the first half of a bit time, then returning to 0 for the second half; DO(B) remains at 0 for the whole bit time. By setting the transmitter to use even parity, the user can test the receiver's parity circuit operation. POWER-UP RESET AND MASTER RESET In the same fashion, DO(B) indicates a logic 0 data bit by pulsing HI while DO(A) remains LO. A null bit is indicated when both signals remain LO. It is illegal for both signals to be logic 1. The user must apply a logic 0 pulse to the Master Reset pin (MR) after power up or upon system reset. Preceding the master reset at power-up an internal power-up reset occurs which will clear the transmitter so that no erroneous data will be transmitted before master reset. Receivers and the internal control logic are reset by Master Reset. The TXCLK is a continuous clock signal of 50% duty cycle synchronous with transmitter data. The clock will always be logic 1 during the first half of a bit time. POWER-UP RESET: An internal power-up reset circuit prevents erroneous data transmission before an external master reset has been applied. FIGURE 5 shows a typical reset and initialization sequence. The user must pulse the MR pin low to reset the device. To load the Control Register from the data bus, the LDCW pin is pulsed low while the desired control data is applied on the data bus. 25-BIT WORD OPERATION PROCESSOR INTERFACE The Transceiver implements a 25-blt word format which may be used in non-ARINC applications to enhance data transfer rate. FIGURE 6 shows a typical read/write timing sequence and FIGURE 7 shows a typical transmitter loading sequence. The format is a simplified version of the 32-bit ARINC word and is illustrated in FIGURE 4. It consists of an 8-bit label, a 16-bit data word, and a parity bit. The parity bit can optionally be replaced with a 17th data bit. The Source/Destination code checking option can be enabled in either receiver. It will operate on bits 9 and 10 of the 25-bit word. As shown in FIGURE 7 a typical sequence begins with the transmitter completing a logic 1 transmission of the previous data block. The TXR signal notifies the user that data may be loaded into the buffer. The user sets ENTX to logic 0 to disable the Transmitter and proceeds to load a total of six ARINC words into the buffer. (Note that up to eight words could have been loaded). MR TMR (SEE TABLE 3) LDCW ,,,,,,,,,,, ,,,,,,,,,,, D0-D15 VALID FIGURE 5. RESET AND INITIALIZATION SEQUENCE 8 ,,, ,,, ,,,,, TPWLD TLL ,,, LD1, LD2, LDCW D0 - D15 TSDW THDW VALID DATA VALID DATA TDTXR TXR SERIAL DATA IN (1 OR 2) BIT TDDRN DR1, DR2 ,,,,, ,,,,, TDDROE ,,, ,,, OE1, 0E2 TDOEDR THSEL TSSEL SEL TOEOE TPWOE SEL VALID D0-D15 SEL VALID TDTS TDDR DATA VALID DATA VALID FIGURE 6. READ/WRITE TIMING TABLE 5. DD-03282 READ/WRITE SPECIFICATION DATA RATE 100 kb/s SYMBOL PARAMETER MIN MAX DATA RATE 12.5 kb/s MIN MAX UNITS WRITE CYCLE TIMING 130 130 ns 0 0 ns 110 110 ns 0 0 ns TPWLD LD1, LD2 and LDCW Pulse Width TLL Delay Between Consecutive Load Pulse from LD1 to LD2 TSDW Data to LD↑ Set-Up Time THDW Data to LD↑ Hold Time TDTXR Delay LD2↑ to TXR↓ TDDRN READ CYCLE TIMING Delay, Bit 32/25 in↑ to DRn↓ TDDROE TPWOE Delay, DRn↓ to OEn↓, OE1 or OE2 pulse width 0 200 0 200 ns TOEOE Delay Between Consecutive OE Pulses 50 50 ns TDOEDR Delay, 2nd OE↑ to DRn Reset (↑) TSSEL SEL to OE↓ to Valid Data 20 20 ns THSEL SEL to OE↑ Hold Time 20 20 ns TDDR Delay OE↓ to Valid Data TDTS Delay OE↑ to Data Hi-Z 840 840 ns 16 128 µs 200 200 200 10 9 50 10 , , , , , , , ,, ,, , ns 200 ns 50 ns WRITE TIMING READ TIMING TXR ENTX LD1 ,, ,,,,,,, ,,,,,,, ,,,,,,,,,, ,,,, ,,,,,,,,,, ,,,, ,,,,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,, ,,,,,,,,,, ,,,, ,,,,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,, ,,,,,,,,,, ,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,, ,,,,,,,,,, ,,,, ,,,,,,, ,,,,,,, ,,,,,,,,,, LD2 D0-D15 (DATA IN) TX DATA (W1) (W2) (W1) (W2) (W1) (W2) (W1) (W2) (W1) (W2) (W1) (W2) WORD 8 WORD 1 4 BIT TIME NULL MIN WORD 2 NOT TO SCALE TX STARTS FIRST WORD USER ENABLES TX USER LOADS 6TH WORD USER LOADS 5TH WORD USER LOADS 4TH WORD USER LOADS 3RD WORD USER LOADS 2ND WORD TXR INDICATES TX IS NOT EMPTY USER LOADS FIRST WORD USER DISABLES TX TXR INDICATES TX IS EMPTY AND USER MAY LOAD DATA TX TRANSMITTS LAST WORD FROM BUFFER FIGURE 7. TYPICAL TRANSMITTER LOAD SEQUENCE DR1 DR2 OE1 OE2 SEL XXXXXX X W1 XX W2 X W1 XXXX W2 D0-D15 (DATA OUT) DR2 INDICATES RX2 IS EMPTY USER READS WORD 1 AND WORD 2 FROM RX2 DR1 INDICATES RX1 IS EMPTY USER READS WORD 1 AND WORD 2 FROM RX1 DR2 INDICATES RECEPTION OF VALID DATA FROM RX2 DR1 INDICATES RECEPTION OF VALID DATA OF FROM RX1 FIGURE 8. TYPICAL RECEIVER READ SEQUENCE 10 TXR TDTXR ENTX TDTD TNUL D0 (A OR B) BIT 2 TSKTX BIT 1 TDENTX TGAP TBIT BIT 25/32 BIT 25/32 BIT 2 BIT 1 TXCK FIGURE 9. TRANSMITTER TIMING TABLE 6. DD-03282 TRANSMITTER TIMING SPECIFICATION DATA RATE 100 kb/s SYMBOL PARAMETER MIN MAX DATA RATE 12.5 kb/s MIN MAX UNITS 200 µs TDTD Delay, ENTX↑ to output data* TNUL Output data null time 4.95 5.05 39.6 40.4 µs TBIT Output data bit time 4.95 5.05 39.6 40.4 µs TSKTX Data skew between TXCK↑(↓) and D0↑ (↓) 0 ±50 0 ±50 ns TGAP Data word gap time 40.4 316.8 323.2 µs TDTXR Delay, end of TX word to TXR↑ 50 ns TDENTX Delay, TXR↑ to ENTX↓ 25 39.6 50 0 0 *This applies only when there has been a 4-bit null since the end of the transmitted data. 11 ns +5V 1 VCC ARINC 429 RECEIVE CH 1 ARINC 429 RECEIVE CH 2 2 DI1(A) 3 DI1(B) 4 DI2(A) 5 DI2(B) +5V +15V ARINC 429 TRANSMIT 6 11 C1 75pF 6 7 TXR 30 SEL -15V 7 9 16 A 4 B 13 14 3 C C 1 5 12 8 DR1 DR2 DD-03282 31 32 TX0 A TX0 B DO(A) DO(B) 39 40 DD-03182 NOTE: C1 = C2 = 500pF FOR LO SPEED OPERATION 37 38 DIGITAL CONTROL INTERFACE 9 10 28 29 34 EN TX 33 +5V C2 75pF OE1 OE2 LD1 LD2 LDCW 8 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MR DBCEN 1MCK TXCK 1 MHZ CLK 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 DIGITAL DATA INTERFACE GND 21 FIGURE 10. TYPICAL TRANSCEIVER/LINE DRIVER INTERCONNECT CONFIGURATION The user then enables the transmitter by setting ENTX to a logic 1 causing the transmitter to begin the sequence of sending out data words. Although not shown in the figure, the transmitter load sequence can be interleaved with the receiver read cycles with no interference between the two operations. TABLE 7. DD-03182 LINE DRIVER SPECIFICATIONS PARAMETER UNITS MIN TYP MAX ABSOLUTE MAXIMUM RATINGS FIGURE 8 shows a typical receiver read sequence. VOLTAGE BETWEEN PINS Both receivers notify the user that valid data has been received by setting their respective DRn lines to logic 0. The user responds by reading the two data words from Receiver 1 and/or Receiver 2. • +V & -V V • V1 & GND V 40 7 • VREF & GND V 6 POWER SUPPLY REQUIREMENTS The SEL line is normally a system address line and may assume any state, but must be valid when the OEn line is pulsed low. • +V VDC 10.5 15 16.5 • -V VDC -10.5 -15 -16.5 • V1 VDC 4.75 5 5.25 • VREF VDC 4.75 5 5.25 Operating Temperature °C -55 +125 Storage Temperature °C -65 +150 THERMAL Lead Temperature (localized 10 sec duration) 12 °C +300 0.520 [13.21] 0.200 ±0.025 [5.08] 0.100 [2.54] (TYP) 2.050 [52.07] 19 EQ SP @ 0.100 = 1.900 [2.54] = [48.26] (TOL NONCUM) (TYP) ±0.025 0.018 [0.46] (TYP) 1 0.051 [1.30] (TYP) 0.037 ±0.022 [0.94] 0.150 ±0.025 [3.81] 0.605 [15.37] 1 2 0.011 [0.28] (TYP) LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN +0.010 DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS] FIGURE 11. DD-03282DC 40-PIN CERAMIC DIP MECHANICAL OUTLINE SERIAL INTERFACE ARINC 429 LINE DRIVER The transmitter clock (TXCK) is free running and in phase with the transmitter data. The transmitter data (DO(A) and DO(B)) are TTL levels. There are always at least 4 null bits between data words. The DD-03282 requires a line driver to put ARINC 429 data on the serial data bus. DDC's DD-03182 ARINC 429 line driver will support ARINC 429, 571, and 575 standards. FIGURE 10 illustrates a typical interconnection configuration between the DD03282 Transceiver and the DD-03182 ARINC 429 Line Driver. TABLE 7 shows the DD-03182 Line Driver Specifications. Refer to the DD-03182 data sheet for further information about the ARINC 429 Line Driver. The receiver signals (DIn (A) and DIn (B) where n=1 or 2) are differential, bipolar, return-to-zero logic signals. FIGURE 10 is an example of how to connect the DD-03282 to the DD-03182 Line Driver. The receive data is normally asynchronous to the transmitter and can also be at a different data rate than the transmitter. 13 ORIENTATION MARK DENOTES PIN 1 D D1 A A1 D3 1 0.020/0.012 [0.53/0.33] (TYP) 1 E E3 E1 D2/E2 (TYP) 1 0.045/0.025 R [1.14/0.64] R 0.031/0.025 [0.81/0.66] e (TYP) 0.020/[0.51] MIN(TYP) MIN INCHES MAX MIN MM MAX A A1 D1 D2 D3 E1 E2 E3 e D E 0.165 0.090 0.650 0.590 0.500 0.650 0.590 0.500 0.050 0.685 0.685 0.180 0.120 0.656 0.630 0.500 0.656 0.630 0.500 0.050 0.695 0.695 4.20 2.29 16.51 14.99 12.70 16.51 14.99 12.70 1.27 17.40 17.40 4.57 3.04 16.66 16.00 BSC 16.66 16.00 BSC BSC 17.65 17.65 1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN ±0.010 2 DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS] FIGURE 12. DD-03282PP 44-PIN PLASTIC PLCC MECHANICAL OUTLINE D D1 ORIENTATION MARK DENOTES PIN 1 1 34 44 33 1 E E1 e 1 (TYP) B 23 11 12 (TYP) 22 0.012 [0.3] R 0.016 [0.40] (TYP) MIN(TYP) A2 A L A1 A MIN MAX INCHES MIN MAX MM 0.093 2.35 A1 0.004 0.010 0.10 0.25 H 0.005 [0.13] R (TYP) (TYP) C MIN (TYP) A2 D D1 E 0.077 0.083 1.95 2.10 0.537 0.557 13.65 14.15 0.390 0.398 9.90 10.10 0.537 0.557 13.65 14.15 E1 L e 0.390 0.398 9.90 10.10 0.026 0.037 0.65 0.95 0.031 BSC 0.80 BSC B H C 0.012 0.018 0.30 0.45 0.077 REF 1.95 REF 0.005 0.009 0.13 0.23 1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN [0.00039] 2 DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS] FIGURE 13. DD-03282GP 44-PIN PLASTIC PQFP MECHANICAL OUTLINE 14 ORDERING INFORMATION ADDITIONAL HARDWARE DD-03282XX-XX0 – ARINC 429 Transceiver DD-03182XX-XXXX – ARINC 429 Line Driver T = Tape and Reel (GP and VP only) Screening: 0 = Standard DDC Procedures 2 = Burn-in (DC package only) Options: 0 = With resistors and fuses 1 = With resistors, no fuses* Screening: 0 = Standard DDC Procedures 2 = Burn-in (ceramic only) Temperature Range: 1 = -55 to +125°C (ceramic only) 2 = -40 to +85°C 9 = -55 to +85°C (GP package only) Package Style/Type: DC = 16-pin ceramic DIP GP = 16-pin plastic SOIC PP = 28-pin plastic PLCC VP = 14-Pin plastic SOIC Temperature Range: 1 = -55 to +125° C (DC package only) 2 = -40 to +85° C 9 = -55 to +85°C (GP package only) ASIC Package Style/Type: DC = 40-pin ceramic DIP PP = 44-pin plastic PLCC GP = 44-pin plastic PQFP *VP version only. For more detailed information, please refer to the DD-03182 data sheet. OTHER APPLICABLE DOCUMENTS ARINC Specification 429 Mark 33 Digital Information Transfer System 15 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7402 Headquarters - Tel: (631) 567-5600 ext. 7402, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com ILC DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 G-0899-1M PRINTED IN THE U.S.A. 16