LTC1840 Dual Fan Controller with 2-Wire Interface U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1840 is a fan controller with two 8-bit current output DACs, two tachometer interfaces, and four general purpose I/O (GPIO) pins. It operates from a single supply with a range of 2.7V to 5.75V. A current output DAC is used to control an external switching regulator, which controls the fan speed. A current output DAC and tachometer allow a controller to form a closed control loop on fan velocity. The GPIO pins can be used as digital inputs or open drain pull-down outputs. Two 8-Bit Current DACs DACs Guaranteed Monotonic Known IC State on Power-Up Serial Interface Watchdog Timer with Disable 2-Wire Serial Interface Compatible with I2CTM and SMBus 2 Programmable Fan Tachometer Interfaces 4 Programmable General Purpose I/Os Small 16-Pin SSOP Package Single 2.7V to 5.75V Supply Operation Fault Output Signal Status Register Fan Blasting Function Nine Addresses Using Two Programming Lines The part features a simple 2-wire I2C and SMBus compatible serial interface that allows communication between many devices. The interface includes a fault status register that reflects the state of the part and which can be polled to find the cause of a fault condition. Other operational characteristics of the part, such as DAC output currents, GPIO modes, and tachometer frequency, are also programmed through the serial interface. Two address pins provide nine possible device addresses. U APPLICATIO S ■ ■ ■ ■ Servers Desktop Computers Power Supplies Cooling Systems The BLAST pin is provided to force the DAC output currents to program the maximum regulator output voltages through a single pin and gate the operation of the serial access timer. , LTC and LT are registered trademarks of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. U TYPICAL APPLICATIO Low Parts Count, High Efficiency Dual Fan Control 3.3V 10µF 10k TO MASTER 12V + 3.3V 0.1µF VCC FAULT GPI04 SDA BLAST SCL RSENSE1 0.05Ω VIN IDACOUTA SYSTEM RESET RUN/SS SENSE LTC1771 PGATE ITH RC1 10k CC1 220pF LTC1840 130Ω LED2 130Ω NC A0 GPI03 RFB1B 28k RSENSE2 0.05Ω LED1 NC A1 IDACOUTB GPI01 TACHB GPI02 TACHA RUN/SS SENSE LTC1771 ITH PGATE RC2 10k CC2 220pF VFB CFB2 100pF + CVIN2 22µF COUT1 150µF 10k TACH OUT 2-NMB 6820PL-04W-B29-D50 FANS 1.1A NOM AT 12V 3.3V RFB2A 75k Si6447DQ L2 47µH + RFB2B 28k MODE GND + DC FAN UPS5817 12V VIN 3.3V RFB1A 75k Si6447DQ L1 47µH GND 3.3V 3.3V CVIN1 22µF MODE VFB CFB1 100pF + DC FAN COUT2 150µF 10k TACH OUT UPS5817 GND ADDRESS = 1110010 (8 OTHERS POSSIBLE) 1840 TA01 1840f 1 LTC1840 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) VCC to GND .................................................... –0.3 to 6V A0, A1 ............................................. –0.3 to (VCC + 0.3V) IDACOUTA, IDACOUTB ............................. –0.3 to (VCC + 0.75V) All other pins ................................................. –0.3 to 6V Operating Temperature LTC1840C ............................................... 0°C to 70°C LTC1840I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW SCL 1 16 VCC SDA 2 15 IDACOUTA A1 3 14 IDACOUTB A0 4 13 BLAST FAULT 5 12 TACHB GPIO1 6 11 TACHA GPIO2 7 10 GPIO4 GND 8 9 LTC1840CGN LTC1840IGN GN PART MARKING GPIO3 1840 1840I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W Consult LTC marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DACs n Resolution DNL Differential Nonlinearity VDACOUT = 1.1V, Guaranteed Monotonic INL Integral Nonlinearity VDACOUT = 1.1V ZSE Zero-Scale Error VDACOUT = 1.1V Output Voltage Rejection 1.1V< VDACOUT < 3.75V IDACOUTA(FS), IDACOUTB(FS) 8 Output Voltage Rejection VCC = 5.75V, 1.1V < VDACOUT < 6.5V Full-Scale Current Sinking VDACOUT = 1.1V Bits ● –0.2 0.1 ±0.9 LSB ±4 LSB 2 µA ±1 LSB ±2 LSB ● 97 95 103 105 µA µA ● 2.7 5.75 V 400 500 600 750 µA µA 2.1 2.4 2.69 V 20 90 160 mV 47 50 53 kHz 0.1 0.5 %/V Power Supply VCC Positive Supply Voltage ICC Supply Current VUVLO UVLO/POR Voltage VUVHYS UVLO/POR Voltage Hysteresis VCC = 3V, A0 and A1 Floating VCC = 5V, A0 and A1 Floating ● (Note 2) Oscillator Performance fOSC Oscillator Frequency PSRR Supply Sensitivity 2.7V < VCC < 5.75V IO Output Current Sink VGPIOX = 0.7V, Internal Pull-Down Enabled ● VIL Digital Input Low Voltage Internal Pull-Down Disabled ● VIH Digital Input High Voltage Internal Pull-Down Disabled ● VIHYST Input Hysteresis (Note 2) ILEAK Leakage Internal Pull-Down Disabled ● GPIO Performance 10 mA 0.3VCC 0.7VCC V V 50 mV ±1 µA 1840f 2 LTC1840 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Inputs SCL, SDA VIH Digital Input High Voltage ● VIL Digital Input Low Voltage ● VLTH Logic Threshold Voltage (Note 2) ILEAK Digital Input Leakage CIN 1.4 V 0.6 V VCC = 5V and 0V, VIN = GND to VCC ±1 µA Digital Input Capacitance (Note 2) 10 pF Digital Output Low Voltage IPULL-UP = 3mA ● 0.4 V IPULL-UP = 1mA ● 0.4 V 1 V Digital Output SDA VOL Digital Output FAULT VOL Digital Output Low Voltage Digital Inputs TACHA, TACHB VIH Digital Input High Voltage VIL Digital Input Low Voltage ILEAK Digital Input Leakage VCC = 5V and 0V, VIN = GND to VCC VLTH Logic Threshold Voltage Measured on BLAST Falling Edge VIHYST Input Hysteresis (Note 2), Measured on Rising Edge ILEAK Digital Input Leakage VCC = 5V and 0V, VIN = GND to VCC ● 0.7VCC V ● 0.3VCC V ±1 µA Digital Input BLAST 0.95 1.0 1.05 20 V mV ±1 µA Address Inputs A0, A1 VIH Input High Voltage VIL Input Low Voltage IIN Input Current ● 0.9VCC ● AX Shorted to GND or VCC, VCC = 5V V 0.1VCC V ±100 µA 100 kHz Timing Characteristics fI2C I2C Operating Frequency (Note 2) 0 t BUF Bus Free Time Between Stop and Start Condition (Note 2) 4.7 µs t hD, STA Hold Time after (Repeated) Start Condition (Note 2) 4 µs t su, STA Repeated Start Condition Setup Time (Note 2) 4.7 µs t su, STO Stop Condition Setup Time (Note 2) t hD, DAT Data Hold Time t su, DAT Data Setup Time t LOW t HIGH 4 µs 300 ns (Note 2) 250 ns Clock Low Period (Note 2) 4.7 µs Clock High Period (Note 2) 4.0 µs tf Clock, Data Fall Time (Note 2) 300 ns tr Clock, Data Rise Time (Note 2) 1000 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Guaranteed by design not subject to test. 1840f 3 LTC1840 U W TYPICAL PERFOR A CE CHARACTERISTICS IDACOUT Full Scale vs VCC, VDACOUT = 1.1V Supply Current vs Temperature (VCC = 3V) Supply Current vs Supply Voltage 550 450 TA = 25°C 100.10 TA = 25°C 440 100.05 500 450 IDACOUT (µA) ICC (µA) ICC (µA) 430 420 100.00 410 99.95 400 400 2.5 4.5 3.5 5.5 390 –50 6.5 75 0 25 50 TEMPERATURE (°C) –25 VCC (V) 100.10 40 20 0 1 100.5 2 3 4 5 6 TA = 25°C 100.3 100.00 100.1 IDACOUT (µA) 60 99.95 99.90 99.9 99.7 99.85 99.5 99.80 99.3 99.75 0.5 VDACOUT (V) 99.1 1.5 2.5 4.5 3.5 0 2 3 4 VDACOUT (V) 5 6 1840 G05 IDACOUT AC Supply Rejection at Full Scale, VCC = 3V DC 1840 G06 DAC Zero Scale Error at VCC = 3V, VDACOUT = 1.1V 20 DAC DNL vs Code at VCC = 3V 0.2 10 TA = 25°C TA = 25°C 0.1 10 DNL (LSB) 15 DAC ZSE (nA) IDACOUT/VCC (µA/V) 1 VDACOUT (V) 1840 G04 5 0 –0.1 5 0 6.5 IDACOUT FS vs VDACOUT at VCC = 5V IDACOUT FS vs VDACOUT at VCC = 3V 100.05 IDACOUT (µA) IDACOUT (µA) 80 5.5 1840 G03 TA = 25°C TA = 25°C 100 4.5 3.5 1840 G02 IDACOUT FS vs VDACOUT at VCC = 3V to 5V 0 99.90 2.5 VCC (V) 1840 G01 120 100 1 100 10 FREQUENCY (kHz) 1000 1840 G07 0 –50 –25 –0.2 50 25 75 0 TEMPERATURE (°C) 100 125 255 1 CODE 1840 G09 1840 G08 1840f 4 LTC1840 U W TYPICAL PERFOR A CE CHARACTERISTICS BLAST Falling Threshold at VCC = 3V DAC INL at VCC = 3V 0.4 1.011 TA = 25°C 1.010 BLASTB THRESHOLD (V) BEST FIT INL (LSB) 0.3 0.2 0.1 0 1.009 1.008 1.007 1.006 1.005 1.004 –0.1 1.003 –0.2 255 0 CODE 1.002 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 1840 G10 1840 G11 U U U PI FU CTIO S SCL (Pin 1): Serial Clock Input. The 2-wire bus master device clocks this pin at a frequency between 0kHz and 100kHz to enable serial bus communications. Data at the SDA pin is shifted in or out on rising SCL edges. SCL has a logic threshold of 1V and an external pull-up resistor or current source is normally required. SDA (Pin 2): Serial Data Input. This is a bidirectional data pin which normally has an external pull-up resistor or current source and can be pulled down by the open drain device on the LTC1840 or by external devices. The master controls SDA during addressing, the writing of data, and read acknowledgment, while the LTC1840 controls SDA when data is being read back and during write acknowledgment. SDA data is shifted in or out on rising SCL edges. SDA has a logic threshold of 1V. A1 (Pin 3): Three State Address Programming Input. This pin can cause three different logic states internally, depending upon whether it is pulled to supply, pulled to ground, or not connected (NC). Combined with the A0 pin, this provides for nine different possible two-wire bus addresses for the LTC1840 (see Table 1). A0 (Pin 4): Three State Address Programming Input. See A1. FAULT (Pin 5): Fault Indicator Pull-Down Output. This pin has an open drain pull-down that is used to signal various fault conditions on the LTC1840. An external 10k pull-up is recommended. GPIO1, GPIO2, GPIO3, GPIO4 (Pins 6, 7, 9, 10): General Purpose Inputs/Outputs. These pins can be used as digital inputs with CMOS logic thresholds or digital outputs/LED drivers with open drain pull-downs that can be programmed to blink. GPIO pins can be programmed to produce faults due to changes in their logic states, and these faults can only be cleared by software or powering the LTC1840 down. All GPIOs default to nonfaulting logic inputs upon power-up and their functionality is changed through the serial interface. GND (Pin 8): Ground. Connect to analog ground plane. TACHA (Pin 11): Tachometer Input A. This pin is a digital input that is designed to interface to the tachometer output from a 3-wire fan. Internal logic counts between rising TACHA edges at serially programmable frequencies of 25kHz, 12.5kHz, 6.25kHz or 3.125kHz and the most recently completed count is stored in a register accessible through the serial interface. The maximum count is 255 and the LTC1840 is programmable to produce faults when a count exceeds this number. This pin has CMOS thresholds and the default conditions are to count at 3.125kHz and to not produce faults. TACHB (Pin 12): Tachometer Input B. See TACHA 1840f 5 LTC1840 U U U PI FU CTIO S BLAST (Pin 13): Blast/Timer Function Input. This is a multifunction digital input pin that controls blast and timer operation. If this pin is in a logic high state at power-up or is transitioned from high to low, it will “blast” the current DAC outputs to full scale (100µA) no matter what their previous state was and set a fault condition. In addition, if BLAST is in a logic high state, the serial access timer is active; this circuit measures time between serial communications to the LTC1840 and forces a blast and trips a fault if the part hasn’t been accessed for about 1.5 minutes. This pin has a 1V logic threshold. 100µA. This current can be programmed to one of 256 values through the serial interface or it can be “blasted” immediately to full scale using the BLAST pin or by the serial access timer if it is enabled and the LTC1840 is not accessed for about 1.5 minutes. This pin will maintain the programmed current to a very tight tolerance from as low as 1.1V to at least 0.75V above VCC. The current DAC is guaranteed to be monotonic over its full 8-bit range. IDACOUTA (Pin 15): Current DAC Output A. See IDACOUTB VCC (Pin 16): Positive Supply. This pin must be closely decoupled to ground (pin 8). A 10µF tantalum and a 0.1µF ceramic capacitor in parallel are recommended. IDACOUTB (Pin 14): Current DAC Output B. This is a high impedance output with a sinking current output of 0µA to W BLOCK DIAGRA IDACOUTA IDACOUTB 15 14 I 13 6 GPIO1 FAULT DETECT 1 7 GPIO2 GPI/O INTERFACE SERIAL INTERFACE SDA BLAST 5 I 8-BIT IDACs SCL FAULT 2 9 GPIO3 8-BIT COUNTER A1 3 OSC REF A0 4 8 GND 10 GPIO4 8-BIT COUNTER ÷ 2, 4, 8, 16 12 11 TACHB TACHA 1840 BD WU W TI I G DIAGRA SDA tsu, DAT tsu, STA thD, DAT tLOW tBUF thD, STA tsu, STO SCL tHIGH thD, STA tr START CONDITION 1840 TD01 tf REPEATED START CONDITION STOP CONDITION START CONDITION 1840f 6 LTC1840 U OPERATIO Typical 2-Wire Serial I2C or SMBus Transmission SDA 1-7 SCL 8 9 1-7 8 9 1-7 8 9 S P START CONDITION STOP CONDITION ADDRESS R/W ACK ACK DATA Serial Interface • Simple 2-wire interface • Multiple devices on same bus • Idle bus must have SDA and SCL lines high • LTC1840 is read/write • Master controls bus • Devices listen for unique address that precedes data The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Acknowledge The acknowledge signal is used for handshaking between the master and the slave. An acknowledge (LOW active) generated by the slave lets the master know that the latest byte of information was received. The acknowledgerelated clock pulse is generated by the master. The transmitter master releases the SDA line (HIGH) during the acknowledge clock pulse. The slave receiver must pull down the SDA line during the acknowledge clock pulse so ACK DATA 1840 TD02 that it remains stable LOW during the HIGH period of this clock pulse. When a slave receiver doesn’t acknowledge the slave address (for example, it’s unable to receive because it’s performing some real-time function), the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If a slave receiver acknowledges the slave address, but some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the “not acknowledge” on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition. Commands Supported The LTC1840 supports read byte, write byte, read word (the second data byte will be all ones) and write word (the second data byte will be ignored) commands. Data Transfer Timing for Write Commands In order to help assure that bad data is not written into the LTC1840, data from a write command is only stored after a valid acknowledge has been performed. The part will detect that SDA is low on the rising edge of SCL that marks the end of the period in which the LTC1840 acknowledges the data write and then latch the data during the following SCL low period. LTC1840 Write Byte Protocol 1 7 1 1 8 1 8 1 1 START 1 1 1 B4 B3 B2 B1 WR ACK X X X X X R2 R1 R0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP SLAVE ADDRESS 0 S 0 REGISTER ADDRESS S 0 DATA BYTE S 0 LTC1840 Read Byte Protocol 1 7 1 1 8 1 START 1 1 1 B4 B3 B2 B1 WR ACK X X X X X R2 R1 R0 ACK SLAVE ADDRESS 0 S 0 REGISTER ADDRESS S 0 1 7 START 1 1 1 B4 B3 B2 B1 SLAVE ADDRESS 1 1 8 1 1 RD ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP 1 S 0 DATA BYTE M 1 1840 TD03 1840f 7 LTC1840 U OPERATIO LTC1840 Device Addressing Register Addresses and Contents It is possible to configure the part to operate with any one of nine separate addresses through the three state A0 and A1 pins. Table 1 shows the correspondence of addresses to the states of the pins: Fault conditions are cleared by the action of writing to the fault register, but the data byte from the write command is not actually loaded into the register. Table 1. Device Addressing LTC1840 Device Address 2-Wire Bus Slave Address Bits (B7,B6,B5 = 111) A0 A1 B4 B3 B2 B1 L NC 0 0 0 0 NC H 0 0 0 1 NC NC 0 0 1 0 H NC 0 0 1 1 L L 0 1 0 0 H H 0 1 0 1 NC L 0 1 1 0 H L 0 1 1 1 L H 1 0 0 0 For the A0 and A1 lines, L refers to a grounded pin, H is a pin shorted to VCC and NC is no connect. The pin voltage will be set to approximately VCC/2 when not connected. Bits B7, B6 and B5 of the address are hardwired to 111. Table 2. LTC1840 Register Address and Contents A TACHA/B FLT (fault) bit will be high if the corresponding TACHA/B FLTEN bit in the status register has been set high and the corresponding TACHA/B counter has overflowed its maximum count of 255. These faults are latched internally and must be cleared by writing to the fault register or by setting TACHA/B FLTEN low. The fault will be reasserted if the counter is still in overflow after a write to the fault register. The TACH FLT bits power-up in the low state. The blast and timer bits become high after blasting and serial access time-out events, respectively. A high GPIOX FLT bit reflects that the GPIOX pin has caused a fault condition; to do so, the pin must be enabled as fault producing in the GPIO setup register (GPIOX FLTEN set high) and the logic state of the pin must change after the enable. The fault is latched internally and must be cleared through software by writing to the fault register or by setting GPIOX FLTEN low; a change in the state of the GPIOX pin from its state at the point of the fault register being written will cause another fault to be signalled. Register Name Register Address (R/W) R2 R1 R0 D7 D6 D5 D4 D3 D2 D1 D0 FAULT 000 TACHA FLT (0) TACHB FLT (0) Blast (0) Timer (0) GPI04 FLT (0) GPI03 FLT (0) GPI02 FLT (0) GPI01 FLT (0) STATUS 001 DIV1 (0) DIV0 (0) *See Note 2 (0/1) (0) (0) (1) Data Byte TACHA FLTEN TACHB FLTEN (0) (0) DACA 010 MSB (0) Bit 6 (0) Bit 5 (0) Bit 4 (0) Bit 3 (0) Bit 2 (0) Bit 1 (0) LSB (0) DACB 011 MSB (0) Bit 6 (0) Bit 5 (0) Bit 4 (0) Bit 3 (0) Bit 2 (0) Bit 1 (0) LSB (0) TACHA 100 Cnt A7 (1) Cnt A6 (1) Cnt A5 (1) Cnt A4 (1) Cnt A3 (1) Cnt A2 (1) Cnt A1 (1) Cnt A0 (1) TACHB 101 Cnt B7 (1) Cnt B6 (1) Cnt B5 (1) Cnt B4 (1) Cnt B3 (1) Cnt B2 (1) Cnt B1 (1) Cnt B0 (1) GPIO Data 110 GPIO4 Pin (N/A) GPIO3 Pin (N/A) GPIO2 Pin (N/A) GPIO1 Pin (N/A) GPIO4 Reg (1) GPIO3 Reg (1) GPIO2 Reg (1) GPIO1 Reg (1) GPIO Setup 111 GPIO4 BLNK (0) GPIO3 BLNK (0) GPIO2 BLNK (0) GPIO1 BLNK (0) Note 1: Number in ( )signifies default bit status upon power-up. GPIO4 FLTEN GPIO3 FLTEN GPIO2 FLTEN GPIO1 FLTEN (0) (0) (0) (0) Note 2: State of bit depends on slave address used. 1840f 8 LTC1840 U OPERATIO DIV1 and DIV0 program the ratio by which the internal 50kHz oscillator frequency is divided down to produce the tachometer clocks (2, 4, 8, or 16). The DIV bits power-up low, which corresponds to a frequency division of 16. For example, if DIV1 and DIV0 are both high, the divide ratio is set to 2. If DIV1 is high and DIV0 is low, the divide ratio is set to 4. If DIV1 is low and DIV0 is high, the divide ratio is set to 8. The TACHA and TACHB registers will be set to all ones by a UVLO condition. The tach counters count between rising edges on the TACHA and TACHB pins. If a counter overflows its maximum count of 255, the latch holding the count results is immediately set to 255 without waiting for the next edge on its TACH pin. This is done so that a suddenly stopped or locked rotor will be easily detectable by reading its corresponding tach register; otherwise, the register would merely hold the previous count and be waiting for a tach signal edge that isn’t coming to update the overflow count. The GPIOX pin bits in the GPIO data register reflect the logic state of the pin itself, while the GPIOX register bits reflect the data that is stored in the register that controls the gate of the internal pull-down for the pin. The logic polarities of the GPIOX bits are the same as those of the GPIOX pins assuming an appropriately sized pull-up resistor (for example, a 1 value for the GPIO1 register bit will force the internal N-channel MOSFET pull-down to an offstate, resulting in a 1 value at the GPIO1 pin). For a GPIO to be used as a digital input, the GPIOX register bit is set high, which turns off the internal pull-down N-channel MOSFET, and the state of the pin can be controlled externally and read back via the GPIOX pin bit. The GPIO register bits power-up in the high state. The GPIOX BLNK bits in the GPIO setup register control whether the internal pull-down on a GPIO shuts on and off at about 1.5Hz when the GPIOX register bit is low, and the GPIOX FLTEN bits control whether a GPIO pin can trigger a fault condition by a change in state. The GPIO FLTEN and GPIO BLNK bits power-up in the low state. Serial Interface Example In this example, an LTC1840 has both address pins open (NC) and the output current of DACA will be programmed to half of full-scale (50µA current sink). Provide a start condition on the bus by pulling SDA from high to low while SCL is high and then write the SDA bit stream 1110010 to the part for the LTC1840 slave address, followed by a 0 to indicate that a write operation will follow. All SDA transitions must happen when SCL is low, or a start or stop condition will be interpreted. The LTC1840 will then pull the SDA line low during the next SCL clock phase to indicate that it is responding to the communication attempt. To write to the DACA output register, write 00000010 to the LTC1840 and wait for the LTC1840 to acknowledge again on the following SCL cycle by pulling SDA low. Next, send the LTC1840 the value indicating the DACA current; writing the SDA data stream 10000000 sets the DAC to sink 50µA. The LTC1840 will then acknowledge a third time by pulling SDA low for the next SCL cycle. Then the data will be written into the internal DACA register and IDACOUTA pin will sink 50µA. Now generate a stop condition by forcing SDA from low to high while SCL is high. Tachometer Interface Operation It is common for fans to have tachometer outputs that produce two pulses per blade revolution. The LTC1840 provides two inputs that interface to circuits that count between rising edges on these pulses. The frequency at which the counting is done is programmable via the serial interface to 25kHz, 12.5kHz, 6.25kHz, and 3.125kHz, equivalent to divide by 2, 4, 8, and 16 operations on the internal 50kHz oscillator. The count values corresponding to these two inputs can also be read via the serial interface. The output registers storing these counts power-up to all ones, and they will also be loaded with all ones whenever a counter overflows between two rising edges to allow for the detection of a suddenly stopped rotor. The part can also be configured to produce a fault as soon as the counter overflows. However, the default state is to not produce such faults, so as to prevent unnecessary fault conditions while the fan is spinning up at start-up. Multiple fans with open drain tachometer output signals can be connected to a single LTC1840 tachometer input in a wired-OR fashion, as long as the fans are not active at the same time. If the fans happen to be spinning simultaneously, the counts in the tach registers will not be meaningful. 1840f 9 LTC1840 U OPERATIO GPIO Operation The GPIO circuits feature N-channel MOSFET open drain pull-downs that can drive LEDs and readback circuitry to allow the logic states of the GPIO pins to be accessed through the serial interface. The circuits that read the logic states of the pins have standard CMOS thresholds. The user must take care to minimize the power dissipation in the pull-downs. LEDs should have series resistors added to limit current and to limit the voltage drop across the internal pull-down if their forward drop is less than about VCC minus 0.7V. The N-channel MOSFET pull-downs can sink 10mA at 0.7V drop to drive LEDs. A series resistor is usually required to limit LED current and the LTC1840 internal power dissipation. See Table 3 for resistor values. Table 3. Recommended LED Resistor Values Recommended Series Resistor (Ω) LED Current (mA) VCC = 3V VCC = 5V 1 1k 3k 3 270 910 5 120 510 10 30 240 Note: LED forward voltage drop assumed to be 2V. FAULT Operation Normally, the FAULT pin internal pull-down is only enabled if one of the fault bits in the fault register is high. But it is also enabled if the part is shut down by the POR block due to low VCC supply. This POR fault does not have a corresponding fault register bit. BLAST and Serial Interface Watchdog Timer Operation The BLAST pin is used to force the DAC output currents to full value instantaneously and also to gate the operation of the serial interface watchdog timer. A blast will occur if the BLAST pin is high when the part comes out of POR or if there is a high to low transition on BLAST after POR. The threshold of the BLAST pin is about 1V, independent of VCC. The serial interface watchdog timer, which will signal a fault condition if the part has not been addressed via the serial interface for about a minute and a half, is only active if the BLAST pin is high. If neither blasts nor an active serial interface watchdog timer are desired, this pin should be tied to ground. If timer operation is desired without having a blast occur at power-up, the pin should be pulled above 1V after the part’s supply has ramped up. The blast state is cleared by writing to the fault register. Current Output DAC Interface to Switching Regulator The output of a current DAC is used to control the output voltage of a switching regulator that powers a fan, which determines the rotational speed of the fan. The resistor divider from the output of the regulator to the feedback pin to ground should be ratioed to give the minimum desired voltage from the fan, which corresponds to the minimum fan speed. The size of the resistor from the output to the feedback pin is then chosen by dividing the difference between the maximum and minimum desired fan voltages by the nominal maximum current output of the DAC, which is 100µA. The value of the resistor from the feedback pin to ground is then derived from the divider ratio and the resistor value just calculated. For example, if the feedback pin of the regulator is at 1.25V with respect to ground and the minimum desired fan voltage is 5V, the top resistor in the divider should be (5V – 1.25V)/1.25V = 3 times larger than the resistor from the feedback node to ground. If the maximum desired fan voltage is 12V, the top resistor value is then (12V – 5V)/ 100µA = 69.8k, and the bottom resistor is 69.8k/3 = 23.2k. See Figure 1. If the feedback pin voltage of a regulator is lower than the 1.1V compliance voltage of either of the LTC1840’s current output DACs, the resistor from the regulator output to the feedback pin can be divided into two resistors, giving the DAC more room to operate. See Figure 2. If more than one fan is controlled by one regulator output, small differences in the actual rotational speeds of the fans may result in audible beat frequencies, which can be very annoying. To avoid this problem, the actual voltages applied to the fans can be varied by adding resistors or diodes in series with some of the fans, resulting in larger differences between their rotational speeds and less noticeable beating. See Figure 3. 1840f 10 LTC1840 U OPERATIO VOUT (5V TO 12V) VFB REGULATOR 1.25V FB R1 69.8k IDAC VOUT (5V TO 12V) LTC1840* R3 69.8k IDAC IDACOUTA 15(14) (IDACOUTB) 1.3V R2 23.2k REGULATOR FB 1840 F01 R1 10k VFB 0.8V IDACOUTA 15(14) (IDACOUTB) 1840 F02 R2 15k *ADDITIONAL DETAILS OMITTED FOR CLARITY Figure 1. Feedback Divider for 1.25V Reference LTC1840* *ADDITIONAL DETAILS OMITTED FOR CLARITY Figure 2. Feedback Divider for 0.8V Reference VOUT BYS10-25 FAN 1 FAN 2 1840 F03 FAN 1, FAN 2: NMB 6820PL-04W-B49-D50 Figure 3. Series Diode to Avoid Beat Frequencies U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.009 (0.229) REF 2 3 4 5 6 7 0.053 – 0.068 (1.351 – 1.727) 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 1098 1840f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC1840 U TYPICAL APPLICATIO Controlling Fan Pair with Automatic Blast Redundancy and Fan Pair with Automatic Tach Muxing 12V + L1 = SUMIDA CDRH125-15OMC CIN, COUT, = PANASONIC EEV-FC1C471P R1, R2 = 1% METAL FILM CIN1B 470µF + CIN2B 470µF 1 10k 2 IN4148 3 TN0205A 4 5 10k CC1B 470pF CC2B 220pF 6 7 CF1B 100pF 8 4.7k LTC1625 16 EXTVCC VIN SYNC TK RUN/SS SW FCB TG ITH B00ST SGND INTVCC VOSENSE VPROG BG PGND CVINB 0.1µF 15 14 TP0101TS Si4410DY L1B 15µH 13 12 MBRS140T3 11 10 9 R1B 75k CMDSH-3 + + Si4410DY R2B 27k CVCCB 4.7µF DC FAN COUT1B 470µF ×2 3.3V + SCL 2 SDA 10k NC 130Ω FAULT NC LED1 3 4 5 3.3V 6 10k -A- 7 8 SDA IDACOUTA A1 IDACOUTB A0 FAULT 15 CIN1 470µF 0.1µF + CIN2 470µF 1 + 10µF 2 14 3 13 SYSTEM BLAST RESET 12 TACHB 4 GPIO1 TACHA GPIO2 GPIO4 GND GPIO3 10k CC1 470pF 11 5 CC2 220pF 6 7 10 CF1 100pF 9 8 10k RUN/SS FCB TK SW TG ITH B00ST SGND INTVCC VOSENSE VPROG BG PGND 10k TACH OUT 2- NMB 5910PL-04W-B59-D50 FANS 2.1A NOM AT 12V 10k 4.7k LTC1625 16 EXTVCC VIN SYNC DC FAN TACH OUT 3.3V LTC1840 1 16 VCC SCL 3.3V (4.5V TO 12V) CBB, 0.22µF CVIN 0.1µF 15 14 13 CB, 0.22µF -A- Si4410DY L1 15µH (4.5V TO 12V) 12 MBRS140T3 11 CMDSH-3 10 9 + R1 75k Si4410DY CVCC 4.7µF ADDRESS = 1110010 (8 OTHERS POSSIBLE) R2 27k BYS10-25 COUT1 + 470µF ×2 DC FAN DC FAN TACH OUT TACH OUT 2- NMB 5920PL-04W-B29-D50 FANS 2.2A NOM AT 12V TO AUTOMATICALLY MUX TACHB BETWEEN THE TWO PARALLEL FANS, SET GPIO2 TO BLINK 1840 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS TM Up to 97% Efficiency; 1.19V ≤ VIN ≤ 36V; 1.19V ≤ VOUT ≤ VIN; Up to 99% Duty Cycle LTC1625 No RSENSE Current Mode Synchronous Step-Down Switching Regulator LTC1695 SMBus/I2C Fan Speed Controller in ThinSOTTM 0.75Ω PMOS Linear Regulator with 180mA Output Current Rating LTC1694/LTC1694-1 SMBus Accelerator Includes DC and AC Pull-Up Current/AC Pull-Up Current Only LTC1771 Ultralow Supply Current Step-Down DC/DC Controller 10µA Supply Current; 93% Efficiency; 1.23V ≤ VOUT ≤ 18V; 2.8V ≤ VIN ≤ 20V; Up to 100% Duty Cycle LTC4300-1 Hot Swappable 2-Wire Bus Buffer Prevents SDA, SCL Corruption During Live Insertion; Bidirectional Bus Buffer; Isolates Backplane and Card Capacitance No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. 1840f 12 Linear Technology Corporation LT/TP 0402 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001